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26 #define DEBUG_TYPE "asm-printer"
28 #include "ARCGenAsmWriter.inc"
32 LLVM_DEBUG(
dbgs() <<
"Unknown condition code passed: " << cc <<
"\n");
33 return "{unknown-cc}";
112 if (
const auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
118 if (
const auto *BE = dyn_cast<MCBinaryExpr>(Expr)) {
119 SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
120 const auto *CE = dyn_cast<MCConstantExpr>(BE->getRHS());
121 assert(SRE && CE &&
"Binary expression must be sym+const.");
122 Offset = CE->getValue();
124 SRE = dyn_cast<MCSymbolRefExpr>(Expr);
125 assert(SRE &&
"Unexpected MCExpr type.");
140 void ARCInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNum,
153 assert(
Op.isExpr() &&
"unknown operand kind in printOperand");
157 void ARCInstPrinter::printMemOperandRI(
const MCInst *
MI,
unsigned OpNum,
160 const MCOperand &offset =
MI->getOperand(OpNum + 1);
161 assert(
base.isReg() &&
"Base should be register.");
162 assert(offset.
isImm() &&
"Offset should be immediate.");
167 void ARCInstPrinter::printPredicateOperand(
const MCInst *
MI,
unsigned OpNum,
171 assert(
Op.isImm() &&
"Predicate operand is immediate.");
175 void ARCInstPrinter::printBRCCPredicateOperand(
const MCInst *
MI,
unsigned OpNum,
178 assert(
Op.isImm() &&
"Predicate operand is immediate.");
187 void ARCInstPrinter::printU6ShiftedBy(
unsigned ShiftBy,
const MCInst *
MI,
192 unsigned Value2 =
Value >> ShiftBy;
193 if (Value2 > 0x3F || (Value2 << ShiftBy !=
Value)) {
194 errs() <<
"!!! Instruction has out-of-range U6 immediate operand:\n"
195 <<
" Opcode is " <<
MI->getOpcode() <<
"; operand value is "
198 errs() <<
" scaled by " << (1 << ShiftBy) <<
"\n";
199 assert(
false &&
"instruction has wrong format");
202 printOperand(
MI, OpNum,
O);
206 printU6ShiftedBy(0,
MI, OpNum,
O);
VariantKind getKind() const
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O)
This is an optimization pass for GlobalISel generic memory operations.
static const char * getRegisterName(unsigned RegNo)
This class is intended to be used as a base class for asm properties and features specific to the tar...
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Instances of this class represent a single low-level machine instruction.
static const char * ARCBRCondCodeToString(ARCCC::BRCondCode BRCC)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
This class implements an extremely fast bulk output stream that can only output to a stream.
const MCSymbol & getSymbol() const
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
static void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI, raw_ostream &OS)
LLVM_NODISCARD std::string lower() const
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printU6(const MCInst *MI, int OpNum, raw_ostream &O)
therefore end up llgh r3 lr r0 br r14 but truncating the load would lh r3 br r14 Functions ret i64 and ought to be implemented ngr r0 br r14 but two address optimizations reverse the order of the AND and ngr r2 lgr r0 br r14 CodeGen SystemZ and ll has several examples of this Out of range displacements are usually handled by loading the full address into a register In many cases it would be better to create an anchor point instead E g i64 base
Represent a reference to a symbol from inside an expression.
StringRef - Represent a constant reference to a string, i.e.
static const char * ARCCondCodeToString(ARCCC::CondCode CC)
static const char * BadConditionCode(T cc)
void printCCOperand(const MCInst *MI, int OpNum, raw_ostream &O)
Instances of this class represent operands of the MCInst class.
Generic base class for all target subtargets.
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.