LLVM 22.0.0git
AArch64InstPrinter.cpp
Go to the documentation of this file.
1//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an AArch64 MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64InstPrinter.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "Utils/AArch64BaseInfo.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/Support/Casting.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/Format.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Support/raw_ostream.h"
28#include <cassert>
29#include <cstdint>
30#include <string>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "asm-printer"
35
36#define GET_INSTRUCTION_NAME
37#define PRINT_ALIAS_INSTR
38#include "AArch64GenAsmWriter.inc"
39#define GET_INSTRUCTION_NAME
40#define PRINT_ALIAS_INSTR
41#include "AArch64GenAsmWriter1.inc"
42
47
52
53bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
54 if (Opt == "no-aliases") {
55 PrintAliases = false;
56 return true;
57 }
58 return false;
59}
60
64
65void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
66 unsigned AltIdx) {
67 markup(OS, Markup::Register) << getRegisterName(Reg, AltIdx);
68}
69
73
74void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
75 StringRef Annot, const MCSubtargetInfo &STI,
76 raw_ostream &O) {
77 // Check for special encodings and print the canonical alias instead.
78
79 unsigned Opcode = MI->getOpcode();
80
81 if (Opcode == AArch64::SYSxt)
82 if (printSysAlias(MI, STI, O)) {
83 printAnnotation(O, Annot);
84 return;
85 }
86
87 if (Opcode == AArch64::SYSLxt)
88 if (printSyslAlias(MI, STI, O)) {
89 printAnnotation(O, Annot);
90 return;
91 }
92
93 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
94 if (printSyspAlias(MI, STI, O)) {
95 printAnnotation(O, Annot);
96 return;
97 }
98
99 // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
100 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
101 if (printRangePrefetchAlias(MI, STI, O, Annot))
102 return;
103 }
104
105 // SBFM/UBFM should print to a nicer aliased form if possible.
106 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
107 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
108 const MCOperand &Op0 = MI->getOperand(0);
109 const MCOperand &Op1 = MI->getOperand(1);
110 const MCOperand &Op2 = MI->getOperand(2);
111 const MCOperand &Op3 = MI->getOperand(3);
112
113 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
114 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
115 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
116 const char *AsmMnemonic = nullptr;
117
118 switch (Op3.getImm()) {
119 default:
120 break;
121 case 7:
122 if (IsSigned)
123 AsmMnemonic = "sxtb";
124 else if (!Is64Bit)
125 AsmMnemonic = "uxtb";
126 break;
127 case 15:
128 if (IsSigned)
129 AsmMnemonic = "sxth";
130 else if (!Is64Bit)
131 AsmMnemonic = "uxth";
132 break;
133 case 31:
134 // *xtw is only valid for signed 64-bit operations.
135 if (Is64Bit && IsSigned)
136 AsmMnemonic = "sxtw";
137 break;
138 }
139
140 if (AsmMnemonic) {
141 O << '\t' << AsmMnemonic << '\t';
142 printRegName(O, Op0.getReg());
143 O << ", ";
144 printRegName(O, getWRegFromXReg(Op1.getReg()));
145 printAnnotation(O, Annot);
146 return;
147 }
148 }
149
150 // All immediate shifts are aliases, implemented using the Bitfield
151 // instruction. In all cases the immediate shift amount shift must be in
152 // the range 0 to (reg.size -1).
153 if (Op2.isImm() && Op3.isImm()) {
154 const char *AsmMnemonic = nullptr;
155 int shift = 0;
156 int64_t immr = Op2.getImm();
157 int64_t imms = Op3.getImm();
158 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
159 AsmMnemonic = "lsl";
160 shift = 31 - imms;
161 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
162 ((imms + 1 == immr))) {
163 AsmMnemonic = "lsl";
164 shift = 63 - imms;
165 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
166 AsmMnemonic = "lsr";
167 shift = immr;
168 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
169 AsmMnemonic = "lsr";
170 shift = immr;
171 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
172 AsmMnemonic = "asr";
173 shift = immr;
174 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
175 AsmMnemonic = "asr";
176 shift = immr;
177 }
178 if (AsmMnemonic) {
179 O << '\t' << AsmMnemonic << '\t';
180 printRegName(O, Op0.getReg());
181 O << ", ";
182 printRegName(O, Op1.getReg());
183 O << ", ";
184 markup(O, Markup::Immediate) << "#" << shift;
185 printAnnotation(O, Annot);
186 return;
187 }
188 }
189
190 // SBFIZ/UBFIZ aliases
191 if (Op2.getImm() > Op3.getImm()) {
192 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
193 printRegName(O, Op0.getReg());
194 O << ", ";
195 printRegName(O, Op1.getReg());
196 O << ", ";
197 markup(O, Markup::Immediate) << "#" << (Is64Bit ? 64 : 32) - Op2.getImm();
198 O << ", ";
199 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1;
200 printAnnotation(O, Annot);
201 return;
202 }
203
204 // Otherwise SBFX/UBFX is the preferred form
205 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
206 printRegName(O, Op0.getReg());
207 O << ", ";
208 printRegName(O, Op1.getReg());
209 O << ", ";
210 markup(O, Markup::Immediate) << "#" << Op2.getImm();
211 O << ", ";
212 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1;
213 printAnnotation(O, Annot);
214 return;
215 }
216
217 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
218 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
219 const MCOperand &Op2 = MI->getOperand(2);
220 int ImmR = MI->getOperand(3).getImm();
221 int ImmS = MI->getOperand(4).getImm();
222
223 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
224 (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) {
225 // BFC takes precedence over its entire range, slightly differently to BFI.
226 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
227 int LSB = (BitWidth - ImmR) % BitWidth;
228 int Width = ImmS + 1;
229
230 O << "\tbfc\t";
231 printRegName(O, Op0.getReg());
232 O << ", ";
233 markup(O, Markup::Immediate) << "#" << LSB;
234 O << ", ";
235 markup(O, Markup::Immediate) << "#" << Width;
236 printAnnotation(O, Annot);
237 return;
238 } else if (ImmS < ImmR) {
239 // BFI alias
240 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
241 int LSB = (BitWidth - ImmR) % BitWidth;
242 int Width = ImmS + 1;
243
244 O << "\tbfi\t";
245 printRegName(O, Op0.getReg());
246 O << ", ";
247 printRegName(O, Op2.getReg());
248 O << ", ";
249 markup(O, Markup::Immediate) << "#" << LSB;
250 O << ", ";
251 markup(O, Markup::Immediate) << "#" << Width;
252 printAnnotation(O, Annot);
253 return;
254 }
255
256 int LSB = ImmR;
257 int Width = ImmS - ImmR + 1;
258 // Otherwise BFXIL the preferred form
259 O << "\tbfxil\t";
260 printRegName(O, Op0.getReg());
261 O << ", ";
262 printRegName(O, Op2.getReg());
263 O << ", ";
264 markup(O, Markup::Immediate) << "#" << LSB;
265 O << ", ";
266 markup(O, Markup::Immediate) << "#" << Width;
267 printAnnotation(O, Annot);
268 return;
269 }
270
271 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
272 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
273 // printed.
274 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
275 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
276 MI->getOperand(1).isExpr()) {
277 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
278 O << "\tmovz\t";
279 else
280 O << "\tmovn\t";
281
282 printRegName(O, MI->getOperand(0).getReg());
283 O << ", ";
284 {
285 WithMarkup M = markup(O, Markup::Immediate);
286 O << "#";
287 MAI.printExpr(O, *MI->getOperand(1).getExpr());
288 }
289 return;
290 }
291
292 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
293 MI->getOperand(2).isExpr()) {
294 O << "\tmovk\t";
295 printRegName(O, MI->getOperand(0).getReg());
296 O << ", ";
297 {
298 WithMarkup M = markup(O, Markup::Immediate);
299 O << "#";
300 MAI.printExpr(O, *MI->getOperand(2).getExpr());
301 }
302 return;
303 }
304
305 auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
306 int64_t SExtVal = SignExtend64(Value, RegWidth);
307 O << "\tmov\t";
308 printRegName(O, MI->getOperand(0).getReg());
309 O << ", ";
310 markup(O, Markup::Immediate) << "#" << formatImm(SExtVal);
311 if (CommentStream) {
312 // Do the opposite to that used for instruction operands.
313 if (getPrintImmHex())
314 *CommentStream << '=' << formatDec(SExtVal) << '\n';
315 else {
316 uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
317 *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
318 }
319 }
320 };
321
322 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
323 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
324 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
325 // that can represent the move is the MOV alias, and the rest get printed
326 // normally.
327 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
328 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
329 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
330 int Shift = MI->getOperand(2).getImm();
331 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
332
333 if (AArch64_AM::isMOVZMovAlias(Value, Shift,
334 Opcode == AArch64::MOVZXi ? 64 : 32)) {
335 PrintMovImm(Value, RegWidth);
336 return;
337 }
338 }
339
340 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
341 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
342 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
343 int Shift = MI->getOperand(2).getImm();
344 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
345 if (RegWidth == 32)
346 Value = Value & 0xffffffff;
347
348 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
349 PrintMovImm(Value, RegWidth);
350 return;
351 }
352 }
353
354 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
355 (MI->getOperand(1).getReg() == AArch64::XZR ||
356 MI->getOperand(1).getReg() == AArch64::WZR) &&
357 MI->getOperand(2).isImm()) {
358 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
359 uint64_t Value = AArch64_AM::decodeLogicalImmediate(
360 MI->getOperand(2).getImm(), RegWidth);
361 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
362 PrintMovImm(Value, RegWidth);
363 return;
364 }
365 }
366
367 if (Opcode == AArch64::SPACE) {
368 O << '\t' << MAI.getCommentString() << " SPACE "
369 << MI->getOperand(1).getImm();
370 printAnnotation(O, Annot);
371 return;
372 }
373
374 if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
375 printInstruction(MI, Address, STI, O);
376
377 printAnnotation(O, Annot);
378
379 if (atomicBarrierDroppedOnZero(Opcode) &&
380 (MI->getOperand(0).getReg() == AArch64::XZR ||
381 MI->getOperand(0).getReg() == AArch64::WZR)) {
382 printAnnotation(O, "acquire semantics dropped since destination is zero");
383 }
384}
385
386static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
387 bool &IsTbx) {
388 switch (Opcode) {
389 case AArch64::TBXv8i8One:
390 case AArch64::TBXv8i8Two:
391 case AArch64::TBXv8i8Three:
392 case AArch64::TBXv8i8Four:
393 IsTbx = true;
394 Layout = ".8b";
395 return true;
396 case AArch64::TBLv8i8One:
397 case AArch64::TBLv8i8Two:
398 case AArch64::TBLv8i8Three:
399 case AArch64::TBLv8i8Four:
400 IsTbx = false;
401 Layout = ".8b";
402 return true;
403 case AArch64::TBXv16i8One:
404 case AArch64::TBXv16i8Two:
405 case AArch64::TBXv16i8Three:
406 case AArch64::TBXv16i8Four:
407 IsTbx = true;
408 Layout = ".16b";
409 return true;
410 case AArch64::TBLv16i8One:
411 case AArch64::TBLv16i8Two:
412 case AArch64::TBLv16i8Three:
413 case AArch64::TBLv16i8Four:
414 IsTbx = false;
415 Layout = ".16b";
416 return true;
417 default:
418 return false;
419 }
420}
421
422struct LdStNInstrDesc {
423 unsigned Opcode;
424 const char *Mnemonic;
425 const char *Layout;
426 int ListOperand;
427 bool HasLane;
428 int NaturalOffset;
429};
430
431static const LdStNInstrDesc LdStNInstInfo[] = {
432 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
433 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
434 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
435 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
436 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
437 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
438 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
439 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
440 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
441 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
442 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
443 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
444 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
445 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
446 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
447 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
448 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
449 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
450 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
451 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
452 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
453 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
454 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
455 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
456 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
457 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
458 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
459 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
460 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
461 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
462 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
463 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
464 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
465 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
466 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
467 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
468 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
469 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
470 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
471 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
472 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
473 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
474 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
475 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
476 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
477 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
478 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
479 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
480 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
481 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
482 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
483 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
484 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
485 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
486 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
487 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
488 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
489 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
490 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
491 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
492 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
493 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
494 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
495 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
496 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
497 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
498 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
499 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
500 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
501 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
502 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
503 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
504 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
505 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
506 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
507 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
508 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
509 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
510 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
511 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
512 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
513 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
514 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
515 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
516 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
517 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
518 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
519 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
520 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
521 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
522 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
523 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
524 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
525 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
526 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
527 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
528 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
529 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
530 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
531 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
532 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
533 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
534 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
535 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
536 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
537 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
538 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
539 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
540 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
541 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
542 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
543 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
544 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
545 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
546 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
547 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
548 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
549 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
550 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
551 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
552 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
553 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
554 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
555 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
556 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
557 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
558 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
559 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
560 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
561 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
562 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
563 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
564 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
565 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
566 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
567 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
568 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
569 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
570 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
571 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
572 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
573 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
574 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
575 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
576 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
577 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
578 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
579 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
580 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
581 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
582 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
583 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
584 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
585 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
586 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
587 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
588 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
589 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
590 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
591 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
592 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
593 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
594 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
595 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
596 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
597 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
598 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
599 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
600 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
601 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
602 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
603 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
604 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
605 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
606 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
607 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
608 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
609 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
610 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
611 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
612 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
613 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
614 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
615 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
616 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
617 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
618 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
619 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
620 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
621 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
622 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
623 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
624 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
625 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
626 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
627 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
628 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
629 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
630 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
631 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
632 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
633 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
634 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
635 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
636 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
637 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
638 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
639 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
640 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
641 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
642 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
643 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
644 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
645 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
646 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
647 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
648 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
649 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
650 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
651 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
652 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
653 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
654 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
655 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
656 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
657 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
658 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
659 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
660 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
661 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
662 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
663 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
664 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
665 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
666 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
667 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
668 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
669 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
670 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
671 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
672 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
673 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
674 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
675 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
676 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
677 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
678 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
679 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
680 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
681 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
682 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
683 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
684 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
685 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
686 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
687 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
688 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
689 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
690 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
691 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
692 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
693 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
694 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
695 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
696 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
697 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
698 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
699 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
700 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
701 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
702 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
703 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
704 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
705 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
706 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
707 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
708 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
709 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
710 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
711 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
712 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
713 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
714 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
715 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
716 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
717 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
718 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
719 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
720 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
721 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
722 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
723 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
724 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
725 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
726 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
727 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
728 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
729 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
730 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
731 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
732 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
733 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
734 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
735 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
736 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
737 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
738 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
739 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
740 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
741 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
742 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
743 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
744 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
745 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
746 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
747 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
748 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
749 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
750 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
751 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
752 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
753 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
754 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
755 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
756 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
757 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
758 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
759 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
760 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
761 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
762 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
763 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
764 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
765 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
766 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
767 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
768 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
769 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
770 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
771 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
772};
773
774static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
775 for (const auto &Info : LdStNInstInfo)
776 if (Info.Opcode == Opcode)
777 return &Info;
778
779 return nullptr;
780}
781
782void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
783 StringRef Annot,
784 const MCSubtargetInfo &STI,
785 raw_ostream &O) {
786 unsigned Opcode = MI->getOpcode();
787 StringRef Layout;
788
789 bool IsTbx;
790 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
791 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
792 printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
793 O << ", ";
794
795 unsigned ListOpNum = IsTbx ? 2 : 1;
796 printVectorList(MI, ListOpNum, STI, O, "");
797
798 O << ", ";
799 printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
800 printAnnotation(O, Annot);
801 return;
802 }
803
804 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
805 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
806
807 // Now onto the operands: first a vector list with possible lane
808 // specifier. E.g. { v0 }[2]
809 int OpNum = LdStDesc->ListOperand;
810 printVectorList(MI, OpNum++, STI, O, "");
811
812 if (LdStDesc->HasLane)
813 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
814
815 // Next the address: [xN]
816 MCRegister AddrReg = MI->getOperand(OpNum++).getReg();
817 O << ", [";
818 printRegName(O, AddrReg);
819 O << ']';
820
821 // Finally, there might be a post-indexed offset.
822 if (LdStDesc->NaturalOffset != 0) {
823 MCRegister Reg = MI->getOperand(OpNum++).getReg();
824 if (Reg != AArch64::XZR) {
825 O << ", ";
826 printRegName(O, Reg);
827 } else {
828 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
829 O << ", ";
830 markup(O, Markup::Immediate) << "#" << LdStDesc->NaturalOffset;
831 }
832 }
833
834 printAnnotation(O, Annot);
835 return;
836 }
837
838 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
839}
840
844
845bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
846 const MCSubtargetInfo &STI,
847 raw_ostream &O,
848 StringRef Annot) {
849 unsigned Opcode = MI->getOpcode();
850
851#ifndef NDEBUG
852 assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
853 "Invalid opcode for RPRFM alias!");
854#endif
855
856 unsigned PRFOp = MI->getOperand(0).getImm();
857 unsigned Mask = 0x18; // 0b11000
858 if ((PRFOp & Mask) != Mask)
859 return false; // Rt != '11xxx', it's a PRFM instruction.
860
861 MCRegister Rm = MI->getOperand(2).getReg();
862
863 // "Rm" must be a 64-bit GPR for RPRFM.
864 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
865 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
866 &MRI.getRegClass(AArch64::GPR64RegClassID));
867
868 unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
869 unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
870
871 assert((SignExtend <= 1) && "sign extend should be a single bit!");
872 assert((Shift <= 1) && "Shift should be a single bit!");
873
874 unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
875
876 // encoded in "option<2>:option<0>:S:Rt<2:0>".
877 unsigned RPRFOp =
878 (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);
879
880 O << "\trprfm ";
881 if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
882 O << RPRFM->Name << ", ";
883 else
884 O << "#" << formatImm(RPRFOp) << ", ";
885 O << getRegisterName(Rm);
886 O << ", [";
887 printOperand(MI, 1, STI, O); // "Rn".
888 O << "]";
889
890 printAnnotation(O, Annot);
891
892 return true;
893}
894
895bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
896 const MCSubtargetInfo &STI,
897 raw_ostream &O) {
898#ifndef NDEBUG
899 unsigned Opcode = MI->getOpcode();
900 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
901#endif
902
903 const MCOperand &Op1 = MI->getOperand(0);
904 const MCOperand &Cn = MI->getOperand(1);
905 const MCOperand &Cm = MI->getOperand(2);
906 const MCOperand &Op2 = MI->getOperand(3);
907
908 unsigned Op1Val = Op1.getImm();
909 unsigned CnVal = Cn.getImm();
910 unsigned CmVal = Cm.getImm();
911 unsigned Op2Val = Op2.getImm();
912
913 uint16_t Encoding = Op2Val;
914 Encoding |= CmVal << 3;
915 Encoding |= CnVal << 7;
916 Encoding |= Op1Val << 11;
917
918 bool NeedsReg = false;
919 bool OptionalReg = false;
920 std::string Ins;
921 std::string Name;
922
923 if (CnVal == 7) {
924 switch (CmVal) {
925 default: return false;
926 // MLBI aliases
927 case 0: {
928 const AArch64MLBI::MLBI *MLBI =
929 AArch64MLBI::lookupMLBIByEncoding(Encoding);
930 if (!MLBI || !MLBI->haveFeatures(STI.getFeatureBits()))
931 return false;
932
933 NeedsReg = MLBI->NeedsReg;
934 Ins = "mlbi\t";
935 Name = std::string(MLBI->Name);
936 } break;
937 // Maybe IC, maybe Prediction Restriction
938 case 1:
939 switch (Op1Val) {
940 default: return false;
941 case 0: goto Search_IC;
942 case 3: goto Search_PRCTX;
943 }
944 // Prediction Restriction aliases
945 case 3: {
946 Search_PRCTX:
947 if (Op1Val != 3 || CnVal != 7 || CmVal != 3)
948 return false;
949
950 const auto Requires =
951 Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
952 if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
953 return false;
954
955 NeedsReg = true;
956 switch (Op2Val) {
957 default: return false;
958 case 4: Ins = "cfp\t"; break;
959 case 5: Ins = "dvp\t"; break;
960 case 6: Ins = "cosp\t"; break;
961 case 7: Ins = "cpp\t"; break;
962 }
963 Name = "RCTX";
964 }
965 break;
966 // IC aliases
967 case 5: {
968 Search_IC:
969 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
970 if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
971 return false;
972
973 NeedsReg = IC->NeedsReg;
974 Ins = "ic\t";
975 Name = std::string(IC->Name);
976 }
977 break;
978 // DC aliases
979 case 4: case 6: case 10: case 11: case 12: case 13: case 14:
980 {
981 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
982 if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
983 return false;
984
985 NeedsReg = true;
986 Ins = "dc\t";
987 Name = std::string(DC->Name);
988 }
989 break;
990 // AT aliases
991 case 8: case 9: {
992 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
993 if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
994 return false;
995
996 NeedsReg = true;
997 Ins = "at\t";
998 Name = std::string(AT->Name);
999 }
1000 break;
1001 // Overlaps with AT and DC
1002 case 15: {
1003 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
1004 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
1005 if (AT && AT->haveFeatures(STI.getFeatureBits())) {
1006 NeedsReg = true;
1007 Ins = "at\t";
1008 Name = std::string(AT->Name);
1009 } else if (DC && DC->haveFeatures(STI.getFeatureBits())) {
1010 NeedsReg = true;
1011 Ins = "dc\t";
1012 Name = std::string(DC->Name);
1013 } else {
1014 return false;
1015 }
1016 } break;
1017 }
1018 } else if (CnVal == 8 || CnVal == 9) {
1019 // TLBI aliases
1020 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1021 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1022 return false;
1023
1024 NeedsReg = TLBI->NeedsReg;
1025 if (STI.hasFeature(AArch64::FeatureAll) ||
1026 STI.hasFeature(AArch64::FeatureTLBID))
1027 OptionalReg = TLBI->OptionalReg;
1028 Ins = "tlbi\t";
1029 Name = std::string(TLBI->Name);
1030 } else if (CnVal == 12) {
1031 if (CmVal != 0) {
1032 // GIC aliases
1033 const AArch64GIC::GIC *GIC = AArch64GIC::lookupGICByEncoding(Encoding);
1034 if (!GIC || !GIC->haveFeatures(STI.getFeatureBits()))
1035 return false;
1036
1037 NeedsReg = true;
1038 Ins = "gic\t";
1039 Name = std::string(GIC->Name);
1040 } else {
1041 // GSB aliases
1042 const AArch64GSB::GSB *GSB = AArch64GSB::lookupGSBByEncoding(Encoding);
1043 if (!GSB || !GSB->haveFeatures(STI.getFeatureBits()))
1044 return false;
1045
1046 NeedsReg = false;
1047 Ins = "gsb\t";
1048 Name = std::string(GSB->Name);
1049 }
1050 } else
1051 return false;
1052
1053 StringRef Reg = getRegisterName(MI->getOperand(4).getReg());
1054 bool NotXZR = Reg != "xzr";
1055
1056 // If a mandatory or optional register is not specified in the TableGen
1057 // (i.e. no register operand should be present), and the register value
1058 // is not xzr/x31, then disassemble to a SYS alias instead.
1059 if (NotXZR && !NeedsReg && !OptionalReg)
1060 return false;
1061
1062 std::string Str = Ins + Name;
1063 llvm::transform(Str, Str.begin(), ::tolower);
1064
1065 O << '\t' << Str;
1066
1067 // For optional registers, don't print the value if it's xzr/x31
1068 // since this defaults to xzr/x31 if register is not specified.
1069 if (NeedsReg || (OptionalReg && NotXZR))
1070 O << ", " << Reg;
1071
1072 return true;
1073}
1074
1075bool AArch64InstPrinter::printSyslAlias(const MCInst *MI,
1076 const MCSubtargetInfo &STI,
1077 raw_ostream &O) {
1078#ifndef NDEBUG
1079 unsigned Opcode = MI->getOpcode();
1080 assert(Opcode == AArch64::SYSLxt && "Invalid opcode for SYSL alias!");
1081#endif
1082
1083 StringRef Reg = getRegisterName(MI->getOperand(0).getReg());
1084 const MCOperand &Op1 = MI->getOperand(1);
1085 const MCOperand &Cn = MI->getOperand(2);
1086 const MCOperand &Cm = MI->getOperand(3);
1087 const MCOperand &Op2 = MI->getOperand(4);
1088
1089 unsigned Op1Val = Op1.getImm();
1090 unsigned CnVal = Cn.getImm();
1091 unsigned CmVal = Cm.getImm();
1092 unsigned Op2Val = Op2.getImm();
1093
1094 uint16_t Encoding = Op2Val;
1095 Encoding |= CmVal << 3;
1096 Encoding |= CnVal << 7;
1097 Encoding |= Op1Val << 11;
1098
1099 std::string Ins;
1100 std::string Name;
1101
1102 if (CnVal == 12) {
1103 if (CmVal == 3) {
1104 // GICR aliases
1105 const AArch64GICR::GICR *GICR =
1106 AArch64GICR::lookupGICRByEncoding(Encoding);
1107 if (!GICR || !GICR->haveFeatures(STI.getFeatureBits()))
1108 return false;
1109
1110 Ins = "gicr";
1111 Name = std::string(GICR->Name);
1112 } else
1113 return false;
1114 } else
1115 return false;
1116
1117 llvm::transform(Name, Name.begin(), ::tolower);
1118
1119 O << '\t' << Ins << '\t' << Reg.str() << ", " << Name;
1120
1121 return true;
1122}
1123
1124bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
1125 const MCSubtargetInfo &STI,
1126 raw_ostream &O) {
1127#ifndef NDEBUG
1128 unsigned Opcode = MI->getOpcode();
1129 assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
1130 "Invalid opcode for SYSP alias!");
1131#endif
1132
1133 const MCOperand &Op1 = MI->getOperand(0);
1134 const MCOperand &Cn = MI->getOperand(1);
1135 const MCOperand &Cm = MI->getOperand(2);
1136 const MCOperand &Op2 = MI->getOperand(3);
1137
1138 unsigned Op1Val = Op1.getImm();
1139 unsigned CnVal = Cn.getImm();
1140 unsigned CmVal = Cm.getImm();
1141 unsigned Op2Val = Op2.getImm();
1142
1143 uint16_t Encoding = Op2Val;
1144 Encoding |= CmVal << 3;
1145 Encoding |= CnVal << 7;
1146 Encoding |= Op1Val << 11;
1147
1148 std::string Ins;
1149 std::string Name;
1150
1151 if (CnVal == 8 || CnVal == 9) {
1152 // TLBIP aliases
1153
1154 if (CnVal == 9) {
1155 if (!STI.hasFeature(AArch64::FeatureXS))
1156 return false;
1157 Encoding &= ~(1 << 7);
1158 }
1159
1160 const AArch64TLBIP::TLBIP *TLBIP =
1161 AArch64TLBIP::lookupTLBIPByEncoding(Encoding);
1162 if (!TLBIP || !TLBIP->haveFeatures(STI.getFeatureBits()))
1163 return false;
1164
1165 Ins = "tlbip\t";
1166 Name = std::string(TLBIP->Name);
1167 if (CnVal == 9)
1168 Name += "nXS";
1169 } else
1170 return false;
1171
1172 std::string Str = Ins + Name;
1173 llvm::transform(Str, Str.begin(), ::tolower);
1174
1175 O << '\t' << Str;
1176 O << ", ";
1177 if (MI->getOperand(4).getReg() == AArch64::XZR)
1178 printSyspXzrPair(MI, 4, STI, O);
1179 else
1180 printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
1181
1182 return true;
1183}
1184
1185template <int EltSize>
1186void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
1187 const MCSubtargetInfo &STI,
1188 raw_ostream &O) {
1189 const MCOperand &RegOp = MI->getOperand(OpNum);
1190 assert(RegOp.isReg() && "Unexpected operand type!");
1191
1192 printRegName(O, RegOp.getReg());
1193 switch (EltSize) {
1194 case 0:
1195 break;
1196 case 8:
1197 O << ".b";
1198 break;
1199 case 16:
1200 O << ".h";
1201 break;
1202 case 32:
1203 O << ".s";
1204 break;
1205 case 64:
1206 O << ".d";
1207 break;
1208 case 128:
1209 O << ".q";
1210 break;
1211 default:
1212 llvm_unreachable("Unsupported element size");
1213 }
1214}
1215
1216template <bool IsVertical>
1217void AArch64InstPrinter::printMatrixTileVector(const MCInst *MI, unsigned OpNum,
1218 const MCSubtargetInfo &STI,
1219 raw_ostream &O) {
1220 const MCOperand &RegOp = MI->getOperand(OpNum);
1221 assert(RegOp.isReg() && "Unexpected operand type!");
1222 StringRef RegName = getRegisterName(RegOp.getReg());
1223
1224 // Insert the horizontal/vertical flag before the suffix.
1225 StringRef Base, Suffix;
1226 std::tie(Base, Suffix) = RegName.split('.');
1227 O << Base << (IsVertical ? "v" : "h") << '.' << Suffix;
1228}
1229
1230void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
1231 const MCSubtargetInfo &STI,
1232 raw_ostream &O) {
1233 const MCOperand &RegOp = MI->getOperand(OpNum);
1234 assert(RegOp.isReg() && "Unexpected operand type!");
1235 printRegName(O, RegOp.getReg());
1236}
1237
1238void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
1239 const MCSubtargetInfo &STI,
1240 raw_ostream &O) {
1241 const MCOperand &MO = MI->getOperand(OpNum);
1242 assert(MO.isImm() && "Unexpected operand type!");
1243 unsigned svcrop = MO.getImm();
1244 const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
1245 assert(SVCR && "Unexpected SVCR operand!");
1246 O << SVCR->Name;
1247}
1248
1249void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1250 const MCSubtargetInfo &STI,
1251 raw_ostream &O) {
1252 const MCOperand &Op = MI->getOperand(OpNo);
1253 if (Op.isReg()) {
1254 printRegName(O, Op.getReg());
1255 } else if (Op.isImm()) {
1256 printImm(MI, OpNo, STI, O);
1257 } else {
1258 assert(Op.isExpr() && "unknown operand kind in printOperand");
1259 MAI.printExpr(O, *Op.getExpr());
1260 }
1261}
1262
1263void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
1264 const MCSubtargetInfo &STI,
1265 raw_ostream &O) {
1266 const MCOperand &Op = MI->getOperand(OpNo);
1267 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm());
1268}
1269
1270void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
1271 const MCSubtargetInfo &STI,
1272 raw_ostream &O) {
1273 const MCOperand &Op = MI->getOperand(OpNo);
1274 markup(O, Markup::Immediate) << format("#%#llx", Op.getImm());
1275}
1276
1277template<int Size>
1278void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
1279 const MCSubtargetInfo &STI,
1280 raw_ostream &O) {
1281 const MCOperand &Op = MI->getOperand(OpNo);
1282 if (Size == 8)
1283 markup(O, Markup::Immediate) << "#" << formatImm((signed char)Op.getImm());
1284 else if (Size == 16)
1285 markup(O, Markup::Immediate) << "#" << formatImm((signed short)Op.getImm());
1286 else
1287 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm());
1288}
1289
1290void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
1291 unsigned Imm, raw_ostream &O) {
1292 const MCOperand &Op = MI->getOperand(OpNo);
1293 if (Op.isReg()) {
1294 MCRegister Reg = Op.getReg();
1295 if (Reg == AArch64::XZR)
1296 markup(O, Markup::Immediate) << "#" << Imm;
1297 else
1298 printRegName(O, Reg);
1299 } else
1300 llvm_unreachable("unknown operand kind in printPostIncOperand64");
1301}
1302
1303void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
1304 const MCSubtargetInfo &STI,
1305 raw_ostream &O) {
1306 const MCOperand &Op = MI->getOperand(OpNo);
1307 assert(Op.isReg() && "Non-register vreg operand!");
1308 printRegName(O, Op.getReg(), AArch64::vreg);
1309}
1310
1311void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
1312 const MCSubtargetInfo &STI,
1313 raw_ostream &O) {
1314 const MCOperand &Op = MI->getOperand(OpNo);
1315 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1316 O << "c" << Op.getImm();
1317}
1318
1319void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1320 const MCSubtargetInfo &STI,
1321 raw_ostream &O) {
1322 const MCOperand &MO = MI->getOperand(OpNum);
1323 if (MO.isImm()) {
1324 unsigned Val = (MO.getImm() & 0xfff);
1325 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1326 unsigned Shift =
1327 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1328 markup(O, Markup::Immediate) << '#' << formatImm(Val);
1329 if (Shift != 0) {
1330 printShifter(MI, OpNum + 1, STI, O);
1331 if (CommentStream)
1332 *CommentStream << '=' << formatImm(Val << Shift) << '\n';
1333 }
1334 } else {
1335 assert(MO.isExpr() && "Unexpected operand type!");
1336 MAI.printExpr(O, *MO.getExpr());
1337 printShifter(MI, OpNum + 1, STI, O);
1338 }
1339}
1340
1341template <typename T>
1342void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
1343 const MCSubtargetInfo &STI,
1344 raw_ostream &O) {
1345 uint64_t Val = MI->getOperand(OpNum).getImm();
1346 WithMarkup M = markup(O, Markup::Immediate);
1347 O << "#0x";
1348 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
1349}
1350
1351void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1352 const MCSubtargetInfo &STI,
1353 raw_ostream &O) {
1354 unsigned Val = MI->getOperand(OpNum).getImm();
1355 // LSL #0 should not be printed.
1356 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
1357 AArch64_AM::getShiftValue(Val) == 0)
1358 return;
1359 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
1360 << " ";
1361 markup(O, Markup::Immediate) << "#" << AArch64_AM::getShiftValue(Val);
1362}
1363
1364void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
1365 const MCSubtargetInfo &STI,
1366 raw_ostream &O) {
1367 printRegName(O, MI->getOperand(OpNum).getReg());
1368 printShifter(MI, OpNum + 1, STI, O);
1369}
1370
1371void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1372 const MCSubtargetInfo &STI,
1373 raw_ostream &O) {
1374 printRegName(O, MI->getOperand(OpNum).getReg());
1375 printArithExtend(MI, OpNum + 1, STI, O);
1376}
1377
1378void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1379 const MCSubtargetInfo &STI,
1380 raw_ostream &O) {
1381 unsigned Val = MI->getOperand(OpNum).getImm();
1382 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1383 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1384
1385 // If the destination or first source register operand is [W]SP, print
1386 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1387 // all.
1388 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1389 MCRegister Dest = MI->getOperand(0).getReg();
1390 MCRegister Src1 = MI->getOperand(1).getReg();
1391 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1392 ExtType == AArch64_AM::UXTX) ||
1393 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1394 ExtType == AArch64_AM::UXTW) ) {
1395 if (ShiftVal != 0) {
1396 O << ", lsl ";
1397 markup(O, Markup::Immediate) << "#" << ShiftVal;
1398 }
1399 return;
1400 }
1401 }
1402 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1403 if (ShiftVal != 0) {
1404 O << " ";
1405 markup(O, Markup::Immediate) << "#" << ShiftVal;
1406 }
1407}
1408
1409void AArch64InstPrinter::printMemExtendImpl(bool SignExtend, bool DoShift,
1410 unsigned Width, char SrcRegKind,
1411 raw_ostream &O) {
1412 // sxtw, sxtx, uxtw or lsl (== uxtx)
1413 bool IsLSL = !SignExtend && SrcRegKind == 'x';
1414 if (IsLSL)
1415 O << "lsl";
1416 else
1417 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1418
1419 if (DoShift || IsLSL) {
1420 O << " ";
1421 markup(O, Markup::Immediate) << "#" << Log2_32(Width / 8);
1422 }
1423}
1424
1425void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1426 raw_ostream &O, char SrcRegKind,
1427 unsigned Width) {
1428 bool SignExtend = MI->getOperand(OpNum).getImm();
1429 bool DoShift = MI->getOperand(OpNum + 1).getImm();
1430 printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
1431}
1432
1433template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
1434void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
1435 unsigned OpNum,
1436 const MCSubtargetInfo &STI,
1437 raw_ostream &O) {
1438 printOperand(MI, OpNum, STI, O);
1439 if (Suffix == 's' || Suffix == 'd')
1440 O << '.' << Suffix;
1441 else
1442 assert(Suffix == 0 && "Unsupported suffix size");
1443
1444 bool DoShift = ExtWidth != 8;
1445 if (SignExtend || DoShift || SrcRegKind == 'w') {
1446 O << ", ";
1447 printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1448 }
1449}
1450
1451template <int EltSize>
1452void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
1453 unsigned OpNum,
1454 const MCSubtargetInfo &STI,
1455 raw_ostream &O) {
1456 MCRegister Reg = MI->getOperand(OpNum).getReg();
1457 if (Reg < AArch64::PN0 || Reg > AArch64::PN15)
1458 llvm_unreachable("Unsupported predicate-as-counter register");
1459 O << "pn" << Reg - AArch64::PN0;
1460
1461 switch (EltSize) {
1462 case 0:
1463 break;
1464 case 8:
1465 O << ".b";
1466 break;
1467 case 16:
1468 O << ".h";
1469 break;
1470 case 32:
1471 O << ".s";
1472 break;
1473 case 64:
1474 O << ".d";
1475 break;
1476 default:
1477 llvm_unreachable("Unsupported element size");
1478 }
1479}
1480
1481void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1482 const MCSubtargetInfo &STI,
1483 raw_ostream &O) {
1484 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1485 O << AArch64CC::getCondCodeName(CC);
1486}
1487
1488void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1489 const MCSubtargetInfo &STI,
1490 raw_ostream &O) {
1491 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1492 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1493}
1494
1495void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1496 const MCSubtargetInfo &STI,
1497 raw_ostream &O) {
1498 O << '[';
1499 printRegName(O, MI->getOperand(OpNum).getReg());
1500 O << ']';
1501}
1502
1503template <int Scale>
1504void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1505 const MCSubtargetInfo &STI,
1506 raw_ostream &O) {
1507 markup(O, Markup::Immediate)
1508 << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1509}
1510
1511template <int Scale, int Offset>
1512void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
1513 const MCSubtargetInfo &STI,
1514 raw_ostream &O) {
1515 unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
1516 O << formatImm(FirstImm);
1517 O << ":" << formatImm(FirstImm + Offset);
1518}
1519
1520void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1521 unsigned Scale, raw_ostream &O) {
1522 const MCOperand MO = MI->getOperand(OpNum);
1523 if (MO.isImm()) {
1524 markup(O, Markup::Immediate) << '#' << formatImm(MO.getImm() * Scale);
1525 } else {
1526 assert(MO.isExpr() && "Unexpected operand type!");
1527 MAI.printExpr(O, *MO.getExpr());
1528 }
1529}
1530
1531void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1532 unsigned Scale, raw_ostream &O) {
1533 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1534 O << '[';
1535 printRegName(O, MI->getOperand(OpNum).getReg());
1536 if (MO1.isImm()) {
1537 O << ", ";
1538 markup(O, Markup::Immediate) << "#" << formatImm(MO1.getImm() * Scale);
1539 } else {
1540 assert(MO1.isExpr() && "Unexpected operand type!");
1541 O << ", ";
1542 MAI.printExpr(O, *MO1.getExpr());
1543 }
1544 O << ']';
1545}
1546
1547void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
1548 const MCSubtargetInfo &STI,
1549 raw_ostream &O) {
1550 unsigned prfop = MI->getOperand(OpNum).getImm();
1551 if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
1552 O << PRFM->Name;
1553 return;
1554 }
1555
1556 O << '#' << formatImm(prfop);
1557}
1558
1559template <bool IsSVEPrefetch>
1560void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1561 const MCSubtargetInfo &STI,
1562 raw_ostream &O) {
1563 unsigned prfop = MI->getOperand(OpNum).getImm();
1564 if (IsSVEPrefetch) {
1565 if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1566 O << PRFM->Name;
1567 return;
1568 }
1569 } else {
1570 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1571 if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
1572 O << PRFM->Name;
1573 return;
1574 }
1575 }
1576
1577 markup(O, Markup::Immediate) << '#' << formatImm(prfop);
1578}
1579
1580void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1581 const MCSubtargetInfo &STI,
1582 raw_ostream &O) {
1583 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1584 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1585 if (PSB)
1586 O << PSB->Name;
1587 else
1588 markup(O, Markup::Immediate) << '#' << formatImm(psbhintop);
1589}
1590
1591void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1592 const MCSubtargetInfo &STI,
1593 raw_ostream &O) {
1594 unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
1595 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1596 if (BTI)
1597 O << BTI->Name;
1598 else
1599 markup(O, Markup::Immediate) << '#' << formatImm(btihintop);
1600}
1601
1602void AArch64InstPrinter::printCMHPriorityHintOp(const MCInst *MI,
1603 unsigned OpNum,
1604 const MCSubtargetInfo &STI,
1605 raw_ostream &O) {
1606 unsigned priorityhint_op = MI->getOperand(OpNum).getImm();
1607 auto PHint =
1608 AArch64CMHPriorityHint::lookupCMHPriorityHintByEncoding(priorityhint_op);
1609 if (PHint)
1610 O << PHint->Name;
1611}
1612
1613void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1614 const MCSubtargetInfo &STI,
1615 raw_ostream &O) {
1616 const MCOperand &MO = MI->getOperand(OpNum);
1617 float FPImm = MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm())
1618 : AArch64_AM::getFPImmFloat(MO.getImm());
1619
1620 // 8 decimal places are enough to perfectly represent permitted floats.
1621 markup(O, Markup::Immediate) << format("#%.8f", FPImm);
1622}
1623
1624static MCRegister getNextVectorRegister(MCRegister Reg, unsigned Stride = 1) {
1625 while (Stride--) {
1626 switch (Reg.id()) {
1627 default:
1628 llvm_unreachable("Vector register expected!");
1629 case AArch64::Q0: Reg = AArch64::Q1; break;
1630 case AArch64::Q1: Reg = AArch64::Q2; break;
1631 case AArch64::Q2: Reg = AArch64::Q3; break;
1632 case AArch64::Q3: Reg = AArch64::Q4; break;
1633 case AArch64::Q4: Reg = AArch64::Q5; break;
1634 case AArch64::Q5: Reg = AArch64::Q6; break;
1635 case AArch64::Q6: Reg = AArch64::Q7; break;
1636 case AArch64::Q7: Reg = AArch64::Q8; break;
1637 case AArch64::Q8: Reg = AArch64::Q9; break;
1638 case AArch64::Q9: Reg = AArch64::Q10; break;
1639 case AArch64::Q10: Reg = AArch64::Q11; break;
1640 case AArch64::Q11: Reg = AArch64::Q12; break;
1641 case AArch64::Q12: Reg = AArch64::Q13; break;
1642 case AArch64::Q13: Reg = AArch64::Q14; break;
1643 case AArch64::Q14: Reg = AArch64::Q15; break;
1644 case AArch64::Q15: Reg = AArch64::Q16; break;
1645 case AArch64::Q16: Reg = AArch64::Q17; break;
1646 case AArch64::Q17: Reg = AArch64::Q18; break;
1647 case AArch64::Q18: Reg = AArch64::Q19; break;
1648 case AArch64::Q19: Reg = AArch64::Q20; break;
1649 case AArch64::Q20: Reg = AArch64::Q21; break;
1650 case AArch64::Q21: Reg = AArch64::Q22; break;
1651 case AArch64::Q22: Reg = AArch64::Q23; break;
1652 case AArch64::Q23: Reg = AArch64::Q24; break;
1653 case AArch64::Q24: Reg = AArch64::Q25; break;
1654 case AArch64::Q25: Reg = AArch64::Q26; break;
1655 case AArch64::Q26: Reg = AArch64::Q27; break;
1656 case AArch64::Q27: Reg = AArch64::Q28; break;
1657 case AArch64::Q28: Reg = AArch64::Q29; break;
1658 case AArch64::Q29: Reg = AArch64::Q30; break;
1659 case AArch64::Q30: Reg = AArch64::Q31; break;
1660 // Vector lists can wrap around.
1661 case AArch64::Q31:
1662 Reg = AArch64::Q0;
1663 break;
1664 case AArch64::Z0: Reg = AArch64::Z1; break;
1665 case AArch64::Z1: Reg = AArch64::Z2; break;
1666 case AArch64::Z2: Reg = AArch64::Z3; break;
1667 case AArch64::Z3: Reg = AArch64::Z4; break;
1668 case AArch64::Z4: Reg = AArch64::Z5; break;
1669 case AArch64::Z5: Reg = AArch64::Z6; break;
1670 case AArch64::Z6: Reg = AArch64::Z7; break;
1671 case AArch64::Z7: Reg = AArch64::Z8; break;
1672 case AArch64::Z8: Reg = AArch64::Z9; break;
1673 case AArch64::Z9: Reg = AArch64::Z10; break;
1674 case AArch64::Z10: Reg = AArch64::Z11; break;
1675 case AArch64::Z11: Reg = AArch64::Z12; break;
1676 case AArch64::Z12: Reg = AArch64::Z13; break;
1677 case AArch64::Z13: Reg = AArch64::Z14; break;
1678 case AArch64::Z14: Reg = AArch64::Z15; break;
1679 case AArch64::Z15: Reg = AArch64::Z16; break;
1680 case AArch64::Z16: Reg = AArch64::Z17; break;
1681 case AArch64::Z17: Reg = AArch64::Z18; break;
1682 case AArch64::Z18: Reg = AArch64::Z19; break;
1683 case AArch64::Z19: Reg = AArch64::Z20; break;
1684 case AArch64::Z20: Reg = AArch64::Z21; break;
1685 case AArch64::Z21: Reg = AArch64::Z22; break;
1686 case AArch64::Z22: Reg = AArch64::Z23; break;
1687 case AArch64::Z23: Reg = AArch64::Z24; break;
1688 case AArch64::Z24: Reg = AArch64::Z25; break;
1689 case AArch64::Z25: Reg = AArch64::Z26; break;
1690 case AArch64::Z26: Reg = AArch64::Z27; break;
1691 case AArch64::Z27: Reg = AArch64::Z28; break;
1692 case AArch64::Z28: Reg = AArch64::Z29; break;
1693 case AArch64::Z29: Reg = AArch64::Z30; break;
1694 case AArch64::Z30: Reg = AArch64::Z31; break;
1695 // Vector lists can wrap around.
1696 case AArch64::Z31:
1697 Reg = AArch64::Z0;
1698 break;
1699 case AArch64::P0: Reg = AArch64::P1; break;
1700 case AArch64::P1: Reg = AArch64::P2; break;
1701 case AArch64::P2: Reg = AArch64::P3; break;
1702 case AArch64::P3: Reg = AArch64::P4; break;
1703 case AArch64::P4: Reg = AArch64::P5; break;
1704 case AArch64::P5: Reg = AArch64::P6; break;
1705 case AArch64::P6: Reg = AArch64::P7; break;
1706 case AArch64::P7: Reg = AArch64::P8; break;
1707 case AArch64::P8: Reg = AArch64::P9; break;
1708 case AArch64::P9: Reg = AArch64::P10; break;
1709 case AArch64::P10: Reg = AArch64::P11; break;
1710 case AArch64::P11: Reg = AArch64::P12; break;
1711 case AArch64::P12: Reg = AArch64::P13; break;
1712 case AArch64::P13: Reg = AArch64::P14; break;
1713 case AArch64::P14: Reg = AArch64::P15; break;
1714 // Vector lists can wrap around.
1715 case AArch64::P15: Reg = AArch64::P0; break;
1716 }
1717 }
1718 return Reg;
1719}
1720
1721template<unsigned size>
1722void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1723 unsigned OpNum,
1724 const MCSubtargetInfo &STI,
1725 raw_ostream &O) {
1726 static_assert(size == 64 || size == 32,
1727 "Template parameter must be either 32 or 64");
1728 MCRegister Reg = MI->getOperand(OpNum).getReg();
1729
1730 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1731 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1732
1733 MCRegister Even = MRI.getSubReg(Reg, Sube);
1734 MCRegister Odd = MRI.getSubReg(Reg, Subo);
1735 printRegName(O, Even);
1736 O << ", ";
1737 printRegName(O, Odd);
1738}
1739
1740void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
1741 const MCSubtargetInfo &STI,
1742 raw_ostream &O) {
1743 unsigned MaxRegs = 8;
1744 unsigned RegMask = MI->getOperand(OpNum).getImm();
1745
1746 unsigned NumRegs = 0;
1747 for (unsigned I = 0; I < MaxRegs; ++I)
1748 if ((RegMask & (1 << I)) != 0)
1749 ++NumRegs;
1750
1751 O << "{";
1752 unsigned Printed = 0;
1753 for (unsigned I = 0; I < MaxRegs; ++I) {
1754 unsigned Reg = RegMask & (1 << I);
1755 if (Reg == 0)
1756 continue;
1757 printRegName(O, AArch64::ZAD0 + I);
1758 if (Printed + 1 != NumRegs)
1759 O << ", ";
1760 ++Printed;
1761 }
1762 O << "}";
1763}
1764
1765void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1766 const MCSubtargetInfo &STI,
1767 raw_ostream &O,
1768 StringRef LayoutSuffix) {
1769 MCRegister Reg = MI->getOperand(OpNum).getReg();
1770
1771 O << "{ ";
1772
1773 // Work out how many registers there are in the list (if there is an actual
1774 // list).
1775 unsigned NumRegs = 1;
1776 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1777 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1778 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
1779 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) ||
1780 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1781 NumRegs = 2;
1782 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1783 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1784 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1785 NumRegs = 3;
1786 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1787 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1788 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
1789 MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1790 NumRegs = 4;
1791
1792 unsigned Stride = 1;
1793 if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1794 Stride = 8;
1795 else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1796 Stride = 4;
1797
1798 // Now forget about the list and find out what the first register is.
1799 if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1800 Reg = FirstReg;
1801 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1802 Reg = FirstReg;
1803 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1804 Reg = FirstReg;
1805 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
1806 Reg = FirstReg;
1807
1808 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1809 // printing (otherwise getRegisterName fails).
1810 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1811 const MCRegisterClass &FPR128RC =
1812 MRI.getRegClass(AArch64::FPR128RegClassID);
1813 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1814 }
1815
1816 if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1817 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
1818 NumRegs > 1 && Stride == 1 &&
1819 // Do not print the range when the last register is lower than the first.
1820 // Because it is a wrap-around register.
1821 Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
1822 printRegName(O, Reg);
1823 O << LayoutSuffix;
1824 if (NumRegs > 1) {
1825 // Set of two sve registers should be separated by ','
1826 StringRef split_char = NumRegs == 2 ? ", " : " - ";
1827 O << split_char;
1828 printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
1829 O << LayoutSuffix;
1830 }
1831 } else {
1832 for (unsigned i = 0; i < NumRegs;
1833 ++i, Reg = getNextVectorRegister(Reg, Stride)) {
1834 // wrap-around sve register
1835 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1836 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
1837 printRegName(O, Reg);
1838 else
1839 printRegName(O, Reg, AArch64::vreg);
1840 O << LayoutSuffix;
1841 if (i + 1 != NumRegs)
1842 O << ", ";
1843 }
1844 }
1845 O << " }";
1846}
1847
1848void
1849AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1850 unsigned OpNum,
1851 const MCSubtargetInfo &STI,
1852 raw_ostream &O) {
1853 printVectorList(MI, OpNum, STI, O, "");
1854}
1855
1856template <unsigned NumLanes, char LaneKind>
1857void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1858 const MCSubtargetInfo &STI,
1859 raw_ostream &O) {
1860 if (LaneKind == 0) {
1861 printVectorList(MI, OpNum, STI, O, "");
1862 return;
1863 }
1864 std::string Suffix(".");
1865 if (NumLanes)
1866 Suffix += itostr(NumLanes) + LaneKind;
1867 else
1868 Suffix += LaneKind;
1869
1870 printVectorList(MI, OpNum, STI, O, Suffix);
1871}
1872
1873template <unsigned Scale>
1874void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1875 const MCSubtargetInfo &STI,
1876 raw_ostream &O) {
1877 O << "[" << Scale * MI->getOperand(OpNum).getImm() << "]";
1878}
1879
1880template <unsigned Scale>
1881void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
1882 const MCSubtargetInfo &STI,
1883 raw_ostream &O) {
1884 O << Scale * MI->getOperand(OpNum).getImm();
1885}
1886
1887void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
1888 unsigned OpNum,
1889 const MCSubtargetInfo &STI,
1890 raw_ostream &O) {
1891 // Do not print the numeric target address when symbolizing.
1892 if (SymbolizeOperands)
1893 return;
1894
1895 const MCOperand &Op = MI->getOperand(OpNum);
1896
1897 // If the label has already been resolved to an immediate offset (say, when
1898 // we're running the disassembler), just print the immediate.
1899 if (Op.isImm()) {
1900 int64_t Offset = Op.getImm() * 4;
1901 if (PrintBranchImmAsAddress)
1902 markup(O, Markup::Target) << formatHex(Address + Offset);
1903 else
1904 markup(O, Markup::Immediate) << "#" << formatImm(Offset);
1905 return;
1906 }
1907
1908 // If the branch target is simply an address then print it in hex.
1909 const MCConstantExpr *BranchTarget =
1910 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1911 int64_t TargetAddress;
1912 if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) {
1913 markup(O, Markup::Target) << formatHex((uint64_t)TargetAddress);
1914 } else {
1915 // Otherwise, just print the expression.
1916 MAI.printExpr(O, *MI->getOperand(OpNum).getExpr());
1917 }
1918}
1919
1920void AArch64InstPrinter::printAdrAdrpLabel(const MCInst *MI, uint64_t Address,
1921 unsigned OpNum,
1922 const MCSubtargetInfo &STI,
1923 raw_ostream &O) {
1924 // Do not print the numeric target address when symbolizing.
1925 // However, do print for ADRP, as this is typically used together with an ADD
1926 // or an immediate-offset ldr/str and the label is likely at the wrong point.
1927 if (SymbolizeOperands && MI->getOpcode() != AArch64::ADRP)
1928 return;
1929
1930 const MCOperand &Op = MI->getOperand(OpNum);
1931
1932 // If the label has already been resolved to an immediate offset (say, when
1933 // we're running the disassembler), just print the immediate.
1934 if (Op.isImm()) {
1935 int64_t Offset = Op.getImm();
1936 if (MI->getOpcode() == AArch64::ADRP) {
1937 Offset = Offset * 4096;
1938 Address = Address & -4096;
1939 }
1940 WithMarkup M = markup(O, Markup::Immediate);
1941 if (PrintBranchImmAsAddress)
1942 markup(O, Markup::Target) << formatHex(Address + Offset);
1943 else
1944 markup(O, Markup::Immediate) << "#" << Offset;
1945 return;
1946 }
1947
1948 // Otherwise, just print the expression.
1949 MAI.printExpr(O, *MI->getOperand(OpNum).getExpr());
1950}
1951
1952void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1953 const MCSubtargetInfo &STI,
1954 raw_ostream &O) {
1955 unsigned Val = MI->getOperand(OpNo).getImm();
1956 unsigned Opcode = MI->getOpcode();
1957
1958 StringRef Name;
1959 if (Opcode == AArch64::ISB) {
1960 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1961 Name = ISB ? ISB->Name : "";
1962 } else if (Opcode == AArch64::TSB) {
1963 auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1964 Name = TSB ? TSB->Name : "";
1965 } else {
1966 auto DB = AArch64DB::lookupDBByEncoding(Val);
1967 Name = DB ? DB->Name : "";
1968 }
1969 if (!Name.empty())
1970 O << Name;
1971 else
1972 markup(O, Markup::Immediate) << "#" << Val;
1973}
1974
1975void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
1976 const MCSubtargetInfo &STI,
1977 raw_ostream &O) {
1978 unsigned Val = MI->getOperand(OpNo).getImm();
1979 assert(MI->getOpcode() == AArch64::DSBnXS);
1980
1981 StringRef Name;
1982 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1983 Name = DB ? DB->Name : "";
1984
1985 if (!Name.empty())
1986 O << Name;
1987 else
1988 markup(O, Markup::Immediate) << "#" << Val;
1989}
1990
1991static bool isValidSysReg(const AArch64SysReg::SysReg &Reg, bool Read,
1992 const MCSubtargetInfo &STI) {
1993 return (Read ? Reg.Readable : Reg.Writeable) &&
1994 Reg.haveFeatures(STI.getFeatureBits());
1995}
1996
1997// Looks up a system register either by encoding. Some system
1998// registers share the same encoding between different architectures,
1999// to work around this tablegen will return a range of registers with the same
2000// encodings. We need to check each register in the range to see if it valid.
2001static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read,
2002 const MCSubtargetInfo &STI) {
2003 auto Range = AArch64SysReg::lookupSysRegByEncoding(Val);
2004 for (auto &Reg : Range) {
2005 if (isValidSysReg(Reg, Read, STI))
2006 return &Reg;
2007 }
2008
2009 return nullptr;
2010}
2011
2012void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
2013 const MCSubtargetInfo &STI,
2014 raw_ostream &O) {
2015 unsigned Val = MI->getOperand(OpNo).getImm();
2016
2017 // Horrible hack for the one register that has identical encodings but
2018 // different names in MSR and MRS. Because of this, one of MRS and MSR is
2019 // going to get the wrong entry
2020 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
2021 O << "DBGDTRRX_EL0";
2022 return;
2023 }
2024
2025 // Horrible hack for two different registers having the same encoding.
2026 if (Val == AArch64SysReg::TRCEXTINSELR) {
2027 O << "TRCEXTINSELR";
2028 return;
2029 }
2030
2031 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
2032
2033 if (Reg)
2034 O << Reg->Name;
2035 else
2036 O << AArch64SysReg::genericRegisterString(Val);
2037}
2038
2039void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
2040 const MCSubtargetInfo &STI,
2041 raw_ostream &O) {
2042 unsigned Val = MI->getOperand(OpNo).getImm();
2043
2044 // Horrible hack for the one register that has identical encodings but
2045 // different names in MSR and MRS. Because of this, one of MRS and MSR is
2046 // going to get the wrong entry
2047 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
2048 O << "DBGDTRTX_EL0";
2049 return;
2050 }
2051
2052 // Horrible hack for two different registers having the same encoding.
2053 if (Val == AArch64SysReg::TRCEXTINSELR) {
2054 O << "TRCEXTINSELR";
2055 return;
2056 }
2057
2058 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
2059
2060 if (Reg)
2061 O << Reg->Name;
2062 else
2063 O << AArch64SysReg::genericRegisterString(Val);
2064}
2065
2066void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
2067 const MCSubtargetInfo &STI,
2068 raw_ostream &O) {
2069 unsigned Val = MI->getOperand(OpNo).getImm();
2070
2071 auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val);
2072 auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val);
2073 if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits()))
2074 O << PStateImm15->Name;
2075 else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits()))
2076 O << PStateImm1->Name;
2077 else
2078 O << "#" << formatImm(Val);
2079}
2080
2081void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
2082 const MCSubtargetInfo &STI,
2083 raw_ostream &O) {
2084 unsigned RawVal = MI->getOperand(OpNo).getImm();
2085 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
2086 markup(O, Markup::Immediate) << format("#%#016llx", Val);
2087}
2088
2089template<int64_t Angle, int64_t Remainder>
2090void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
2091 const MCSubtargetInfo &STI,
2092 raw_ostream &O) {
2093 unsigned Val = MI->getOperand(OpNo).getImm();
2094 markup(O, Markup::Immediate) << "#" << (Val * Angle) + Remainder;
2095}
2096
2097void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
2098 const MCSubtargetInfo &STI,
2099 raw_ostream &O) {
2100 unsigned Val = MI->getOperand(OpNum).getImm();
2101 if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
2102 O << Pat->Name;
2103 else
2104 markup(O, Markup::Immediate) << '#' << formatImm(Val);
2105}
2106
2107void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
2108 unsigned OpNum,
2109 const MCSubtargetInfo &STI,
2110 raw_ostream &O) {
2111 unsigned Val = MI->getOperand(OpNum).getImm();
2112 // Pattern has only 1 bit
2113 if (Val > 1)
2114 llvm_unreachable("Invalid vector length specifier");
2115 if (auto Pat =
2116 AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
2117 O << Pat->Name;
2118 else
2119 llvm_unreachable("Invalid vector length specifier");
2120}
2121
2122template <char suffix>
2123void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
2124 const MCSubtargetInfo &STI,
2125 raw_ostream &O) {
2126 switch (suffix) {
2127 case 0:
2128 case 'b':
2129 case 'h':
2130 case 's':
2131 case 'd':
2132 case 'q':
2133 break;
2134 default: llvm_unreachable("Invalid kind specifier.");
2135 }
2136
2137 MCRegister Reg = MI->getOperand(OpNum).getReg();
2138 printRegName(O, Reg);
2139 if (suffix != 0)
2140 O << '.' << suffix;
2141}
2142
2143template <typename T>
2144void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
2145 std::make_unsigned_t<T> HexValue = Value;
2146
2147 if (getPrintImmHex())
2148 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)HexValue);
2149 else
2150 markup(O, Markup::Immediate) << '#' << formatDec(Value);
2151
2152 if (CommentStream) {
2153 // Do the opposite to that used for instruction operands.
2154 if (getPrintImmHex())
2155 *CommentStream << '=' << formatDec(HexValue) << '\n';
2156 else
2157 *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
2158 }
2159}
2160
2161template <typename T>
2162void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
2163 const MCSubtargetInfo &STI,
2164 raw_ostream &O) {
2165 unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
2166 unsigned Shift = MI->getOperand(OpNum + 1).getImm();
2167 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2168 "Unexpected shift type!");
2169
2170 // #0 lsl #8 is never pretty printed
2171 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
2172 markup(O, Markup::Immediate) << '#' << formatImm(UnscaledVal);
2173 printShifter(MI, OpNum + 1, STI, O);
2174 return;
2175 }
2176
2177 T Val;
2178 if (std::is_signed<T>())
2179 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2180 else
2181 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2182
2183 printImmSVE(Val, O);
2184}
2185
2186template <typename T>
2187void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
2188 const MCSubtargetInfo &STI,
2189 raw_ostream &O) {
2190 typedef std::make_signed_t<T> SignedT;
2191 typedef std::make_unsigned_t<T> UnsignedT;
2192
2193 uint64_t Val = MI->getOperand(OpNum).getImm();
2194 UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
2195
2196 // Prefer the default format for 16bit values, hex otherwise.
2197 if ((int16_t)PrintVal == (SignedT)PrintVal)
2198 printImmSVE((T)PrintVal, O);
2199 else if ((uint16_t)PrintVal == PrintVal)
2200 printImmSVE(PrintVal, O);
2201 else
2202 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)PrintVal);
2203}
2204
2205template <int Width>
2206void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
2207 const MCSubtargetInfo &STI,
2208 raw_ostream &O) {
2209 unsigned Base;
2210 switch (Width) {
2211 case 8: Base = AArch64::B0; break;
2212 case 16: Base = AArch64::H0; break;
2213 case 32: Base = AArch64::S0; break;
2214 case 64: Base = AArch64::D0; break;
2215 case 128: Base = AArch64::Q0; break;
2216 default:
2217 llvm_unreachable("Unsupported width");
2218 }
2219 MCRegister Reg = MI->getOperand(OpNum).getReg();
2220 printRegName(O, Reg - AArch64::Z0 + Base);
2221}
2222
2223template <unsigned ImmIs0, unsigned ImmIs1>
2224void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
2225 const MCSubtargetInfo &STI,
2226 raw_ostream &O) {
2227 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
2228 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
2229 unsigned Val = MI->getOperand(OpNum).getImm();
2230 markup(O, Markup::Immediate)
2231 << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
2232}
2233
2234void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
2235 const MCSubtargetInfo &STI,
2236 raw_ostream &O) {
2237 MCRegister Reg = MI->getOperand(OpNum).getReg();
2238 printRegName(O, getWRegFromXReg(Reg));
2239}
2240
2241void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
2242 const MCSubtargetInfo &STI,
2243 raw_ostream &O) {
2244 MCRegister Reg = MI->getOperand(OpNum).getReg();
2245 printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
2246}
2247
2248void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
2249 const MCSubtargetInfo &STI,
2250 raw_ostream &O) {
2251 MCRegister Reg = MI->getOperand(OpNum).getReg();
2252 assert(Reg == AArch64::XZR &&
2253 "MC representation of SyspXzrPair should be XZR");
2254 O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
2255}
2256
2257void AArch64InstPrinter::printPHintOp(const MCInst *MI, unsigned OpNum,
2258 const MCSubtargetInfo &STI,
2259 raw_ostream &O) {
2260 unsigned Op = MI->getOperand(OpNum).getImm();
2261 auto PH = AArch64PHint::lookupPHintByEncoding(Op);
2262 if (PH)
2263 O << PH->Name;
2264 else
2265 markup(O, Markup::Immediate) << '#' << formatImm(Op);
2266}
getNextVectorRegister
static MCRegister getNextVectorRegister(MCRegister Reg, unsigned Stride=1)
Definition AArch64InstPrinter.cpp:1624
lookupSysReg
static const AArch64SysReg::SysReg * lookupSysReg(unsigned Val, bool Read, const MCSubtargetInfo &STI)
Definition AArch64InstPrinter.cpp:2001
getLdStNInstrDesc
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
Definition AArch64InstPrinter.cpp:774
LdStNInstInfo
static const LdStNInstrDesc LdStNInstInfo[]
Definition AArch64InstPrinter.cpp:431
isValidSysReg
static bool isValidSysReg(const AArch64SysReg::SysReg &Reg, bool Read, const MCSubtargetInfo &STI)
Definition AArch64InstPrinter.cpp:1991
isTblTbxInstruction
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
Definition AArch64InstPrinter.cpp:386
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Info
Analysis containing CSE Info
Definition CSEInfo.cpp:27
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
RegName
#define RegName(no)
I
#define I(x, y, z)
Definition MD5.cpp:58
Reg
Register Reg
Definition MachineSink.cpp:2117
T
#define T
Definition Mips16ISelLowering.cpp:353
Range
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
StringExtras.h
This file contains some functions that are useful when dealing with strings.
llvm::AArch64AppleInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition AArch64InstPrinter.cpp:782
llvm::AArch64AppleInstPrinter::AArch64AppleInstPrinter
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition AArch64InstPrinter.cpp:48
llvm::AArch64AppleInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64AppleInstPrinter::getRegName
StringRef getRegName(MCRegister Reg) const override
Definition AArch64InstPrinter.cpp:841
llvm::AArch64InstPrinter::printMRSSystemRegister
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2012
llvm::AArch64InstPrinter::printImm
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1263
llvm::AArch64InstPrinter::printAlignedLabel
void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1887
llvm::AArch64InstPrinter::printAMIndexedWB
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1531
llvm::AArch64InstPrinter::printMatrix
void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1186
llvm::AArch64InstPrinter::printAdrAdrpLabel
void printAdrAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1920
llvm::AArch64InstPrinter::printPrefetchOp
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1560
llvm::AArch64InstPrinter::printZPRasFPR
void printZPRasFPR(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2206
llvm::AArch64InstPrinter::printInstruction
virtual void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printAMNoIndex
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1495
llvm::AArch64InstPrinter::printUImm12Offset
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1520
llvm::AArch64InstPrinter::printSVCROp
void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1238
llvm::AArch64InstPrinter::AArch64InstPrinter
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition AArch64InstPrinter.cpp:43
llvm::AArch64InstPrinter::printCondCode
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1481
llvm::AArch64InstPrinter::printBarriernXSOption
void printBarriernXSOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1975
llvm::AArch64InstPrinter::printSystemPStateField
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2066
llvm::AArch64InstPrinter::printShifter
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1351
llvm::AArch64InstPrinter::printPSBHintOp
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1580
llvm::AArch64InstPrinter::printCMHPriorityHintOp
void printCMHPriorityHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1602
llvm::AArch64InstPrinter::printGPR64x8
void printGPR64x8(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2241
llvm::AArch64InstPrinter::printSIMDType10Operand
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2081
llvm::AArch64InstPrinter::getRegName
virtual StringRef getRegName(MCRegister Reg) const
Definition AArch64InstPrinter.cpp:70
llvm::AArch64InstPrinter::printMemExtend
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
Definition AArch64InstPrinter.cpp:1425
llvm::AArch64InstPrinter::printMatrixTileVector
void printMatrixTileVector(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1217
llvm::AArch64InstPrinter::printSysAlias
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:895
llvm::AArch64InstPrinter::printSysCROperand
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1311
llvm::AArch64InstPrinter::applyTargetSpecificCLOption
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
Definition AArch64InstPrinter.cpp:53
llvm::AArch64InstPrinter::printRPRFMOperand
void printRPRFMOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1547
llvm::AArch64InstPrinter::printVectorList
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
Definition AArch64InstPrinter.cpp:1765
llvm::AArch64InstPrinter::printImplicitlyTypedVectorList
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
Definition AArch64InstPrinter.cpp:1849
llvm::AArch64InstPrinter::printGPRSeqPairsClassOperand
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1722
llvm::AArch64InstPrinter::printExtendedRegister
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1371
llvm::AArch64InstPrinter::printRangePrefetchAlias
bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O, StringRef Annot)
Definition AArch64InstPrinter.cpp:845
llvm::AArch64InstPrinter::printMSRSystemRegister
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2039
llvm::AArch64InstPrinter::printSVERegOp
void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2123
llvm::AArch64InstPrinter::printPHintOp
void printPHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2257
llvm::AArch64InstPrinter::printMatrixTile
void printMatrixTile(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1230
llvm::AArch64InstPrinter::printFPImmOperand
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1613
llvm::AArch64InstPrinter::printMemExtendImpl
void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1409
llvm::AArch64InstPrinter::printSVEVecLenSpecifier
void printSVEVecLenSpecifier(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2107
llvm::AArch64InstPrinter::printBTIHintOp
void printBTIHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1591
llvm::AArch64InstPrinter::printSyspXzrPair
void printSyspXzrPair(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2248
llvm::AArch64InstPrinter::printArithExtend
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1378
llvm::AArch64InstPrinter::printOperand
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1249
llvm::AArch64InstPrinter::printAliasInstr
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printImmScale
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1504
llvm::AArch64InstPrinter::printSImm
void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1278
llvm::AArch64InstPrinter::printAddSubImm
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1319
llvm::AArch64InstPrinter::printImmSVE
void printImmSVE(T Value, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2144
llvm::AArch64InstPrinter::printShiftedRegister
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1364
llvm::AArch64InstPrinter::printComplexRotationOp
void printComplexRotationOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2090
llvm::AArch64InstPrinter::printGPR64as32
void printGPR64as32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2234
llvm::AArch64InstPrinter::printSyspAlias
bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1124
llvm::AArch64InstPrinter::printRegName
void printRegName(raw_ostream &OS, MCRegister Reg) override
Print the assembler register name.
Definition AArch64InstPrinter.cpp:61
llvm::AArch64InstPrinter::printMatrixTileList
void printMatrixTileList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1740
llvm::AArch64InstPrinter::printMatrixIndex
void printMatrixIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1881
llvm::AArch64InstPrinter::printImmRangeScale
void printImmRangeScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1512
llvm::AArch64InstPrinter::printTypedVectorList
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1857
llvm::AArch64InstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition AArch64InstPrinter.cpp:74
llvm::AArch64InstPrinter::printLogicalImm
void printLogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1342
llvm::AArch64InstPrinter::printSVEPattern
void printSVEPattern(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2097
llvm::AArch64InstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64InstPrinter::printVRegOperand
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1303
llvm::AArch64InstPrinter::printPostIncOperand
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1290
llvm::AArch64InstPrinter::printPredicateAsCounter
void printPredicateAsCounter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1452
llvm::AArch64InstPrinter::printVectorIndex
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1874
llvm::AArch64InstPrinter::printSyslAlias
bool printSyslAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1075
llvm::AArch64InstPrinter::printImm8OptLsl
void printImm8OptLsl(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2162
llvm::AArch64InstPrinter::printRegWithShiftExtend
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1434
llvm::AArch64InstPrinter::printImmHex
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1270
llvm::AArch64InstPrinter::printInverseCondCode
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1488
llvm::AArch64InstPrinter::printExactFPImm
void printExactFPImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2224
llvm::AArch64InstPrinter::printBarrierOption
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:1952
llvm::AArch64InstPrinter::printSVELogicalImm
void printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AArch64InstPrinter.cpp:2187
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:64
llvm::MCInstPrinter::markup
WithMarkup markup(raw_ostream &OS, Markup M)
Definition MCInstPrinter.cpp:227
llvm::MCInstPrinter::formatHex
format_object< int64_t > formatHex(int64_t Value) const
Definition MCInstPrinter.cpp:190
llvm::MCInstPrinter::MII
const MCInstrInfo & MII
Definition MCInstPrinter.h:53
llvm::MCInstPrinter::CommentStream
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition MCInstPrinter.h:51
llvm::MCInstPrinter::getPrintImmHex
bool getPrintImmHex() const
Definition MCInstPrinter.h:163
llvm::MCInstPrinter::SymbolizeOperands
bool SymbolizeOperands
If true, symbolize branch target and memory reference operands.
Definition MCInstPrinter.h:78
llvm::MCInstPrinter::formatDec
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
Definition MCInstPrinter.cpp:186
llvm::MCInstPrinter::MRI
const MCRegisterInfo & MRI
Definition MCInstPrinter.h:54
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition MCInstPrinter.cpp:50
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition MCInstPrinter.h:52
llvm::MCInstPrinter::formatImm
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition MCInstPrinter.h:176
llvm::MCInstPrinter::PrintBranchImmAsAddress
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition MCInstPrinter.h:75
llvm::MCInstPrinter::MCInstPrinter
MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, const MCRegisterInfo &mri)
Definition MCInstPrinter.h:90
llvm::MCInstPrinter::PrintAliases
bool PrintAliases
True if we prefer aliases (e.g. nop) to raw mnemonics.
Definition MCInstPrinter.h:64
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCOperand::isImm
bool isImm() const
Definition MCInst.h:66
llvm::MCOperand::isReg
bool isReg() const
Definition MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition MCInst.h:68
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition MCInst.h:118
llvm::MCOperand::getDFPImm
uint64_t getDFPImm() const
Definition MCInst.h:104
llvm::MCOperand::isExpr
bool isExpr() const
Definition MCInst.h:69
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition MCRegisterInfo.h:36
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:150
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition MCSubtargetInfo.h:115
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint16_t
uint64_t
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition AArch64BaseInfo.h:281
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition AArch64BaseInfo.h:303
llvm::AArch64PHint::lookupPHintByEncoding
const PHint * lookupPHintByEncoding(uint16_t)
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition AArch64BaseInfo.cpp:176
llvm::AArch64_AM::isMOVNMovAlias
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition AArch64AddressingModes.h:850
llvm::AArch64_AM::decodeLogicalImmediate
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
Definition AArch64AddressingModes.h:293
llvm::AArch64_AM::getShiftValue
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
Definition AArch64AddressingModes.h:85
llvm::AArch64_AM::isAnyMOVWMovAlias
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
Definition AArch64AddressingModes.h:862
llvm::AArch64_AM::getArithShiftValue
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
Definition AArch64AddressingModes.h:118
llvm::AArch64_AM::getFPImmFloat
static float getFPImmFloat(unsigned Imm)
Definition AArch64AddressingModes.h:343
llvm::AArch64_AM::isMOVZMovAlias
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition AArch64AddressingModes.h:839
llvm::AArch64_AM::ShiftExtendType
ShiftExtendType
Definition AArch64AddressingModes.h:32
llvm::AArch64_AM::LSL
@ LSL
Definition AArch64AddressingModes.h:34
llvm::AArch64_AM::UXTW
@ UXTW
Definition AArch64AddressingModes.h:42
llvm::AArch64_AM::UXTX
@ UXTX
Definition AArch64AddressingModes.h:43
llvm::AArch64_AM::getShiftExtendName
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
Definition AArch64AddressingModes.h:52
llvm::AArch64_AM::decodeAdvSIMDModImmType10
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
Definition AArch64AddressingModes.h:663
llvm::AArch64_AM::getArithExtendType
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
Definition AArch64AddressingModes.h:138
llvm::AArch64_AM::getShiftType
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
Definition AArch64AddressingModes.h:73
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Offset
@ Offset
Definition DWP.cpp:477
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1655
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
llvm::transform
OutputIt transform(R &&Range, OutputIt d_first, UnaryFunction F)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere.
Definition STLExtras.h:1968
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition MathExtras.h:331
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:998
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition AArch64BaseInfo.h:207
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition Format.h:129
llvm::bit_cast
To bit_cast(const From &from) noexcept
Definition bit.h:90
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:22
llvm::getWRegFromXReg
static MCRegister getWRegFromXReg(MCRegister Reg)
Definition AArch64BaseInfo.h:30
llvm::BitWidth
constexpr unsigned BitWidth
Definition BitmaskEnum.h:220
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:572
llvm::maskTrailingOnes
constexpr T maskTrailingOnes(unsigned N)
Create a bitmask with the N right-most bits set to 1, and all other bits set to 0.
Definition MathExtras.h:77
llvm::itostr
std::string itostr(int64_t X)
Definition StringExtras.h:337
raw_ostream.h
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition AArch64BaseInfo.h:396
llvm::SysAlias::Name
const char * Name
Definition AArch64BaseInfo.h:388
Generated on for LLVM by doxygen 1.14.0