35 #define DEBUG_TYPE "asm-printer"
37 #define GET_INSTRUCTION_NAME
38 #define PRINT_ALIAS_INSTR
39 #include "AArch64GenAsmWriter.inc"
40 #define GET_INSTRUCTION_NAME
41 #define PRINT_ALIAS_INSTR
42 #include "AArch64GenAsmWriter1.inc"
55 if (Opt ==
"no-aliases") {
67 unsigned AltIdx)
const {
80 unsigned Opcode =
MI->getOpcode();
82 if (Opcode == AArch64::SYSxt)
88 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
95 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
101 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
102 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
108 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
109 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
111 const char *AsmMnemonic =
nullptr;
118 AsmMnemonic =
"sxtb";
120 AsmMnemonic =
"uxtb";
124 AsmMnemonic =
"sxth";
126 AsmMnemonic =
"uxth";
130 if (Is64Bit && IsSigned)
131 AsmMnemonic =
"sxtw";
136 O <<
'\t' << AsmMnemonic <<
'\t';
149 const char *AsmMnemonic =
nullptr;
151 int64_t immr = Op2.
getImm();
152 int64_t imms = Op3.
getImm();
153 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
156 }
else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
157 ((imms + 1 == immr))) {
160 }
else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
163 }
else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
166 }
else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
169 }
else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
174 O <<
'\t' << AsmMnemonic <<
'\t';
186 O <<
'\t' << (IsSigned ?
"sbfiz" :
"ubfiz") <<
'\t';
190 O <<
", " <<
markup(
"<imm:") <<
"#" << (Is64Bit ? 64 : 32) - Op2.
getImm()
198 O <<
'\t' << (IsSigned ?
"sbfx" :
"ubfx") <<
'\t';
209 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
212 int ImmR =
MI->getOperand(3).getImm();
213 int ImmS =
MI->getOperand(4).getImm();
215 if ((Op2.
getReg() == AArch64::WZR || Op2.
getReg() == AArch64::XZR) &&
216 (ImmR == 0 || ImmS < ImmR) &&
219 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
221 int Width = ImmS + 1;
225 O <<
", " <<
markup(
"<imm:") <<
"#" << LSB <<
markup(
">") <<
", "
229 }
else if (ImmS < ImmR) {
231 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
233 int Width = ImmS + 1;
239 O <<
", " <<
markup(
"<imm:") <<
"#" << LSB <<
markup(
">") <<
", "
246 int Width = ImmS - ImmR + 1;
252 O <<
", " <<
markup(
"<imm:") <<
"#" << LSB <<
markup(
">") <<
", "
261 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
262 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
263 MI->getOperand(1).isExpr()) {
264 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
270 O <<
", " <<
markup(
"<imm:") <<
"#";
276 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
277 MI->getOperand(2).isExpr()) {
280 O <<
", " <<
markup(
"<imm:") <<
"#";
291 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
292 MI->getOperand(1).isImm() &&
MI->getOperand(2).isImm()) {
293 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
294 int Shift =
MI->getOperand(2).getImm();
298 Opcode == AArch64::MOVZXi ? 64 : 32)) {
301 O <<
", " <<
markup(
"<imm:") <<
"#"
307 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
308 MI->getOperand(1).isImm() &&
MI->getOperand(2).isImm()) {
309 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
310 int Shift =
MI->getOperand(2).getImm();
318 O <<
", " <<
markup(
"<imm:") <<
"#"
324 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
325 (
MI->getOperand(1).getReg() == AArch64::XZR ||
326 MI->getOperand(1).getReg() == AArch64::WZR) &&
327 MI->getOperand(2).isImm()) {
328 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
330 MI->getOperand(2).getImm(), RegWidth);
334 O <<
", " <<
markup(
"<imm:") <<
"#"
340 if (Opcode == AArch64::SPACE) {
342 <<
MI->getOperand(1).getImm();
349 if (Opcode == AArch64::TSB) {
360 (
MI->getOperand(0).getReg() == AArch64::XZR ||
361 MI->getOperand(0).getReg() == AArch64::WZR)) {
369 case AArch64::TBXv8i8One:
370 case AArch64::TBXv8i8Two:
371 case AArch64::TBXv8i8Three:
372 case AArch64::TBXv8i8Four:
376 case AArch64::TBLv8i8One:
377 case AArch64::TBLv8i8Two:
378 case AArch64::TBLv8i8Three:
379 case AArch64::TBLv8i8Four:
383 case AArch64::TBXv16i8One:
384 case AArch64::TBXv16i8Two:
385 case AArch64::TBXv16i8Three:
386 case AArch64::TBXv16i8Four:
390 case AArch64::TBLv16i8One:
391 case AArch64::TBLv16i8Two:
392 case AArch64::TBLv16i8Three:
393 case AArch64::TBLv16i8Four:
412 { AArch64::LD1i8,
"ld1",
".b", 1,
true, 0 },
413 { AArch64::LD1i16,
"ld1",
".h", 1,
true, 0 },
414 { AArch64::LD1i32,
"ld1",
".s", 1,
true, 0 },
415 { AArch64::LD1i64,
"ld1",
".d", 1,
true, 0 },
416 { AArch64::LD1i8_POST,
"ld1",
".b", 2,
true, 1 },
417 { AArch64::LD1i16_POST,
"ld1",
".h", 2,
true, 2 },
418 { AArch64::LD1i32_POST,
"ld1",
".s", 2,
true, 4 },
419 { AArch64::LD1i64_POST,
"ld1",
".d", 2,
true, 8 },
420 { AArch64::LD1Rv16b,
"ld1r",
".16b", 0,
false, 0 },
421 { AArch64::LD1Rv8h,
"ld1r",
".8h", 0,
false, 0 },
422 { AArch64::LD1Rv4s,
"ld1r",
".4s", 0,
false, 0 },
423 { AArch64::LD1Rv2d,
"ld1r",
".2d", 0,
false, 0 },
424 { AArch64::LD1Rv8b,
"ld1r",
".8b", 0,
false, 0 },
425 { AArch64::LD1Rv4h,
"ld1r",
".4h", 0,
false, 0 },
426 { AArch64::LD1Rv2s,
"ld1r",
".2s", 0,
false, 0 },
427 { AArch64::LD1Rv1d,
"ld1r",
".1d", 0,
false, 0 },
428 { AArch64::LD1Rv16b_POST,
"ld1r",
".16b", 1,
false, 1 },
429 { AArch64::LD1Rv8h_POST,
"ld1r",
".8h", 1,
false, 2 },
430 { AArch64::LD1Rv4s_POST,
"ld1r",
".4s", 1,
false, 4 },
431 { AArch64::LD1Rv2d_POST,
"ld1r",
".2d", 1,
false, 8 },
432 { AArch64::LD1Rv8b_POST,
"ld1r",
".8b", 1,
false, 1 },
433 { AArch64::LD1Rv4h_POST,
"ld1r",
".4h", 1,
false, 2 },
434 { AArch64::LD1Rv2s_POST,
"ld1r",
".2s", 1,
false, 4 },
435 { AArch64::LD1Rv1d_POST,
"ld1r",
".1d", 1,
false, 8 },
436 { AArch64::LD1Onev16b,
"ld1",
".16b", 0,
false, 0 },
437 { AArch64::LD1Onev8h,
"ld1",
".8h", 0,
false, 0 },
438 { AArch64::LD1Onev4s,
"ld1",
".4s", 0,
false, 0 },
439 { AArch64::LD1Onev2d,
"ld1",
".2d", 0,
false, 0 },
440 { AArch64::LD1Onev8b,
"ld1",
".8b", 0,
false, 0 },
441 { AArch64::LD1Onev4h,
"ld1",
".4h", 0,
false, 0 },
442 { AArch64::LD1Onev2s,
"ld1",
".2s", 0,
false, 0 },
443 { AArch64::LD1Onev1d,
"ld1",
".1d", 0,
false, 0 },
444 { AArch64::LD1Onev16b_POST,
"ld1",
".16b", 1,
false, 16 },
445 { AArch64::LD1Onev8h_POST,
"ld1",
".8h", 1,
false, 16 },
446 { AArch64::LD1Onev4s_POST,
"ld1",
".4s", 1,
false, 16 },
447 { AArch64::LD1Onev2d_POST,
"ld1",
".2d", 1,
false, 16 },
448 { AArch64::LD1Onev8b_POST,
"ld1",
".8b", 1,
false, 8 },
449 { AArch64::LD1Onev4h_POST,
"ld1",
".4h", 1,
false, 8 },
450 { AArch64::LD1Onev2s_POST,
"ld1",
".2s", 1,
false, 8 },
451 { AArch64::LD1Onev1d_POST,
"ld1",
".1d", 1,
false, 8 },
452 { AArch64::LD1Twov16b,
"ld1",
".16b", 0,
false, 0 },
453 { AArch64::LD1Twov8h,
"ld1",
".8h", 0,
false, 0 },
454 { AArch64::LD1Twov4s,
"ld1",
".4s", 0,
false, 0 },
455 { AArch64::LD1Twov2d,
"ld1",
".2d", 0,
false, 0 },
456 { AArch64::LD1Twov8b,
"ld1",
".8b", 0,
false, 0 },
457 { AArch64::LD1Twov4h,
"ld1",
".4h", 0,
false, 0 },
458 { AArch64::LD1Twov2s,
"ld1",
".2s", 0,
false, 0 },
459 { AArch64::LD1Twov1d,
"ld1",
".1d", 0,
false, 0 },
460 { AArch64::LD1Twov16b_POST,
"ld1",
".16b", 1,
false, 32 },
461 { AArch64::LD1Twov8h_POST,
"ld1",
".8h", 1,
false, 32 },
462 { AArch64::LD1Twov4s_POST,
"ld1",
".4s", 1,
false, 32 },
463 { AArch64::LD1Twov2d_POST,
"ld1",
".2d", 1,
false, 32 },
464 { AArch64::LD1Twov8b_POST,
"ld1",
".8b", 1,
false, 16 },
465 { AArch64::LD1Twov4h_POST,
"ld1",
".4h", 1,
false, 16 },
466 { AArch64::LD1Twov2s_POST,
"ld1",
".2s", 1,
false, 16 },
467 { AArch64::LD1Twov1d_POST,
"ld1",
".1d", 1,
false, 16 },
468 { AArch64::LD1Threev16b,
"ld1",
".16b", 0,
false, 0 },
469 { AArch64::LD1Threev8h,
"ld1",
".8h", 0,
false, 0 },
470 { AArch64::LD1Threev4s,
"ld1",
".4s", 0,
false, 0 },
471 { AArch64::LD1Threev2d,
"ld1",
".2d", 0,
false, 0 },
472 { AArch64::LD1Threev8b,
"ld1",
".8b", 0,
false, 0 },
473 { AArch64::LD1Threev4h,
"ld1",
".4h", 0,
false, 0 },
474 { AArch64::LD1Threev2s,
"ld1",
".2s", 0,
false, 0 },
475 { AArch64::LD1Threev1d,
"ld1",
".1d", 0,
false, 0 },
476 { AArch64::LD1Threev16b_POST,
"ld1",
".16b", 1,
false, 48 },
477 { AArch64::LD1Threev8h_POST,
"ld1",
".8h", 1,
false, 48 },
478 { AArch64::LD1Threev4s_POST,
"ld1",
".4s", 1,
false, 48 },
479 { AArch64::LD1Threev2d_POST,
"ld1",
".2d", 1,
false, 48 },
480 { AArch64::LD1Threev8b_POST,
"ld1",
".8b", 1,
false, 24 },
481 { AArch64::LD1Threev4h_POST,
"ld1",
".4h", 1,
false, 24 },
482 { AArch64::LD1Threev2s_POST,
"ld1",
".2s", 1,
false, 24 },
483 { AArch64::LD1Threev1d_POST,
"ld1",
".1d", 1,
false, 24 },
484 { AArch64::LD1Fourv16b,
"ld1",
".16b", 0,
false, 0 },
485 { AArch64::LD1Fourv8h,
"ld1",
".8h", 0,
false, 0 },
486 { AArch64::LD1Fourv4s,
"ld1",
".4s", 0,
false, 0 },
487 { AArch64::LD1Fourv2d,
"ld1",
".2d", 0,
false, 0 },
488 { AArch64::LD1Fourv8b,
"ld1",
".8b", 0,
false, 0 },
489 { AArch64::LD1Fourv4h,
"ld1",
".4h", 0,
false, 0 },
490 { AArch64::LD1Fourv2s,
"ld1",
".2s", 0,
false, 0 },
491 { AArch64::LD1Fourv1d,
"ld1",
".1d", 0,
false, 0 },
492 { AArch64::LD1Fourv16b_POST,
"ld1",
".16b", 1,
false, 64 },
493 { AArch64::LD1Fourv8h_POST,
"ld1",
".8h", 1,
false, 64 },
494 { AArch64::LD1Fourv4s_POST,
"ld1",
".4s", 1,
false, 64 },
495 { AArch64::LD1Fourv2d_POST,
"ld1",
".2d", 1,
false, 64 },
496 { AArch64::LD1Fourv8b_POST,
"ld1",
".8b", 1,
false, 32 },
497 { AArch64::LD1Fourv4h_POST,
"ld1",
".4h", 1,
false, 32 },
498 { AArch64::LD1Fourv2s_POST,
"ld1",
".2s", 1,
false, 32 },
499 { AArch64::LD1Fourv1d_POST,
"ld1",
".1d", 1,
false, 32 },
500 { AArch64::LD2i8,
"ld2",
".b", 1,
true, 0 },
501 { AArch64::LD2i16,
"ld2",
".h", 1,
true, 0 },
502 { AArch64::LD2i32,
"ld2",
".s", 1,
true, 0 },
503 { AArch64::LD2i64,
"ld2",
".d", 1,
true, 0 },
504 { AArch64::LD2i8_POST,
"ld2",
".b", 2,
true, 2 },
505 { AArch64::LD2i16_POST,
"ld2",
".h", 2,
true, 4 },
506 { AArch64::LD2i32_POST,
"ld2",
".s", 2,
true, 8 },
507 { AArch64::LD2i64_POST,
"ld2",
".d", 2,
true, 16 },
508 { AArch64::LD2Rv16b,
"ld2r",
".16b", 0,
false, 0 },
509 { AArch64::LD2Rv8h,
"ld2r",
".8h", 0,
false, 0 },
510 { AArch64::LD2Rv4s,
"ld2r",
".4s", 0,
false, 0 },
511 { AArch64::LD2Rv2d,
"ld2r",
".2d", 0,
false, 0 },
512 { AArch64::LD2Rv8b,
"ld2r",
".8b", 0,
false, 0 },
513 { AArch64::LD2Rv4h,
"ld2r",
".4h", 0,
false, 0 },
514 { AArch64::LD2Rv2s,
"ld2r",
".2s", 0,
false, 0 },
515 { AArch64::LD2Rv1d,
"ld2r",
".1d", 0,
false, 0 },
516 { AArch64::LD2Rv16b_POST,
"ld2r",
".16b", 1,
false, 2 },
517 { AArch64::LD2Rv8h_POST,
"ld2r",
".8h", 1,
false, 4 },
518 { AArch64::LD2Rv4s_POST,
"ld2r",
".4s", 1,
false, 8 },
519 { AArch64::LD2Rv2d_POST,
"ld2r",
".2d", 1,
false, 16 },
520 { AArch64::LD2Rv8b_POST,
"ld2r",
".8b", 1,
false, 2 },
521 { AArch64::LD2Rv4h_POST,
"ld2r",
".4h", 1,
false, 4 },
522 { AArch64::LD2Rv2s_POST,
"ld2r",
".2s", 1,
false, 8 },
523 { AArch64::LD2Rv1d_POST,
"ld2r",
".1d", 1,
false, 16 },
524 { AArch64::LD2Twov16b,
"ld2",
".16b", 0,
false, 0 },
525 { AArch64::LD2Twov8h,
"ld2",
".8h", 0,
false, 0 },
526 { AArch64::LD2Twov4s,
"ld2",
".4s", 0,
false, 0 },
527 { AArch64::LD2Twov2d,
"ld2",
".2d", 0,
false, 0 },
528 { AArch64::LD2Twov8b,
"ld2",
".8b", 0,
false, 0 },
529 { AArch64::LD2Twov4h,
"ld2",
".4h", 0,
false, 0 },
530 { AArch64::LD2Twov2s,
"ld2",
".2s", 0,
false, 0 },
531 { AArch64::LD2Twov16b_POST,
"ld2",
".16b", 1,
false, 32 },
532 { AArch64::LD2Twov8h_POST,
"ld2",
".8h", 1,
false, 32 },
533 { AArch64::LD2Twov4s_POST,
"ld2",
".4s", 1,
false, 32 },
534 { AArch64::LD2Twov2d_POST,
"ld2",
".2d", 1,
false, 32 },
535 { AArch64::LD2Twov8b_POST,
"ld2",
".8b", 1,
false, 16 },
536 { AArch64::LD2Twov4h_POST,
"ld2",
".4h", 1,
false, 16 },
537 { AArch64::LD2Twov2s_POST,
"ld2",
".2s", 1,
false, 16 },
538 { AArch64::LD3i8,
"ld3",
".b", 1,
true, 0 },
539 { AArch64::LD3i16,
"ld3",
".h", 1,
true, 0 },
540 { AArch64::LD3i32,
"ld3",
".s", 1,
true, 0 },
541 { AArch64::LD3i64,
"ld3",
".d", 1,
true, 0 },
542 { AArch64::LD3i8_POST,
"ld3",
".b", 2,
true, 3 },
543 { AArch64::LD3i16_POST,
"ld3",
".h", 2,
true, 6 },
544 { AArch64::LD3i32_POST,
"ld3",
".s", 2,
true, 12 },
545 { AArch64::LD3i64_POST,
"ld3",
".d", 2,
true, 24 },
546 { AArch64::LD3Rv16b,
"ld3r",
".16b", 0,
false, 0 },
547 { AArch64::LD3Rv8h,
"ld3r",
".8h", 0,
false, 0 },
548 { AArch64::LD3Rv4s,
"ld3r",
".4s", 0,
false, 0 },
549 { AArch64::LD3Rv2d,
"ld3r",
".2d", 0,
false, 0 },
550 { AArch64::LD3Rv8b,
"ld3r",
".8b", 0,
false, 0 },
551 { AArch64::LD3Rv4h,
"ld3r",
".4h", 0,
false, 0 },
552 { AArch64::LD3Rv2s,
"ld3r",
".2s", 0,
false, 0 },
553 { AArch64::LD3Rv1d,
"ld3r",
".1d", 0,
false, 0 },
554 { AArch64::LD3Rv16b_POST,
"ld3r",
".16b", 1,
false, 3 },
555 { AArch64::LD3Rv8h_POST,
"ld3r",
".8h", 1,
false, 6 },
556 { AArch64::LD3Rv4s_POST,
"ld3r",
".4s", 1,
false, 12 },
557 { AArch64::LD3Rv2d_POST,
"ld3r",
".2d", 1,
false, 24 },
558 { AArch64::LD3Rv8b_POST,
"ld3r",
".8b", 1,
false, 3 },
559 { AArch64::LD3Rv4h_POST,
"ld3r",
".4h", 1,
false, 6 },
560 { AArch64::LD3Rv2s_POST,
"ld3r",
".2s", 1,
false, 12 },
561 { AArch64::LD3Rv1d_POST,
"ld3r",
".1d", 1,
false, 24 },
562 { AArch64::LD3Threev16b,
"ld3",
".16b", 0,
false, 0 },
563 { AArch64::LD3Threev8h,
"ld3",
".8h", 0,
false, 0 },
564 { AArch64::LD3Threev4s,
"ld3",
".4s", 0,
false, 0 },
565 { AArch64::LD3Threev2d,
"ld3",
".2d", 0,
false, 0 },
566 { AArch64::LD3Threev8b,
"ld3",
".8b", 0,
false, 0 },
567 { AArch64::LD3Threev4h,
"ld3",
".4h", 0,
false, 0 },
568 { AArch64::LD3Threev2s,
"ld3",
".2s", 0,
false, 0 },
569 { AArch64::LD3Threev16b_POST,
"ld3",
".16b", 1,
false, 48 },
570 { AArch64::LD3Threev8h_POST,
"ld3",
".8h", 1,
false, 48 },
571 { AArch64::LD3Threev4s_POST,
"ld3",
".4s", 1,
false, 48 },
572 { AArch64::LD3Threev2d_POST,
"ld3",
".2d", 1,
false, 48 },
573 { AArch64::LD3Threev8b_POST,
"ld3",
".8b", 1,
false, 24 },
574 { AArch64::LD3Threev4h_POST,
"ld3",
".4h", 1,
false, 24 },
575 { AArch64::LD3Threev2s_POST,
"ld3",
".2s", 1,
false, 24 },
576 { AArch64::LD4i8,
"ld4",
".b", 1,
true, 0 },
577 { AArch64::LD4i16,
"ld4",
".h", 1,
true, 0 },
578 { AArch64::LD4i32,
"ld4",
".s", 1,
true, 0 },
579 { AArch64::LD4i64,
"ld4",
".d", 1,
true, 0 },
580 { AArch64::LD4i8_POST,
"ld4",
".b", 2,
true, 4 },
581 { AArch64::LD4i16_POST,
"ld4",
".h", 2,
true, 8 },
582 { AArch64::LD4i32_POST,
"ld4",
".s", 2,
true, 16 },
583 { AArch64::LD4i64_POST,
"ld4",
".d", 2,
true, 32 },
584 { AArch64::LD4Rv16b,
"ld4r",
".16b", 0,
false, 0 },
585 { AArch64::LD4Rv8h,
"ld4r",
".8h", 0,
false, 0 },
586 { AArch64::LD4Rv4s,
"ld4r",
".4s", 0,
false, 0 },
587 { AArch64::LD4Rv2d,
"ld4r",
".2d", 0,
false, 0 },
588 { AArch64::LD4Rv8b,
"ld4r",
".8b", 0,
false, 0 },
589 { AArch64::LD4Rv4h,
"ld4r",
".4h", 0,
false, 0 },
590 { AArch64::LD4Rv2s,
"ld4r",
".2s", 0,
false, 0 },
591 { AArch64::LD4Rv1d,
"ld4r",
".1d", 0,
false, 0 },
592 { AArch64::LD4Rv16b_POST,
"ld4r",
".16b", 1,
false, 4 },
593 { AArch64::LD4Rv8h_POST,
"ld4r",
".8h", 1,
false, 8 },
594 { AArch64::LD4Rv4s_POST,
"ld4r",
".4s", 1,
false, 16 },
595 { AArch64::LD4Rv2d_POST,
"ld4r",
".2d", 1,
false, 32 },
596 { AArch64::LD4Rv8b_POST,
"ld4r",
".8b", 1,
false, 4 },
597 { AArch64::LD4Rv4h_POST,
"ld4r",
".4h", 1,
false, 8 },
598 { AArch64::LD4Rv2s_POST,
"ld4r",
".2s", 1,
false, 16 },
599 { AArch64::LD4Rv1d_POST,
"ld4r",
".1d", 1,
false, 32 },
600 { AArch64::LD4Fourv16b,
"ld4",
".16b", 0,
false, 0 },
601 { AArch64::LD4Fourv8h,
"ld4",
".8h", 0,
false, 0 },
602 { AArch64::LD4Fourv4s,
"ld4",
".4s", 0,
false, 0 },
603 { AArch64::LD4Fourv2d,
"ld4",
".2d", 0,
false, 0 },
604 { AArch64::LD4Fourv8b,
"ld4",
".8b", 0,
false, 0 },
605 { AArch64::LD4Fourv4h,
"ld4",
".4h", 0,
false, 0 },
606 { AArch64::LD4Fourv2s,
"ld4",
".2s", 0,
false, 0 },
607 { AArch64::LD4Fourv16b_POST,
"ld4",
".16b", 1,
false, 64 },
608 { AArch64::LD4Fourv8h_POST,
"ld4",
".8h", 1,
false, 64 },
609 { AArch64::LD4Fourv4s_POST,
"ld4",
".4s", 1,
false, 64 },
610 { AArch64::LD4Fourv2d_POST,
"ld4",
".2d", 1,
false, 64 },
611 { AArch64::LD4Fourv8b_POST,
"ld4",
".8b", 1,
false, 32 },
612 { AArch64::LD4Fourv4h_POST,
"ld4",
".4h", 1,
false, 32 },
613 { AArch64::LD4Fourv2s_POST,
"ld4",
".2s", 1,
false, 32 },
614 { AArch64::ST1i8,
"st1",
".b", 0,
true, 0 },
615 { AArch64::ST1i16,
"st1",
".h", 0,
true, 0 },
616 { AArch64::ST1i32,
"st1",
".s", 0,
true, 0 },
617 { AArch64::ST1i64,
"st1",
".d", 0,
true, 0 },
618 { AArch64::ST1i8_POST,
"st1",
".b", 1,
true, 1 },
619 { AArch64::ST1i16_POST,
"st1",
".h", 1,
true, 2 },
620 { AArch64::ST1i32_POST,
"st1",
".s", 1,
true, 4 },
621 { AArch64::ST1i64_POST,
"st1",
".d", 1,
true, 8 },
622 { AArch64::ST1Onev16b,
"st1",
".16b", 0,
false, 0 },
623 { AArch64::ST1Onev8h,
"st1",
".8h", 0,
false, 0 },
624 { AArch64::ST1Onev4s,
"st1",
".4s", 0,
false, 0 },
625 { AArch64::ST1Onev2d,
"st1",
".2d", 0,
false, 0 },
626 { AArch64::ST1Onev8b,
"st1",
".8b", 0,
false, 0 },
627 { AArch64::ST1Onev4h,
"st1",
".4h", 0,
false, 0 },
628 { AArch64::ST1Onev2s,
"st1",
".2s", 0,
false, 0 },
629 { AArch64::ST1Onev1d,
"st1",
".1d", 0,
false, 0 },
630 { AArch64::ST1Onev16b_POST,
"st1",
".16b", 1,
false, 16 },
631 { AArch64::ST1Onev8h_POST,
"st1",
".8h", 1,
false, 16 },
632 { AArch64::ST1Onev4s_POST,
"st1",
".4s", 1,
false, 16 },
633 { AArch64::ST1Onev2d_POST,
"st1",
".2d", 1,
false, 16 },
634 { AArch64::ST1Onev8b_POST,
"st1",
".8b", 1,
false, 8 },
635 { AArch64::ST1Onev4h_POST,
"st1",
".4h", 1,
false, 8 },
636 { AArch64::ST1Onev2s_POST,
"st1",
".2s", 1,
false, 8 },
637 { AArch64::ST1Onev1d_POST,
"st1",
".1d", 1,
false, 8 },
638 { AArch64::ST1Twov16b,
"st1",
".16b", 0,
false, 0 },
639 { AArch64::ST1Twov8h,
"st1",
".8h", 0,
false, 0 },
640 { AArch64::ST1Twov4s,
"st1",
".4s", 0,
false, 0 },
641 { AArch64::ST1Twov2d,
"st1",
".2d", 0,
false, 0 },
642 { AArch64::ST1Twov8b,
"st1",
".8b", 0,
false, 0 },
643 { AArch64::ST1Twov4h,
"st1",
".4h", 0,
false, 0 },
644 { AArch64::ST1Twov2s,
"st1",
".2s", 0,
false, 0 },
645 { AArch64::ST1Twov1d,
"st1",
".1d", 0,
false, 0 },
646 { AArch64::ST1Twov16b_POST,
"st1",
".16b", 1,
false, 32 },
647 { AArch64::ST1Twov8h_POST,
"st1",
".8h", 1,
false, 32 },
648 { AArch64::ST1Twov4s_POST,
"st1",
".4s", 1,
false, 32 },
649 { AArch64::ST1Twov2d_POST,
"st1",
".2d", 1,
false, 32 },
650 { AArch64::ST1Twov8b_POST,
"st1",
".8b", 1,
false, 16 },
651 { AArch64::ST1Twov4h_POST,
"st1",
".4h", 1,
false, 16 },
652 { AArch64::ST1Twov2s_POST,
"st1",
".2s", 1,
false, 16 },
653 { AArch64::ST1Twov1d_POST,
"st1",
".1d", 1,
false, 16 },
654 { AArch64::ST1Threev16b,
"st1",
".16b", 0,
false, 0 },
655 { AArch64::ST1Threev8h,
"st1",
".8h", 0,
false, 0 },
656 { AArch64::ST1Threev4s,
"st1",
".4s", 0,
false, 0 },
657 { AArch64::ST1Threev2d,
"st1",
".2d", 0,
false, 0 },
658 { AArch64::ST1Threev8b,
"st1",
".8b", 0,
false, 0 },
659 { AArch64::ST1Threev4h,
"st1",
".4h", 0,
false, 0 },
660 { AArch64::ST1Threev2s,
"st1",
".2s", 0,
false, 0 },
661 { AArch64::ST1Threev1d,
"st1",
".1d", 0,
false, 0 },
662 { AArch64::ST1Threev16b_POST,
"st1",
".16b", 1,
false, 48 },
663 { AArch64::ST1Threev8h_POST,
"st1",
".8h", 1,
false, 48 },
664 { AArch64::ST1Threev4s_POST,
"st1",
".4s", 1,
false, 48 },
665 { AArch64::ST1Threev2d_POST,
"st1",
".2d", 1,
false, 48 },
666 { AArch64::ST1Threev8b_POST,
"st1",
".8b", 1,
false, 24 },
667 { AArch64::ST1Threev4h_POST,
"st1",
".4h", 1,
false, 24 },
668 { AArch64::ST1Threev2s_POST,
"st1",
".2s", 1,
false, 24 },
669 { AArch64::ST1Threev1d_POST,
"st1",
".1d", 1,
false, 24 },
670 { AArch64::ST1Fourv16b,
"st1",
".16b", 0,
false, 0 },
671 { AArch64::ST1Fourv8h,
"st1",
".8h", 0,
false, 0 },
672 { AArch64::ST1Fourv4s,
"st1",
".4s", 0,
false, 0 },
673 { AArch64::ST1Fourv2d,
"st1",
".2d", 0,
false, 0 },
674 { AArch64::ST1Fourv8b,
"st1",
".8b", 0,
false, 0 },
675 { AArch64::ST1Fourv4h,
"st1",
".4h", 0,
false, 0 },
676 { AArch64::ST1Fourv2s,
"st1",
".2s", 0,
false, 0 },
677 { AArch64::ST1Fourv1d,
"st1",
".1d", 0,
false, 0 },
678 { AArch64::ST1Fourv16b_POST,
"st1",
".16b", 1,
false, 64 },
679 { AArch64::ST1Fourv8h_POST,
"st1",
".8h", 1,
false, 64 },
680 { AArch64::ST1Fourv4s_POST,
"st1",
".4s", 1,
false, 64 },
681 { AArch64::ST1Fourv2d_POST,
"st1",
".2d", 1,
false, 64 },
682 { AArch64::ST1Fourv8b_POST,
"st1",
".8b", 1,
false, 32 },
683 { AArch64::ST1Fourv4h_POST,
"st1",
".4h", 1,
false, 32 },
684 { AArch64::ST1Fourv2s_POST,
"st1",
".2s", 1,
false, 32 },
685 { AArch64::ST1Fourv1d_POST,
"st1",
".1d", 1,
false, 32 },
686 { AArch64::ST2i8,
"st2",
".b", 0,
true, 0 },
687 { AArch64::ST2i16,
"st2",
".h", 0,
true, 0 },
688 { AArch64::ST2i32,
"st2",
".s", 0,
true, 0 },
689 { AArch64::ST2i64,
"st2",
".d", 0,
true, 0 },
690 { AArch64::ST2i8_POST,
"st2",
".b", 1,
true, 2 },
691 { AArch64::ST2i16_POST,
"st2",
".h", 1,
true, 4 },
692 { AArch64::ST2i32_POST,
"st2",
".s", 1,
true, 8 },
693 { AArch64::ST2i64_POST,
"st2",
".d", 1,
true, 16 },
694 { AArch64::ST2Twov16b,
"st2",
".16b", 0,
false, 0 },
695 { AArch64::ST2Twov8h,
"st2",
".8h", 0,
false, 0 },
696 { AArch64::ST2Twov4s,
"st2",
".4s", 0,
false, 0 },
697 { AArch64::ST2Twov2d,
"st2",
".2d", 0,
false, 0 },
698 { AArch64::ST2Twov8b,
"st2",
".8b", 0,
false, 0 },
699 { AArch64::ST2Twov4h,
"st2",
".4h", 0,
false, 0 },
700 { AArch64::ST2Twov2s,
"st2",
".2s", 0,
false, 0 },
701 { AArch64::ST2Twov16b_POST,
"st2",
".16b", 1,
false, 32 },
702 { AArch64::ST2Twov8h_POST,
"st2",
".8h", 1,
false, 32 },
703 { AArch64::ST2Twov4s_POST,
"st2",
".4s", 1,
false, 32 },
704 { AArch64::ST2Twov2d_POST,
"st2",
".2d", 1,
false, 32 },
705 { AArch64::ST2Twov8b_POST,
"st2",
".8b", 1,
false, 16 },
706 { AArch64::ST2Twov4h_POST,
"st2",
".4h", 1,
false, 16 },
707 { AArch64::ST2Twov2s_POST,
"st2",
".2s", 1,
false, 16 },
708 { AArch64::ST3i8,
"st3",
".b", 0,
true, 0 },
709 { AArch64::ST3i16,
"st3",
".h", 0,
true, 0 },
710 { AArch64::ST3i32,
"st3",
".s", 0,
true, 0 },
711 { AArch64::ST3i64,
"st3",
".d", 0,
true, 0 },
712 { AArch64::ST3i8_POST,
"st3",
".b", 1,
true, 3 },
713 { AArch64::ST3i16_POST,
"st3",
".h", 1,
true, 6 },
714 { AArch64::ST3i32_POST,
"st3",
".s", 1,
true, 12 },
715 { AArch64::ST3i64_POST,
"st3",
".d", 1,
true, 24 },
716 { AArch64::ST3Threev16b,
"st3",
".16b", 0,
false, 0 },
717 { AArch64::ST3Threev8h,
"st3",
".8h", 0,
false, 0 },
718 { AArch64::ST3Threev4s,
"st3",
".4s", 0,
false, 0 },
719 { AArch64::ST3Threev2d,
"st3",
".2d", 0,
false, 0 },
720 { AArch64::ST3Threev8b,
"st3",
".8b", 0,
false, 0 },
721 { AArch64::ST3Threev4h,
"st3",
".4h", 0,
false, 0 },
722 { AArch64::ST3Threev2s,
"st3",
".2s", 0,
false, 0 },
723 { AArch64::ST3Threev16b_POST,
"st3",
".16b", 1,
false, 48 },
724 { AArch64::ST3Threev8h_POST,
"st3",
".8h", 1,
false, 48 },
725 { AArch64::ST3Threev4s_POST,
"st3",
".4s", 1,
false, 48 },
726 { AArch64::ST3Threev2d_POST,
"st3",
".2d", 1,
false, 48 },
727 { AArch64::ST3Threev8b_POST,
"st3",
".8b", 1,
false, 24 },
728 { AArch64::ST3Threev4h_POST,
"st3",
".4h", 1,
false, 24 },
729 { AArch64::ST3Threev2s_POST,
"st3",
".2s", 1,
false, 24 },
730 { AArch64::ST4i8,
"st4",
".b", 0,
true, 0 },
731 { AArch64::ST4i16,
"st4",
".h", 0,
true, 0 },
732 { AArch64::ST4i32,
"st4",
".s", 0,
true, 0 },
733 { AArch64::ST4i64,
"st4",
".d", 0,
true, 0 },
734 { AArch64::ST4i8_POST,
"st4",
".b", 1,
true, 4 },
735 { AArch64::ST4i16_POST,
"st4",
".h", 1,
true, 8 },
736 { AArch64::ST4i32_POST,
"st4",
".s", 1,
true, 16 },
737 { AArch64::ST4i64_POST,
"st4",
".d", 1,
true, 32 },
738 { AArch64::ST4Fourv16b,
"st4",
".16b", 0,
false, 0 },
739 { AArch64::ST4Fourv8h,
"st4",
".8h", 0,
false, 0 },
740 { AArch64::ST4Fourv4s,
"st4",
".4s", 0,
false, 0 },
741 { AArch64::ST4Fourv2d,
"st4",
".2d", 0,
false, 0 },
742 { AArch64::ST4Fourv8b,
"st4",
".8b", 0,
false, 0 },
743 { AArch64::ST4Fourv4h,
"st4",
".4h", 0,
false, 0 },
744 { AArch64::ST4Fourv2s,
"st4",
".2s", 0,
false, 0 },
745 { AArch64::ST4Fourv16b_POST,
"st4",
".16b", 1,
false, 64 },
746 { AArch64::ST4Fourv8h_POST,
"st4",
".8h", 1,
false, 64 },
747 { AArch64::ST4Fourv4s_POST,
"st4",
".4s", 1,
false, 64 },
748 { AArch64::ST4Fourv2d_POST,
"st4",
".2d", 1,
false, 64 },
749 { AArch64::ST4Fourv8b_POST,
"st4",
".8b", 1,
false, 32 },
750 { AArch64::ST4Fourv4h_POST,
"st4",
".4h", 1,
false, 32 },
751 { AArch64::ST4Fourv2s_POST,
"st4",
".2s", 1,
false, 32 },
756 if (
Info.Opcode == Opcode)
766 unsigned Opcode =
MI->getOpcode();
771 O <<
"\t" << (IsTbx ?
"tbx" :
"tbl") << Layout <<
'\t';
775 unsigned ListOpNum = IsTbx ? 2 : 1;
779 printRegName(
O,
MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
785 O <<
"\t" << LdStDesc->Mnemonic << LdStDesc->Layout <<
'\t';
789 int OpNum = LdStDesc->ListOperand;
792 if (LdStDesc->HasLane)
793 O <<
'[' <<
MI->getOperand(OpNum++).getImm() <<
']';
796 unsigned AddrReg =
MI->getOperand(OpNum++).getReg();
802 if (LdStDesc->NaturalOffset != 0) {
803 unsigned Reg =
MI->getOperand(OpNum++).getReg();
804 if (
Reg != AArch64::XZR) {
808 assert(LdStDesc->NaturalOffset &&
"no offset on post-inc instruction?");
809 O <<
", " <<
markup(
"<imm:") <<
"#" << LdStDesc->NaturalOffset
829 unsigned Opcode =
MI->getOpcode();
832 assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
833 "Invalid opcode for RPRFM alias!");
836 unsigned PRFOp =
MI->getOperand(0).getImm();
837 unsigned Mask = 0x18;
841 unsigned Rm =
MI->getOperand(2).getReg();
848 unsigned SignExtend =
MI->getOperand(3).getImm();
849 unsigned Shift =
MI->getOperand(4).getImm();
851 assert((SignExtend <= 1) &&
"sign extend should be a single bit!");
852 assert((
Shift <= 1) &&
"Shift should be a single bit!");
854 unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
858 (SignExtend << 5) | (Option0 << 4) | (
Shift << 3) | (PRFOp & 0x7);
861 if (
auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
862 O << RPRFM->Name <<
", ";
879 unsigned Opcode =
MI->getOpcode();
880 assert(Opcode == AArch64::SYSxt &&
"Invalid opcode for SYS alias!");
888 unsigned Op1Val = Op1.
getImm();
889 unsigned CnVal = Cn.
getImm();
890 unsigned CmVal = Cm.
getImm();
891 unsigned Op2Val = Op2.
getImm();
894 Encoding |= CmVal << 3;
895 Encoding |= CnVal << 7;
896 Encoding |= Op1Val << 11;
904 default:
return false;
908 default:
return false;
909 case 0:
goto Search_IC;
910 case 3:
goto Search_PRCTX;
915 if (Op1Val != 3 || CnVal != 7 || CmVal != 3)
918 const auto Requires =
919 Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
925 default:
return false;
926 case 4:
Ins =
"cfp\t";
break;
927 case 5:
Ins =
"dvp\t";
break;
928 case 6:
Ins =
"cosp\t";
break;
929 case 7:
Ins =
"cpp\t";
break;
937 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
943 Name = std::string(IC->
Name);
947 case 4:
case 6:
case 10:
case 11:
case 12:
case 13:
case 14:
949 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
955 Name = std::string(DC->
Name);
960 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
966 Name = std::string(AT->
Name);
970 }
else if (CnVal == 8 || CnVal == 9) {
978 Name = std::string(TLBI->
Name);
983 std::string Str =
Ins + Name;
999 unsigned Opcode =
MI->getOpcode();
1000 assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
1001 "Invalid opcode for SYSP alias!");
1009 unsigned Op1Val = Op1.
getImm();
1010 unsigned CnVal = Cn.
getImm();
1011 unsigned CmVal = Cm.
getImm();
1012 unsigned Op2Val = Op2.
getImm();
1015 Encoding |= CmVal << 3;
1016 Encoding |= CnVal << 7;
1017 Encoding |= Op1Val << 11;
1022 if (CnVal == 8 || CnVal == 9) {
1028 Encoding &= ~(1 << 7);
1036 Name = std::string(TLBI->
Name);
1042 std::string Str =
Ins + Name;
1047 if (
MI->getOperand(4).getReg() == AArch64::XZR)
1050 printGPRSeqPairsClassOperand<64>(
MI, 4, STI,
O);
1055 template <
int EltSize>
1060 assert(RegOp.
isReg() &&
"Unexpected operand type!");
1086 template <
bool IsVertical>
1091 assert(RegOp.
isReg() &&
"Unexpected operand type!");
1097 O <<
Base << (IsVertical ?
"v" :
"h") <<
'.' << Suffix;
1104 assert(RegOp.
isReg() &&
"Unexpected operand type!");
1113 unsigned svcrop = MO.
getImm();
1114 const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
1115 assert(SVCR &&
"Unexpected SVCR operand!");
1124 unsigned Reg =
Op.getReg();
1126 }
else if (
Op.isImm()) {
1129 assert(
Op.isExpr() &&
"unknown operand kind in printOperand");
1130 Op.getExpr()->print(
O, &
MAI);
1156 else if (Size == 16)
1167 unsigned Reg =
Op.getReg();
1168 if (
Reg == AArch64::XZR)
1180 assert(
Op.isReg() &&
"Non-register vreg operand!");
1181 unsigned Reg =
Op.getReg();
1189 assert(
Op.isImm() &&
"System instruction C[nm] operands must be immediates!");
1190 O <<
"c" <<
Op.getImm();
1198 unsigned Val = (MO.
getImm() & 0xfff);
1199 assert(Val == MO.
getImm() &&
"Add/sub immediate out of range!");
1215 template <
typename T>
1219 uint64_t Val =
MI->getOperand(OpNum).getImm();
1220 O <<
markup(
"<imm:") <<
"#0x";
1228 unsigned Val =
MI->getOperand(OpNum).getImm();
1255 unsigned Val =
MI->getOperand(OpNum).getImm();
1263 unsigned Dest =
MI->getOperand(0).getReg();
1264 unsigned Src1 =
MI->getOperand(1).getReg();
1265 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1267 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1270 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << ShiftVal <<
markup(
">");
1276 O <<
" " <<
markup(
"<imm:") <<
"#" << ShiftVal <<
markup(
">");
1283 bool IsLSL = !SignExtend && SrcRegKind ==
'x';
1287 O << (SignExtend ?
's' :
'u') <<
"xt" << SrcRegKind;
1289 if (DoShift || IsLSL) {
1302 bool SignExtend =
MI->getOperand(OpNum).getImm();
1303 bool DoShift =
MI->getOperand(OpNum + 1).getImm();
1307 template <
bool SignExtend,
int ExtW
idth,
char SrcRegKind,
char Suffix>
1313 if (Suffix ==
's' || Suffix ==
'd')
1316 assert(Suffix == 0 &&
"Unsupported suffix size");
1318 bool DoShift = ExtWidth != 8;
1319 if (SignExtend || DoShift || SrcRegKind ==
'w') {
1325 template <
int EltSize>
1330 unsigned Reg =
MI->getOperand(OpNum).getReg();
1332 assert(
Reg <= AArch64::P15 &&
"Unsupported predicate register");
1333 O <<
"pn" << (
Reg - AArch64::P0);
1376 template <
int Scale>
1384 template <
int Scale,
int Offset>
1388 unsigned FirstImm = Scale *
MI->getOperand(OpNum).getImm();
1424 unsigned prfop =
MI->getOperand(OpNum).getImm();
1425 if (
auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
1433 template <
bool IsSVEPrefetch>
1437 unsigned prfop =
MI->getOperand(OpNum).getImm();
1438 if (IsSVEPrefetch) {
1439 if (
auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1444 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1457 unsigned psbhintop =
MI->getOperand(OpNum).getImm();
1458 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1468 unsigned btihintop =
MI->getOperand(OpNum).getImm() ^ 32;
1469 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1492 case AArch64::Q0:
Reg = AArch64::Q1;
break;
1493 case AArch64::Q1:
Reg = AArch64::Q2;
break;
1494 case AArch64::Q2:
Reg = AArch64::Q3;
break;
1495 case AArch64::Q3:
Reg = AArch64::Q4;
break;
1496 case AArch64::Q4:
Reg = AArch64::Q5;
break;
1497 case AArch64::Q5:
Reg = AArch64::Q6;
break;
1498 case AArch64::Q6:
Reg = AArch64::Q7;
break;
1499 case AArch64::Q7:
Reg = AArch64::Q8;
break;
1500 case AArch64::Q8:
Reg = AArch64::Q9;
break;
1501 case AArch64::Q9:
Reg = AArch64::Q10;
break;
1502 case AArch64::Q10:
Reg = AArch64::Q11;
break;
1503 case AArch64::Q11:
Reg = AArch64::Q12;
break;
1504 case AArch64::Q12:
Reg = AArch64::Q13;
break;
1505 case AArch64::Q13:
Reg = AArch64::Q14;
break;
1506 case AArch64::Q14:
Reg = AArch64::Q15;
break;
1507 case AArch64::Q15:
Reg = AArch64::Q16;
break;
1508 case AArch64::Q16:
Reg = AArch64::Q17;
break;
1509 case AArch64::Q17:
Reg = AArch64::Q18;
break;
1510 case AArch64::Q18:
Reg = AArch64::Q19;
break;
1511 case AArch64::Q19:
Reg = AArch64::Q20;
break;
1512 case AArch64::Q20:
Reg = AArch64::Q21;
break;
1513 case AArch64::Q21:
Reg = AArch64::Q22;
break;
1514 case AArch64::Q22:
Reg = AArch64::Q23;
break;
1515 case AArch64::Q23:
Reg = AArch64::Q24;
break;
1516 case AArch64::Q24:
Reg = AArch64::Q25;
break;
1517 case AArch64::Q25:
Reg = AArch64::Q26;
break;
1518 case AArch64::Q26:
Reg = AArch64::Q27;
break;
1519 case AArch64::Q27:
Reg = AArch64::Q28;
break;
1520 case AArch64::Q28:
Reg = AArch64::Q29;
break;
1521 case AArch64::Q29:
Reg = AArch64::Q30;
break;
1522 case AArch64::Q30:
Reg = AArch64::Q31;
break;
1527 case AArch64::Z0:
Reg = AArch64::Z1;
break;
1528 case AArch64::Z1:
Reg = AArch64::Z2;
break;
1529 case AArch64::Z2:
Reg = AArch64::Z3;
break;
1530 case AArch64::Z3:
Reg = AArch64::Z4;
break;
1531 case AArch64::Z4:
Reg = AArch64::Z5;
break;
1532 case AArch64::Z5:
Reg = AArch64::Z6;
break;
1533 case AArch64::Z6:
Reg = AArch64::Z7;
break;
1534 case AArch64::Z7:
Reg = AArch64::Z8;
break;
1535 case AArch64::Z8:
Reg = AArch64::Z9;
break;
1536 case AArch64::Z9:
Reg = AArch64::Z10;
break;
1537 case AArch64::Z10:
Reg = AArch64::Z11;
break;
1538 case AArch64::Z11:
Reg = AArch64::Z12;
break;
1539 case AArch64::Z12:
Reg = AArch64::Z13;
break;
1540 case AArch64::Z13:
Reg = AArch64::Z14;
break;
1541 case AArch64::Z14:
Reg = AArch64::Z15;
break;
1542 case AArch64::Z15:
Reg = AArch64::Z16;
break;
1543 case AArch64::Z16:
Reg = AArch64::Z17;
break;
1544 case AArch64::Z17:
Reg = AArch64::Z18;
break;
1545 case AArch64::Z18:
Reg = AArch64::Z19;
break;
1546 case AArch64::Z19:
Reg = AArch64::Z20;
break;
1547 case AArch64::Z20:
Reg = AArch64::Z21;
break;
1548 case AArch64::Z21:
Reg = AArch64::Z22;
break;
1549 case AArch64::Z22:
Reg = AArch64::Z23;
break;
1550 case AArch64::Z23:
Reg = AArch64::Z24;
break;
1551 case AArch64::Z24:
Reg = AArch64::Z25;
break;
1552 case AArch64::Z25:
Reg = AArch64::Z26;
break;
1553 case AArch64::Z26:
Reg = AArch64::Z27;
break;
1554 case AArch64::Z27:
Reg = AArch64::Z28;
break;
1555 case AArch64::Z28:
Reg = AArch64::Z29;
break;
1556 case AArch64::Z29:
Reg = AArch64::Z30;
break;
1557 case AArch64::Z30:
Reg = AArch64::Z31;
break;
1562 case AArch64::P0:
Reg = AArch64::P1;
break;
1565 case AArch64::P3:
Reg = AArch64::P4;
break;
1566 case AArch64::P4:
Reg = AArch64::P5;
break;
1567 case AArch64::P5:
Reg = AArch64::P6;
break;
1568 case AArch64::P6:
Reg = AArch64::P7;
break;
1569 case AArch64::P7:
Reg = AArch64::P8;
break;
1570 case AArch64::P8:
Reg = AArch64::P9;
break;
1571 case AArch64::P9:
Reg = AArch64::P10;
break;
1572 case AArch64::P10:
Reg = AArch64::P11;
break;
1573 case AArch64::P11:
Reg = AArch64::P12;
break;
1574 case AArch64::P12:
Reg = AArch64::P13;
break;
1575 case AArch64::P13:
Reg = AArch64::P14;
break;
1576 case AArch64::P14:
Reg = AArch64::P15;
break;
1578 case AArch64::P15:
Reg = AArch64::P0;
break;
1584 template<
unsigned size>
1589 static_assert(
size == 64 ||
size == 32,
1590 "Template parameter must be either 32 or 64");
1591 unsigned Reg =
MI->getOperand(OpNum).getReg();
1593 unsigned Sube = (
size == 32) ? AArch64::sube32 : AArch64::sube64;
1594 unsigned Subo = (
size == 32) ? AArch64::subo32 : AArch64::subo64;
1606 unsigned MaxRegs = 8;
1607 unsigned RegMask =
MI->getOperand(OpNum).getImm();
1609 unsigned NumRegs = 0;
1610 for (
unsigned I = 0;
I < MaxRegs; ++
I)
1611 if ((RegMask & (1 <<
I)) != 0)
1615 unsigned Printed = 0;
1616 for (
unsigned I = 0;
I < MaxRegs; ++
I) {
1617 unsigned Reg = RegMask & (1 <<
I);
1621 if (Printed + 1 != NumRegs)
1632 unsigned Reg =
MI->getOperand(OpNum).getReg();
1638 unsigned NumRegs = 1;
1655 unsigned Stride = 1;
1681 NumRegs > 1 && Stride == 1 &&
1689 StringRef split_char = NumRegs == 2 ?
", " :
" - ";
1695 for (
unsigned i = 0;
i < NumRegs;
1704 if (
i + 1 != NumRegs)
1719 template <
unsigned NumLanes,
char LaneKind>
1723 std::string Suffix(
".");
1725 Suffix += itostr(NumLanes) + LaneKind;
1732 template <
unsigned Scale>
1736 O <<
"[" << Scale *
MI->getOperand(OpNum).getImm() <<
"]";
1742 O <<
MI->getOperand(OpNum).getImm();
1766 dyn_cast<MCConstantExpr>(
MI->getOperand(OpNum).getExpr());
1767 int64_t TargetAddress;
1785 const int64_t
Offset =
Op.getImm() * 4096;
1802 unsigned Val =
MI->getOperand(OpNo).getImm();
1803 unsigned Opcode =
MI->getOpcode();
1806 if (Opcode == AArch64::ISB) {
1807 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1808 Name = ISB ? ISB->Name :
"";
1809 }
else if (Opcode == AArch64::TSB) {
1810 auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1811 Name = TSB ? TSB->Name :
"";
1813 auto DB = AArch64DB::lookupDBByEncoding(Val);
1814 Name =
DB ?
DB->Name :
"";
1825 unsigned Val =
MI->getOperand(OpNo).getImm();
1826 assert(
MI->getOpcode() == AArch64::DSBnXS);
1829 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1830 Name =
DB ?
DB->Name :
"";
1840 return (
Reg && (Read ?
Reg->Readable :
Reg->Writeable) &&
1863 unsigned Val =
MI->getOperand(OpNo).getImm();
1868 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1869 O <<
"DBGDTRRX_EL0";
1874 if (Val == AArch64SysReg::TRCEXTINSELR) {
1875 O <<
"TRCEXTINSELR";
1890 unsigned Val =
MI->getOperand(OpNo).getImm();
1895 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1896 O <<
"DBGDTRTX_EL0";
1901 if (Val == AArch64SysReg::TRCEXTINSELR) {
1902 O <<
"TRCEXTINSELR";
1917 unsigned Val =
MI->getOperand(OpNo).getImm();
1919 auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val);
1920 auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val);
1921 if (PStateImm15 && PStateImm15->haveFeatures(STI.
getFeatureBits()))
1922 O << PStateImm15->Name;
1923 else if (PStateImm1 && PStateImm1->haveFeatures(STI.
getFeatureBits()))
1924 O << PStateImm1->Name;
1932 unsigned RawVal =
MI->getOperand(OpNo).getImm();
1937 template<
int64_t Angle,
int64_t Remainder>
1941 unsigned Val =
MI->getOperand(OpNo).getImm();
1942 O <<
markup(
"<imm:") <<
"#" << (Val * Angle) + Remainder <<
markup(
">");
1948 unsigned Val =
MI->getOperand(OpNum).getImm();
1949 if (
auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1959 unsigned Val =
MI->getOperand(OpNum).getImm();
1964 AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
1970 template <
char suffix>
1985 unsigned Reg =
MI->getOperand(OpNum).getReg();
1991 template <
typename T>
1993 std::make_unsigned_t<T> HexValue =
Value;
2009 template <
typename T>
2013 unsigned UnscaledVal =
MI->getOperand(OpNum).getImm();
2014 unsigned Shift =
MI->getOperand(OpNum + 1).getImm();
2016 "Unexepected shift type!");
2026 if (std::is_signed<T>())
2034 template <
typename T>
2038 typedef std::make_signed_t<T> SignedT;
2039 typedef std::make_unsigned_t<T> UnsignedT;
2041 uint64_t Val =
MI->getOperand(OpNum).getImm();
2045 if ((int16_t)PrintVal == (SignedT)PrintVal)
2047 else if ((
uint16_t)PrintVal == PrintVal)
2053 template <
int W
idth>
2059 case 8:
Base = AArch64::B0;
break;
2060 case 16:
Base = AArch64::H0;
break;
2061 case 32:
Base = AArch64::S0;
break;
2062 case 64:
Base = AArch64::D0;
break;
2063 case 128:
Base = AArch64::Q0;
break;
2067 unsigned Reg =
MI->getOperand(OpNum).getReg();
2071 template <
unsigned ImmIs0,
unsigned ImmIs1>
2075 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
2076 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
2077 unsigned Val =
MI->getOperand(OpNum).getImm();
2078 O <<
markup(
"<imm:") <<
"#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr)
2085 unsigned Reg =
MI->getOperand(OpNum).getReg();
2092 unsigned Reg =
MI->getOperand(OpNum).getReg();
2099 unsigned Reg =
MI->getOperand(OpNum).getReg();
2101 "MC representation of SyspXzrPair should be XZR");