LLVM 17.0.0git
AArch64InstPrinter.cpp
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1//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an AArch64 MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64InstPrinter.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "Utils/AArch64BaseInfo.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/Casting.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/Format.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31#include <string>
32
33using namespace llvm;
34
35#define DEBUG_TYPE "asm-printer"
36
37#define GET_INSTRUCTION_NAME
38#define PRINT_ALIAS_INSTR
39#include "AArch64GenAsmWriter.inc"
40#define GET_INSTRUCTION_NAME
41#define PRINT_ALIAS_INSTR
42#include "AArch64GenAsmWriter1.inc"
43
44AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
45 const MCInstrInfo &MII,
46 const MCRegisterInfo &MRI)
47 : MCInstPrinter(MAI, MII, MRI) {}
48
49AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
50 const MCInstrInfo &MII,
51 const MCRegisterInfo &MRI)
52 : AArch64InstPrinter(MAI, MII, MRI) {}
53
54bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
55 if (Opt == "no-aliases") {
56 PrintAliases = false;
57 return true;
58 }
59 return false;
60}
61
62void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
63 OS << markup("<reg:") << getRegisterName(Reg) << markup(">");
64}
65
66void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
67 unsigned AltIdx) const {
68 OS << markup("<reg:") << getRegisterName(Reg, AltIdx) << markup(">");
69}
70
71StringRef AArch64InstPrinter::getRegName(MCRegister Reg) const {
72 return getRegisterName(Reg);
73}
74
75void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
76 StringRef Annot, const MCSubtargetInfo &STI,
77 raw_ostream &O) {
78 // Check for special encodings and print the canonical alias instead.
79
80 unsigned Opcode = MI->getOpcode();
81
82 if (Opcode == AArch64::SYSxt)
83 if (printSysAlias(MI, STI, O)) {
84 printAnnotation(O, Annot);
85 return;
86 }
87
88 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
89 if (printSyspAlias(MI, STI, O)) {
90 printAnnotation(O, Annot);
91 return;
92 }
93
94 // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
95 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
96 if (printRangePrefetchAlias(MI, STI, O, Annot))
97 return;
98 }
99
100 // SBFM/UBFM should print to a nicer aliased form if possible.
101 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
102 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
103 const MCOperand &Op0 = MI->getOperand(0);
104 const MCOperand &Op1 = MI->getOperand(1);
105 const MCOperand &Op2 = MI->getOperand(2);
106 const MCOperand &Op3 = MI->getOperand(3);
107
108 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
109 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
110 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
111 const char *AsmMnemonic = nullptr;
112
113 switch (Op3.getImm()) {
114 default:
115 break;
116 case 7:
117 if (IsSigned)
118 AsmMnemonic = "sxtb";
119 else if (!Is64Bit)
120 AsmMnemonic = "uxtb";
121 break;
122 case 15:
123 if (IsSigned)
124 AsmMnemonic = "sxth";
125 else if (!Is64Bit)
126 AsmMnemonic = "uxth";
127 break;
128 case 31:
129 // *xtw is only valid for signed 64-bit operations.
130 if (Is64Bit && IsSigned)
131 AsmMnemonic = "sxtw";
132 break;
133 }
134
135 if (AsmMnemonic) {
136 O << '\t' << AsmMnemonic << '\t';
137 printRegName(O, Op0.getReg());
138 O << ", ";
139 printRegName(O, getWRegFromXReg(Op1.getReg()));
140 printAnnotation(O, Annot);
141 return;
142 }
143 }
144
145 // All immediate shifts are aliases, implemented using the Bitfield
146 // instruction. In all cases the immediate shift amount shift must be in
147 // the range 0 to (reg.size -1).
148 if (Op2.isImm() && Op3.isImm()) {
149 const char *AsmMnemonic = nullptr;
150 int shift = 0;
151 int64_t immr = Op2.getImm();
152 int64_t imms = Op3.getImm();
153 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
154 AsmMnemonic = "lsl";
155 shift = 31 - imms;
156 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
157 ((imms + 1 == immr))) {
158 AsmMnemonic = "lsl";
159 shift = 63 - imms;
160 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
161 AsmMnemonic = "lsr";
162 shift = immr;
163 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
164 AsmMnemonic = "lsr";
165 shift = immr;
166 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
167 AsmMnemonic = "asr";
168 shift = immr;
169 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
170 AsmMnemonic = "asr";
171 shift = immr;
172 }
173 if (AsmMnemonic) {
174 O << '\t' << AsmMnemonic << '\t';
175 printRegName(O, Op0.getReg());
176 O << ", ";
177 printRegName(O, Op1.getReg());
178 O << ", " << markup("<imm:") << "#" << shift << markup(">");
179 printAnnotation(O, Annot);
180 return;
181 }
182 }
183
184 // SBFIZ/UBFIZ aliases
185 if (Op2.getImm() > Op3.getImm()) {
186 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
187 printRegName(O, Op0.getReg());
188 O << ", ";
189 printRegName(O, Op1.getReg());
190 O << ", " << markup("<imm:") << "#" << (Is64Bit ? 64 : 32) - Op2.getImm()
191 << markup(">") << ", " << markup("<imm:") << "#" << Op3.getImm() + 1
192 << markup(">");
193 printAnnotation(O, Annot);
194 return;
195 }
196
197 // Otherwise SBFX/UBFX is the preferred form
198 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
199 printRegName(O, Op0.getReg());
200 O << ", ";
201 printRegName(O, Op1.getReg());
202 O << ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">") << ", "
203 << markup("<imm:") << "#" << Op3.getImm() - Op2.getImm() + 1
204 << markup(">");
205 printAnnotation(O, Annot);
206 return;
207 }
208
209 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
210 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
211 const MCOperand &Op2 = MI->getOperand(2);
212 int ImmR = MI->getOperand(3).getImm();
213 int ImmS = MI->getOperand(4).getImm();
214
215 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
216 (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) {
217 // BFC takes precedence over its entire range, sligtly differently to BFI.
218 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
219 int LSB = (BitWidth - ImmR) % BitWidth;
220 int Width = ImmS + 1;
221
222 O << "\tbfc\t";
223 printRegName(O, Op0.getReg());
224 O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
225 << markup("<imm:") << "#" << Width << markup(">");
226 printAnnotation(O, Annot);
227 return;
228 } else if (ImmS < ImmR) {
229 // BFI alias
230 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
231 int LSB = (BitWidth - ImmR) % BitWidth;
232 int Width = ImmS + 1;
233
234 O << "\tbfi\t";
235 printRegName(O, Op0.getReg());
236 O << ", ";
237 printRegName(O, Op2.getReg());
238 O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
239 << markup("<imm:") << "#" << Width << markup(">");
240 printAnnotation(O, Annot);
241 return;
242 }
243
244 int LSB = ImmR;
245 int Width = ImmS - ImmR + 1;
246 // Otherwise BFXIL the preferred form
247 O << "\tbfxil\t";
248 printRegName(O, Op0.getReg());
249 O << ", ";
250 printRegName(O, Op2.getReg());
251 O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
252 << markup("<imm:") << "#" << Width << markup(">");
253 printAnnotation(O, Annot);
254 return;
255 }
256
257 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
258 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
259 // printed.
260 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
261 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
262 MI->getOperand(1).isExpr()) {
263 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
264 O << "\tmovz\t";
265 else
266 O << "\tmovn\t";
267
268 printRegName(O, MI->getOperand(0).getReg());
269 O << ", " << markup("<imm:") << "#";
270 MI->getOperand(1).getExpr()->print(O, &MAI);
271 O << markup(">");
272 return;
273 }
274
275 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
276 MI->getOperand(2).isExpr()) {
277 O << "\tmovk\t";
278 printRegName(O, MI->getOperand(0).getReg());
279 O << ", " << markup("<imm:") << "#";
280 MI->getOperand(2).getExpr()->print(O, &MAI);
281 O << markup(">");
282 return;
283 }
284
285 auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
286 int64_t SExtVal = SignExtend64(Value, RegWidth);
287 O << "\tmov\t";
288 printRegName(O, MI->getOperand(0).getReg());
289 O << ", " << markup("<imm:") << "#"
290 << formatImm(SExtVal) << markup(">");
291 if (CommentStream) {
292 // Do the opposite to that used for instruction operands.
293 if (getPrintImmHex())
294 *CommentStream << '=' << formatDec(SExtVal) << '\n';
295 else {
296 uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
297 *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
298 }
299 }
300 };
301
302 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
303 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
304 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
305 // that can represent the move is the MOV alias, and the rest get printed
306 // normally.
307 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
308 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
309 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
310 int Shift = MI->getOperand(2).getImm();
311 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
312
313 if (AArch64_AM::isMOVZMovAlias(Value, Shift,
314 Opcode == AArch64::MOVZXi ? 64 : 32)) {
315 PrintMovImm(Value, RegWidth);
316 return;
317 }
318 }
319
320 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
321 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
322 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
323 int Shift = MI->getOperand(2).getImm();
324 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
325 if (RegWidth == 32)
326 Value = Value & 0xffffffff;
327
328 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
329 PrintMovImm(Value, RegWidth);
330 return;
331 }
332 }
333
334 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
335 (MI->getOperand(1).getReg() == AArch64::XZR ||
336 MI->getOperand(1).getReg() == AArch64::WZR) &&
337 MI->getOperand(2).isImm()) {
338 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
339 uint64_t Value = AArch64_AM::decodeLogicalImmediate(
340 MI->getOperand(2).getImm(), RegWidth);
341 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
342 PrintMovImm(Value, RegWidth);
343 return;
344 }
345 }
346
347 if (Opcode == AArch64::SPACE) {
348 O << '\t' << MAI.getCommentString() << " SPACE "
349 << MI->getOperand(1).getImm();
350 printAnnotation(O, Annot);
351 return;
352 }
353
354 // Instruction TSB is specified as a one operand instruction, but 'csync' is
355 // not encoded, so for printing it is treated as a special case here:
356 if (Opcode == AArch64::TSB) {
357 O << "\ttsb\tcsync";
358 return;
359 }
360
361 if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
362 printInstruction(MI, Address, STI, O);
363
364 printAnnotation(O, Annot);
365
366 if (atomicBarrierDroppedOnZero(Opcode) &&
367 (MI->getOperand(0).getReg() == AArch64::XZR ||
368 MI->getOperand(0).getReg() == AArch64::WZR)) {
369 printAnnotation(O, "acquire semantics dropped since destination is zero");
370 }
371}
372
373static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
374 bool &IsTbx) {
375 switch (Opcode) {
376 case AArch64::TBXv8i8One:
377 case AArch64::TBXv8i8Two:
378 case AArch64::TBXv8i8Three:
379 case AArch64::TBXv8i8Four:
380 IsTbx = true;
381 Layout = ".8b";
382 return true;
383 case AArch64::TBLv8i8One:
384 case AArch64::TBLv8i8Two:
385 case AArch64::TBLv8i8Three:
386 case AArch64::TBLv8i8Four:
387 IsTbx = false;
388 Layout = ".8b";
389 return true;
390 case AArch64::TBXv16i8One:
391 case AArch64::TBXv16i8Two:
392 case AArch64::TBXv16i8Three:
393 case AArch64::TBXv16i8Four:
394 IsTbx = true;
395 Layout = ".16b";
396 return true;
397 case AArch64::TBLv16i8One:
398 case AArch64::TBLv16i8Two:
399 case AArch64::TBLv16i8Three:
400 case AArch64::TBLv16i8Four:
401 IsTbx = false;
402 Layout = ".16b";
403 return true;
404 default:
405 return false;
406 }
407}
408
409struct LdStNInstrDesc {
410 unsigned Opcode;
411 const char *Mnemonic;
412 const char *Layout;
413 int ListOperand;
414 bool HasLane;
415 int NaturalOffset;
416};
417
418static const LdStNInstrDesc LdStNInstInfo[] = {
419 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
420 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
421 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
422 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
423 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
424 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
425 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
426 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
427 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
428 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
429 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
430 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
431 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
432 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
433 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
434 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
435 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
436 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
437 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
438 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
439 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
440 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
441 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
442 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
443 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
444 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
445 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
446 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
447 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
448 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
449 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
450 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
451 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
452 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
453 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
454 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
455 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
456 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
457 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
458 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
459 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
460 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
461 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
462 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
463 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
464 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
465 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
466 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
467 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
468 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
469 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
470 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
471 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
472 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
473 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
474 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
475 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
476 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
477 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
478 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
479 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
480 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
481 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
482 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
483 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
484 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
485 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
486 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
487 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
488 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
489 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
490 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
491 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
492 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
493 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
494 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
495 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
496 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
497 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
498 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
499 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
500 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
501 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
502 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
503 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
504 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
505 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
506 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
507 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
508 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
509 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
510 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
511 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
512 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
513 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
514 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
515 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
516 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
517 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
518 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
519 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
520 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
521 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
522 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
523 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
524 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
525 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
526 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
527 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
528 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
529 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
530 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
531 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
532 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
533 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
534 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
535 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
536 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
537 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
538 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
539 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
540 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
541 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
542 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
543 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
544 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
545 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
546 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
547 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
548 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
549 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
550 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
551 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
552 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
553 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
554 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
555 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
556 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
557 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
558 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
559 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
560 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
561 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
562 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
563 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
564 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
565 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
566 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
567 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
568 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
569 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
570 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
571 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
572 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
573 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
574 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
575 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
576 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
577 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
578 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
579 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
580 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
581 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
582 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
583 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
584 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
585 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
586 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
587 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
588 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
589 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
590 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
591 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
592 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
593 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
594 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
595 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
596 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
597 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
598 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
599 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
600 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
601 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
602 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
603 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
604 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
605 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
606 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
607 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
608 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
609 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
610 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
611 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
612 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
613 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
614 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
615 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
616 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
617 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
618 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
619 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
620 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
621 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
622 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
623 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
624 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
625 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
626 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
627 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
628 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
629 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
630 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
631 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
632 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
633 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
634 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
635 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
636 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
637 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
638 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
639 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
640 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
641 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
642 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
643 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
644 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
645 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
646 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
647 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
648 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
649 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
650 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
651 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
652 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
653 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
654 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
655 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
656 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
657 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
658 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
659 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
660 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
661 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
662 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
663 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
664 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
665 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
666 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
667 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
668 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
669 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
670 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
671 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
672 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
673 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
674 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
675 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
676 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
677 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
678 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
679 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
680 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
681 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
682 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
683 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
684 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
685 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
686 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
687 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
688 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
689 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
690 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
691 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
692 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
693 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
694 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
695 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
696 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
697 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
698 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
699 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
700 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
701 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
702 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
703 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
704 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
705 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
706 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
707 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
708 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
709 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
710 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
711 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
712 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
713 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
714 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
715 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
716 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
717 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
718 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
719 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
720 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
721 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
722 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
723 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
724 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
725 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
726 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
727 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
728 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
729 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
730 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
731 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
732 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
733 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
734 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
735 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
736 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
737 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
738 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
739 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
740 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
741 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
742 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
743 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
744 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
745 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
746 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
747 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
748 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
749 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
750 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
751 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
752 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
753 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
754 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
755 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
756 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
757 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
758 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
759};
760
761static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
762 for (const auto &Info : LdStNInstInfo)
763 if (Info.Opcode == Opcode)
764 return &Info;
765
766 return nullptr;
767}
768
769void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
770 StringRef Annot,
771 const MCSubtargetInfo &STI,
772 raw_ostream &O) {
773 unsigned Opcode = MI->getOpcode();
774 StringRef Layout;
775
776 bool IsTbx;
777 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
778 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
779 printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
780 O << ", ";
781
782 unsigned ListOpNum = IsTbx ? 2 : 1;
783 printVectorList(MI, ListOpNum, STI, O, "");
784
785 O << ", ";
786 printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
787 printAnnotation(O, Annot);
788 return;
789 }
790
791 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
792 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
793
794 // Now onto the operands: first a vector list with possible lane
795 // specifier. E.g. { v0 }[2]
796 int OpNum = LdStDesc->ListOperand;
797 printVectorList(MI, OpNum++, STI, O, "");
798
799 if (LdStDesc->HasLane)
800 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
801
802 // Next the address: [xN]
803 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
804 O << ", [";
805 printRegName(O, AddrReg);
806 O << ']';
807
808 // Finally, there might be a post-indexed offset.
809 if (LdStDesc->NaturalOffset != 0) {
810 unsigned Reg = MI->getOperand(OpNum++).getReg();
811 if (Reg != AArch64::XZR) {
812 O << ", ";
813 printRegName(O, Reg);
814 } else {
815 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
816 O << ", " << markup("<imm:") << "#" << LdStDesc->NaturalOffset
817 << markup(">");
818 }
819 }
820
821 printAnnotation(O, Annot);
822 return;
823 }
824
825 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
826}
827
828StringRef AArch64AppleInstPrinter::getRegName(MCRegister Reg) const {
829 return getRegisterName(Reg);
830}
831
832bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
833 const MCSubtargetInfo &STI,
834 raw_ostream &O,
835 StringRef Annot) {
836 unsigned Opcode = MI->getOpcode();
837
838#ifndef NDEBUG
839 assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) &&
840 "Invalid opcode for RPRFM alias!");
841#endif
842
843 unsigned PRFOp = MI->getOperand(0).getImm();
844 unsigned Mask = 0x18; // 0b11000
845 if ((PRFOp & Mask) != Mask)
846 return false; // Rt != '11xxx', it's a PRFM instruction.
847
848 unsigned Rm = MI->getOperand(2).getReg();
849
850 // "Rm" must be a 64-bit GPR for RPRFM.
851 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
852 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32,
853 &MRI.getRegClass(AArch64::GPR64RegClassID));
854
855 unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
856 unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
857
858 assert((SignExtend <= 1) && "sign extend should be a single bit!");
859 assert((Shift <= 1) && "Shift should be a single bit!");
860
861 unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
862
863 // encoded in "option<2>:option<0>:S:Rt<2:0>".
864 unsigned RPRFOp =
865 (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);
866
867 O << "\trprfm ";
868 if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp))
869 O << RPRFM->Name << ", ";
870 else
871 O << "#" << formatImm(RPRFOp) << ", ";
872 O << getRegisterName(Rm);
873 O << ", [";
874 printOperand(MI, 1, STI, O); // "Rn".
875 O << "]";
876
877 printAnnotation(O, Annot);
878
879 return true;
880}
881
882bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
883 const MCSubtargetInfo &STI,
884 raw_ostream &O) {
885#ifndef NDEBUG
886 unsigned Opcode = MI->getOpcode();
887 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
888#endif
889
890 const MCOperand &Op1 = MI->getOperand(0);
891 const MCOperand &Cn = MI->getOperand(1);
892 const MCOperand &Cm = MI->getOperand(2);
893 const MCOperand &Op2 = MI->getOperand(3);
894
895 unsigned Op1Val = Op1.getImm();
896 unsigned CnVal = Cn.getImm();
897 unsigned CmVal = Cm.getImm();
898 unsigned Op2Val = Op2.getImm();
899
900 uint16_t Encoding = Op2Val;
901 Encoding |= CmVal << 3;
902 Encoding |= CnVal << 7;
903 Encoding |= Op1Val << 11;
904
905 bool NeedsReg;
906 std::string Ins;
907 std::string Name;
908
909 if (CnVal == 7) {
910 switch (CmVal) {
911 default: return false;
912 // Maybe IC, maybe Prediction Restriction
913 case 1:
914 switch (Op1Val) {
915 default: return false;
916 case 0: goto Search_IC;
917 case 3: goto Search_PRCTX;
918 }
919 // Prediction Restriction aliases
920 case 3: {
921 Search_PRCTX:
922 if (Op1Val != 3 || CnVal != 7 || CmVal != 3)
923 return false;
924
925 const auto Requires =
926 Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes;
927 if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
928 return false;
929
930 NeedsReg = true;
931 switch (Op2Val) {
932 default: return false;
933 case 4: Ins = "cfp\t"; break;
934 case 5: Ins = "dvp\t"; break;
935 case 6: Ins = "cosp\t"; break;
936 case 7: Ins = "cpp\t"; break;
937 }
938 Name = "RCTX";
939 }
940 break;
941 // IC aliases
942 case 5: {
943 Search_IC:
944 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
945 if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
946 return false;
947
948 NeedsReg = IC->NeedsReg;
949 Ins = "ic\t";
950 Name = std::string(IC->Name);
951 }
952 break;
953 // DC aliases
954 case 4: case 6: case 10: case 11: case 12: case 13: case 14:
955 {
956 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
957 if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
958 return false;
959
960 NeedsReg = true;
961 Ins = "dc\t";
962 Name = std::string(DC->Name);
963 }
964 break;
965 // AT aliases
966 case 8: case 9: {
967 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
968 if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
969 return false;
970
971 NeedsReg = true;
972 Ins = "at\t";
973 Name = std::string(AT->Name);
974 }
975 break;
976 }
977 } else if (CnVal == 8 || CnVal == 9) {
978 // TLBI aliases
979 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
980 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
981 return false;
982
983 NeedsReg = TLBI->NeedsReg;
984 Ins = "tlbi\t";
985 Name = std::string(TLBI->Name);
986 }
987 else
988 return false;
989
990 std::string Str = Ins + Name;
991 std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
992
993 O << '\t' << Str;
994 if (NeedsReg) {
995 O << ", ";
996 printRegName(O, MI->getOperand(4).getReg());
997 }
998
999 return true;
1000}
1001
1002bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
1003 const MCSubtargetInfo &STI,
1004 raw_ostream &O) {
1005#ifndef NDEBUG
1006 unsigned Opcode = MI->getOpcode();
1007 assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
1008 "Invalid opcode for SYSP alias!");
1009#endif
1010
1011 const MCOperand &Op1 = MI->getOperand(0);
1012 const MCOperand &Cn = MI->getOperand(1);
1013 const MCOperand &Cm = MI->getOperand(2);
1014 const MCOperand &Op2 = MI->getOperand(3);
1015
1016 unsigned Op1Val = Op1.getImm();
1017 unsigned CnVal = Cn.getImm();
1018 unsigned CmVal = Cm.getImm();
1019 unsigned Op2Val = Op2.getImm();
1020
1021 uint16_t Encoding = Op2Val;
1022 Encoding |= CmVal << 3;
1023 Encoding |= CnVal << 7;
1024 Encoding |= Op1Val << 11;
1025
1026 std::string Ins;
1027 std::string Name;
1028
1029 if (CnVal == 8 || CnVal == 9) {
1030 // TLBIP aliases
1031
1032 if (CnVal == 9) {
1033 if (!STI.hasFeature(AArch64::FeatureXS))
1034 return false;
1035 Encoding &= ~(1 << 7);
1036 }
1037
1038 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1039 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1040 return false;
1041
1042 Ins = "tlbip\t";
1043 Name = std::string(TLBI->Name);
1044 if (CnVal == 9)
1045 Name += "nXS";
1046 } else
1047 return false;
1048
1049 std::string Str = Ins + Name;
1050 std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
1051
1052 O << '\t' << Str;
1053 O << ", ";
1054 if (MI->getOperand(4).getReg() == AArch64::XZR)
1055 printSyspXzrPair(MI, 4, STI, O);
1056 else
1057 printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
1058
1059 return true;
1060}
1061
1062template <int EltSize>
1063void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
1064 const MCSubtargetInfo &STI,
1065 raw_ostream &O) {
1066 const MCOperand &RegOp = MI->getOperand(OpNum);
1067 assert(RegOp.isReg() && "Unexpected operand type!");
1068
1069 printRegName(O, RegOp.getReg());
1070 switch (EltSize) {
1071 case 0:
1072 break;
1073 case 8:
1074 O << ".b";
1075 break;
1076 case 16:
1077 O << ".h";
1078 break;
1079 case 32:
1080 O << ".s";
1081 break;
1082 case 64:
1083 O << ".d";
1084 break;
1085 case 128:
1086 O << ".q";
1087 break;
1088 default:
1089 llvm_unreachable("Unsupported element size");
1090 }
1091}
1092
1093template <bool IsVertical>
1094void AArch64InstPrinter::printMatrixTileVector(const MCInst *MI, unsigned OpNum,
1095 const MCSubtargetInfo &STI,
1096 raw_ostream &O) {
1097 const MCOperand &RegOp = MI->getOperand(OpNum);
1098 assert(RegOp.isReg() && "Unexpected operand type!");
1099 StringRef RegName = getRegisterName(RegOp.getReg());
1100
1101 // Insert the horizontal/vertical flag before the suffix.
1102 StringRef Base, Suffix;
1103 std::tie(Base, Suffix) = RegName.split('.');
1104 O << Base << (IsVertical ? "v" : "h") << '.' << Suffix;
1105}
1106
1107void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
1108 const MCSubtargetInfo &STI,
1109 raw_ostream &O) {
1110 const MCOperand &RegOp = MI->getOperand(OpNum);
1111 assert(RegOp.isReg() && "Unexpected operand type!");
1112 printRegName(O, RegOp.getReg());
1113}
1114
1115void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
1116 const MCSubtargetInfo &STI,
1117 raw_ostream &O) {
1118 const MCOperand &MO = MI->getOperand(OpNum);
1119 assert(MO.isImm() && "Unexpected operand type!");
1120 unsigned svcrop = MO.getImm();
1121 const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
1122 assert(SVCR && "Unexpected SVCR operand!");
1123 O << SVCR->Name;
1124}
1125
1126void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1127 const MCSubtargetInfo &STI,
1128 raw_ostream &O) {
1129 const MCOperand &Op = MI->getOperand(OpNo);
1130 if (Op.isReg()) {
1131 unsigned Reg = Op.getReg();
1132 printRegName(O, Reg);
1133 } else if (Op.isImm()) {
1134 printImm(MI, OpNo, STI, O);
1135 } else {
1136 assert(Op.isExpr() && "unknown operand kind in printOperand");
1137 Op.getExpr()->print(O, &MAI);
1138 }
1139}
1140
1141void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
1142 const MCSubtargetInfo &STI,
1143 raw_ostream &O) {
1144 const MCOperand &Op = MI->getOperand(OpNo);
1145 O << markup("<imm:") << "#" << formatImm(Op.getImm()) << markup(">");
1146}
1147
1148void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
1149 const MCSubtargetInfo &STI,
1150 raw_ostream &O) {
1151 const MCOperand &Op = MI->getOperand(OpNo);
1152 O << markup("<imm:") << format("#%#llx", Op.getImm()) << markup(">");
1153}
1154
1155template<int Size>
1156void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
1157 const MCSubtargetInfo &STI,
1158 raw_ostream &O) {
1159 const MCOperand &Op = MI->getOperand(OpNo);
1160 if (Size == 8)
1161 O << markup("<imm:") << "#" << formatImm((signed char)Op.getImm())
1162 << markup(">");
1163 else if (Size == 16)
1164 O << markup("<imm:") << "#" << formatImm((signed short)Op.getImm())
1165 << markup(">");
1166 else
1167 O << markup("<imm:") << "#" << formatImm(Op.getImm()) << markup(">");
1168}
1169
1170void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
1171 unsigned Imm, raw_ostream &O) {
1172 const MCOperand &Op = MI->getOperand(OpNo);
1173 if (Op.isReg()) {
1174 unsigned Reg = Op.getReg();
1175 if (Reg == AArch64::XZR)
1176 O << markup("<imm:") << "#" << Imm << markup(">");
1177 else
1178 printRegName(O, Reg);
1179 } else
1180 llvm_unreachable("unknown operand kind in printPostIncOperand64");
1181}
1182
1183void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
1184 const MCSubtargetInfo &STI,
1185 raw_ostream &O) {
1186 const MCOperand &Op = MI->getOperand(OpNo);
1187 assert(Op.isReg() && "Non-register vreg operand!");
1188 unsigned Reg = Op.getReg();
1189 printRegName(O, Reg, AArch64::vreg);
1190}
1191
1192void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
1193 const MCSubtargetInfo &STI,
1194 raw_ostream &O) {
1195 const MCOperand &Op = MI->getOperand(OpNo);
1196 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1197 O << "c" << Op.getImm();
1198}
1199
1200void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1201 const MCSubtargetInfo &STI,
1202 raw_ostream &O) {
1203 const MCOperand &MO = MI->getOperand(OpNum);
1204 if (MO.isImm()) {
1205 unsigned Val = (MO.getImm() & 0xfff);
1206 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1207 unsigned Shift =
1208 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1209 O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
1210 if (Shift != 0) {
1211 printShifter(MI, OpNum + 1, STI, O);
1212 if (CommentStream)
1213 *CommentStream << '=' << formatImm(Val << Shift) << '\n';
1214 }
1215 } else {
1216 assert(MO.isExpr() && "Unexpected operand type!");
1217 MO.getExpr()->print(O, &MAI);
1218 printShifter(MI, OpNum + 1, STI, O);
1219 }
1220}
1221
1222template <typename T>
1223void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
1224 const MCSubtargetInfo &STI,
1225 raw_ostream &O) {
1226 uint64_t Val = MI->getOperand(OpNum).getImm();
1227 O << markup("<imm:") << "#0x";
1228 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
1229 O << markup(">");
1230}
1231
1232void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1233 const MCSubtargetInfo &STI,
1234 raw_ostream &O) {
1235 unsigned Val = MI->getOperand(OpNum).getImm();
1236 // LSL #0 should not be printed.
1237 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
1238 AArch64_AM::getShiftValue(Val) == 0)
1239 return;
1240 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
1241 << " " << markup("<imm:") << "#" << AArch64_AM::getShiftValue(Val)
1242 << markup(">");
1243}
1244
1245void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
1246 const MCSubtargetInfo &STI,
1247 raw_ostream &O) {
1248 printRegName(O, MI->getOperand(OpNum).getReg());
1249 printShifter(MI, OpNum + 1, STI, O);
1250}
1251
1252void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1253 const MCSubtargetInfo &STI,
1254 raw_ostream &O) {
1255 printRegName(O, MI->getOperand(OpNum).getReg());
1256 printArithExtend(MI, OpNum + 1, STI, O);
1257}
1258
1259void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1260 const MCSubtargetInfo &STI,
1261 raw_ostream &O) {
1262 unsigned Val = MI->getOperand(OpNum).getImm();
1263 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1264 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1265
1266 // If the destination or first source register operand is [W]SP, print
1267 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1268 // all.
1269 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1270 unsigned Dest = MI->getOperand(0).getReg();
1271 unsigned Src1 = MI->getOperand(1).getReg();
1272 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1273 ExtType == AArch64_AM::UXTX) ||
1274 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1275 ExtType == AArch64_AM::UXTW) ) {
1276 if (ShiftVal != 0)
1277 O << ", lsl " << markup("<imm:") << "#" << ShiftVal << markup(">");
1278 return;
1279 }
1280 }
1281 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1282 if (ShiftVal != 0)
1283 O << " " << markup("<imm:") << "#" << ShiftVal << markup(">");
1284}
1285
1286static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width,
1287 char SrcRegKind, raw_ostream &O,
1288 bool UseMarkup) {
1289 // sxtw, sxtx, uxtw or lsl (== uxtx)
1290 bool IsLSL = !SignExtend && SrcRegKind == 'x';
1291 if (IsLSL)
1292 O << "lsl";
1293 else
1294 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1295
1296 if (DoShift || IsLSL) {
1297 O << " ";
1298 if (UseMarkup)
1299 O << "<imm:";
1300 O << "#" << Log2_32(Width / 8);
1301 if (UseMarkup)
1302 O << ">";
1303 }
1304}
1305
1306void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1307 raw_ostream &O, char SrcRegKind,
1308 unsigned Width) {
1309 bool SignExtend = MI->getOperand(OpNum).getImm();
1310 bool DoShift = MI->getOperand(OpNum + 1).getImm();
1311 printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O, UseMarkup);
1312}
1313
1314template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
1315void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
1316 unsigned OpNum,
1317 const MCSubtargetInfo &STI,
1318 raw_ostream &O) {
1319 printOperand(MI, OpNum, STI, O);
1320 if (Suffix == 's' || Suffix == 'd')
1321 O << '.' << Suffix;
1322 else
1323 assert(Suffix == 0 && "Unsupported suffix size");
1324
1325 bool DoShift = ExtWidth != 8;
1326 if (SignExtend || DoShift || SrcRegKind == 'w') {
1327 O << ", ";
1328 printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O, UseMarkup);
1329 }
1330}
1331
1332template <int EltSize>
1333void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
1334 unsigned OpNum,
1335 const MCSubtargetInfo &STI,
1336 raw_ostream &O) {
1337 unsigned Reg = MI->getOperand(OpNum).getReg();
1338
1339 assert(Reg <= AArch64::P15 && "Unsupported predicate register");
1340 O << "pn" << (Reg - AArch64::P0);
1341 switch (EltSize) {
1342 case 0:
1343 break;
1344 case 8:
1345 O << ".b";
1346 break;
1347 case 16:
1348 O << ".h";
1349 break;
1350 case 32:
1351 O << ".s";
1352 break;
1353 case 64:
1354 O << ".d";
1355 break;
1356 default:
1357 llvm_unreachable("Unsupported element size");
1358 }
1359}
1360
1361void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1362 const MCSubtargetInfo &STI,
1363 raw_ostream &O) {
1364 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1365 O << AArch64CC::getCondCodeName(CC);
1366}
1367
1368void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1369 const MCSubtargetInfo &STI,
1370 raw_ostream &O) {
1371 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1372 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1373}
1374
1375void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1376 const MCSubtargetInfo &STI,
1377 raw_ostream &O) {
1378 O << '[';
1379 printRegName(O, MI->getOperand(OpNum).getReg());
1380 O << ']';
1381}
1382
1383template <int Scale>
1384void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1385 const MCSubtargetInfo &STI,
1386 raw_ostream &O) {
1387 O << markup("<imm:") << '#'
1388 << formatImm(Scale * MI->getOperand(OpNum).getImm()) << markup(">");
1389}
1390
1391template <int Scale, int Offset>
1392void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
1393 const MCSubtargetInfo &STI,
1394 raw_ostream &O) {
1395 unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
1396 O << formatImm(FirstImm);
1397 O << ":" << formatImm(FirstImm + Offset);
1398}
1399
1400void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1401 unsigned Scale, raw_ostream &O) {
1402 const MCOperand MO = MI->getOperand(OpNum);
1403 if (MO.isImm()) {
1404 O << markup("<imm:") << '#' << formatImm(MO.getImm() * Scale)
1405 << markup(">");
1406 } else {
1407 assert(MO.isExpr() && "Unexpected operand type!");
1408 MO.getExpr()->print(O, &MAI);
1409 }
1410}
1411
1412void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1413 unsigned Scale, raw_ostream &O) {
1414 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1415 O << '[';
1416 printRegName(O, MI->getOperand(OpNum).getReg());
1417 if (MO1.isImm()) {
1418 O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale)
1419 << markup(">");
1420 } else {
1421 assert(MO1.isExpr() && "Unexpected operand type!");
1422 O << ", ";
1423 MO1.getExpr()->print(O, &MAI);
1424 }
1425 O << ']';
1426}
1427
1428void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
1429 const MCSubtargetInfo &STI,
1430 raw_ostream &O) {
1431 unsigned prfop = MI->getOperand(OpNum).getImm();
1432 if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) {
1433 O << PRFM->Name;
1434 return;
1435 }
1436
1437 O << '#' << formatImm(prfop);
1438}
1439
1440template <bool IsSVEPrefetch>
1441void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1442 const MCSubtargetInfo &STI,
1443 raw_ostream &O) {
1444 unsigned prfop = MI->getOperand(OpNum).getImm();
1445 if (IsSVEPrefetch) {
1446 if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1447 O << PRFM->Name;
1448 return;
1449 }
1450 } else {
1451 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1452 if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
1453 O << PRFM->Name;
1454 return;
1455 }
1456 }
1457
1458 O << markup("<imm:") << '#' << formatImm(prfop) << markup(">");
1459}
1460
1461void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1462 const MCSubtargetInfo &STI,
1463 raw_ostream &O) {
1464 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1465 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1466 if (PSB)
1467 O << PSB->Name;
1468 else
1469 O << markup("<imm:") << '#' << formatImm(psbhintop) << markup(">");
1470}
1471
1472void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1473 const MCSubtargetInfo &STI,
1474 raw_ostream &O) {
1475 unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
1476 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1477 if (BTI)
1478 O << BTI->Name;
1479 else
1480 O << markup("<imm:") << '#' << formatImm(btihintop) << markup(">");
1481}
1482
1483void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1484 const MCSubtargetInfo &STI,
1485 raw_ostream &O) {
1486 const MCOperand &MO = MI->getOperand(OpNum);
1487 float FPImm = MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm())
1488 : AArch64_AM::getFPImmFloat(MO.getImm());
1489
1490 // 8 decimal places are enough to perfectly represent permitted floats.
1491 O << markup("<imm:") << format("#%.8f", FPImm) << markup(">");
1492}
1493
1494static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1495 while (Stride--) {
1496 switch (Reg) {
1497 default:
1498 llvm_unreachable("Vector register expected!");
1499 case AArch64::Q0: Reg = AArch64::Q1; break;
1500 case AArch64::Q1: Reg = AArch64::Q2; break;
1501 case AArch64::Q2: Reg = AArch64::Q3; break;
1502 case AArch64::Q3: Reg = AArch64::Q4; break;
1503 case AArch64::Q4: Reg = AArch64::Q5; break;
1504 case AArch64::Q5: Reg = AArch64::Q6; break;
1505 case AArch64::Q6: Reg = AArch64::Q7; break;
1506 case AArch64::Q7: Reg = AArch64::Q8; break;
1507 case AArch64::Q8: Reg = AArch64::Q9; break;
1508 case AArch64::Q9: Reg = AArch64::Q10; break;
1509 case AArch64::Q10: Reg = AArch64::Q11; break;
1510 case AArch64::Q11: Reg = AArch64::Q12; break;
1511 case AArch64::Q12: Reg = AArch64::Q13; break;
1512 case AArch64::Q13: Reg = AArch64::Q14; break;
1513 case AArch64::Q14: Reg = AArch64::Q15; break;
1514 case AArch64::Q15: Reg = AArch64::Q16; break;
1515 case AArch64::Q16: Reg = AArch64::Q17; break;
1516 case AArch64::Q17: Reg = AArch64::Q18; break;
1517 case AArch64::Q18: Reg = AArch64::Q19; break;
1518 case AArch64::Q19: Reg = AArch64::Q20; break;
1519 case AArch64::Q20: Reg = AArch64::Q21; break;
1520 case AArch64::Q21: Reg = AArch64::Q22; break;
1521 case AArch64::Q22: Reg = AArch64::Q23; break;
1522 case AArch64::Q23: Reg = AArch64::Q24; break;
1523 case AArch64::Q24: Reg = AArch64::Q25; break;
1524 case AArch64::Q25: Reg = AArch64::Q26; break;
1525 case AArch64::Q26: Reg = AArch64::Q27; break;
1526 case AArch64::Q27: Reg = AArch64::Q28; break;
1527 case AArch64::Q28: Reg = AArch64::Q29; break;
1528 case AArch64::Q29: Reg = AArch64::Q30; break;
1529 case AArch64::Q30: Reg = AArch64::Q31; break;
1530 // Vector lists can wrap around.
1531 case AArch64::Q31:
1532 Reg = AArch64::Q0;
1533 break;
1534 case AArch64::Z0: Reg = AArch64::Z1; break;
1535 case AArch64::Z1: Reg = AArch64::Z2; break;
1536 case AArch64::Z2: Reg = AArch64::Z3; break;
1537 case AArch64::Z3: Reg = AArch64::Z4; break;
1538 case AArch64::Z4: Reg = AArch64::Z5; break;
1539 case AArch64::Z5: Reg = AArch64::Z6; break;
1540 case AArch64::Z6: Reg = AArch64::Z7; break;
1541 case AArch64::Z7: Reg = AArch64::Z8; break;
1542 case AArch64::Z8: Reg = AArch64::Z9; break;
1543 case AArch64::Z9: Reg = AArch64::Z10; break;
1544 case AArch64::Z10: Reg = AArch64::Z11; break;
1545 case AArch64::Z11: Reg = AArch64::Z12; break;
1546 case AArch64::Z12: Reg = AArch64::Z13; break;
1547 case AArch64::Z13: Reg = AArch64::Z14; break;
1548 case AArch64::Z14: Reg = AArch64::Z15; break;
1549 case AArch64::Z15: Reg = AArch64::Z16; break;
1550 case AArch64::Z16: Reg = AArch64::Z17; break;
1551 case AArch64::Z17: Reg = AArch64::Z18; break;
1552 case AArch64::Z18: Reg = AArch64::Z19; break;
1553 case AArch64::Z19: Reg = AArch64::Z20; break;
1554 case AArch64::Z20: Reg = AArch64::Z21; break;
1555 case AArch64::Z21: Reg = AArch64::Z22; break;
1556 case AArch64::Z22: Reg = AArch64::Z23; break;
1557 case AArch64::Z23: Reg = AArch64::Z24; break;
1558 case AArch64::Z24: Reg = AArch64::Z25; break;
1559 case AArch64::Z25: Reg = AArch64::Z26; break;
1560 case AArch64::Z26: Reg = AArch64::Z27; break;
1561 case AArch64::Z27: Reg = AArch64::Z28; break;
1562 case AArch64::Z28: Reg = AArch64::Z29; break;
1563 case AArch64::Z29: Reg = AArch64::Z30; break;
1564 case AArch64::Z30: Reg = AArch64::Z31; break;
1565 // Vector lists can wrap around.
1566 case AArch64::Z31:
1567 Reg = AArch64::Z0;
1568 break;
1569 case AArch64::P0: Reg = AArch64::P1; break;
1570 case AArch64::P1: Reg = AArch64::P2; break;
1571 case AArch64::P2: Reg = AArch64::P3; break;
1572 case AArch64::P3: Reg = AArch64::P4; break;
1573 case AArch64::P4: Reg = AArch64::P5; break;
1574 case AArch64::P5: Reg = AArch64::P6; break;
1575 case AArch64::P6: Reg = AArch64::P7; break;
1576 case AArch64::P7: Reg = AArch64::P8; break;
1577 case AArch64::P8: Reg = AArch64::P9; break;
1578 case AArch64::P9: Reg = AArch64::P10; break;
1579 case AArch64::P10: Reg = AArch64::P11; break;
1580 case AArch64::P11: Reg = AArch64::P12; break;
1581 case AArch64::P12: Reg = AArch64::P13; break;
1582 case AArch64::P13: Reg = AArch64::P14; break;
1583 case AArch64::P14: Reg = AArch64::P15; break;
1584 // Vector lists can wrap around.
1585 case AArch64::P15: Reg = AArch64::P0; break;
1586 }
1587 }
1588 return Reg;
1589}
1590
1591template<unsigned size>
1592void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1593 unsigned OpNum,
1594 const MCSubtargetInfo &STI,
1595 raw_ostream &O) {
1596 static_assert(size == 64 || size == 32,
1597 "Template parameter must be either 32 or 64");
1598 unsigned Reg = MI->getOperand(OpNum).getReg();
1599
1600 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1601 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1602
1603 unsigned Even = MRI.getSubReg(Reg, Sube);
1604 unsigned Odd = MRI.getSubReg(Reg, Subo);
1605 printRegName(O, Even);
1606 O << ", ";
1607 printRegName(O, Odd);
1608}
1609
1610void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
1611 const MCSubtargetInfo &STI,
1612 raw_ostream &O) {
1613 unsigned MaxRegs = 8;
1614 unsigned RegMask = MI->getOperand(OpNum).getImm();
1615
1616 unsigned NumRegs = 0;
1617 for (unsigned I = 0; I < MaxRegs; ++I)
1618 if ((RegMask & (1 << I)) != 0)
1619 ++NumRegs;
1620
1621 O << "{";
1622 unsigned Printed = 0;
1623 for (unsigned I = 0; I < MaxRegs; ++I) {
1624 unsigned Reg = RegMask & (1 << I);
1625 if (Reg == 0)
1626 continue;
1627 printRegName(O, AArch64::ZAD0 + I);
1628 if (Printed + 1 != NumRegs)
1629 O << ", ";
1630 ++Printed;
1631 }
1632 O << "}";
1633}
1634
1635void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1636 const MCSubtargetInfo &STI,
1637 raw_ostream &O,
1638 StringRef LayoutSuffix) {
1639 unsigned Reg = MI->getOperand(OpNum).getReg();
1640
1641 O << "{ ";
1642
1643 // Work out how many registers there are in the list (if there is an actual
1644 // list).
1645 unsigned NumRegs = 1;
1646 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1647 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1648 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
1649 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) ||
1650 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1651 NumRegs = 2;
1652 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1653 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1654 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1655 NumRegs = 3;
1656 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1657 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1658 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
1659 MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1660 NumRegs = 4;
1661
1662 unsigned Stride = 1;
1663 if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
1664 Stride = 8;
1665 else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
1666 Stride = 4;
1667
1668 // Now forget about the list and find out what the first register is.
1669 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1670 Reg = FirstReg;
1671 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1672 Reg = FirstReg;
1673 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1674 Reg = FirstReg;
1675 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
1676 Reg = FirstReg;
1677
1678 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1679 // printing (otherwise getRegisterName fails).
1680 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1681 const MCRegisterClass &FPR128RC =
1682 MRI.getRegClass(AArch64::FPR128RegClassID);
1683 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1684 }
1685
1686 if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1687 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
1688 NumRegs > 1 && Stride == 1 &&
1689 // Do not print the range when the last register is lower than the first.
1690 // Because it is a wrap-around register.
1691 Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
1692 printRegName(O, Reg);
1693 O << LayoutSuffix;
1694 if (NumRegs > 1) {
1695 // Set of two sve registers should be separated by ','
1696 StringRef split_char = NumRegs == 2 ? ", " : " - ";
1697 O << split_char;
1698 printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
1699 O << LayoutSuffix;
1700 }
1701 } else {
1702 for (unsigned i = 0; i < NumRegs;
1703 ++i, Reg = getNextVectorRegister(Reg, Stride)) {
1704 // wrap-around sve register
1705 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
1706 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
1707 printRegName(O, Reg);
1708 else
1709 printRegName(O, Reg, AArch64::vreg);
1710 O << LayoutSuffix;
1711 if (i + 1 != NumRegs)
1712 O << ", ";
1713 }
1714 }
1715 O << " }";
1716}
1717
1718void
1719AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1720 unsigned OpNum,
1721 const MCSubtargetInfo &STI,
1722 raw_ostream &O) {
1723 printVectorList(MI, OpNum, STI, O, "");
1724}
1725
1726template <unsigned NumLanes, char LaneKind>
1727void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1728 const MCSubtargetInfo &STI,
1729 raw_ostream &O) {
1730 std::string Suffix(".");
1731 if (NumLanes)
1732 Suffix += itostr(NumLanes) + LaneKind;
1733 else
1734 Suffix += LaneKind;
1735
1736 printVectorList(MI, OpNum, STI, O, Suffix);
1737}
1738
1739template <unsigned Scale>
1740void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1741 const MCSubtargetInfo &STI,
1742 raw_ostream &O) {
1743 O << "[" << Scale * MI->getOperand(OpNum).getImm() << "]";
1744}
1745
1746void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
1747 const MCSubtargetInfo &STI,
1748 raw_ostream &O) {
1749 O << MI->getOperand(OpNum).getImm();
1750}
1751
1752void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
1753 unsigned OpNum,
1754 const MCSubtargetInfo &STI,
1755 raw_ostream &O) {
1756 const MCOperand &Op = MI->getOperand(OpNum);
1757
1758 // If the label has already been resolved to an immediate offset (say, when
1759 // we're running the disassembler), just print the immediate.
1760 if (Op.isImm()) {
1761 O << markup("<imm:");
1762 int64_t Offset = Op.getImm() * 4;
1763 if (PrintBranchImmAsAddress)
1764 O << formatHex(Address + Offset);
1765 else
1766 O << "#" << formatImm(Offset);
1767 O << markup(">");
1768 return;
1769 }
1770
1771 // If the branch target is simply an address then print it in hex.
1772 const MCConstantExpr *BranchTarget =
1773 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1774 int64_t TargetAddress;
1775 if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) {
1776 O << formatHex((uint64_t)TargetAddress);
1777 } else {
1778 // Otherwise, just print the expression.
1779 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1780 }
1781}
1782
1783void AArch64InstPrinter::printAdrAdrpLabel(const MCInst *MI, uint64_t Address,
1784 unsigned OpNum,
1785 const MCSubtargetInfo &STI,
1786 raw_ostream &O) {
1787 const MCOperand &Op = MI->getOperand(OpNum);
1788
1789 // If the label has already been resolved to an immediate offset (say, when
1790 // we're running the disassembler), just print the immediate.
1791 if (Op.isImm()) {
1792 int64_t Offset = Op.getImm();
1793 if (MI->getOpcode() == AArch64::ADRP) {
1794 Offset = Offset * 4096;
1795 Address = Address & -4096;
1796 }
1797 O << markup("<imm:");
1798 if (PrintBranchImmAsAddress)
1799 O << formatHex(Address + Offset);
1800 else
1801 O << "#" << Offset;
1802 O << markup(">");
1803 return;
1804 }
1805
1806 // Otherwise, just print the expression.
1807 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1808}
1809
1810void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1811 const MCSubtargetInfo &STI,
1812 raw_ostream &O) {
1813 unsigned Val = MI->getOperand(OpNo).getImm();
1814 unsigned Opcode = MI->getOpcode();
1815
1816 StringRef Name;
1817 if (Opcode == AArch64::ISB) {
1818 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1819 Name = ISB ? ISB->Name : "";
1820 } else if (Opcode == AArch64::TSB) {
1821 auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1822 Name = TSB ? TSB->Name : "";
1823 } else {
1824 auto DB = AArch64DB::lookupDBByEncoding(Val);
1825 Name = DB ? DB->Name : "";
1826 }
1827 if (!Name.empty())
1828 O << Name;
1829 else
1830 O << markup("<imm:") << "#" << Val << markup(">");
1831}
1832
1833void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
1834 const MCSubtargetInfo &STI,
1835 raw_ostream &O) {
1836 unsigned Val = MI->getOperand(OpNo).getImm();
1837 assert(MI->getOpcode() == AArch64::DSBnXS);
1838
1839 StringRef Name;
1840 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1841 Name = DB ? DB->Name : "";
1842
1843 if (!Name.empty())
1844 O << Name;
1845 else
1846 O << markup("<imm:") << "#" << Val << markup(">");
1847}
1848
1849static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read,
1850 const MCSubtargetInfo &STI) {
1851 return (Reg && (Read ? Reg->Readable : Reg->Writeable) &&
1852 Reg->haveFeatures(STI.getFeatureBits()));
1853}
1854
1855// Looks up a system register either by encoding or by name. Some system
1856// registers share the same encoding between different architectures,
1857// therefore a tablegen lookup by encoding will return an entry regardless
1858// of the register's predication on a specific subtarget feature. To work
1859// around this problem we keep an alternative name for such registers and
1860// look them up by that name if the first lookup was unsuccessful.
1861static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read,
1862 const MCSubtargetInfo &STI) {
1863 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1864
1865 if (Reg && !isValidSysReg(Reg, Read, STI))
1866 Reg = AArch64SysReg::lookupSysRegByName(Reg->AltName);
1867
1868 return Reg;
1869}
1870
1871void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1872 const MCSubtargetInfo &STI,
1873 raw_ostream &O) {
1874 unsigned Val = MI->getOperand(OpNo).getImm();
1875
1876 // Horrible hack for the one register that has identical encodings but
1877 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1878 // going to get the wrong entry
1879 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1880 O << "DBGDTRRX_EL0";
1881 return;
1882 }
1883
1884 // Horrible hack for two different registers having the same encoding.
1885 if (Val == AArch64SysReg::TRCEXTINSELR) {
1886 O << "TRCEXTINSELR";
1887 return;
1888 }
1889
1890 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
1891
1892 if (isValidSysReg(Reg, true /*Read*/, STI))
1893 O << Reg->Name;
1894 else
1895 O << AArch64SysReg::genericRegisterString(Val);
1896}
1897
1898void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1899 const MCSubtargetInfo &STI,
1900 raw_ostream &O) {
1901 unsigned Val = MI->getOperand(OpNo).getImm();
1902
1903 // Horrible hack for the one register that has identical encodings but
1904 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1905 // going to get the wrong entry
1906 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1907 O << "DBGDTRTX_EL0";
1908 return;
1909 }
1910
1911 // Horrible hack for two different registers having the same encoding.
1912 if (Val == AArch64SysReg::TRCEXTINSELR) {
1913 O << "TRCEXTINSELR";
1914 return;
1915 }
1916
1917 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
1918
1919 if (isValidSysReg(Reg, false /*Read*/, STI))
1920 O << Reg->Name;
1921 else
1922 O << AArch64SysReg::genericRegisterString(Val);
1923}
1924
1925void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1926 const MCSubtargetInfo &STI,
1927 raw_ostream &O) {
1928 unsigned Val = MI->getOperand(OpNo).getImm();
1929
1930 auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val);
1931 auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val);
1932 if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits()))
1933 O << PStateImm15->Name;
1934 else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits()))
1935 O << PStateImm1->Name;
1936 else
1937 O << "#" << formatImm(Val);
1938}
1939
1940void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1941 const MCSubtargetInfo &STI,
1942 raw_ostream &O) {
1943 unsigned RawVal = MI->getOperand(OpNo).getImm();
1944 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1945 O << markup("<imm:") << format("#%#016llx", Val) << markup(">");
1946}
1947
1948template<int64_t Angle, int64_t Remainder>
1949void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1950 const MCSubtargetInfo &STI,
1951 raw_ostream &O) {
1952 unsigned Val = MI->getOperand(OpNo).getImm();
1953 O << markup("<imm:") << "#" << (Val * Angle) + Remainder << markup(">");
1954}
1955
1956void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1957 const MCSubtargetInfo &STI,
1958 raw_ostream &O) {
1959 unsigned Val = MI->getOperand(OpNum).getImm();
1960 if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1961 O << Pat->Name;
1962 else
1963 O << markup("<imm:") << '#' << formatImm(Val) << markup(">");
1964}
1965
1966void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
1967 unsigned OpNum,
1968 const MCSubtargetInfo &STI,
1969 raw_ostream &O) {
1970 unsigned Val = MI->getOperand(OpNum).getImm();
1971 // Pattern has only 1 bit
1972 if (Val > 1)
1973 llvm_unreachable("Invalid vector length specifier");
1974 if (auto Pat =
1975 AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val))
1976 O << Pat->Name;
1977 else
1978 llvm_unreachable("Invalid vector length specifier");
1979}
1980
1981template <char suffix>
1982void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
1983 const MCSubtargetInfo &STI,
1984 raw_ostream &O) {
1985 switch (suffix) {
1986 case 0:
1987 case 'b':
1988 case 'h':
1989 case 's':
1990 case 'd':
1991 case 'q':
1992 break;
1993 default: llvm_unreachable("Invalid kind specifier.");
1994 }
1995
1996 unsigned Reg = MI->getOperand(OpNum).getReg();
1997 printRegName(O, Reg);
1998 if (suffix != 0)
1999 O << '.' << suffix;
2000}
2001
2002template <typename T>
2003void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
2004 std::make_unsigned_t<T> HexValue = Value;
2005
2006 if (getPrintImmHex())
2007 O << markup("<imm:") << '#' << formatHex((uint64_t)HexValue) << markup(">");
2008 else
2009 O << markup("<imm:") << '#' << formatDec(Value) << markup(">");
2010
2011 if (CommentStream) {
2012 // Do the opposite to that used for instruction operands.
2013 if (getPrintImmHex())
2014 *CommentStream << '=' << formatDec(HexValue) << '\n';
2015 else
2016 *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
2017 }
2018}
2019
2020template <typename T>
2021void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
2022 const MCSubtargetInfo &STI,
2023 raw_ostream &O) {
2024 unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
2025 unsigned Shift = MI->getOperand(OpNum + 1).getImm();
2026 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2027 "Unexepected shift type!");
2028
2029 // #0 lsl #8 is never pretty printed
2030 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
2031 O << markup("<imm:") << '#' << formatImm(UnscaledVal) << markup(">");
2032 printShifter(MI, OpNum + 1, STI, O);
2033 return;
2034 }
2035
2036 T Val;
2037 if (std::is_signed<T>())
2038 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2039 else
2040 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
2041
2042 printImmSVE(Val, O);
2043}
2044
2045template <typename T>
2046void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
2047 const MCSubtargetInfo &STI,
2048 raw_ostream &O) {
2049 typedef std::make_signed_t<T> SignedT;
2050 typedef std::make_unsigned_t<T> UnsignedT;
2051
2052 uint64_t Val = MI->getOperand(OpNum).getImm();
2053 UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
2054
2055 // Prefer the default format for 16bit values, hex otherwise.
2056 if ((int16_t)PrintVal == (SignedT)PrintVal)
2057 printImmSVE((T)PrintVal, O);
2058 else if ((uint16_t)PrintVal == PrintVal)
2059 printImmSVE(PrintVal, O);
2060 else
2061 O << markup("<imm:") << '#' << formatHex((uint64_t)PrintVal) << markup(">");
2062}
2063
2064template <int Width>
2065void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
2066 const MCSubtargetInfo &STI,
2067 raw_ostream &O) {
2068 unsigned Base;
2069 switch (Width) {
2070 case 8: Base = AArch64::B0; break;
2071 case 16: Base = AArch64::H0; break;
2072 case 32: Base = AArch64::S0; break;
2073 case 64: Base = AArch64::D0; break;
2074 case 128: Base = AArch64::Q0; break;
2075 default:
2076 llvm_unreachable("Unsupported width");
2077 }
2078 unsigned Reg = MI->getOperand(OpNum).getReg();
2079 printRegName(O, Reg - AArch64::Z0 + Base);
2080}
2081
2082template <unsigned ImmIs0, unsigned ImmIs1>
2083void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
2084 const MCSubtargetInfo &STI,
2085 raw_ostream &O) {
2086 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
2087 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
2088 unsigned Val = MI->getOperand(OpNum).getImm();
2089 O << markup("<imm:") << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr)
2090 << markup(">");
2091}
2092
2093void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
2094 const MCSubtargetInfo &STI,
2095 raw_ostream &O) {
2096 unsigned Reg = MI->getOperand(OpNum).getReg();
2097 printRegName(O, getWRegFromXReg(Reg));
2098}
2099
2100void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
2101 const MCSubtargetInfo &STI,
2102 raw_ostream &O) {
2103 unsigned Reg = MI->getOperand(OpNum).getReg();
2104 printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
2105}
2106
2107void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
2108 const MCSubtargetInfo &STI,
2109 raw_ostream &O) {
2110 unsigned Reg = MI->getOperand(OpNum).getReg();
2111 assert(Reg == AArch64::XZR &&
2112 "MC representation of SyspXzrPair should be XZR");
2113 O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
2114}
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
getNextVectorRegister
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride=1)
Definition: AArch64InstPrinter.cpp:1494
lookupSysReg
static const AArch64SysReg::SysReg * lookupSysReg(unsigned Val, bool Read, const MCSubtargetInfo &STI)
Definition: AArch64InstPrinter.cpp:1861
getLdStNInstrDesc
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
Definition: AArch64InstPrinter.cpp:761
LdStNInstInfo
static const LdStNInstrDesc LdStNInstInfo[]
Definition: AArch64InstPrinter.cpp:418
isTblTbxInstruction
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
Definition: AArch64InstPrinter.cpp:373
isValidSysReg
static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read, const MCSubtargetInfo &STI)
Definition: AArch64InstPrinter.cpp:1849
printMemExtendImpl
static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, raw_ostream &O, bool UseMarkup)
Definition: AArch64InstPrinter.cpp:1286
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Name
std::string Name
Definition: ELFObjHandler.cpp:77
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
RegName
#define RegName(no)
I
#define I(x, y, z)
Definition: MD5.cpp:58
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
STLExtras.h
This file contains some templates that are useful if you are working with the STL at all.
OS
raw_pwrite_stream & OS
Definition: SampleProfWriter.cpp:53
StringExtras.h
This file contains some functions that are useful when dealing with strings.
llvm::AArch64AppleInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AArch64InstPrinter.cpp:769
llvm::AArch64AppleInstPrinter::AArch64AppleInstPrinter
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64InstPrinter.cpp:49
llvm::AArch64AppleInstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64AppleInstPrinter::getRegName
StringRef getRegName(MCRegister Reg) const override
Definition: AArch64InstPrinter.cpp:828
llvm::AArch64InstPrinter::printMRSSystemRegister
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1871
llvm::AArch64InstPrinter::printImm
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1141
llvm::AArch64InstPrinter::printAlignedLabel
void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1752
llvm::AArch64InstPrinter::printAMIndexedWB
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1412
llvm::AArch64InstPrinter::printMatrix
void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1063
llvm::AArch64InstPrinter::printAdrAdrpLabel
void printAdrAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1783
llvm::AArch64InstPrinter::printPrefetchOp
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1441
llvm::AArch64InstPrinter::printZPRasFPR
void printZPRasFPR(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2065
llvm::AArch64InstPrinter::printInstruction
virtual void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printAMNoIndex
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1375
llvm::AArch64InstPrinter::printUImm12Offset
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1400
llvm::AArch64InstPrinter::printSVCROp
void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1115
llvm::AArch64InstPrinter::AArch64InstPrinter
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AArch64InstPrinter.cpp:44
llvm::AArch64InstPrinter::printCondCode
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1361
llvm::AArch64InstPrinter::printBarriernXSOption
void printBarriernXSOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1833
llvm::AArch64InstPrinter::printSystemPStateField
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1925
llvm::AArch64InstPrinter::printShifter
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1232
llvm::AArch64InstPrinter::printPSBHintOp
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1461
llvm::AArch64InstPrinter::printGPR64x8
void printGPR64x8(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2100
llvm::AArch64InstPrinter::printSIMDType10Operand
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1940
llvm::AArch64InstPrinter::getRegName
virtual StringRef getRegName(MCRegister Reg) const
Definition: AArch64InstPrinter.cpp:71
llvm::AArch64InstPrinter::printMemExtend
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
Definition: AArch64InstPrinter.cpp:1306
llvm::AArch64InstPrinter::printMatrixTileVector
void printMatrixTileVector(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1094
llvm::AArch64InstPrinter::printSysAlias
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:882
llvm::AArch64InstPrinter::printSysCROperand
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1192
llvm::AArch64InstPrinter::applyTargetSpecificCLOption
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
Definition: AArch64InstPrinter.cpp:54
llvm::AArch64InstPrinter::printRPRFMOperand
void printRPRFMOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1428
llvm::AArch64InstPrinter::printVectorList
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
Definition: AArch64InstPrinter.cpp:1635
llvm::AArch64InstPrinter::printImplicitlyTypedVectorList
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
Definition: AArch64InstPrinter.cpp:1719
llvm::AArch64InstPrinter::printGPRSeqPairsClassOperand
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1592
llvm::AArch64InstPrinter::printExtendedRegister
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1252
llvm::AArch64InstPrinter::printRangePrefetchAlias
bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O, StringRef Annot)
Definition: AArch64InstPrinter.cpp:832
llvm::AArch64InstPrinter::printMSRSystemRegister
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1898
llvm::AArch64InstPrinter::printSVERegOp
void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1982
llvm::AArch64InstPrinter::printMatrixTile
void printMatrixTile(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1107
llvm::AArch64InstPrinter::printFPImmOperand
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1483
llvm::AArch64InstPrinter::printSVEVecLenSpecifier
void printSVEVecLenSpecifier(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1966
llvm::AArch64InstPrinter::printBTIHintOp
void printBTIHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1472
llvm::AArch64InstPrinter::printSyspXzrPair
void printSyspXzrPair(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2107
llvm::AArch64InstPrinter::printArithExtend
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1259
llvm::AArch64InstPrinter::printOperand
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1126
llvm::AArch64InstPrinter::printAliasInstr
virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::AArch64InstPrinter::printImmScale
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1384
llvm::AArch64InstPrinter::printSImm
void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1156
llvm::AArch64InstPrinter::printAddSubImm
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1200
llvm::AArch64InstPrinter::printImmSVE
void printImmSVE(T Value, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2003
llvm::AArch64InstPrinter::printShiftedRegister
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1245
llvm::AArch64InstPrinter::printComplexRotationOp
void printComplexRotationOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1949
llvm::AArch64InstPrinter::printGPR64as32
void printGPR64as32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2093
llvm::AArch64InstPrinter::printSyspAlias
bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1002
llvm::AArch64InstPrinter::printMatrixTileList
void printMatrixTileList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1610
llvm::AArch64InstPrinter::printImmRangeScale
void printImmRangeScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1392
llvm::AArch64InstPrinter::printTypedVectorList
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1727
llvm::AArch64InstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AArch64InstPrinter.cpp:75
llvm::AArch64InstPrinter::printRegName
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
Definition: AArch64InstPrinter.cpp:62
llvm::AArch64InstPrinter::printLogicalImm
void printLogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1223
llvm::AArch64InstPrinter::printMatrixIndex
void printMatrixIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1746
llvm::AArch64InstPrinter::printSVEPattern
void printSVEPattern(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1956
llvm::AArch64InstPrinter::getRegisterName
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=AArch64::NoRegAltName)
llvm::AArch64InstPrinter::printVRegOperand
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1183
llvm::AArch64InstPrinter::printPostIncOperand
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1170
llvm::AArch64InstPrinter::printPredicateAsCounter
void printPredicateAsCounter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1333
llvm::AArch64InstPrinter::printVectorIndex
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1740
llvm::AArch64InstPrinter::printImm8OptLsl
void printImm8OptLsl(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2021
llvm::AArch64InstPrinter::printRegWithShiftExtend
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1315
llvm::AArch64InstPrinter::printImmHex
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1148
llvm::AArch64InstPrinter::printInverseCondCode
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1368
llvm::AArch64InstPrinter::printExactFPImm
void printExactFPImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2083
llvm::AArch64InstPrinter::printBarrierOption
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:1810
llvm::AArch64InstPrinter::printSVELogicalImm
void printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Definition: AArch64InstPrinter.cpp:2046
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::MCAsmInfo::getCommentString
StringRef getCommentString() const
Definition: MCAsmInfo.h:655
llvm::MCExpr::print
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:44
llvm::MCInstPrinter::UseMarkup
bool UseMarkup
True if we are printing marked up assembly.
Definition: MCInstPrinter.h:56
llvm::MCInstPrinter::formatHex
format_object< int64_t > formatHex(int64_t Value) const
Definition: MCInstPrinter.cpp:198
llvm::MCInstPrinter::CommentStream
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:49
llvm::MCInstPrinter::getPrintImmHex
bool getPrintImmHex() const
Definition: MCInstPrinter.h:122
llvm::MCInstPrinter::markup
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
Definition: MCInstPrinter.cpp:174
llvm::MCInstPrinter::formatDec
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
Definition: MCInstPrinter.cpp:194
llvm::MCInstPrinter::MRI
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:52
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition: MCInstPrinter.cpp:50
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:50
llvm::MCInstPrinter::formatImm
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:135
llvm::MCInstPrinter::PrintBranchImmAsAddress
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:70
llvm::MCInstPrinter::PrintAliases
bool PrintAliases
True if we prefer aliases (e.g. nop) to raw mnemonics.
Definition: MCInstPrinter.h:59
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition: MCInst.h:64
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::MCOperand::getDFPImm
uint64_t getDFPImm() const
Definition: MCInst.h:100
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: MCRegisterInfo.h:543
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:32
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AArch64CC::getCondCodeName
static const char * getCondCodeName(CondCode Code)
Definition: AArch64BaseInfo.h:282
llvm::AArch64CC::getInvertedCondCode
static CondCode getInvertedCondCode(CondCode Code)
Definition: AArch64BaseInfo.h:304
llvm::AArch64SysReg::lookupSysRegByEncoding
const SysReg * lookupSysRegByEncoding(uint16_t)
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition: AArch64BaseInfo.cpp:170
llvm::AArch64SysReg::lookupSysRegByName
const SysReg * lookupSysRegByName(StringRef)
llvm::AArch64_AM::isMOVNMovAlias
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition: AArch64AddressingModes.h:829
llvm::AArch64_AM::decodeLogicalImmediate
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
Definition: AArch64AddressingModes.h:294
llvm::AArch64_AM::getShiftValue
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
Definition: AArch64AddressingModes.h:86
llvm::AArch64_AM::isAnyMOVWMovAlias
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
Definition: AArch64AddressingModes.h:841
llvm::AArch64_AM::getArithShiftValue
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
Definition: AArch64AddressingModes.h:119
llvm::AArch64_AM::getFPImmFloat
static float getFPImmFloat(unsigned Imm)
Definition: AArch64AddressingModes.h:344
llvm::AArch64_AM::isMOVZMovAlias
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
Definition: AArch64AddressingModes.h:818
llvm::AArch64_AM::ShiftExtendType
ShiftExtendType
Definition: AArch64AddressingModes.h:33
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:35
llvm::AArch64_AM::UXTW
@ UXTW
Definition: AArch64AddressingModes.h:43
llvm::AArch64_AM::UXTX
@ UXTX
Definition: AArch64AddressingModes.h:44
llvm::AArch64_AM::getShiftExtendName
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
Definition: AArch64AddressingModes.h:53
llvm::AArch64_AM::decodeAdvSIMDModImmType10
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
Definition: AArch64AddressingModes.h:642
llvm::AArch64_AM::getArithExtendType
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
Definition: AArch64AddressingModes.h:139
llvm::AArch64_AM::getShiftType
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
Definition: AArch64AddressingModes.h:74
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:440
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1777
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:382
llvm::atomicBarrierDroppedOnZero
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
Definition: AArch64BaseInfo.h:208
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::getWRegFromXReg
static unsigned getWRegFromXReg(unsigned Reg)
Definition: AArch64BaseInfo.h:30
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:184
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:557
raw_ostream.h
llvm::SysAlias::haveFeatures
bool haveFeatures(FeatureBitset ActiveFeatures) const
Definition: AArch64BaseInfo.h:347
llvm::SysAlias::Name
const char * Name
Definition: AArch64BaseInfo.h:339
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