34 #define DEBUG_TYPE "arm-disassembler"
53 void advanceITState() {
58 bool instrInITBlock() {
59 return !ITStates.empty();
63 bool instrLastInITBlock() {
64 return ITStates.size() == 1;
71 void setITState(
char Firstcond,
char Mask) {
73 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
74 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
75 assert(NumTZ <= 3 &&
"Invalid IT mask!");
77 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
79 ITStates.push_back(CCBits ^
Else);
81 ITStates.push_back(CCBits);
85 std::vector<unsigned char> ITStates;
91 unsigned getVPTPred() {
93 if (instrInVPTBlock())
94 Pred = VPTStates.back();
98 void advanceVPTState() {
102 bool instrInVPTBlock() {
103 return !VPTStates.empty();
106 bool instrLastInVPTBlock() {
107 return VPTStates.size() == 1;
110 void setVPTState(
char Mask) {
112 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
113 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
115 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116 bool T = ((
Mask >> Pos) & 1) == 0;
136 ~ARMDisassembler()
override =
default;
151 mutable ITStatus ITBlock;
152 mutable VPTStatus VPTBlock;
554 template <
int shift,
int WriteBack>
616 template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
651 template <
bool Writeback>
667 template <
unsigned MinLog,
unsigned MaxLog>
671 template <
unsigned start>
687 template <
bool scalar, OperandDecoder predicate_decoder>
702 #include "ARMGenDisassemblerTables.inc"
707 return new ARMDisassembler(STI, Ctx);
715 switch (
MI.getOpcode()) {
734 if (
MI.getOperand(0).getReg() == ARM::SP &&
735 MI.getOperand(1).getReg() != ARM::SP)
738 default:
return Result;
746 if (STI.getFeatureBits()[ARM::ModeThumb])
747 return getThumbInstruction(
MI, Size, Bytes, Address, CS);
748 return getARMInstruction(
MI, Size, Bytes, Address, CS);
757 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
758 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
762 if (Bytes.
size() < 4) {
769 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
773 decodeInstruction(DecoderTableARM32,
MI,
Insn, Address,
this, STI);
784 const DecodeTable Tables[] = {
785 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
786 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
787 {DecoderTableNEONDup32,
true}, {DecoderTablev8NEON32,
false},
788 {DecoderTablev8Crypto32,
false},
791 for (
auto Table : Tables) {
792 Result = decodeInstruction(Table.P,
MI,
Insn, Address,
this, STI);
804 decodeInstruction(DecoderTableCoProc32,
MI,
Insn, Address,
this, STI);
864 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
865 if (
I ==
MI.end())
break;
866 if (OpInfo[
i].isOptionalDef() && OpInfo[
i].RegClass == ARM::CCRRegClassID) {
867 if (
i > 0 && OpInfo[
i-1].isPredicate())
continue;
879 for (
unsigned i = 0;
i < NumOps; ++
i) {
891 ARMDisassembler::AddThumbPredicate(
MCInst &
MI)
const {
894 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
898 switch (
MI.getOpcode()) {
915 if (ITBlock.instrInITBlock())
921 if (
MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
930 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
947 if (ITBlock.instrInITBlock()) {
948 CC = ITBlock.getITCC();
949 ITBlock.advanceITState();
950 }
else if (VPTBlock.instrInVPTBlock()) {
951 VCC = VPTBlock.getVPTPred();
952 VPTBlock.advanceVPTState();
959 for (
unsigned i = 0;
i < NumOps; ++
i, ++CCI) {
960 if (OpInfo[
i].isPredicate() || CCI ==
MI.end())
break;
976 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
994 "Inactive register in vpred_r is not tied to an output!");
1010 void ARMDisassembler::UpdateThumbVFPPredicate(
1013 CC = ITBlock.getITCC();
1016 if (ITBlock.instrInITBlock())
1017 ITBlock.advanceITState();
1018 else if (VPTBlock.instrInVPTBlock()) {
1019 CC = VPTBlock.getVPTPred();
1020 VPTBlock.advanceVPTState();
1026 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
1027 if (OpInfo[
i].isPredicate() ) {
1035 I->setReg(ARM::CPSR);
1045 CommentStream = &CS;
1047 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
1048 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
1051 if (Bytes.
size() < 2) {
1056 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
1058 decodeInstruction(DecoderTableThumb16,
MI, Insn16, Address,
this, STI);
1061 Check(Result, AddThumbPredicate(
MI));
1065 Result = decodeInstruction(DecoderTableThumbSBit16,
MI, Insn16, Address,
this,
1069 bool InITBlock = ITBlock.instrInITBlock();
1070 Check(Result, AddThumbPredicate(
MI));
1076 decodeInstruction(DecoderTableThumb216,
MI, Insn16, Address,
this, STI);
1082 if (
MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
1085 Check(Result, AddThumbPredicate(
MI));
1090 if (
MI.getOpcode() == ARM::t2IT) {
1091 unsigned Firstcond =
MI.getOperand(0).getImm();
1092 unsigned Mask =
MI.getOperand(1).getImm();
1093 ITBlock.setITState(Firstcond,
Mask);
1097 CS <<
"unpredictable IT predicate sequence";
1104 if (Bytes.
size() < 4) {
1110 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
1113 decodeInstruction(DecoderTableMVE32,
MI, Insn32, Address,
this, STI);
1119 if (
isVPTOpcode(
MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1122 Check(Result, AddThumbPredicate(
MI));
1125 unsigned Mask =
MI.getOperand(0).getImm();
1126 VPTBlock.setVPTState(
Mask);
1133 decodeInstruction(DecoderTableThumb32,
MI, Insn32, Address,
this, STI);
1136 bool InITBlock = ITBlock.instrInITBlock();
1137 Check(Result, AddThumbPredicate(
MI));
1143 decodeInstruction(DecoderTableThumb232,
MI, Insn32, Address,
this, STI);
1146 Check(Result, AddThumbPredicate(
MI));
1150 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1152 decodeInstruction(DecoderTableVFP32,
MI, Insn32, Address,
this, STI);
1155 UpdateThumbVFPPredicate(Result,
MI);
1161 decodeInstruction(DecoderTableVFPV832,
MI, Insn32, Address,
this, STI);
1167 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1168 Result = decodeInstruction(DecoderTableNEONDup32,
MI, Insn32, Address,
this,
1172 Check(Result, AddThumbPredicate(
MI));
1177 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1179 NEONLdStInsn &= 0xF0FFFFFF;
1180 NEONLdStInsn |= 0x04000000;
1181 Result = decodeInstruction(DecoderTableNEONLoadStore32,
MI, NEONLdStInsn,
1182 Address,
this, STI);
1185 Check(Result, AddThumbPredicate(
MI));
1190 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1192 NEONDataInsn &= 0xF0FFFFFF;
1193 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
1194 NEONDataInsn |= 0x12000000;
1195 Result = decodeInstruction(DecoderTableNEONData32,
MI, NEONDataInsn,
1196 Address,
this, STI);
1199 Check(Result, AddThumbPredicate(
MI));
1204 NEONCryptoInsn &= 0xF0FFFFFF;
1205 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
1206 NEONCryptoInsn |= 0x12000000;
1207 Result = decodeInstruction(DecoderTablev8Crypto32,
MI, NEONCryptoInsn,
1208 Address,
this, STI);
1215 NEONv8Insn &= 0xF3FFFFFF;
1216 Result = decodeInstruction(DecoderTablev8NEON32,
MI, NEONv8Insn, Address,
1224 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1226 ? DecoderTableThumb2CDE32
1227 : DecoderTableThumb2CoProc32;
1229 decodeInstruction(DecoderTable,
MI, Insn32, Address,
this, STI);
1232 Check(Result, AddThumbPredicate(
MI));
1252 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1254 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1255 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1259 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1261 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1262 ARM::R12, 0, ARM::LR, ARM::APSR
1368 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1369 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1399 if ((RegNo & 1) || RegNo > 10)
1452 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1454 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1462 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1463 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1464 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1465 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1466 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1467 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1468 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1469 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1490 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1491 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1492 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1493 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1494 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1495 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1496 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1497 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1504 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1506 bool hasD32 = featureBits[ARM::FeatureD32];
1508 if (RegNo > 31 || (!hasD32 && RegNo > 15))
1541 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1542 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1543 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1544 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1550 if (RegNo > 31 || (RegNo & 1) != 0)
1560 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1561 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1562 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1563 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1564 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1580 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1581 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1582 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1583 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1584 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1585 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1586 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1587 ARM::D28_D30, ARM::D29_D31
1607 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1634 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1635 unsigned type = fieldFromInstruction(Val, 5, 2);
1636 unsigned imm = fieldFromInstruction(Val, 7, 5);
1661 unsigned Op =
Shift | (imm << 3);
1672 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1673 unsigned type = fieldFromInstruction(Val, 5, 2);
1674 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1708 bool NeedDisjointWriteback =
false;
1709 unsigned WritebackReg = 0;
1714 case ARM::LDMIA_UPD:
1715 case ARM::LDMDB_UPD:
1716 case ARM::LDMIB_UPD:
1717 case ARM::LDMDA_UPD:
1718 case ARM::t2LDMIA_UPD:
1719 case ARM::t2LDMDB_UPD:
1720 case ARM::t2STMIA_UPD:
1721 case ARM::t2STMDB_UPD:
1722 NeedDisjointWriteback =
true;
1732 for (
unsigned i = 0;
i < 16; ++
i) {
1733 if (Val & (1 <<
i)) {
1742 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1756 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1757 unsigned regs = fieldFromInstruction(Val, 0, 8);
1760 if (regs == 0 || (Vd + regs) > 32) {
1761 regs = Vd + regs > 32 ? 32 - Vd : regs;
1768 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1781 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1782 unsigned regs = fieldFromInstruction(Val, 1, 7);
1785 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1786 regs = Vd + regs > 32 ? 32 - Vd : regs;
1794 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1810 unsigned msb = fieldFromInstruction(Val, 5, 5);
1811 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1823 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1824 uint32_t lsb_mask = (1U << lsb) - 1;
1835 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
1836 unsigned CRd = fieldFromInstruction(
Insn, 12, 4);
1837 unsigned coproc = fieldFromInstruction(
Insn, 8, 4);
1838 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
1839 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
1840 unsigned U = fieldFromInstruction(
Insn, 23, 1);
1842 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1845 case ARM::LDC_OFFSET:
1848 case ARM::LDC_OPTION:
1849 case ARM::LDCL_OFFSET:
1851 case ARM::LDCL_POST:
1852 case ARM::LDCL_OPTION:
1853 case ARM::STC_OFFSET:
1856 case ARM::STC_OPTION:
1857 case ARM::STCL_OFFSET:
1859 case ARM::STCL_POST:
1860 case ARM::STCL_OPTION:
1861 case ARM::t2LDC_OFFSET:
1862 case ARM::t2LDC_PRE:
1863 case ARM::t2LDC_POST:
1864 case ARM::t2LDC_OPTION:
1865 case ARM::t2LDCL_OFFSET:
1866 case ARM::t2LDCL_PRE:
1867 case ARM::t2LDCL_POST:
1868 case ARM::t2LDCL_OPTION:
1869 case ARM::t2STC_OFFSET:
1870 case ARM::t2STC_PRE:
1871 case ARM::t2STC_POST:
1872 case ARM::t2STC_OPTION:
1873 case ARM::t2STCL_OFFSET:
1874 case ARM::t2STCL_PRE:
1875 case ARM::t2STCL_POST:
1876 case ARM::t2STCL_OPTION:
1877 case ARM::t2LDC2_OFFSET:
1878 case ARM::t2LDC2L_OFFSET:
1879 case ARM::t2LDC2_PRE:
1880 case ARM::t2LDC2L_PRE:
1881 case ARM::t2STC2_OFFSET:
1882 case ARM::t2STC2L_OFFSET:
1883 case ARM::t2STC2_PRE:
1884 case ARM::t2STC2L_PRE:
1885 case ARM::LDC2_OFFSET:
1886 case ARM::LDC2L_OFFSET:
1888 case ARM::LDC2L_PRE:
1889 case ARM::STC2_OFFSET:
1890 case ARM::STC2L_OFFSET:
1892 case ARM::STC2L_PRE:
1893 case ARM::t2LDC2_OPTION:
1894 case ARM::t2STC2_OPTION:
1895 case ARM::t2LDC2_POST:
1896 case ARM::t2LDC2L_POST:
1897 case ARM::t2STC2_POST:
1898 case ARM::t2STC2L_POST:
1899 case ARM::LDC2_POST:
1900 case ARM::LDC2L_POST:
1901 case ARM::STC2_POST:
1902 case ARM::STC2L_POST:
1903 if (coproc == 0xA || coproc == 0xB ||
1904 (featureBits[ARM::HasV8_1MMainlineOps] &&
1905 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1906 coproc == 0xE || coproc == 0xF)))
1913 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1922 case ARM::t2LDC2_OFFSET:
1923 case ARM::t2LDC2L_OFFSET:
1924 case ARM::t2LDC2_PRE:
1925 case ARM::t2LDC2L_PRE:
1926 case ARM::t2STC2_OFFSET:
1927 case ARM::t2STC2L_OFFSET:
1928 case ARM::t2STC2_PRE:
1929 case ARM::t2STC2L_PRE:
1930 case ARM::LDC2_OFFSET:
1931 case ARM::LDC2L_OFFSET:
1933 case ARM::LDC2L_PRE:
1934 case ARM::STC2_OFFSET:
1935 case ARM::STC2L_OFFSET:
1937 case ARM::STC2L_PRE:
1938 case ARM::t2LDC_OFFSET:
1939 case ARM::t2LDCL_OFFSET:
1940 case ARM::t2LDC_PRE:
1941 case ARM::t2LDCL_PRE:
1942 case ARM::t2STC_OFFSET:
1943 case ARM::t2STCL_OFFSET:
1944 case ARM::t2STC_PRE:
1945 case ARM::t2STCL_PRE:
1946 case ARM::LDC_OFFSET:
1947 case ARM::LDCL_OFFSET:
1950 case ARM::STC_OFFSET:
1951 case ARM::STCL_OFFSET:
1957 case ARM::t2LDC2_POST:
1958 case ARM::t2LDC2L_POST:
1959 case ARM::t2STC2_POST:
1960 case ARM::t2STC2L_POST:
1961 case ARM::LDC2_POST:
1962 case ARM::LDC2L_POST:
1963 case ARM::STC2_POST:
1964 case ARM::STC2L_POST:
1965 case ARM::t2LDC_POST:
1966 case ARM::t2LDCL_POST:
1967 case ARM::t2STC_POST:
1968 case ARM::t2STCL_POST:
1970 case ARM::LDCL_POST:
1972 case ARM::STCL_POST:
1983 case ARM::LDC_OFFSET:
1986 case ARM::LDC_OPTION:
1987 case ARM::LDCL_OFFSET:
1989 case ARM::LDCL_POST:
1990 case ARM::LDCL_OPTION:
1991 case ARM::STC_OFFSET:
1994 case ARM::STC_OPTION:
1995 case ARM::STCL_OFFSET:
1997 case ARM::STCL_POST:
1998 case ARM::STCL_OPTION:
2014 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2015 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
2016 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2017 unsigned imm = fieldFromInstruction(
Insn, 0, 12);
2018 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2019 unsigned reg = fieldFromInstruction(
Insn, 25, 1);
2020 unsigned P = fieldFromInstruction(
Insn, 24, 1);
2021 unsigned W = fieldFromInstruction(
Insn, 21, 1);
2025 case ARM::STR_POST_IMM:
2026 case ARM::STR_POST_REG:
2027 case ARM::STRB_POST_IMM:
2028 case ARM::STRB_POST_REG:
2029 case ARM::STRT_POST_REG:
2030 case ARM::STRT_POST_IMM:
2031 case ARM::STRBT_POST_REG:
2032 case ARM::STRBT_POST_IMM:
2045 case ARM::LDR_POST_IMM:
2046 case ARM::LDR_POST_REG:
2047 case ARM::LDRB_POST_IMM:
2048 case ARM::LDRB_POST_REG:
2049 case ARM::LDRBT_POST_REG:
2050 case ARM::LDRBT_POST_IMM:
2051 case ARM::LDRT_POST_REG:
2052 case ARM::LDRT_POST_IMM:
2064 if (!fieldFromInstruction(
Insn, 23, 1))
2067 bool writeback = (
P == 0) || (
W == 1);
2068 unsigned idx_mode = 0;
2071 else if (!
P && writeback)
2074 if (writeback && (Rn == 15 || Rn == Rt))
2081 switch( fieldFromInstruction(
Insn, 5, 2)) {
2097 unsigned amt = fieldFromInstruction(
Insn, 7, 5);
2120 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2121 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2122 unsigned type = fieldFromInstruction(Val, 5, 2);
2123 unsigned imm = fieldFromInstruction(Val, 7, 5);
2124 unsigned U = fieldFromInstruction(Val, 12, 1);
2177 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
2178 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2179 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2180 unsigned type = fieldFromInstruction(
Insn, 22, 1);
2181 unsigned imm = fieldFromInstruction(
Insn, 8, 4);
2182 unsigned U = ((~fieldFromInstruction(
Insn, 23, 1)) & 1) << 8;
2183 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2184 unsigned W = fieldFromInstruction(
Insn, 21, 1);
2185 unsigned P = fieldFromInstruction(
Insn, 24, 1);
2186 unsigned Rt2 = Rt + 1;
2188 bool writeback = (
W == 1) | (
P == 0);
2194 case ARM::STRD_POST:
2197 case ARM::LDRD_POST:
2206 case ARM::STRD_POST:
2207 if (
P == 0 &&
W == 1)
2210 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2212 if (
type && Rm == 15)
2216 if (!
type && fieldFromInstruction(
Insn, 8, 4))
2221 case ARM::STRH_POST:
2224 if (writeback && (Rn == 15 || Rn == Rt))
2226 if (!
type && Rm == 15)
2231 case ARM::LDRD_POST:
2232 if (
type && Rn == 15) {
2237 if (
P == 0 &&
W == 1)
2239 if (!
type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2241 if (!
type && writeback && Rn == 15)
2243 if (writeback && (Rn == Rt || Rn == Rt2))
2248 case ARM::LDRH_POST:
2249 if (
type && Rn == 15) {
2256 if (!
type && Rm == 15)
2258 if (!
type && writeback && (Rn == 15 || Rn == Rt))
2262 case ARM::LDRSH_PRE:
2263 case ARM::LDRSH_POST:
2265 case ARM::LDRSB_PRE:
2266 case ARM::LDRSB_POST:
2267 if (
type && Rn == 15) {
2272 if (
type && (Rt == 15 || (writeback && Rn == Rt)))
2274 if (!
type && (Rt == 15 || Rm == 15))
2276 if (!
type && writeback && (Rn == 15 || Rn == Rt))
2293 case ARM::STRD_POST:
2296 case ARM::STRH_POST:
2310 case ARM::STRD_POST:
2313 case ARM::LDRD_POST:
2326 case ARM::LDRD_POST:
2329 case ARM::LDRH_POST:
2331 case ARM::LDRSH_PRE:
2332 case ARM::LDRSH_POST:
2334 case ARM::LDRSB_PRE:
2335 case ARM::LDRSB_POST:
2369 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2370 unsigned mode = fieldFromInstruction(
Insn, 23, 2);
2399 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2400 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2401 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2402 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2424 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2425 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2426 unsigned reglist = fieldFromInstruction(
Insn, 0, 16);
2434 case ARM::LDMDA_UPD:
2440 case ARM::LDMDB_UPD:
2446 case ARM::LDMIA_UPD:
2452 case ARM::LDMIB_UPD:
2458 case ARM::STMDA_UPD:
2464 case ARM::STMDB_UPD:
2470 case ARM::STMIA_UPD:
2476 case ARM::STMIB_UPD:
2484 if (fieldFromInstruction(
Insn, 20, 1) == 0) {
2486 if (!(fieldFromInstruction(
Insn, 22, 1) == 1 &&
2487 fieldFromInstruction(
Insn, 20, 1) == 0))
2514 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2515 unsigned imm8 = fieldFromInstruction(
Insn, 0, 8);
2528 if (imm8 == 0x10 &&
pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2537 unsigned imod = fieldFromInstruction(
Insn, 18, 2);
2538 unsigned M = fieldFromInstruction(
Insn, 17, 1);
2539 unsigned iflags = fieldFromInstruction(
Insn, 6, 3);
2540 unsigned mode = fieldFromInstruction(
Insn, 0, 5);
2546 if (fieldFromInstruction(
Insn, 5, 1) != 0 ||
2547 fieldFromInstruction(
Insn, 16, 1) != 0 ||
2548 fieldFromInstruction(
Insn, 20, 8) != 0x10)
2563 }
else if (imod && !
M) {
2568 }
else if (!imod &&
M) {
2585 unsigned imod = fieldFromInstruction(
Insn, 9, 2);
2586 unsigned M = fieldFromInstruction(
Insn, 8, 1);
2587 unsigned iflags = fieldFromInstruction(
Insn, 5, 3);
2588 unsigned mode = fieldFromInstruction(
Insn, 0, 5);
2604 }
else if (imod && !
M) {
2609 }
else if (!imod &&
M) {
2615 int imm = fieldFromInstruction(
Insn, 0, 8);
2628 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
2630 unsigned Opcode = ARM::t2HINT;
2633 Opcode = ARM::t2PACBTI;
2634 }
else if (imm == 0x1D) {
2635 Opcode = ARM::t2PAC;
2636 }
else if (imm == 0x2D) {
2637 Opcode = ARM::t2AUT;
2638 }
else if (imm == 0x0F) {
2639 Opcode = ARM::t2BTI;
2643 if (Opcode == ARM::t2HINT) {
2655 unsigned Rd = fieldFromInstruction(
Insn, 8, 4);
2658 imm |= (fieldFromInstruction(
Insn, 0, 8) << 0);
2659 imm |= (fieldFromInstruction(
Insn, 12, 3) << 8);
2660 imm |= (fieldFromInstruction(
Insn, 16, 4) << 12);
2661 imm |= (fieldFromInstruction(
Insn, 26, 1) << 11);
2680 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2681 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2684 imm |= (fieldFromInstruction(
Insn, 0, 12) << 0);
2685 imm |= (fieldFromInstruction(
Insn, 16, 4) << 12);
2708 unsigned Rd = fieldFromInstruction(
Insn, 16, 4);
2709 unsigned Rn = fieldFromInstruction(
Insn, 0, 4);
2710 unsigned Rm = fieldFromInstruction(
Insn, 8, 4);
2711 unsigned Ra = fieldFromInstruction(
Insn, 12, 4);
2712 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2737 unsigned Pred = fieldFromInstruction(
Insn, 28, 4);
2738 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2739 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2759 unsigned Imm = fieldFromInstruction(
Insn, 9, 1);
2764 if (!FeatureBits[ARM::HasV8_1aOps] ||
2765 !FeatureBits[ARM::HasV8Ops])
2770 if (fieldFromInstruction(
Insn, 20,12) != 0xf11 ||
2771 fieldFromInstruction(
Insn, 4,4) != 0)
2773 if (fieldFromInstruction(
Insn, 10,10) != 0 ||
2774 fieldFromInstruction(
Insn, 0,4) != 0)
2788 unsigned add = fieldFromInstruction(Val, 12, 1);
2789 unsigned imm = fieldFromInstruction(Val, 0, 12);
2790 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2795 if (!
add) imm *= -1;
2796 if (imm == 0 && !
add) imm = INT32_MIN;
2809 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2811 unsigned U = fieldFromInstruction(Val, 8, 1);
2812 unsigned imm = fieldFromInstruction(Val, 0, 8);
2830 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2832 unsigned U = fieldFromInstruction(Val, 8, 1);
2833 unsigned imm = fieldFromInstruction(Val, 0, 8);
2863 unsigned S = fieldFromInstruction(
Insn, 26, 1);
2864 unsigned J1 = fieldFromInstruction(
Insn, 13, 1);
2865 unsigned J2 = fieldFromInstruction(
Insn, 11, 1);
2866 unsigned I1 = !(J1 ^
S);
2867 unsigned I2 = !(J2 ^
S);
2868 unsigned imm10 = fieldFromInstruction(
Insn, 16, 10);
2869 unsigned imm11 = fieldFromInstruction(
Insn, 0, 11);
2870 unsigned tmp = (
S << 23) | (
I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2871 int imm32 = SignExtend32<25>(
tmp << 1);
2873 true, 4, Inst, Decoder))
2884 unsigned pred = fieldFromInstruction(
Insn, 28, 4);
2885 unsigned imm = fieldFromInstruction(
Insn, 0, 24) << 2;
2889 imm |= fieldFromInstruction(
Insn, 24, 1) << 1;
2891 true, 4, Inst, Decoder))
2897 true, 4, Inst, Decoder))
2914 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2915 unsigned align = fieldFromInstruction(Val, 4, 2);
2932 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
2933 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
2934 unsigned wb = fieldFromInstruction(
Insn, 16, 4);
2935 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
2936 Rn |= fieldFromInstruction(
Insn, 4, 2) << 4;
2937 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
2941 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2942 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2943 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2944 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2945 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2946 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2947 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2948 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2949 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2956 case ARM::VLD2b16wb_fixed:
2957 case ARM::VLD2b16wb_register:
2958 case ARM::VLD2b32wb_fixed:
2959 case ARM::VLD2b32wb_register:
2960 case ARM::VLD2b8wb_fixed:
2961 case ARM::VLD2b8wb_register:
2975 case ARM::VLD3d8_UPD:
2976 case ARM::VLD3d16_UPD:
2977 case ARM::VLD3d32_UPD:
2981 case ARM::VLD4d8_UPD:
2982 case ARM::VLD4d16_UPD:
2983 case ARM::VLD4d32_UPD:
2990 case ARM::VLD3q8_UPD:
2991 case ARM::VLD3q16_UPD:
2992 case ARM::VLD3q32_UPD:
2996 case ARM::VLD4q8_UPD:
2997 case ARM::VLD4q16_UPD:
2998 case ARM::VLD4q32_UPD:
3011 case ARM::VLD3d8_UPD:
3012 case ARM::VLD3d16_UPD:
3013 case ARM::VLD3d32_UPD:
3017 case ARM::VLD4d8_UPD:
3018 case ARM::VLD4d16_UPD:
3019 case ARM::VLD4d32_UPD:
3026 case ARM::VLD3q8_UPD:
3027 case ARM::VLD3q16_UPD:
3028 case ARM::VLD3q32_UPD:
3032 case ARM::VLD4q8_UPD:
3033 case ARM::VLD4q16_UPD:
3034 case ARM::VLD4q32_UPD:
3047 case ARM::VLD4d8_UPD:
3048 case ARM::VLD4d16_UPD:
3049 case ARM::VLD4d32_UPD:
3056 case ARM::VLD4q8_UPD:
3057 case ARM::VLD4q16_UPD:
3058 case ARM::VLD4q32_UPD:
3068 case ARM::VLD1d8wb_fixed:
3069 case ARM::VLD1d16wb_fixed:
3070 case ARM::VLD1d32wb_fixed:
3071 case ARM::VLD1d64wb_fixed:
3072 case ARM::VLD1d8wb_register:
3073 case ARM::VLD1d16wb_register:
3074 case ARM::VLD1d32wb_register:
3075 case ARM::VLD1d64wb_register:
3076 case ARM::VLD1q8wb_fixed:
3077 case ARM::VLD1q16wb_fixed:
3078 case ARM::VLD1q32wb_fixed:
3079 case ARM::VLD1q64wb_fixed:
3080 case ARM::VLD1q8wb_register:
3081 case ARM::VLD1q16wb_register:
3082 case ARM::VLD1q32wb_register:
3083 case ARM::VLD1q64wb_register:
3084 case ARM::VLD1d8Twb_fixed:
3085 case ARM::VLD1d8Twb_register:
3086 case ARM::VLD1d16Twb_fixed:
3087 case ARM::VLD1d16Twb_register:
3088 case ARM::VLD1d32Twb_fixed:
3089 case ARM::VLD1d32Twb_register:
3090 case ARM::VLD1d64Twb_fixed:
3091 case ARM::VLD1d64Twb_register:
3092 case ARM::VLD1d8Qwb_fixed:
3093 case ARM::VLD1d8Qwb_register:
3094 case ARM::VLD1d16Qwb_fixed:
3095 case ARM::VLD1d16Qwb_register:
3096 case ARM::VLD1d32Qwb_fixed:
3097 case ARM::VLD1d32Qwb_register:
3098 case ARM::VLD1d64Qwb_fixed:
3099 case ARM::VLD1d64Qwb_register:
3100 case ARM::VLD2d8wb_fixed:
3101 case ARM::VLD2d16wb_fixed:
3102 case ARM::VLD2d32wb_fixed:
3103 case ARM::VLD2q8wb_fixed:
3104 case ARM::VLD2q16wb_fixed:
3105 case ARM::VLD2q32wb_fixed:
3106 case ARM::VLD2d8wb_register:
3107 case ARM::VLD2d16wb_register:
3108 case ARM::VLD2d32wb_register:
3109 case ARM::VLD2q8wb_register:
3110 case ARM::VLD2q16wb_register:
3111 case ARM::VLD2q32wb_register:
3112 case ARM::VLD2b8wb_fixed:
3113 case ARM::VLD2b16wb_fixed:
3114 case ARM::VLD2b32wb_fixed:
3115 case ARM::VLD2b8wb_register:
3116 case ARM::VLD2b16wb_register:
3117 case ARM::VLD2b32wb_register:
3120 case ARM::VLD3d8_UPD:
3121 case ARM::VLD3d16_UPD:
3122 case ARM::VLD3d32_UPD:
3123 case ARM::VLD3q8_UPD:
3124 case ARM::VLD3q16_UPD:
3125 case ARM::VLD3q32_UPD:
3126 case ARM::VLD4d8_UPD:
3127 case ARM::VLD4d16_UPD:
3128 case ARM::VLD4d32_UPD:
3129 case ARM::VLD4q8_UPD:
3130 case ARM::VLD4q16_UPD:
3131 case ARM::VLD4q32_UPD:
3158 case ARM::VLD1d8wb_fixed:
3159 case ARM::VLD1d16wb_fixed:
3160 case ARM::VLD1d32wb_fixed:
3161 case ARM::VLD1d64wb_fixed:
3162 case ARM::VLD1d8Twb_fixed:
3163 case ARM::VLD1d16Twb_fixed:
3164 case ARM::VLD1d32Twb_fixed:
3165 case ARM::VLD1d64Twb_fixed:
3166 case ARM::VLD1d8Qwb_fixed:
3167 case ARM::VLD1d16Qwb_fixed:
3168 case ARM::VLD1d32Qwb_fixed:
3169 case ARM::VLD1d64Qwb_fixed:
3170 case ARM::VLD1d8wb_register:
3171 case ARM::VLD1d16wb_register:
3172 case ARM::VLD1d32wb_register:
3173 case ARM::VLD1d64wb_register:
3174 case ARM::VLD1q8wb_fixed:
3175 case ARM::VLD1q16wb_fixed:
3176 case ARM::VLD1q32wb_fixed:
3177 case ARM::VLD1q64wb_fixed:
3178 case ARM::VLD1q8wb_register:
3179 case ARM::VLD1q16wb_register:
3180 case ARM::VLD1q32wb_register:
3181 case ARM::VLD1q64wb_register:
3185 if (Rm != 0xD && Rm != 0xF &&
3189 case ARM::VLD2d8wb_fixed:
3190 case ARM::VLD2d16wb_fixed:
3191 case ARM::VLD2d32wb_fixed:
3192 case ARM::VLD2b8wb_fixed:
3193 case ARM::VLD2b16wb_fixed:
3194 case ARM::VLD2b32wb_fixed:
3195 case ARM::VLD2q8wb_fixed:
3196 case ARM::VLD2q16wb_fixed:
3197 case ARM::VLD2q32wb_fixed:
3207 unsigned type = fieldFromInstruction(
Insn, 8, 4);
3208 unsigned align = fieldFromInstruction(
Insn, 4, 2);
3213 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3221 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3224 unsigned type = fieldFromInstruction(
Insn, 8, 4);
3225 unsigned align = fieldFromInstruction(
Insn, 4, 2);
3229 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3237 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3240 unsigned align = fieldFromInstruction(
Insn, 4, 2);
3243 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3251 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3254 unsigned load = fieldFromInstruction(
Insn, 21, 1);
3264 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3265 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3266 unsigned wb = fieldFromInstruction(
Insn, 16, 4);
3267 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3268 Rn |= fieldFromInstruction(
Insn, 4, 2) << 4;
3269 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3273 case ARM::VST1d8wb_fixed:
3274 case ARM::VST1d16wb_fixed:
3275 case ARM::VST1d32wb_fixed:
3276 case ARM::VST1d64wb_fixed:
3277 case ARM::VST1d8wb_register:
3278 case ARM::VST1d16wb_register:
3279 case ARM::VST1d32wb_register:
3280 case ARM::VST1d64wb_register:
3281 case ARM::VST1q8wb_fixed:
3282 case ARM::VST1q16wb_fixed:
3283 case ARM::VST1q32wb_fixed:
3284 case ARM::VST1q64wb_fixed:
3285 case ARM::VST1q8wb_register:
3286 case ARM::VST1q16wb_register:
3287 case ARM::VST1q32wb_register:
3288 case ARM::VST1q64wb_register:
3289 case ARM::VST1d8Twb_fixed:
3290 case ARM::VST1d16Twb_fixed:
3291 case ARM::VST1d32Twb_fixed:
3292 case ARM::VST1d64Twb_fixed:
3293 case ARM::VST1d8Twb_register:
3294 case ARM::VST1d16Twb_register:
3295 case ARM::VST1d32Twb_register:
3296 case ARM::VST1d64Twb_register:
3297 case ARM::VST1d8Qwb_fixed:
3298 case ARM::VST1d16Qwb_fixed:
3299 case ARM::VST1d32Qwb_fixed:
3300 case ARM::VST1d64Qwb_fixed:
3301 case ARM::VST1d8Qwb_register:
3302 case ARM::VST1d16Qwb_register:
3303 case ARM::VST1d32Qwb_register:
3304 case ARM::VST1d64Qwb_register:
3305 case ARM::VST2d8wb_fixed:
3306 case ARM::VST2d16wb_fixed:
3307 case ARM::VST2d32wb_fixed:
3308 case ARM::VST2d8wb_register:
3309 case ARM::VST2d16wb_register:
3310 case ARM::VST2d32wb_register:
3311 case ARM::VST2q8wb_fixed:
3312 case ARM::VST2q16wb_fixed:
3313 case ARM::VST2q32wb_fixed:
3314 case ARM::VST2q8wb_register:
3315 case ARM::VST2q16wb_register:
3316 case ARM::VST2q32wb_register:
3317 case ARM::VST2b8wb_fixed:
3318 case ARM::VST2b16wb_fixed:
3319 case ARM::VST2b32wb_fixed:
3320 case ARM::VST2b8wb_register:
3321 case ARM::VST2b16wb_register:
3322 case ARM::VST2b32wb_register:
3327 case ARM::VST3d8_UPD:
3328 case ARM::VST3d16_UPD:
3329 case ARM::VST3d32_UPD:
3330 case ARM::VST3q8_UPD:
3331 case ARM::VST3q16_UPD:
3332 case ARM::VST3q32_UPD:
3333 case ARM::VST4d8_UPD:
3334 case ARM::VST4d16_UPD:
3335 case ARM::VST4d32_UPD:
3336 case ARM::VST4q8_UPD:
3337 case ARM::VST4q16_UPD:
3338 case ARM::VST4q32_UPD:
3355 else if (Rm != 0xF) {
3360 case ARM::VST1d8wb_fixed:
3361 case ARM::VST1d16wb_fixed:
3362 case ARM::VST1d32wb_fixed:
3363 case ARM::VST1d64wb_fixed:
3364 case ARM::VST1q8wb_fixed:
3365 case ARM::VST1q16wb_fixed:
3366 case ARM::VST1q32wb_fixed:
3367 case ARM::VST1q64wb_fixed:
3368 case ARM::VST1d8Twb_fixed:
3369 case ARM::VST1d16Twb_fixed:
3370 case ARM::VST1d32Twb_fixed:
3371 case ARM::VST1d64Twb_fixed:
3372 case ARM::VST1d8Qwb_fixed:
3373 case ARM::VST1d16Qwb_fixed:
3374 case ARM::VST1d32Qwb_fixed:
3375 case ARM::VST1d64Qwb_fixed:
3376 case ARM::VST2d8wb_fixed:
3377 case ARM::VST2d16wb_fixed:
3378 case ARM::VST2d32wb_fixed:
3379 case ARM::VST2q8wb_fixed:
3380 case ARM::VST2q16wb_fixed:
3381 case ARM::VST2q32wb_fixed:
3382 case ARM::VST2b8wb_fixed:
3383 case ARM::VST2b16wb_fixed:
3384 case ARM::VST2b32wb_fixed:
3394 case ARM::VST1q16wb_fixed:
3395 case ARM::VST1q16wb_register:
3396 case ARM::VST1q32wb_fixed:
3397 case ARM::VST1q32wb_register:
3398 case ARM::VST1q64wb_fixed:
3399 case ARM::VST1q64wb_register:
3400 case ARM::VST1q8wb_fixed:
3401 case ARM::VST1q8wb_register:
3405 case ARM::VST2d16wb_fixed:
3406 case ARM::VST2d16wb_register:
3407 case ARM::VST2d32wb_fixed:
3408 case ARM::VST2d32wb_register:
3409 case ARM::VST2d8wb_fixed:
3410 case ARM::VST2d8wb_register:
3417 case ARM::VST2b16wb_fixed:
3418 case ARM::VST2b16wb_register:
3419 case ARM::VST2b32wb_fixed:
3420 case ARM::VST2b32wb_register:
3421 case ARM::VST2b8wb_fixed:
3422 case ARM::VST2b8wb_register:
3436 case ARM::VST3d8_UPD:
3437 case ARM::VST3d16_UPD:
3438 case ARM::VST3d32_UPD:
3442 case ARM::VST4d8_UPD:
3443 case ARM::VST4d16_UPD:
3444 case ARM::VST4d32_UPD:
3451 case ARM::VST3q8_UPD:
3452 case ARM::VST3q16_UPD:
3453 case ARM::VST3q32_UPD:
3457 case ARM::VST4q8_UPD:
3458 case ARM::VST4q16_UPD:
3459 case ARM::VST4q32_UPD:
3472 case ARM::VST3d8_UPD:
3473 case ARM::VST3d16_UPD:
3474 case ARM::VST3d32_UPD:
3478 case ARM::VST4d8_UPD:
3479 case ARM::VST4d16_UPD:
3480 case ARM::VST4d32_UPD:
3487 case ARM::VST3q8_UPD:
3488 case ARM::VST3q16_UPD:
3489 case ARM::VST3q32_UPD:
3493 case ARM::VST4q8_UPD:
3494 case ARM::VST4q16_UPD:
3495 case ARM::VST4q32_UPD:
3508 case ARM::VST4d8_UPD:
3509 case ARM::VST4d16_UPD:
3510 case ARM::VST4d32_UPD:
3517 case ARM::VST4q8_UPD:
3518 case ARM::VST4q16_UPD:
3519 case ARM::VST4q32_UPD:
3535 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3536 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3537 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3538 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3539 unsigned align = fieldFromInstruction(
Insn, 4, 1);
3540 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3547 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
3548 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
3549 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
3550 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
3571 if (Rm != 0xD && Rm != 0xF &&
3583 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3584 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3585 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3586 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3587 unsigned align = fieldFromInstruction(
Insn, 4, 1);
3588 unsigned size = 1 << fieldFromInstruction(
Insn, 6, 2);
3592 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
3593 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
3594 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
3595 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
3599 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
3600 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
3601 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
3602 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3619 if (Rm != 0xD && Rm != 0xF) {
3632 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3633 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3634 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3635 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3636 unsigned inc = fieldFromInstruction(
Insn, 5, 1) + 1;
3655 else if (Rm != 0xF) {
3668 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3669 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3670 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3671 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3672 unsigned size = fieldFromInstruction(
Insn, 6, 2);
3673 unsigned inc = fieldFromInstruction(
Insn, 5, 1) + 1;
3674 unsigned align = fieldFromInstruction(
Insn, 4, 1);
3708 else if (Rm != 0xF) {
3721 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3722 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3723 unsigned imm = fieldFromInstruction(
Insn, 0, 4);
3724 imm |= fieldFromInstruction(
Insn, 16, 3) << 4;
3725 imm |= fieldFromInstruction(
Insn, 24, 1) << 7;
3726 imm |= fieldFromInstruction(
Insn, 8, 4) << 8;
3727 imm |= fieldFromInstruction(
Insn, 5, 1) << 12;
3728 unsigned Q = fieldFromInstruction(
Insn, 6, 1);
3741 case ARM::VORRiv4i16:
3742 case ARM::VORRiv2i32:
3743 case ARM::VBICiv4i16:
3744 case ARM::VBICiv2i32:
3748 case ARM::VORRiv8i16:
3749 case ARM::VORRiv4i32:
3750 case ARM::VBICiv8i16:
3751 case ARM::VBICiv4i32:
3767 unsigned Qd = ((fieldFromInstruction(
Insn, 22, 1) << 3) |
3768 fieldFromInstruction(
Insn, 13, 3));
3769 unsigned cmode = fieldFromInstruction(
Insn, 8, 4);
3770 unsigned imm = fieldFromInstruction(
Insn, 0, 4);
3771 imm |= fieldFromInstruction(
Insn, 16, 3) << 4;
3772 imm |= fieldFromInstruction(
Insn, 28, 1) << 7;
3774 imm |= fieldFromInstruction(
Insn, 5, 1) << 12;
3776 if (cmode == 0xF && Inst.
getOpcode() == ARM::MVE_VMVNimmi32)
3796 unsigned Qd = fieldFromInstruction(
Insn, 13, 3);
3797 Qd |= fieldFromInstruction(
Insn, 22, 1) << 3;
3802 unsigned Qn = fieldFromInstruction(
Insn, 17, 3);
3803 Qn |= fieldFromInstruction(
Insn, 7, 1) << 3;
3806 unsigned Qm = fieldFromInstruction(
Insn, 1, 3);
3807 Qm |= fieldFromInstruction(
Insn, 5, 1) << 3;
3810 if (!fieldFromInstruction(
Insn, 12, 1))
3822 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3823 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3824 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3825 Rm |= fieldFromInstruction(
Insn, 5, 1) << 4;
3826 unsigned size = fieldFromInstruction(
Insn, 18, 2);
3870 unsigned Rd = fieldFromInstruction(
Insn, 12, 4);
3871 Rd |= fieldFromInstruction(
Insn, 22, 1) << 4;
3872 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
3873 Rn |= fieldFromInstruction(
Insn, 7, 1) << 4;
3874 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
3875 Rm |= fieldFromInstruction(
Insn, 5, 1) << 4;
3876 unsigned op = fieldFromInstruction(
Insn, 6, 1);
3907 unsigned dst = fieldFromInstruction(
Insn, 8, 3);
3908 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
3931 true, 2, Inst, Decoder))
3940 true, 4, Inst, Decoder))
3949 true, 2, Inst, Decoder))
3959 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3960 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3975 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3976 unsigned imm = fieldFromInstruction(Val, 3, 5);
3988 unsigned imm = Val << 2;
4010 unsigned Rn = fieldFromInstruction(Val, 6, 4);
4011 unsigned Rm = fieldFromInstruction(Val, 2, 4);
4012 unsigned imm = fieldFromInstruction(Val, 0, 2);
4040 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4041 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4044 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4046 bool hasMP = featureBits[ARM::FeatureMP];
4047 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4102 if (!hasV7Ops || !hasMP)
4110 unsigned addrmode = fieldFromInstruction(
Insn, 4, 2);
4111 addrmode |= fieldFromInstruction(
Insn, 0, 4) << 2;
4112 addrmode |= fieldFromInstruction(
Insn, 16, 4) << 6;
4124 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4125 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4126 unsigned U = fieldFromInstruction(
Insn, 9, 1);
4127 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
4130 unsigned add = fieldFromInstruction(
Insn, 9, 1);
4133 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4135 bool hasMP = featureBits[ARM::FeatureMP];
4136 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4146 case ARM::t2LDRSBi8:
4152 case ARM::t2LDRSHi8:
4169 case ARM::t2LDRSHi8:
4175 case ARM::t2LDRSBi8:
4191 if (!hasV7Ops || !hasMP)
4209 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4210 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4211 unsigned imm = fieldFromInstruction(
Insn, 0, 12);
4215 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4217 bool hasMP = featureBits[ARM::FeatureMP];
4218 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4225 case ARM::t2LDRHi12:
4228 case ARM::t2LDRSHi12:
4231 case ARM::t2LDRBi12:
4234 case ARM::t2LDRSBi12:
4251 case ARM::t2LDRSHi12:
4253 case ARM::t2LDRHi12:
4256 case ARM::t2LDRSBi12:
4271 case ARM::t2PLDWi12:
4272 if (!hasV7Ops || !hasMP)
4289 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4290 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4291 unsigned imm = fieldFromInstruction(
Insn, 0, 8);
4329 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4330 unsigned U = fieldFromInstruction(
Insn, 23, 1);
4331 int imm = fieldFromInstruction(
Insn, 0, 12);
4334 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4336 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4340 case ARM::t2LDRBpci:
4341 case ARM::t2LDRHpci:
4344 case ARM::t2LDRSBpci:
4347 case ARM::t2LDRSHpci:
4383 int imm = Val & 0xFF;
4385 if (!(Val & 0x100)) imm *= -1;
4397 int imm = Val & 0x7F;
4412 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4413 unsigned imm = fieldFromInstruction(Val, 0, 9);
4428 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4429 unsigned imm = fieldFromInstruction(Val, 0, 8);
4444 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4445 unsigned imm = fieldFromInstruction(Val, 0, 8);
4457 int imm = Val & 0xFF;
4460 else if (!(Val & 0x100))
4467 template <
int shift>
4470 int imm = Val & 0x7F;
4473 else if (!(Val & 0x80))
4475 if (imm != INT32_MIN)
4476 imm *= (1U <<
shift);
4487 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4488 unsigned imm = fieldFromInstruction(Val, 0, 9);
4529 template <
int shift>
4535 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4536 unsigned imm = fieldFromInstruction(Val, 0, 8);
4540 if (!
Check(
S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4546 template <
int shift,
int WriteBack>
4552 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4553 unsigned imm = fieldFromInstruction(Val, 0, 8);
4559 if (!
Check(
S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4570 unsigned Rt = fieldFromInstruction(
Insn, 12, 4);
4571 unsigned Rn = fieldFromInstruction(
Insn, 16, 4);
4572 unsigned addr = fieldFromInstruction(
Insn, 0, 8);
4573 addr |= fieldFromInstruction(
Insn, 9, 1) << 8;
4575 unsigned load = fieldFromInstruction(
Insn, 20, 1);
4579 case ARM::t2LDR_PRE:
4580 case ARM::t2LDR_POST:
4583 case ARM::t2LDRB_PRE:
4584 case ARM::t2LDRB_POST:
4587 case ARM::t2LDRH_PRE:
4588 case ARM::t2LDRH_POST:
4591 case ARM::t2LDRSB_PRE:
4592 case ARM::t2LDRSB_POST:
4598 case ARM::t2LDRSH_PRE:
4599 case ARM::t2LDRSH_POST:
4632 unsigned Rn = fieldFromInstruction(Val, 13, 4);
4633 unsigned imm = fieldFromInstruction(Val, 0, 12);
4638 case ARM::t2STRBi12:
4639 case ARM::t2STRHi12:
4657 unsigned imm = fieldFromInstruction(
Insn, 0, 7);
4672 unsigned Rdm = fieldFromInstruction(
Insn, 0, 3);
4673 Rdm |= fieldFromInstruction(
Insn, 7, 1) << 3;
4680 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
4681 unsigned Rm = fieldFromInstruction(
Insn, 3, 4);
4695 unsigned imod = fieldFromInstruction(
Insn, 4, 1) | 0x2;
4696 unsigned flags = fieldFromInstruction(
Insn, 0, 3);
4708 unsigned Rm = fieldFromInstruction(
Insn, 0, 4);
4709 unsigned add = fieldFromInstruction(
Insn, 4, 1);
4722 unsigned Rn = fieldFromInstruction(
Insn, 3, 4);
4723 unsigned Qm = fieldFromInstruction(
Insn, 0, 3);
4733 template <
int shift>
4738 unsigned Qm = fieldFromInstruction(
Insn, 8, 3);
4739 int imm = fieldFromInstruction(
Insn, 0, 7);