34 #define DEBUG_TYPE "arm-disassembler" 53 void advanceITState() {
58 bool instrInITBlock() {
59 return !ITStates.empty();
63 bool instrLastInITBlock() {
64 return ITStates.size() == 1;
71 void setITState(
char Firstcond,
char Mask) {
73 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
74 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
75 assert(NumTZ <= 3 &&
"Invalid IT mask!");
77 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78 unsigned Else = (Mask >> Pos) & 1;
79 ITStates.push_back(CCBits ^ Else);
81 ITStates.push_back(CCBits);
85 std::vector<unsigned char> ITStates;
91 unsigned getVPTPred() {
93 if (instrInVPTBlock())
94 Pred = VPTStates.back();
98 void advanceVPTState() {
102 bool instrInVPTBlock() {
103 return !VPTStates.empty();
106 bool instrLastInVPTBlock() {
107 return VPTStates.size() == 1;
110 void setVPTState(
char Mask) {
112 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
113 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
115 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116 bool T = ((Mask >> Pos) & 1) == 0;
136 ~ARMDisassembler()
override =
default;
154 mutable ITStatus ITBlock;
155 mutable VPTStatus VPTBlock;
181 uint64_t
Address,
const void *Decoder);
183 uint64_t
Address,
const void *Decoder);
185 uint64_t
Address,
const void *Decoder);
187 uint64_t
Address,
const void *Decoder);
189 unsigned RegNo, uint64_t
Address,
190 const void *Decoder);
192 unsigned RegNo, uint64_t
Address,
193 const void *Decoder);
195 unsigned RegNo, uint64_t
Address,
196 const void *Decoder);
198 MCInst &Inst,
unsigned RegNo, uint64_t
Address,
const void *Decoder);
200 uint64_t
Address,
const void *Decoder);
202 uint64_t
Address,
const void *Decoder);
204 uint64_t
Address,
const void *Decoder);
206 uint64_t
Address,
const void *Decoder);
208 uint64_t
Address,
const void *Decoder);
210 uint64_t
Address,
const void *Decoder);
212 uint64_t
Address,
const void *Decoder);
214 uint64_t
Address,
const void *Decoder);
216 uint64_t
Address,
const void *Decoder);
220 const void *Decoder);
222 uint64_t
Address,
const void *Decoder);
224 uint64_t
Address,
const void *Decoder);
226 uint64_t
Address,
const void *Decoder);
228 uint64_t
Address,
const void *Decoder);
230 uint64_t
Address,
const void *Decoder);
232 unsigned RegNo, uint64_t
Address,
233 const void *Decoder);
236 uint64_t
Address,
const void *Decoder);
238 uint64_t
Address,
const void *Decoder);
240 uint64_t
Address,
const void *Decoder);
242 uint64_t
Address,
const void *Decoder);
244 uint64_t
Address,
const void *Decoder);
247 uint64_t
Address,
const void *Decoder);
249 uint64_t
Address,
const void *Decoder);
253 const void *Decoder);
255 uint64_t
Address,
const void *Decoder);
257 uint64_t
Address,
const void *Decoder);
259 uint64_t
Address,
const void *Decoder);
261 uint64_t
Address,
const void *Decoder);
266 const void *Decoder);
268 uint64_t
Address,
const void *Decoder);
270 uint64_t
Address,
const void *Decoder);
272 uint64_t
Address,
const void *Decoder);
274 uint64_t
Address,
const void *Decoder);
276 uint64_t
Address,
const void *Decoder);
278 uint64_t
Address,
const void *Decoder);
280 uint64_t
Address,
const void *Decoder);
282 uint64_t
Address,
const void *Decoder);
284 uint64_t
Address,
const void *Decoder);
286 uint64_t
Address,
const void *Decoder);
288 uint64_t
Address,
const void *Decoder);
290 uint64_t
Address,
const void *Decoder);
292 uint64_t
Address,
const void *Decoder);
294 uint64_t
Address,
const void *Decoder);
296 uint64_t
Address,
const void *Decoder);
298 uint64_t
Address,
const void *Decoder);
300 uint64_t
Address,
const void *Decoder);
302 uint64_t
Address,
const void *Decoder);
304 uint64_t
Address,
const void *Decoder);
306 uint64_t
Address,
const void *Decoder);
308 uint64_t
Address,
const void *Decoder);
310 uint64_t
Address,
const void *Decoder);
312 uint64_t
Address,
const void *Decoder);
314 uint64_t
Address,
const void *Decoder);
316 uint64_t
Address,
const void *Decoder);
318 uint64_t
Address,
const void *Decoder);
320 uint64_t
Address,
const void *Decoder);
322 uint64_t
Address,
const void *Decoder);
324 uint64_t
Address,
const void *Decoder);
326 uint64_t
Address,
const void *Decoder);
328 uint64_t
Address,
const void *Decoder);
330 uint64_t
Address,
const void *Decoder);
332 uint64_t
Address,
const void *Decoder);
334 uint64_t
Address,
const void *Decoder);
336 uint64_t
Address,
const void *Decoder);
338 uint64_t
Address,
const void *Decoder);
341 uint64_t
Address,
const void *Decoder);
343 uint64_t
Address,
const void *Decoder);
345 uint64_t
Address,
const void *Decoder);
347 uint64_t
Address,
const void *Decoder);
349 uint64_t
Address,
const void *Decoder);
351 uint64_t
Address,
const void *Decoder);
353 uint64_t
Address,
const void *Decoder);
355 uint64_t
Address,
const void *Decoder);
357 uint64_t
Address,
const void *Decoder);
359 uint64_t
Address,
const void *Decoder);
361 uint64_t
Address,
const void *Decoder);
363 uint64_t
Address,
const void *Decoder);
365 uint64_t
Address,
const void *Decoder);
367 uint64_t
Address,
const void *Decoder);
369 uint64_t
Address,
const void *Decoder);
371 uint64_t
Address,
const void *Decoder);
373 uint64_t
Address,
const void *Decoder);
375 uint64_t
Address,
const void *Decoder);
377 uint64_t
Address,
const void *Decoder);
379 uint64_t
Address,
const void *Decoder);
381 uint64_t
Address,
const void *Decoder);
383 uint64_t
Address,
const void *Decoder);
385 uint64_t
Address,
const void *Decoder);
387 uint64_t
Address,
const void *Decoder);
389 uint64_t
Address,
const void *Decoder);
391 uint64_t
Address,
const void *Decoder);
395 const void *Decoder);
398 uint64_t
Address,
const void *Decoder);
400 uint64_t
Address,
const void *Decoder);
402 uint64_t
Address,
const void *Decoder);
404 uint64_t
Address,
const void *Decoder);
406 uint64_t
Address,
const void *Decoder);
408 uint64_t
Address,
const void *Decoder);
410 uint64_t
Address,
const void *Decoder);
412 uint64_t
Address,
const void *Decoder);
414 uint64_t
Address,
const void *Decoder);
416 uint64_t
Address,
const void *Decoder);
418 uint64_t
Address,
const void* Decoder);
420 uint64_t
Address,
const void* Decoder);
422 uint64_t
Address,
const void* Decoder);
424 uint64_t
Address,
const void* Decoder);
426 uint64_t
Address,
const void *Decoder);
428 uint64_t
Address,
const void *Decoder);
430 uint64_t
Address,
const void *Decoder);
433 const void *Decoder);
435 uint64_t
Address,
const void *Decoder);
437 uint64_t
Address,
const void *Decoder);
440 uint64_t
Address,
const void *Decoder);
442 uint64_t
Address,
const void *Decoder);
445 uint64_t
Address,
const void *Decoder);
446 template<
int shift,
int WriteBack>
448 uint64_t
Address,
const void *Decoder);
450 uint64_t
Address,
const void *Decoder);
452 uint64_t
Address,
const void *Decoder);
454 uint64_t
Address,
const void *Decoder);
456 uint64_t
Address,
const void *Decoder);
458 uint64_t
Address,
const void *Decoder);
460 uint64_t
Address,
const void *Decoder);
462 uint64_t
Address,
const void *Decoder);
464 uint64_t
Address,
const void *Decoder);
466 uint64_t
Address,
const void *Decoder);
468 uint64_t
Address,
const void *Decoder);
470 uint64_t
Address,
const void *Decoder);
472 uint64_t
Address,
const void *Decoder);
474 uint64_t
Address,
const void *Decoder);
476 uint64_t
Address,
const void *Decoder);
478 uint64_t
Address,
const void *Decoder);
480 uint64_t
Address,
const void *Decoder);
482 uint64_t
Address,
const void *Decoder);
485 uint64_t
Address,
const void *Decoder);
487 uint64_t
Address,
const void *Decoder);
489 uint64_t
Address,
const void *Decoder);
491 template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
493 uint64_t
Address,
const void *Decoder);
496 const void *Decoder);
499 const void *Decoder);
501 const void *Decoder);
504 const void *Decoder);
506 const void *Decoder);
508 uint64_t
Address,
const void *Decoder);
510 uint64_t
Address,
const void *Decoder);
513 const void *Decoder);
516 const void *Decoder);
519 const void *Decoder);
523 const void *Decoder);
524 template<
bool Writeback>
527 const void *Decoder);
530 uint64_t
Address,
const void *Decoder);
533 uint64_t
Address,
const void *Decoder);
536 uint64_t
Address,
const void *Decoder);
537 template<
unsigned MinLog,
unsigned MaxLog>
540 const void *Decoder);
544 const void *Decoder);
545 template<
unsigned start>
548 const void *Decoder);
551 const void *Decoder);
554 const void *Decoder);
556 uint64_t
Address,
const void *Decoder);
558 uint64_t
Address,
const void *Decoder);
559 template<
bool scalar, OperandDecoder predicate_decoder>
561 uint64_t
Address,
const void *Decoder);
563 uint64_t
Address,
const void *Decoder);
565 uint64_t
Address,
const void *Decoder);
568 const void *Decoder);
569 #include "ARMGenDisassemblerTables.inc" 574 return new ARMDisassembler(STI, Ctx);
606 default:
return Result;
614 if (STI.getFeatureBits()[ARM::ModeThumb])
615 return getThumbInstruction(MI,
Size, Bytes,
Address, OS, CS);
616 return getARMInstruction(MI,
Size, Bytes,
Address, OS, CS);
626 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
627 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 631 if (Bytes.
size() < 4) {
638 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
653 const DecodeTable Tables[] = {
654 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
655 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
656 {DecoderTableNEONDup32,
true}, {DecoderTablev8NEON32,
false},
657 {DecoderTablev8Crypto32,
false},
660 for (
auto Table : Tables) {
703 MCInst &MI,
const void *Decoder) {
720 const void *Decoder) {
733 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
734 if (I == MI.
end())
break;
735 if (OpInfo[i].isOptionalDef() && OpInfo[i].
RegClass == ARM::CCRRegClassID) {
736 if (i > 0 && OpInfo[i-1].isPredicate())
continue;
748 for (
unsigned i = 0; i < NumOps; ++i) {
760 ARMDisassembler::AddThumbPredicate(
MCInst &MI)
const {
763 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
784 if (ITBlock.instrInITBlock())
790 if (MI.
getOperand(0).
getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
799 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
816 if (ITBlock.instrInITBlock()) {
817 CC = ITBlock.getITCC();
818 ITBlock.advanceITState();
819 }
else if (VPTBlock.instrInVPTBlock()) {
820 VCC = VPTBlock.getVPTPred();
821 VPTBlock.advanceVPTState();
828 for (
unsigned i = 0; i < NumOps; ++i, ++CCI) {
829 if (OpInfo[i].isPredicate() || CCI == MI.
end())
break;
845 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
860 "Inactive register in vpred_r is not tied to an output!");
875 void ARMDisassembler::UpdateThumbVFPPredicate(
878 CC = ITBlock.getITCC();
881 if (ITBlock.instrInITBlock())
882 ITBlock.advanceITState();
883 else if (VPTBlock.instrInVPTBlock()) {
884 CC = VPTBlock.getVPTPred();
885 VPTBlock.advanceVPTState();
891 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
892 if (OpInfo[i].isPredicate() ) {
900 I->setReg(ARM::CPSR);
913 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
914 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
917 if (Bytes.
size() < 2) {
922 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
927 Check(Result, AddThumbPredicate(MI));
935 bool InITBlock = ITBlock.instrInITBlock();
936 Check(Result, AddThumbPredicate(MI));
948 if (MI.
getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
951 Check(Result, AddThumbPredicate(MI));
959 ITBlock.setITState(Firstcond, Mask);
963 CS <<
"unpredictable IT predicate sequence";
970 if (Bytes.
size() < 4) {
976 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
988 Check(Result, AddThumbPredicate(MI));
992 VPTBlock.setVPTState(Mask);
1002 bool InITBlock = ITBlock.instrInITBlock();
1003 Check(Result, AddThumbPredicate(MI));
1012 Check(Result, AddThumbPredicate(MI));
1016 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1021 UpdateThumbVFPPredicate(Result, MI);
1033 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1038 Check(Result, AddThumbPredicate(MI));
1043 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1045 NEONLdStInsn &= 0xF0FFFFFF;
1046 NEONLdStInsn |= 0x04000000;
1051 Check(Result, AddThumbPredicate(MI));
1056 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1058 NEONDataInsn &= 0xF0FFFFFF;
1059 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
1060 NEONDataInsn |= 0x12000000;
1065 Check(Result, AddThumbPredicate(MI));
1070 NEONCryptoInsn &= 0xF0FFFFFF;
1071 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
1072 NEONCryptoInsn |= 0x12000000;
1081 NEONv8Insn &= 0xF3FFFFFF;
1094 Check(Result, AddThumbPredicate(MI));
1114 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1116 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1117 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1121 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1123 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1124 ARM::R12, 0, ARM::LR, ARM::APSR
1128 uint64_t
Address,
const void *Decoder) {
1139 const void *Decoder) {
1153 uint64_t
Address,
const void *Decoder) {
1166 uint64_t
Address,
const void *Decoder) {
1181 uint64_t
Address,
const void *Decoder) {
1199 uint64_t
Address,
const void *Decoder) {
1208 uint64_t
Address,
const void *Decoder) {
1215 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1216 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1220 uint64_t
Address,
const void *Decoder) {
1226 if ((RegNo & 1) || RegNo == 0xe)
1235 uint64_t
Address,
const void *Decoder) {
1254 Register = ARM::R12;
1265 uint64_t
Address,
const void *Decoder) {
1269 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1271 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1279 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1280 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1281 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1282 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1283 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1284 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1285 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1286 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1290 uint64_t
Address,
const void *Decoder) {
1300 uint64_t
Address,
const void *Decoder) {
1305 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1306 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1307 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1308 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1309 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1310 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1311 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1312 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1316 uint64_t
Address,
const void *Decoder) {
1318 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1320 bool hasD32 = featureBits[ARM::FeatureD32];
1322 if (RegNo > 31 || (!hasD32 && RegNo > 15))
1331 uint64_t
Address,
const void *Decoder) {
1338 uint64_t
Address,
const void *Decoder) {
1346 uint64_t
Address,
const void *Decoder) {
1353 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1354 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1355 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1356 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1360 uint64_t
Address,
const void *Decoder) {
1361 if (RegNo > 31 || (RegNo & 1) != 0)
1371 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1372 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1373 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1374 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1375 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1380 uint64_t
Address,
const void *Decoder) {
1390 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1391 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1392 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1393 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1394 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1395 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1396 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1397 ARM::D28_D30, ARM::D29_D31
1403 const void *Decoder) {
1413 uint64_t
Address,
const void *Decoder) {
1417 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1430 uint64_t
Address,
const void *Decoder) {
1439 uint64_t
Address,
const void *Decoder) {
1442 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1443 unsigned type = fieldFromInstruction(Val, 5, 2);
1444 unsigned imm = fieldFromInstruction(Val, 7, 5);
1469 unsigned Op = Shift | (imm << 3);
1476 uint64_t
Address,
const void *Decoder) {
1479 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1480 unsigned type = fieldFromInstruction(Val, 5, 2);
1481 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1511 uint64_t
Address,
const void *Decoder) {
1514 bool NeedDisjointWriteback =
false;
1515 unsigned WritebackReg = 0;
1520 case ARM::LDMIA_UPD:
1521 case ARM::LDMDB_UPD:
1522 case ARM::LDMIB_UPD:
1523 case ARM::LDMDA_UPD:
1524 case ARM::t2LDMIA_UPD:
1525 case ARM::t2LDMDB_UPD:
1526 case ARM::t2STMIA_UPD:
1527 case ARM::t2STMDB_UPD:
1528 NeedDisjointWriteback =
true;
1538 for (
unsigned i = 0; i < 16; ++i) {
1539 if (Val & (1 << i)) {
1548 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1558 uint64_t
Address,
const void *Decoder) {
1561 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1562 unsigned regs = fieldFromInstruction(Val, 0, 8);
1565 if (regs == 0 || (Vd + regs) > 32) {
1566 regs = Vd + regs > 32 ? 32 - Vd : regs;
1573 for (
unsigned i = 0; i < (regs - 1); ++i) {
1582 uint64_t
Address,
const void *Decoder) {
1585 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1586 unsigned regs = fieldFromInstruction(Val, 1, 7);
1589 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1590 regs = Vd + regs > 32 ? 32 - Vd : regs;
1592 regs = std::min(16u, regs);
1598 for (
unsigned i = 0; i < (regs - 1); ++i) {
1607 uint64_t
Address,
const void *Decoder) {
1613 unsigned msb = fieldFromInstruction(Val, 5, 5);
1614 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1626 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1627 uint32_t lsb_mask = (1U << lsb) - 1;
1634 uint64_t
Address,
const void *Decoder) {
1637 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1638 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1639 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1640 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1641 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1642 unsigned U = fieldFromInstruction(Insn, 23, 1);
1644 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1647 case ARM::LDC_OFFSET:
1650 case ARM::LDC_OPTION:
1651 case ARM::LDCL_OFFSET:
1653 case ARM::LDCL_POST:
1654 case ARM::LDCL_OPTION:
1655 case ARM::STC_OFFSET:
1658 case ARM::STC_OPTION:
1659 case ARM::STCL_OFFSET:
1661 case ARM::STCL_POST:
1662 case ARM::STCL_OPTION:
1663 case ARM::t2LDC_OFFSET:
1664 case ARM::t2LDC_PRE:
1665 case ARM::t2LDC_POST:
1666 case ARM::t2LDC_OPTION:
1667 case ARM::t2LDCL_OFFSET:
1668 case ARM::t2LDCL_PRE:
1669 case ARM::t2LDCL_POST:
1670 case ARM::t2LDCL_OPTION:
1671 case ARM::t2STC_OFFSET:
1672 case ARM::t2STC_PRE:
1673 case ARM::t2STC_POST:
1674 case ARM::t2STC_OPTION:
1675 case ARM::t2STCL_OFFSET:
1676 case ARM::t2STCL_PRE:
1677 case ARM::t2STCL_POST:
1678 case ARM::t2STCL_OPTION:
1679 case ARM::t2LDC2_OFFSET:
1680 case ARM::t2LDC2L_OFFSET:
1681 case ARM::t2LDC2_PRE:
1682 case ARM::t2LDC2L_PRE:
1683 case ARM::t2STC2_OFFSET:
1684 case ARM::t2STC2L_OFFSET:
1685 case ARM::t2STC2_PRE:
1686 case ARM::t2STC2L_PRE:
1687 case ARM::LDC2_OFFSET:
1688 case ARM::LDC2L_OFFSET:
1690 case ARM::LDC2L_PRE:
1691 case ARM::STC2_OFFSET:
1692 case ARM::STC2L_OFFSET:
1694 case ARM::STC2L_PRE:
1695 case ARM::t2LDC2_OPTION:
1696 case ARM::t2STC2_OPTION:
1697 case ARM::t2LDC2_POST:
1698 case ARM::t2LDC2L_POST:
1699 case ARM::t2STC2_POST:
1700 case ARM::t2STC2L_POST:
1701 case ARM::LDC2_POST:
1702 case ARM::LDC2L_POST:
1703 case ARM::STC2_POST:
1704 case ARM::STC2L_POST:
1705 if (coproc == 0xA || coproc == 0xB ||
1706 (featureBits[ARM::HasV8_1MMainlineOps] &&
1707 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1708 coproc == 0xE || coproc == 0xF)))
1715 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1724 case ARM::t2LDC2_OFFSET:
1725 case ARM::t2LDC2L_OFFSET:
1726 case ARM::t2LDC2_PRE:
1727 case ARM::t2LDC2L_PRE:
1728 case ARM::t2STC2_OFFSET:
1729 case ARM::t2STC2L_OFFSET:
1730 case ARM::t2STC2_PRE:
1731 case ARM::t2STC2L_PRE:
1732 case ARM::LDC2_OFFSET:
1733 case ARM::LDC2L_OFFSET:
1735 case ARM::LDC2L_PRE:
1736 case ARM::STC2_OFFSET:
1737 case ARM::STC2L_OFFSET:
1739 case ARM::STC2L_PRE:
1740 case ARM::t2LDC_OFFSET:
1741 case ARM::t2LDCL_OFFSET:
1742 case ARM::t2LDC_PRE:
1743 case ARM::t2LDCL_PRE:
1744 case ARM::t2STC_OFFSET:
1745 case ARM::t2STCL_OFFSET:
1746 case ARM::t2STC_PRE:
1747 case ARM::t2STCL_PRE:
1748 case ARM::LDC_OFFSET:
1749 case ARM::LDCL_OFFSET:
1752 case ARM::STC_OFFSET:
1753 case ARM::STCL_OFFSET:
1759 case ARM::t2LDC2_POST:
1760 case ARM::t2LDC2L_POST:
1761 case ARM::t2STC2_POST:
1762 case ARM::t2STC2L_POST:
1763 case ARM::LDC2_POST:
1764 case ARM::LDC2L_POST:
1765 case ARM::STC2_POST:
1766 case ARM::STC2L_POST:
1767 case ARM::t2LDC_POST:
1768 case ARM::t2LDCL_POST:
1769 case ARM::t2STC_POST:
1770 case ARM::t2STCL_POST:
1772 case ARM::LDCL_POST:
1774 case ARM::STCL_POST:
1785 case ARM::LDC_OFFSET:
1788 case ARM::LDC_OPTION:
1789 case ARM::LDCL_OFFSET:
1791 case ARM::LDCL_POST:
1792 case ARM::LDCL_OPTION:
1793 case ARM::STC_OFFSET:
1796 case ARM::STC_OPTION:
1797 case ARM::STCL_OFFSET:
1799 case ARM::STCL_POST:
1800 case ARM::STCL_OPTION:
1813 uint64_t
Address,
const void *Decoder) {
1816 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1817 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1818 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1819 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1820 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1821 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1822 unsigned P = fieldFromInstruction(Insn, 24, 1);
1823 unsigned W = fieldFromInstruction(Insn, 21, 1);
1827 case ARM::STR_POST_IMM:
1828 case ARM::STR_POST_REG:
1829 case ARM::STRB_POST_IMM:
1830 case ARM::STRB_POST_REG:
1831 case ARM::STRT_POST_REG:
1832 case ARM::STRT_POST_IMM:
1833 case ARM::STRBT_POST_REG:
1834 case ARM::STRBT_POST_IMM:
1847 case ARM::LDR_POST_IMM:
1848 case ARM::LDR_POST_REG:
1849 case ARM::LDRB_POST_IMM:
1850 case ARM::LDRB_POST_REG:
1851 case ARM::LDRBT_POST_REG:
1852 case ARM::LDRBT_POST_IMM:
1853 case ARM::LDRT_POST_REG:
1854 case ARM::LDRT_POST_IMM:
1866 if (!fieldFromInstruction(Insn, 23, 1))
1869 bool writeback = (P == 0) || (W == 1);
1870 unsigned idx_mode = 0;
1873 else if (!P && writeback)
1876 if (writeback && (Rn == 15 || Rn == Rt))
1883 switch( fieldFromInstruction(Insn, 5, 2)) {
1899 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1918 uint64_t
Address,
const void *Decoder) {
1921 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1922 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1923 unsigned type = fieldFromInstruction(Val, 5, 2);
1924 unsigned imm = fieldFromInstruction(Val, 7, 5);
1925 unsigned U = fieldFromInstruction(Val, 12, 1);
1962 uint64_t
Address,
const void *Decoder) {
1965 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1966 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1967 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1968 unsigned type = fieldFromInstruction(Insn, 22, 1);
1969 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1970 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1971 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1972 unsigned W = fieldFromInstruction(Insn, 21, 1);
1973 unsigned P = fieldFromInstruction(Insn, 24, 1);
1974 unsigned Rt2 = Rt + 1;
1976 bool writeback = (W == 1) | (P == 0);
1982 case ARM::STRD_POST:
1985 case ARM::LDRD_POST:
1994 case ARM::STRD_POST:
1995 if (P == 0 && W == 1)
1998 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2000 if (type && Rm == 15)
2004 if (!type && fieldFromInstruction(Insn, 8, 4))
2009 case ARM::STRH_POST:
2012 if (writeback && (Rn == 15 || Rn == Rt))
2014 if (!type && Rm == 15)
2019 case ARM::LDRD_POST:
2020 if (type && Rn == 15) {
2025 if (P == 0 && W == 1)
2027 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2029 if (!type && writeback && Rn == 15)
2031 if (writeback && (Rn == Rt || Rn == Rt2))
2036 case ARM::LDRH_POST:
2037 if (type && Rn == 15) {
2044 if (!type && Rm == 15)
2046 if (!type && writeback && (Rn == 15 || Rn == Rt))
2050 case ARM::LDRSH_PRE:
2051 case ARM::LDRSH_POST:
2053 case ARM::LDRSB_PRE:
2054 case ARM::LDRSB_POST:
2055 if (type && Rn == 15) {
2060 if (type && (Rt == 15 || (writeback && Rn == Rt)))
2062 if (!type && (Rt == 15 || Rm == 15))
2064 if (!type && writeback && (Rn == 15 || Rn == Rt))
2081 case ARM::STRD_POST:
2084 case ARM::STRH_POST:
2098 case ARM::STRD_POST:
2101 case ARM::LDRD_POST:
2114 case ARM::LDRD_POST:
2117 case ARM::LDRH_POST:
2119 case ARM::LDRSH_PRE:
2120 case ARM::LDRSH_POST:
2122 case ARM::LDRSB_PRE:
2123 case ARM::LDRSB_POST:
2153 uint64_t
Address,
const void *Decoder) {
2156 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2157 unsigned mode = fieldFromInstruction(Insn, 23, 2);
2182 uint64_t
Address,
const void *Decoder) {
2185 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2186 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2187 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2188 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2206 uint64_t
Address,
const void *Decoder) {
2209 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2210 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2211 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2219 case ARM::LDMDA_UPD:
2225 case ARM::LDMDB_UPD:
2231 case ARM::LDMIA_UPD:
2237 case ARM::LDMIB_UPD:
2243 case ARM::STMDA_UPD:
2249 case ARM::STMDB_UPD:
2255 case ARM::STMIA_UPD:
2261 case ARM::STMIB_UPD:
2269 if (fieldFromInstruction(Insn, 20, 1) == 0) {
2271 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2272 fieldFromInstruction(Insn, 20, 1) == 0))
2297 uint64_t
Address,
const void *Decoder) {
2298 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2299 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2312 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2319 uint64_t
Address,
const void *Decoder) {
2320 unsigned imod = fieldFromInstruction(Insn, 18, 2);
2321 unsigned M = fieldFromInstruction(Insn, 17, 1);
2322 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2323 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2329 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2330 fieldFromInstruction(Insn, 16, 1) != 0 ||
2331 fieldFromInstruction(Insn, 20, 8) != 0x10)
2346 }
else if (imod && !M) {
2351 }
else if (!imod && M) {
2366 uint64_t
Address,
const void *Decoder) {
2367 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2368 unsigned M = fieldFromInstruction(Insn, 8, 1);
2369 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2370 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2386 }
else if (imod && !M) {
2391 }
else if (!imod && M) {
2397 int imm = fieldFromInstruction(Insn, 0, 8);
2408 uint64_t
Address,
const void *Decoder) {
2411 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2414 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2415 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2416 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2417 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2432 uint64_t
Address,
const void *Decoder) {
2435 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2436 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2439 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2440 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2459 uint64_t
Address,
const void *Decoder) {
2462 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2463 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2464 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2465 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2466 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2487 uint64_t
Address,
const void *Decoder) {
2490 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2491 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2492 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2508 uint64_t
Address,
const void *Decoder) {
2511 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2516 if (!FeatureBits[ARM::HasV8_1aOps] ||
2517 !FeatureBits[ARM::HasV8Ops])
2522 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2523 fieldFromInstruction(Insn, 4,4) != 0)
2525 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2526 fieldFromInstruction(Insn, 0,4) != 0)
2536 uint64_t
Address,
const void *Decoder) {
2539 unsigned add = fieldFromInstruction(Val, 12, 1);
2540 unsigned imm = fieldFromInstruction(Val, 0, 12);
2541 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2546 if (!add) imm *= -1;
2547 if (imm == 0 && !add) imm = INT32_MIN;
2556 uint64_t
Address,
const void *Decoder) {
2559 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2561 unsigned U = fieldFromInstruction(Val, 8, 1);
2562 unsigned imm = fieldFromInstruction(Val, 0, 8);
2576 uint64_t
Address,
const void *Decoder) {
2579 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2581 unsigned U = fieldFromInstruction(Val, 8, 1);
2582 unsigned imm = fieldFromInstruction(Val, 0, 8);
2596 uint64_t
Address,
const void *Decoder) {
2602 uint64_t
Address,
const void *Decoder) {
2611 unsigned S = fieldFromInstruction(Insn, 26, 1);
2612 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2613 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2614 unsigned I1 = !(J1 ^ S);
2615 unsigned I2 = !(J2 ^ S);
2616 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2617 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2618 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2619 int imm32 = SignExtend32<25>(tmp << 1);
2621 true, 4, Inst, Decoder))
2629 uint64_t
Address,
const void *Decoder) {
2632 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2633 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2637 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2639 true, 4, Inst, Decoder))
2645 true, 4, Inst, Decoder))
2654 uint64_t
Address,
const void *Decoder) {
2657 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2658 unsigned align = fieldFromInstruction(Val, 4, 2);
2671 uint64_t
Address,
const void *Decoder) {
2674 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2675 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2676 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2677 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2678 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2679 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2683 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2684 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2685 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2686 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2687 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2688 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2689 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2690 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2691 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2698 case ARM::VLD2b16wb_fixed:
2699 case ARM::VLD2b16wb_register:
2700 case ARM::VLD2b32wb_fixed:
2701 case ARM::VLD2b32wb_register:
2702 case ARM::VLD2b8wb_fixed:
2703 case ARM::VLD2b8wb_register:
2717 case ARM::VLD3d8_UPD:
2718 case ARM::VLD3d16_UPD:
2719 case ARM::VLD3d32_UPD:
2723 case ARM::VLD4d8_UPD:
2724 case ARM::VLD4d16_UPD:
2725 case ARM::VLD4d32_UPD:
2732 case ARM::VLD3q8_UPD:
2733 case ARM::VLD3q16_UPD:
2734 case ARM::VLD3q32_UPD:
2738 case ARM::VLD4q8_UPD:
2739 case ARM::VLD4q16_UPD:
2740 case ARM::VLD4q32_UPD:
2753 case ARM::VLD3d8_UPD:
2754 case ARM::VLD3d16_UPD:
2755 case ARM::VLD3d32_UPD:
2759 case ARM::VLD4d8_UPD:
2760 case ARM::VLD4d16_UPD:
2761 case ARM::VLD4d32_UPD:
2768 case ARM::VLD3q8_UPD:
2769 case ARM::VLD3q16_UPD:
2770 case ARM::VLD3q32_UPD:
2774 case ARM::VLD4q8_UPD:
2775 case ARM::VLD4q16_UPD:
2776 case ARM::VLD4q32_UPD:
2789 case ARM::VLD4d8_UPD:
2790 case ARM::VLD4d16_UPD:
2791 case ARM::VLD4d32_UPD:
2798 case ARM::VLD4q8_UPD:
2799 case ARM::VLD4q16_UPD:
2800 case ARM::VLD4q32_UPD:
2810 case ARM::VLD1d8wb_fixed:
2811 case ARM::VLD1d16wb_fixed:
2812 case ARM::VLD1d32wb_fixed:
2813 case ARM::VLD1d64wb_fixed:
2814 case ARM::VLD1d8wb_register:
2815 case ARM::VLD1d16wb_register:
2816 case ARM::VLD1d32wb_register:
2817 case ARM::VLD1d64wb_register:
2818 case ARM::VLD1q8wb_fixed:
2819 case ARM::VLD1q16wb_fixed:
2820 case ARM::VLD1q32wb_fixed:
2821 case ARM::VLD1q64wb_fixed:
2822 case ARM::VLD1q8wb_register:
2823 case ARM::VLD1q16wb_register:
2824 case ARM::VLD1q32wb_register:
2825 case ARM::VLD1q64wb_register:
2826 case ARM::VLD1d8Twb_fixed:
2827 case ARM::VLD1d8Twb_register:
2828 case ARM::VLD1d16Twb_fixed:
2829 case ARM::VLD1d16Twb_register:
2830 case ARM::VLD1d32Twb_fixed:
2831 case ARM::VLD1d32Twb_register:
2832 case ARM::VLD1d64Twb_fixed:
2833 case ARM::VLD1d64Twb_register:
2834 case ARM::VLD1d8Qwb_fixed:
2835 case ARM::VLD1d8Qwb_register:
2836 case ARM::VLD1d16Qwb_fixed:
2837 case ARM::VLD1d16Qwb_register:
2838 case ARM::VLD1d32Qwb_fixed:
2839 case ARM::VLD1d32Qwb_register:
2840 case ARM::VLD1d64Qwb_fixed:
2841 case ARM::VLD1d64Qwb_register:
2842 case ARM::VLD2d8wb_fixed:
2843 case ARM::VLD2d16wb_fixed:
2844 case ARM::VLD2d32wb_fixed:
2845 case ARM::VLD2q8wb_fixed:
2846 case ARM::VLD2q16wb_fixed:
2847 case ARM::VLD2q32wb_fixed:
2848 case ARM::VLD2d8wb_register:
2849 case ARM::VLD2d16wb_register:
2850 case ARM::VLD2d32wb_register:
2851 case ARM::VLD2q8wb_register:
2852 case ARM::VLD2q16wb_register:
2853 case ARM::VLD2q32wb_register:
2854 case ARM::VLD2b8wb_fixed:
2855 case ARM::VLD2b16wb_fixed:
2856 case ARM::VLD2b32wb_fixed:
2857 case ARM::VLD2b8wb_register:
2858 case ARM::VLD2b16wb_register:
2859 case ARM::VLD2b32wb_register:
2862 case ARM::VLD3d8_UPD:
2863 case ARM::VLD3d16_UPD:
2864 case ARM::VLD3d32_UPD:
2865 case ARM::VLD3q8_UPD:
2866 case ARM::VLD3q16_UPD:
2867 case ARM::VLD3q32_UPD:
2868 case ARM::VLD4d8_UPD:
2869 case ARM::VLD4d16_UPD:
2870 case ARM::VLD4d32_UPD:
2871 case ARM::VLD4q8_UPD:
2872 case ARM::VLD4q16_UPD:
2873 case ARM::VLD4q32_UPD:
2900 case ARM::VLD1d8wb_fixed:
2901 case ARM::VLD1d16wb_fixed:
2902 case ARM::VLD1d32wb_fixed:
2903 case ARM::VLD1d64wb_fixed:
2904 case ARM::VLD1d8Twb_fixed:
2905 case ARM::VLD1d16Twb_fixed:
2906 case ARM::VLD1d32Twb_fixed:
2907 case ARM::VLD1d64Twb_fixed:
2908 case ARM::VLD1d8Qwb_fixed:
2909 case ARM::VLD1d16Qwb_fixed:
2910 case ARM::VLD1d32Qwb_fixed:
2911 case ARM::VLD1d64Qwb_fixed:
2912 case ARM::VLD1d8wb_register:
2913 case ARM::VLD1d16wb_register:
2914 case ARM::VLD1d32wb_register:
2915 case ARM::VLD1d64wb_register:
2916 case ARM::VLD1q8wb_fixed:
2917 case ARM::VLD1q16wb_fixed:
2918 case ARM::VLD1q32wb_fixed:
2919 case ARM::VLD1q64wb_fixed:
2920 case ARM::VLD1q8wb_register:
2921 case ARM::VLD1q16wb_register:
2922 case ARM::VLD1q32wb_register:
2923 case ARM::VLD1q64wb_register:
2927 if (Rm != 0xD && Rm != 0xF &&
2931 case ARM::VLD2d8wb_fixed:
2932 case ARM::VLD2d16wb_fixed:
2933 case ARM::VLD2d32wb_fixed:
2934 case ARM::VLD2b8wb_fixed:
2935 case ARM::VLD2b16wb_fixed:
2936 case ARM::VLD2b32wb_fixed:
2937 case ARM::VLD2q8wb_fixed:
2938 case ARM::VLD2q16wb_fixed:
2939 case ARM::VLD2q32wb_fixed:
2947 uint64_t
Address,
const void *Decoder) {
2948 unsigned type = fieldFromInstruction(Insn, 8, 4);
2949 unsigned align = fieldFromInstruction(Insn, 4, 2);
2954 unsigned load = fieldFromInstruction(Insn, 21, 1);
2960 uint64_t
Address,
const void *Decoder) {
2961 unsigned size = fieldFromInstruction(Insn, 6, 2);
2964 unsigned type = fieldFromInstruction(Insn, 8, 4);
2965 unsigned align = fieldFromInstruction(Insn, 4, 2);
2969 unsigned load = fieldFromInstruction(Insn, 21, 1);
2975 uint64_t
Address,
const void *Decoder) {
2976 unsigned size = fieldFromInstruction(Insn, 6, 2);
2979 unsigned align = fieldFromInstruction(Insn, 4, 2);
2982 unsigned load = fieldFromInstruction(Insn, 21, 1);
2988 uint64_t
Address,
const void *Decoder) {
2989 unsigned size = fieldFromInstruction(Insn, 6, 2);
2992 unsigned load = fieldFromInstruction(Insn, 21, 1);
2998 uint64_t
Address,
const void *Decoder) {
3001 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3002 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3003 unsigned wb = fieldFromInstruction(Insn, 16, 4);
3004 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3005 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3006 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3010 case ARM::VST1d8wb_fixed:
3011 case ARM::VST1d16wb_fixed:
3012 case ARM::VST1d32wb_fixed:
3013 case ARM::VST1d64wb_fixed:
3014 case ARM::VST1d8wb_register:
3015 case ARM::VST1d16wb_register:
3016 case ARM::VST1d32wb_register:
3017 case ARM::VST1d64wb_register:
3018 case ARM::VST1q8wb_fixed:
3019 case ARM::VST1q16wb_fixed:
3020 case ARM::VST1q32wb_fixed:
3021 case ARM::VST1q64wb_fixed:
3022 case ARM::VST1q8wb_register:
3023 case ARM::VST1q16wb_register:
3024 case ARM::VST1q32wb_register:
3025 case ARM::VST1q64wb_register:
3026 case ARM::VST1d8Twb_fixed:
3027 case ARM::VST1d16Twb_fixed:
3028 case ARM::VST1d32Twb_fixed:
3029 case ARM::VST1d64Twb_fixed:
3030 case ARM::VST1d8Twb_register:
3031 case ARM::VST1d16Twb_register:
3032 case ARM::VST1d32Twb_register:
3033 case ARM::VST1d64Twb_register:
3034 case ARM::VST1d8Qwb_fixed:
3035 case ARM::VST1d16Qwb_fixed:
3036 case ARM::VST1d32Qwb_fixed:
3037 case ARM::VST1d64Qwb_fixed:
3038 case ARM::VST1d8Qwb_register:
3039 case ARM::VST1d16Qwb_register:
3040 case ARM::VST1d32Qwb_register:
3041 case ARM::VST1d64Qwb_register:
3042 case ARM::VST2d8wb_fixed:
3043 case ARM::VST2d16wb_fixed:
3044 case ARM::VST2d32wb_fixed:
3045 case ARM::VST2d8wb_register:
3046 case ARM::VST2d16wb_register:
3047 case ARM::VST2d32wb_register:
3048 case ARM::VST2q8wb_fixed:
3049 case ARM::VST2q16wb_fixed:
3050 case ARM::VST2q32wb_fixed:
3051 case ARM::VST2q8wb_register:
3052 case ARM::VST2q16wb_register:
3053 case ARM::VST2q32wb_register:
3054 case ARM::VST2b8wb_fixed:
3055 case ARM::VST2b16wb_fixed:
3056 case ARM::VST2b32wb_fixed:
3057 case ARM::VST2b8wb_register:
3058 case ARM::VST2b16wb_register:
3059 case ARM::VST2b32wb_register:
3064 case ARM::VST3d8_UPD:
3065 case ARM::VST3d16_UPD:
3066 case ARM::VST3d32_UPD:
3067 case ARM::VST3q8_UPD:
3068 case ARM::VST3q16_UPD:
3069 case ARM::VST3q32_UPD:
3070 case ARM::VST4d8_UPD:
3071 case ARM::VST4d16_UPD:
3072 case ARM::VST4d32_UPD:
3073 case ARM::VST4q8_UPD:
3074 case ARM::VST4q16_UPD:
3075 case ARM::VST4q32_UPD:
3092 else if (Rm != 0xF) {
3097 case ARM::VST1d8wb_fixed:
3098 case ARM::VST1d16wb_fixed:
3099 case ARM::VST1d32wb_fixed:
3100 case ARM::VST1d64wb_fixed:
3101 case ARM::VST1q8wb_fixed:
3102 case ARM::VST1q16wb_fixed:
3103 case ARM::VST1q32wb_fixed:
3104 case ARM::VST1q64wb_fixed:
3105 case ARM::VST1d8Twb_fixed:
3106 case ARM::VST1d16Twb_fixed:
3107 case ARM::VST1d32Twb_fixed:
3108 case ARM::VST1d64Twb_fixed:
3109 case ARM::VST1d8Qwb_fixed:
3110 case ARM::VST1d16Qwb_fixed:
3111 case ARM::VST1d32Qwb_fixed:
3112 case ARM::VST1d64Qwb_fixed:
3113 case ARM::VST2d8wb_fixed:
3114 case ARM::VST2d16wb_fixed:
3115 case ARM::VST2d32wb_fixed:
3116 case ARM::VST2q8wb_fixed:
3117 case ARM::VST2q16wb_fixed:
3118 case ARM::VST2q32wb_fixed:
3119 case ARM::VST2b8wb_fixed:
3120 case ARM::VST2b16wb_fixed:
3121 case ARM::VST2b32wb_fixed:
3131 case ARM::VST1q16wb_fixed:
3132 case ARM::VST1q16wb_register:
3133 case ARM::VST1q32wb_fixed:
3134 case ARM::VST1q32wb_register:
3135 case ARM::VST1q64wb_fixed:
3136 case ARM::VST1q64wb_register:
3137 case ARM::VST1q8wb_fixed:
3138 case ARM::VST1q8wb_register:
3142 case ARM::VST2d16wb_fixed:
3143 case ARM::VST2d16wb_register:
3144 case ARM::VST2d32wb_fixed:
3145 case ARM::VST2d32wb_register:
3146 case ARM::VST2d8wb_fixed:
3147 case ARM::VST2d8wb_register:
3154 case ARM::VST2b16wb_fixed:
3155 case ARM::VST2b16wb_register:
3156 case ARM::VST2b32wb_fixed:
3157 case ARM::VST2b32wb_register:
3158 case ARM::VST2b8wb_fixed:
3159 case ARM::VST2b8wb_register:
3173 case ARM::VST3d8_UPD:
3174 case ARM::VST3d16_UPD:
3175 case ARM::VST3d32_UPD:
3179 case ARM::VST4d8_UPD:
3180 case ARM::VST4d16_UPD:
3181 case ARM::VST4d32_UPD:
3188 case ARM::VST3q8_UPD:
3189 case ARM::VST3q16_UPD:
3190 case ARM::VST3q32_UPD:
3194 case ARM::VST4q8_UPD:
3195 case ARM::VST4q16_UPD:
3196 case ARM::VST4q32_UPD:
3209 case ARM::VST3d8_UPD:
3210 case ARM::VST3d16_UPD:
3211 case ARM::VST3d32_UPD:
3215 case ARM::VST4d8_UPD:
3216 case ARM::VST4d16_UPD:
3217 case ARM::VST4d32_UPD:
3224 case ARM::VST3q8_UPD:
3225 case ARM::VST3q16_UPD:
3226 case ARM::VST3q32_UPD:
3230 case ARM::VST4q8_UPD:
3231 case ARM::VST4q16_UPD:
3232 case ARM::VST4q32_UPD:
3245 case ARM::VST4d8_UPD:
3246 case ARM::VST4d16_UPD:
3247 case ARM::VST4d32_UPD:
3254 case ARM::VST4q8_UPD:
3255 case ARM::VST4q16_UPD:
3256 case ARM::VST4q32_UPD:
3268 uint64_t
Address,
const void *Decoder) {
3271 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3272 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3273 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3274 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3275 unsigned align = fieldFromInstruction(Insn, 4, 1);
3276 unsigned size = fieldFromInstruction(Insn, 6, 2);
3278 if (size == 0 && align == 1)
3280 align *= (1 <<
size);
3283 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
3284 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
3285 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
3286 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
3307 if (Rm != 0xD && Rm != 0xF &&
3315 uint64_t
Address,
const void *Decoder) {
3318 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3319 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3320 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3321 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3322 unsigned align = fieldFromInstruction(Insn, 4, 1);
3323 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3327 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
3328 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
3329 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
3330 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
3334 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
3335 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
3336 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
3337 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3354 if (Rm != 0xD && Rm != 0xF) {
3363 uint64_t
Address,
const void *Decoder) {
3366 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3367 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3368 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3369 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3370 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3389 else if (Rm != 0xF) {
3398 uint64_t
Address,
const void *Decoder) {
3401 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3402 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3403 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3404 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3405 unsigned size = fieldFromInstruction(Insn, 6, 2);
3406 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3407 unsigned align = fieldFromInstruction(Insn, 4, 1);
3441 else if (Rm != 0xF) {
3451 uint64_t
Address,
const void *Decoder) {
3454 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3455 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3456 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3457 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3458 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3459 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3460 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3461 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3474 case ARM::VORRiv4i16:
3475 case ARM::VORRiv2i32:
3476 case ARM::VBICiv4i16:
3477 case ARM::VBICiv2i32:
3481 case ARM::VORRiv8i16:
3482 case ARM::VORRiv4i32:
3483 case ARM::VBICiv8i16:
3484 case ARM::VBICiv4i32:
3497 uint64_t
Address,
const void *Decoder) {
3500 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3501 fieldFromInstruction(Insn, 13, 3));
3502 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3503 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3504 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3505 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3507 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3509 if (cmode == 0xF && Inst.
getOpcode() == ARM::MVE_VMVNimmi32)
3525 uint64_t
Address,
const void *Decoder) {
3528 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3529 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3534 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3535 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3538 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3539 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3542 if (!fieldFromInstruction(Insn, 12, 1))
3550 uint64_t
Address,
const void *Decoder) {
3553 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3554 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3555 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3556 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3557 unsigned size = fieldFromInstruction(Insn, 18, 2);
3569 uint64_t
Address,
const void *Decoder) {
3575 uint64_t
Address,
const void *Decoder) {
3581 uint64_t
Address,
const void *Decoder) {
3587 uint64_t
Address,
const void *Decoder) {
3593 uint64_t
Address,
const void *Decoder) {
3596 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3597 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3598 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3599 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3600 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3601 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3602 unsigned op = fieldFromInstruction(Insn, 6, 1);
3629 uint64_t
Address,
const void *Decoder) {
3632 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3633 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3653 uint64_t
Address,
const void *Decoder) {
3655 true, 2, Inst, Decoder))
3661 uint64_t
Address,
const void *Decoder) {
3663 true, 4, Inst, Decoder))
3669 uint64_t
Address,
const void *Decoder) {
3671 true, 2, Inst, Decoder))
3677 uint64_t
Address,
const void *Decoder) {
3680 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3681 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3692 uint64_t
Address,
const void *Decoder) {
3695 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3696 unsigned imm = fieldFromInstruction(Val, 3, 5);
3706 uint64_t
Address,
const void *Decoder) {
3707 unsigned imm = Val << 2;
3716 uint64_t
Address,
const void *Decoder) {
3724 uint64_t
Address,
const void *Decoder) {
3727 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3728 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3729 unsigned imm = fieldFromInstruction(Val, 0, 2);
3753 uint64_t
Address,
const void *Decoder) {
3756 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3757 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3760 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3762 bool hasMP = featureBits[ARM::FeatureMP];
3763 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3818 if (!hasV7Ops || !hasMP)
3826 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3827 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3828 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3836 uint64_t
Address,
const void* Decoder) {
3839 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3840 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3841 unsigned U = fieldFromInstruction(Insn, 9, 1);
3842 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3845 unsigned add = fieldFromInstruction(Insn, 9, 1);
3848 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3850 bool hasMP = featureBits[ARM::FeatureMP];
3851 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3861 case ARM::t2LDRSBi8:
3867 case ARM::t2LDRSHi8:
3884 case ARM::t2LDRSHi8:
3890 case ARM::t2LDRSBi8:
3906 if (!hasV7Ops || !hasMP)
3920 uint64_t
Address,
const void* Decoder) {
3923 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3924 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3925 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3929 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3931 bool hasMP = featureBits[ARM::FeatureMP];
3932 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3939 case ARM::t2LDRHi12:
3942 case ARM::t2LDRSHi12:
3945 case ARM::t2LDRBi12:
3948 case ARM::t2LDRSBi12:
3965 case ARM::t2LDRSHi12:
3967 case ARM::t2LDRHi12:
3970 case ARM::t2LDRSBi12:
3985 case ARM::t2PLDWi12:
3986 if (!hasV7Ops || !hasMP)
4000 uint64_t
Address,
const void* Decoder) {
4003 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4004 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4005 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4039 uint64_t
Address,
const void* Decoder) {
4042 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4043 unsigned U = fieldFromInstruction(Insn, 23, 1);
4044 int imm = fieldFromInstruction(Insn, 0, 12);
4047 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4049 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4053 case ARM::t2LDRBpci:
4054 case ARM::t2LDRHpci:
4057 case ARM::t2LDRSBpci:
4060 case ARM::t2LDRSHpci:
4092 uint64_t
Address,
const void *Decoder) {
4096 int imm = Val & 0xFF;
4098 if (!(Val & 0x100)) imm *= -1;
4106 const void *Decoder) {
4110 int imm = Val & 0x7F;
4121 uint64_t
Address,
const void *Decoder) {
4124 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4125 unsigned imm = fieldFromInstruction(Val, 0, 9);
4137 const void *Decoder) {
4140 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4141 unsigned imm = fieldFromInstruction(Val, 0, 8);
4152 uint64_t
Address,
const void *Decoder) {
4155 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4156 unsigned imm = fieldFromInstruction(Val, 0, 8);
4167 uint64_t
Address,
const void *Decoder) {
4168 int imm = Val & 0xFF;
4171 else if (!(Val & 0x100))
4180 uint64_t
Address,
const void *Decoder) {
4181 int imm = Val & 0x7F;
4184 else if (!(Val & 0x80))
4186 if (imm != INT32_MIN)
4187 imm *= (1U << shift);
4194 uint64_t
Address,
const void *Decoder) {
4197 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4198 unsigned imm = fieldFromInstruction(Val, 0, 9);
4242 const void *Decoder) {
4245 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4246 unsigned imm = fieldFromInstruction(Val, 0, 8);
4250 if (!
Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4256 template<
int shift,
int WriteBack>
4259 const void *Decoder) {
4262 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4263 unsigned imm = fieldFromInstruction(Val, 0, 8);
4269 if (!
Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4276 uint64_t
Address,
const void *Decoder) {
4279 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4280 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4281 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4282 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4284 unsigned load = fieldFromInstruction(Insn, 20, 1);
4288 case ARM::t2LDR_PRE:
4289 case ARM::t2LDR_POST:
4292 case ARM::t2LDRB_PRE:
4293 case ARM::t2LDRB_POST:
4296 case ARM::t2LDRH_PRE:
4297 case ARM::t2LDRH_POST:
4300 case ARM::t2LDRSB_PRE:
4301 case ARM::t2LDRSB_POST:
4307 case ARM::t2LDRSH_PRE:
4308 case ARM::t2LDRSH_POST:
4337 uint64_t
Address,
const void *Decoder) {
4340 unsigned Rn = fieldFromInstruction(Val, 13, 4);
4341 unsigned imm = fieldFromInstruction(Val, 0, 12);
4346 case ARM::t2STRBi12:
4347 case ARM::t2STRHi12:
4363 uint64_t
Address,
const void *Decoder) {
4364 unsigned imm = fieldFromInstruction(Insn, 0, 7);
4374 uint64_t
Address,
const void *Decoder) {
4378 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4379 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4386 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
4387 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4399 uint64_t
Address,
const void *Decoder) {
4400 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4401 unsigned flags = fieldFromInstruction(Insn, 0, 3);
4410 uint64_t
Address,
const void *Decoder) {
4412 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4413 unsigned add = fieldFromInstruction(Insn, 4, 1);
4423 uint64_t
Address,
const void *Decoder) {
4425 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4426 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4438 uint64_t
Address,
const void *Decoder) {
4440 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4441 int imm = fieldFromInstruction(Insn, 0, 7);
4446 if(!fieldFromInstruction(Insn, 7, 1)) {
4452 if (imm != INT32_MIN)
4453 imm *= (1U << shift);
4460 uint64_t
Address,
const void *Decoder) {
4468 unsigned S = (Val >> 23) & 1;
4469 unsigned J1 = (Val >> 22) & 1;
4470 unsigned J2 = (Val >> 21) & 1;
4471 unsigned I1 = !(J1 ^ S);
4472 unsigned I2 = !(J2 ^ S);
4473 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4474 int imm32 = SignExtend32<25>(tmp << 1);
4477 (Address & ~2u) + imm32 + 4,
4478 true, 4, Inst, Decoder))
4484 uint64_t
Address,
const void *Decoder) {
4485 if (Val == 0xA || Val == 0xB)
4489 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4500 uint64_t
Address,
const void *Decoder) {
4503 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4504 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4516 uint64_t
Address,
const void *Decoder) {
4519 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4520 if (pred == 0xE || pred == 0xF) {
4521 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4536 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4540 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4541 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4542 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4543 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4544 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4558 uint64_t
Address,
const void *Decoder) {
4559 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4561 unsigned byte = fieldFromInstruction(Val, 8, 2);
4562 unsigned imm = fieldFromInstruction(Val, 0, 8);
4579 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4580 unsigned rot = fieldFromInstruction(Val, 7, 5);
4581 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4590 uint64_t
Address,
const void *Decoder) {
4592 true, 2, Inst, Decoder))
4599 const void *Decoder) {
4607 unsigned S = (Val >> 23) & 1;
4608 unsigned J1 = (Val >> 22) & 1;
4609 unsigned J2 = (Val >> 21) & 1;
4610 unsigned I1 = !(J1 ^ S);
4611 unsigned I2 = !(J2 ^ S);
4612 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4613 int imm32 = SignExtend32<25>(tmp << 1);
4616 true, 4, Inst, Decoder))
4622 uint64_t
Address,
const void *Decoder) {
4631 uint64_t
Address,
const void *Decoder) {
4640 uint64_t
Address,
const void *Decoder) {
4643 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4645 if (FeatureBits[ARM::FeatureMClass]) {
4646 unsigned ValLow = Val & 0xff;
4665 if (!(FeatureBits[ARM::HasV7Ops]))
4673 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4683 if (!(FeatureBits[ARM::Feature8MSecExt]))
4693 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4694 if (!(FeatureBits[ARM::HasV7Ops])) {
4707 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4708 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4722 uint64_t
Address,
const void *Decoder) {
4723 unsigned R = fieldFromInstruction(Val, 5, 1);
4724 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4729 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4737 uint64_t
Address,
const void *Decoder) {
4740 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4741 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4742 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4759 const void *Decoder) {
4762 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4763 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4764 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4765 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4770 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4784 uint64_t
Address,
const void *Decoder) {
4787 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4788 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4789 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4790 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4791 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4792 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4809 uint64_t
Address,
const void *Decoder) {
4812 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4813 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4814 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4815 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4816 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4817 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4818 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4836 uint64_t
Address,
const void *Decoder) {
4839 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4840 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4841 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4842 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4843 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4844 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4861 uint64_t
Address,
const void *Decoder) {
4864 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4865 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4866 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4867 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4868 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4869 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4886 uint64_t
Address,
const void *Decoder) {
4889 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4890 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4891 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4892 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4893 unsigned size = fieldFromInstruction(Insn, 10, 2);
4901 if (fieldFromInstruction(Insn, 4, 1))
4903 index = fieldFromInstruction(Insn, 5, 3);
4906 if (fieldFromInstruction(Insn, 5, 1))
4908 index = fieldFromInstruction(Insn, 6, 2);
4909 if (fieldFromInstruction(Insn, 4, 1))
4913 if (fieldFromInstruction(Insn, 6, 1))
4915 index = fieldFromInstruction(Insn, 7, 1);
4917 switch (fieldFromInstruction(Insn, 4, 2)) {
4953 uint64_t
Address,
const void *Decoder) {
4956 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4957 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4958 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4959 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4960 unsigned size = fieldFromInstruction(Insn, 10, 2);
4968 if (fieldFromInstruction(Insn, 4, 1))
4970 index = fieldFromInstruction(Insn, 5, 3);
4973 if (fieldFromInstruction(Insn, 5, 1))
4975 index = fieldFromInstruction(Insn, 6, 2);
4976 if (fieldFromInstruction(Insn, 4, 1))
4980 if (fieldFromInstruction(Insn, 6, 1))
4982 index = fieldFromInstruction(Insn, 7, 1);
4984 switch (fieldFromInstruction(Insn, 4, 2)) {
5018 uint64_t
Address,
const void *Decoder) {
5021 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5022 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5023 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5024 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5025 unsigned size = fieldFromInstruction(Insn, 10, 2);
5034 index = fieldFromInstruction(Insn, 5, 3);
5035 if (fieldFromInstruction(Insn, 4, 1))
5039 index = fieldFromInstruction(Insn, 6, 2);
5040 if (fieldFromInstruction(Insn, 4, 1))
5042 if (fieldFromInstruction(Insn, 5, 1))
5046 if (fieldFromInstruction(Insn, 5, 1))
5048 index = fieldFromInstruction(Insn, 7, 1);
5049 if (fieldFromInstruction(Insn, 4, 1) != 0)
5051 if (fieldFromInstruction(Insn, 6, 1))
5085 uint64_t
Address,
const void *Decoder) {
5088 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5089 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5090 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5091 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5092 unsigned size = fieldFromInstruction(Insn, 10, 2);
5101 index = fieldFromInstruction(Insn, 5, 3);
5102 if (fieldFromInstruction(Insn, 4, 1))
5106 index = fieldFromInstruction(Insn, 6, 2);
5107 if (fieldFromInstruction(Insn, 4, 1))
5109 if (fieldFromInstruction(Insn, 5, 1))
5113 if (fieldFromInstruction(Insn, 5, 1))
5115 index = fieldFromInstruction(Insn, 7, 1);
5116 if (fieldFromInstruction(Insn, 4, 1) != 0)
5118 if (fieldFromInstruction(Insn, 6, 1))