34 #define DEBUG_TYPE "arm-disassembler" 53 void advanceITState() {
58 bool instrInITBlock() {
59 return !ITStates.empty();
63 bool instrLastInITBlock() {
64 return ITStates.size() == 1;
71 void setITState(
char Firstcond,
char Mask) {
73 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
74 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
75 assert(NumTZ <= 3 &&
"Invalid IT mask!");
77 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78 unsigned Else = (Mask >> Pos) & 1;
79 ITStates.push_back(CCBits ^ Else);
81 ITStates.push_back(CCBits);
85 std::vector<unsigned char> ITStates;
91 unsigned getVPTPred() {
93 if (instrInVPTBlock())
94 Pred = VPTStates.back();
98 void advanceVPTState() {
102 bool instrInVPTBlock() {
103 return !VPTStates.empty();
106 bool instrLastInVPTBlock() {
107 return VPTStates.size() == 1;
110 void setVPTState(
char Mask) {
112 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
113 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
115 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116 bool T = ((Mask >> Pos) & 1) == 0;
136 ~ARMDisassembler()
override =
default;
154 mutable ITStatus ITBlock;
155 mutable VPTStatus VPTBlock;
181 uint64_t
Address,
const void *Decoder);
183 uint64_t
Address,
const void *Decoder);
185 uint64_t
Address,
const void *Decoder);
187 uint64_t
Address,
const void *Decoder);
189 unsigned RegNo, uint64_t
Address,
190 const void *Decoder);
192 unsigned RegNo, uint64_t
Address,
193 const void *Decoder);
195 unsigned RegNo, uint64_t
Address,
196 const void *Decoder);
198 MCInst &Inst,
unsigned RegNo, uint64_t
Address,
const void *Decoder);
200 uint64_t
Address,
const void *Decoder);
202 uint64_t
Address,
const void *Decoder);
204 uint64_t
Address,
const void *Decoder);
206 uint64_t
Address,
const void *Decoder);
208 uint64_t
Address,
const void *Decoder);
210 uint64_t
Address,
const void *Decoder);
212 uint64_t
Address,
const void *Decoder);
214 uint64_t
Address,
const void *Decoder);
216 uint64_t
Address,
const void *Decoder);
220 const void *Decoder);
222 uint64_t
Address,
const void *Decoder);
224 uint64_t
Address,
const void *Decoder);
226 uint64_t
Address,
const void *Decoder);
228 uint64_t
Address,
const void *Decoder);
230 uint64_t
Address,
const void *Decoder);
232 unsigned RegNo, uint64_t
Address,
233 const void *Decoder);
236 uint64_t
Address,
const void *Decoder);
238 uint64_t
Address,
const void *Decoder);
240 uint64_t
Address,
const void *Decoder);
242 uint64_t
Address,
const void *Decoder);
244 uint64_t
Address,
const void *Decoder);
247 uint64_t
Address,
const void *Decoder);
249 uint64_t
Address,
const void *Decoder);
253 const void *Decoder);
255 uint64_t
Address,
const void *Decoder);
257 uint64_t
Address,
const void *Decoder);
259 uint64_t
Address,
const void *Decoder);
261 uint64_t
Address,
const void *Decoder);
266 const void *Decoder);
268 uint64_t
Address,
const void *Decoder);
270 uint64_t
Address,
const void *Decoder);
272 uint64_t
Address,
const void *Decoder);
274 uint64_t
Address,
const void *Decoder);
276 uint64_t
Address,
const void *Decoder);
278 uint64_t
Address,
const void *Decoder);
280 uint64_t
Address,
const void *Decoder);
282 uint64_t
Address,
const void *Decoder);
284 uint64_t
Address,
const void *Decoder);
286 uint64_t
Address,
const void *Decoder);
288 uint64_t
Address,
const void *Decoder);
290 uint64_t
Address,
const void *Decoder);
292 uint64_t
Address,
const void *Decoder);
294 uint64_t
Address,
const void *Decoder);
296 uint64_t
Address,
const void *Decoder);
298 uint64_t
Address,
const void *Decoder);
300 uint64_t
Address,
const void *Decoder);
302 uint64_t
Address,
const void *Decoder);
304 uint64_t
Address,
const void *Decoder);
306 uint64_t
Address,
const void *Decoder);
308 uint64_t
Address,
const void *Decoder);
310 uint64_t
Address,
const void *Decoder);
312 uint64_t
Address,
const void *Decoder);
314 uint64_t
Address,
const void *Decoder);
316 uint64_t
Address,
const void *Decoder);
318 uint64_t
Address,
const void *Decoder);
320 uint64_t
Address,
const void *Decoder);
322 uint64_t
Address,
const void *Decoder);
324 uint64_t
Address,
const void *Decoder);
326 uint64_t
Address,
const void *Decoder);
328 uint64_t
Address,
const void *Decoder);
330 uint64_t
Address,
const void *Decoder);
332 uint64_t
Address,
const void *Decoder);
334 uint64_t
Address,
const void *Decoder);
336 uint64_t
Address,
const void *Decoder);
338 uint64_t
Address,
const void *Decoder);
341 uint64_t
Address,
const void *Decoder);
343 uint64_t
Address,
const void *Decoder);
345 uint64_t
Address,
const void *Decoder);
347 uint64_t
Address,
const void *Decoder);
349 uint64_t
Address,
const void *Decoder);
351 uint64_t
Address,
const void *Decoder);
353 uint64_t
Address,
const void *Decoder);
355 uint64_t
Address,
const void *Decoder);
357 uint64_t
Address,
const void *Decoder);
359 uint64_t
Address,
const void *Decoder);
361 uint64_t
Address,
const void *Decoder);
363 uint64_t
Address,
const void *Decoder);
365 uint64_t
Address,
const void *Decoder);
367 uint64_t
Address,
const void *Decoder);
369 uint64_t
Address,
const void *Decoder);
371 uint64_t
Address,
const void *Decoder);
373 uint64_t
Address,
const void *Decoder);
375 uint64_t
Address,
const void *Decoder);
377 uint64_t
Address,
const void *Decoder);
379 uint64_t
Address,
const void *Decoder);
381 uint64_t
Address,
const void *Decoder);
383 uint64_t
Address,
const void *Decoder);
385 uint64_t
Address,
const void *Decoder);
387 uint64_t
Address,
const void *Decoder);
389 uint64_t
Address,
const void *Decoder);
391 uint64_t
Address,
const void *Decoder);
395 const void *Decoder);
398 uint64_t
Address,
const void *Decoder);
400 uint64_t
Address,
const void *Decoder);
402 uint64_t
Address,
const void *Decoder);
404 uint64_t
Address,
const void *Decoder);
406 uint64_t
Address,
const void *Decoder);
408 uint64_t
Address,
const void *Decoder);
410 uint64_t
Address,
const void *Decoder);
412 uint64_t
Address,
const void *Decoder);
414 uint64_t
Address,
const void *Decoder);
416 uint64_t
Address,
const void *Decoder);
418 uint64_t
Address,
const void* Decoder);
420 uint64_t
Address,
const void* Decoder);
422 uint64_t
Address,
const void* Decoder);
424 uint64_t
Address,
const void* Decoder);
426 uint64_t
Address,
const void *Decoder);
428 uint64_t
Address,
const void *Decoder);
430 uint64_t
Address,
const void *Decoder);
433 const void *Decoder);
435 uint64_t
Address,
const void *Decoder);
437 uint64_t
Address,
const void *Decoder);
440 uint64_t
Address,
const void *Decoder);
442 uint64_t
Address,
const void *Decoder);
445 uint64_t
Address,
const void *Decoder);
446 template<
int shift,
int WriteBack>
448 uint64_t
Address,
const void *Decoder);
450 uint64_t
Address,
const void *Decoder);
452 uint64_t
Address,
const void *Decoder);
454 uint64_t
Address,
const void *Decoder);
456 uint64_t
Address,
const void *Decoder);
458 uint64_t
Address,
const void *Decoder);
460 uint64_t
Address,
const void *Decoder);
462 uint64_t
Address,
const void *Decoder);
464 uint64_t
Address,
const void *Decoder);
466 uint64_t
Address,
const void *Decoder);
468 uint64_t
Address,
const void *Decoder);
470 uint64_t
Address,
const void *Decoder);
472 uint64_t
Address,
const void *Decoder);
474 uint64_t
Address,
const void *Decoder);
476 uint64_t
Address,
const void *Decoder);
478 uint64_t
Address,
const void *Decoder);
480 uint64_t
Address,
const void *Decoder);
482 uint64_t
Address,
const void *Decoder);
485 uint64_t
Address,
const void *Decoder);
487 uint64_t
Address,
const void *Decoder);
489 uint64_t
Address,
const void *Decoder);
491 template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
493 uint64_t
Address,
const void *Decoder);
496 const void *Decoder);
499 const void *Decoder);
501 const void *Decoder);
504 const void *Decoder);
506 const void *Decoder);
508 uint64_t
Address,
const void *Decoder);
510 uint64_t
Address,
const void *Decoder);
513 const void *Decoder);
516 const void *Decoder);
519 const void *Decoder);
523 const void *Decoder);
524 template<
bool Writeback>
527 const void *Decoder);
530 uint64_t
Address,
const void *Decoder);
533 uint64_t
Address,
const void *Decoder);
536 uint64_t
Address,
const void *Decoder);
537 template<
unsigned MinLog,
unsigned MaxLog>
540 const void *Decoder);
544 const void *Decoder);
545 template<
unsigned start>
548 const void *Decoder);
551 const void *Decoder);
554 const void *Decoder);
556 uint64_t
Address,
const void *Decoder);
558 uint64_t
Address,
const void *Decoder);
559 template<
bool scalar, OperandDecoder predicate_decoder>
561 uint64_t
Address,
const void *Decoder);
563 uint64_t
Address,
const void *Decoder);
566 const void *Decoder);
567 #include "ARMGenDisassemblerTables.inc" 572 return new ARMDisassembler(STI, Ctx);
604 default:
return Result;
612 if (STI.getFeatureBits()[ARM::ModeThumb])
613 return getThumbInstruction(MI,
Size, Bytes,
Address, OS, CS);
614 return getARMInstruction(MI,
Size, Bytes,
Address, OS, CS);
624 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
625 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 629 if (Bytes.
size() < 4) {
636 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
651 const DecodeTable Tables[] = {
652 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
653 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
654 {DecoderTableNEONDup32,
true}, {DecoderTablev8NEON32,
false},
655 {DecoderTablev8Crypto32,
false},
658 for (
auto Table : Tables) {
701 MCInst &MI,
const void *Decoder) {
718 const void *Decoder) {
731 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
732 if (I == MI.
end())
break;
733 if (OpInfo[i].isOptionalDef() && OpInfo[i].
RegClass == ARM::CCRRegClassID) {
734 if (i > 0 && OpInfo[i-1].isPredicate())
continue;
746 for (
unsigned i = 0; i < NumOps; ++i) {
758 ARMDisassembler::AddThumbPredicate(
MCInst &MI)
const {
761 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
782 if (ITBlock.instrInITBlock())
788 if (MI.
getOperand(0).
getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
797 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
814 if (ITBlock.instrInITBlock()) {
815 CC = ITBlock.getITCC();
816 ITBlock.advanceITState();
817 }
else if (VPTBlock.instrInVPTBlock()) {
818 VCC = VPTBlock.getVPTPred();
819 VPTBlock.advanceVPTState();
826 for (
unsigned i = 0; i < NumOps; ++i, ++CCI) {
827 if (OpInfo[i].isPredicate() || CCI == MI.
end())
break;
843 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
858 "Inactive register in vpred_r is not tied to an output!");
873 void ARMDisassembler::UpdateThumbVFPPredicate(
876 CC = ITBlock.getITCC();
879 if (ITBlock.instrInITBlock())
880 ITBlock.advanceITState();
881 else if (VPTBlock.instrInVPTBlock()) {
882 CC = VPTBlock.getVPTPred();
883 VPTBlock.advanceVPTState();
889 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
890 if (OpInfo[i].isPredicate() ) {
898 I->setReg(ARM::CPSR);
911 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
912 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
915 if (Bytes.
size() < 2) {
920 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
925 Check(Result, AddThumbPredicate(MI));
933 bool InITBlock = ITBlock.instrInITBlock();
934 Check(Result, AddThumbPredicate(MI));
946 if (MI.
getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
949 Check(Result, AddThumbPredicate(MI));
957 ITBlock.setITState(Firstcond, Mask);
961 CS <<
"unpredictable IT predicate sequence";
968 if (Bytes.
size() < 4) {
974 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
986 Check(Result, AddThumbPredicate(MI));
990 VPTBlock.setVPTState(Mask);
1000 bool InITBlock = ITBlock.instrInITBlock();
1001 Check(Result, AddThumbPredicate(MI));
1010 Check(Result, AddThumbPredicate(MI));
1014 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1019 UpdateThumbVFPPredicate(Result, MI);
1031 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1036 Check(Result, AddThumbPredicate(MI));
1041 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1043 NEONLdStInsn &= 0xF0FFFFFF;
1044 NEONLdStInsn |= 0x04000000;
1049 Check(Result, AddThumbPredicate(MI));
1054 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1056 NEONDataInsn &= 0xF0FFFFFF;
1057 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
1058 NEONDataInsn |= 0x12000000;
1063 Check(Result, AddThumbPredicate(MI));
1068 NEONCryptoInsn &= 0xF0FFFFFF;
1069 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
1070 NEONCryptoInsn |= 0x12000000;
1079 NEONv8Insn &= 0xF3FFFFFF;
1092 Check(Result, AddThumbPredicate(MI));
1112 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1114 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1115 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1119 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1121 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1122 ARM::R12, 0, ARM::LR, ARM::APSR
1126 uint64_t
Address,
const void *Decoder) {
1137 const void *Decoder) {
1151 uint64_t
Address,
const void *Decoder) {
1164 uint64_t
Address,
const void *Decoder) {
1179 uint64_t
Address,
const void *Decoder) {
1197 uint64_t
Address,
const void *Decoder) {
1206 uint64_t
Address,
const void *Decoder) {
1213 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1214 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1218 uint64_t
Address,
const void *Decoder) {
1224 if ((RegNo & 1) || RegNo == 0xe)
1233 uint64_t
Address,
const void *Decoder) {
1252 Register = ARM::R12;
1263 uint64_t
Address,
const void *Decoder) {
1267 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1269 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1277 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1278 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1279 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1280 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1281 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1282 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1283 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1284 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1288 uint64_t
Address,
const void *Decoder) {
1298 uint64_t
Address,
const void *Decoder) {
1303 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1304 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1305 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1306 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1307 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1308 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1309 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1310 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1314 uint64_t
Address,
const void *Decoder) {
1316 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1318 bool hasD32 = featureBits[ARM::FeatureD32];
1320 if (RegNo > 31 || (!hasD32 && RegNo > 15))
1329 uint64_t
Address,
const void *Decoder) {
1336 uint64_t
Address,
const void *Decoder) {
1344 uint64_t
Address,
const void *Decoder) {
1351 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1352 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1353 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1354 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1358 uint64_t
Address,
const void *Decoder) {
1359 if (RegNo > 31 || (RegNo & 1) != 0)
1369 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1370 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1371 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1372 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1373 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1378 uint64_t
Address,
const void *Decoder) {
1388 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1389 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1390 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1391 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1392 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1393 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1394 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1395 ARM::D28_D30, ARM::D29_D31
1401 const void *Decoder) {
1411 uint64_t
Address,
const void *Decoder) {
1415 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1428 uint64_t
Address,
const void *Decoder) {
1437 uint64_t
Address,
const void *Decoder) {
1440 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1441 unsigned type = fieldFromInstruction(Val, 5, 2);
1442 unsigned imm = fieldFromInstruction(Val, 7, 5);
1467 unsigned Op = Shift | (imm << 3);
1474 uint64_t
Address,
const void *Decoder) {
1477 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1478 unsigned type = fieldFromInstruction(Val, 5, 2);
1479 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1509 uint64_t
Address,
const void *Decoder) {
1512 bool NeedDisjointWriteback =
false;
1513 unsigned WritebackReg = 0;
1518 case ARM::LDMIA_UPD:
1519 case ARM::LDMDB_UPD:
1520 case ARM::LDMIB_UPD:
1521 case ARM::LDMDA_UPD:
1522 case ARM::t2LDMIA_UPD:
1523 case ARM::t2LDMDB_UPD:
1524 case ARM::t2STMIA_UPD:
1525 case ARM::t2STMDB_UPD:
1526 NeedDisjointWriteback =
true;
1536 for (
unsigned i = 0; i < 16; ++i) {
1537 if (Val & (1 << i)) {
1546 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1556 uint64_t
Address,
const void *Decoder) {
1559 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1560 unsigned regs = fieldFromInstruction(Val, 0, 8);
1563 if (regs == 0 || (Vd + regs) > 32) {
1564 regs = Vd + regs > 32 ? 32 - Vd : regs;
1571 for (
unsigned i = 0; i < (regs - 1); ++i) {
1580 uint64_t
Address,
const void *Decoder) {
1583 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1584 unsigned regs = fieldFromInstruction(Val, 1, 7);
1587 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1588 regs = Vd + regs > 32 ? 32 - Vd : regs;
1590 regs = std::min(16u, regs);
1596 for (
unsigned i = 0; i < (regs - 1); ++i) {
1605 uint64_t
Address,
const void *Decoder) {
1611 unsigned msb = fieldFromInstruction(Val, 5, 5);
1612 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1624 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1625 uint32_t lsb_mask = (1U << lsb) - 1;
1632 uint64_t
Address,
const void *Decoder) {
1635 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1636 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1637 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1638 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1639 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1640 unsigned U = fieldFromInstruction(Insn, 23, 1);
1642 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1645 case ARM::LDC_OFFSET:
1648 case ARM::LDC_OPTION:
1649 case ARM::LDCL_OFFSET:
1651 case ARM::LDCL_POST:
1652 case ARM::LDCL_OPTION:
1653 case ARM::STC_OFFSET:
1656 case ARM::STC_OPTION:
1657 case ARM::STCL_OFFSET:
1659 case ARM::STCL_POST:
1660 case ARM::STCL_OPTION:
1661 case ARM::t2LDC_OFFSET:
1662 case ARM::t2LDC_PRE:
1663 case ARM::t2LDC_POST:
1664 case ARM::t2LDC_OPTION:
1665 case ARM::t2LDCL_OFFSET:
1666 case ARM::t2LDCL_PRE:
1667 case ARM::t2LDCL_POST:
1668 case ARM::t2LDCL_OPTION:
1669 case ARM::t2STC_OFFSET:
1670 case ARM::t2STC_PRE:
1671 case ARM::t2STC_POST:
1672 case ARM::t2STC_OPTION:
1673 case ARM::t2STCL_OFFSET:
1674 case ARM::t2STCL_PRE:
1675 case ARM::t2STCL_POST:
1676 case ARM::t2STCL_OPTION:
1677 case ARM::t2LDC2_OFFSET:
1678 case ARM::t2LDC2L_OFFSET:
1679 case ARM::t2LDC2_PRE:
1680 case ARM::t2LDC2L_PRE:
1681 case ARM::t2STC2_OFFSET:
1682 case ARM::t2STC2L_OFFSET:
1683 case ARM::t2STC2_PRE:
1684 case ARM::t2STC2L_PRE:
1685 case ARM::LDC2_OFFSET:
1686 case ARM::LDC2L_OFFSET:
1688 case ARM::LDC2L_PRE:
1689 case ARM::STC2_OFFSET:
1690 case ARM::STC2L_OFFSET:
1692 case ARM::STC2L_PRE:
1693 case ARM::t2LDC2_OPTION:
1694 case ARM::t2STC2_OPTION:
1695 case ARM::t2LDC2_POST:
1696 case ARM::t2LDC2L_POST:
1697 case ARM::t2STC2_POST:
1698 case ARM::t2STC2L_POST:
1699 case ARM::LDC2_POST:
1700 case ARM::LDC2L_POST:
1701 case ARM::STC2_POST:
1702 case ARM::STC2L_POST:
1703 if (coproc == 0xA || coproc == 0xB ||
1704 (featureBits[ARM::HasV8_1MMainlineOps] &&
1705 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1706 coproc == 0xE || coproc == 0xF)))
1713 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1722 case ARM::t2LDC2_OFFSET:
1723 case ARM::t2LDC2L_OFFSET:
1724 case ARM::t2LDC2_PRE:
1725 case ARM::t2LDC2L_PRE:
1726 case ARM::t2STC2_OFFSET:
1727 case ARM::t2STC2L_OFFSET:
1728 case ARM::t2STC2_PRE:
1729 case ARM::t2STC2L_PRE:
1730 case ARM::LDC2_OFFSET:
1731 case ARM::LDC2L_OFFSET:
1733 case ARM::LDC2L_PRE:
1734 case ARM::STC2_OFFSET:
1735 case ARM::STC2L_OFFSET:
1737 case ARM::STC2L_PRE:
1738 case ARM::t2LDC_OFFSET:
1739 case ARM::t2LDCL_OFFSET:
1740 case ARM::t2LDC_PRE:
1741 case ARM::t2LDCL_PRE:
1742 case ARM::t2STC_OFFSET:
1743 case ARM::t2STCL_OFFSET:
1744 case ARM::t2STC_PRE:
1745 case ARM::t2STCL_PRE:
1746 case ARM::LDC_OFFSET:
1747 case ARM::LDCL_OFFSET:
1750 case ARM::STC_OFFSET:
1751 case ARM::STCL_OFFSET:
1757 case ARM::t2LDC2_POST:
1758 case ARM::t2LDC2L_POST:
1759 case ARM::t2STC2_POST:
1760 case ARM::t2STC2L_POST:
1761 case ARM::LDC2_POST:
1762 case ARM::LDC2L_POST:
1763 case ARM::STC2_POST:
1764 case ARM::STC2L_POST:
1765 case ARM::t2LDC_POST:
1766 case ARM::t2LDCL_POST:
1767 case ARM::t2STC_POST:
1768 case ARM::t2STCL_POST:
1770 case ARM::LDCL_POST:
1772 case ARM::STCL_POST:
1783 case ARM::LDC_OFFSET:
1786 case ARM::LDC_OPTION:
1787 case ARM::LDCL_OFFSET:
1789 case ARM::LDCL_POST:
1790 case ARM::LDCL_OPTION:
1791 case ARM::STC_OFFSET:
1794 case ARM::STC_OPTION:
1795 case ARM::STCL_OFFSET:
1797 case ARM::STCL_POST:
1798 case ARM::STCL_OPTION:
1811 uint64_t
Address,
const void *Decoder) {
1814 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1815 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1816 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1817 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1818 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1819 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1820 unsigned P = fieldFromInstruction(Insn, 24, 1);
1821 unsigned W = fieldFromInstruction(Insn, 21, 1);
1825 case ARM::STR_POST_IMM:
1826 case ARM::STR_POST_REG:
1827 case ARM::STRB_POST_IMM:
1828 case ARM::STRB_POST_REG:
1829 case ARM::STRT_POST_REG:
1830 case ARM::STRT_POST_IMM:
1831 case ARM::STRBT_POST_REG:
1832 case ARM::STRBT_POST_IMM:
1845 case ARM::LDR_POST_IMM:
1846 case ARM::LDR_POST_REG:
1847 case ARM::LDRB_POST_IMM:
1848 case ARM::LDRB_POST_REG:
1849 case ARM::LDRBT_POST_REG:
1850 case ARM::LDRBT_POST_IMM:
1851 case ARM::LDRT_POST_REG:
1852 case ARM::LDRT_POST_IMM:
1864 if (!fieldFromInstruction(Insn, 23, 1))
1867 bool writeback = (P == 0) || (W == 1);
1868 unsigned idx_mode = 0;
1871 else if (!P && writeback)
1874 if (writeback && (Rn == 15 || Rn == Rt))
1881 switch( fieldFromInstruction(Insn, 5, 2)) {
1897 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1916 uint64_t
Address,
const void *Decoder) {
1919 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1920 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1921 unsigned type = fieldFromInstruction(Val, 5, 2);
1922 unsigned imm = fieldFromInstruction(Val, 7, 5);
1923 unsigned U = fieldFromInstruction(Val, 12, 1);
1960 uint64_t
Address,
const void *Decoder) {
1963 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1964 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1965 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1966 unsigned type = fieldFromInstruction(Insn, 22, 1);
1967 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1968 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1969 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1970 unsigned W = fieldFromInstruction(Insn, 21, 1);
1971 unsigned P = fieldFromInstruction(Insn, 24, 1);
1972 unsigned Rt2 = Rt + 1;
1974 bool writeback = (W == 1) | (P == 0);
1980 case ARM::STRD_POST:
1983 case ARM::LDRD_POST:
1992 case ARM::STRD_POST:
1993 if (P == 0 && W == 1)
1996 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1998 if (type && Rm == 15)
2002 if (!type && fieldFromInstruction(Insn, 8, 4))
2007 case ARM::STRH_POST:
2010 if (writeback && (Rn == 15 || Rn == Rt))
2012 if (!type && Rm == 15)
2017 case ARM::LDRD_POST:
2018 if (type && Rn == 15) {
2023 if (P == 0 && W == 1)
2025 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2027 if (!type && writeback && Rn == 15)
2029 if (writeback && (Rn == Rt || Rn == Rt2))
2034 case ARM::LDRH_POST:
2035 if (type && Rn == 15) {
2042 if (!type && Rm == 15)
2044 if (!type && writeback && (Rn == 15 || Rn == Rt))
2048 case ARM::LDRSH_PRE:
2049 case ARM::LDRSH_POST:
2051 case ARM::LDRSB_PRE:
2052 case ARM::LDRSB_POST:
2053 if (type && Rn == 15) {
2058 if (type && (Rt == 15 || (writeback && Rn == Rt)))
2060 if (!type && (Rt == 15 || Rm == 15))
2062 if (!type && writeback && (Rn == 15 || Rn == Rt))
2079 case ARM::STRD_POST:
2082 case ARM::STRH_POST:
2096 case ARM::STRD_POST:
2099 case ARM::LDRD_POST:
2112 case ARM::LDRD_POST:
2115 case ARM::LDRH_POST:
2117 case ARM::LDRSH_PRE:
2118 case ARM::LDRSH_POST:
2120 case ARM::LDRSB_PRE:
2121 case ARM::LDRSB_POST:
2151 uint64_t
Address,
const void *Decoder) {
2154 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2155 unsigned mode = fieldFromInstruction(Insn, 23, 2);
2180 uint64_t
Address,
const void *Decoder) {
2183 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2184 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2185 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2186 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2204 uint64_t
Address,
const void *Decoder) {
2207 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2208 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2209 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2217 case ARM::LDMDA_UPD:
2223 case ARM::LDMDB_UPD:
2229 case ARM::LDMIA_UPD:
2235 case ARM::LDMIB_UPD:
2241 case ARM::STMDA_UPD:
2247 case ARM::STMDB_UPD:
2253 case ARM::STMIA_UPD:
2259 case ARM::STMIB_UPD:
2267 if (fieldFromInstruction(Insn, 20, 1) == 0) {
2269 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2270 fieldFromInstruction(Insn, 20, 1) == 0))
2295 uint64_t
Address,
const void *Decoder) {
2296 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2297 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2310 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2317 uint64_t
Address,
const void *Decoder) {
2318 unsigned imod = fieldFromInstruction(Insn, 18, 2);
2319 unsigned M = fieldFromInstruction(Insn, 17, 1);
2320 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2321 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2327 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2328 fieldFromInstruction(Insn, 16, 1) != 0 ||
2329 fieldFromInstruction(Insn, 20, 8) != 0x10)
2344 }
else if (imod && !M) {
2349 }
else if (!imod && M) {
2364 uint64_t
Address,
const void *Decoder) {
2365 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2366 unsigned M = fieldFromInstruction(Insn, 8, 1);
2367 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2368 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2384 }
else if (imod && !M) {
2389 }
else if (!imod && M) {
2395 int imm = fieldFromInstruction(Insn, 0, 8);
2406 uint64_t
Address,
const void *Decoder) {
2409 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2412 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2413 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2414 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2415 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2430 uint64_t
Address,
const void *Decoder) {
2433 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2434 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2437 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2438 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2457 uint64_t
Address,
const void *Decoder) {
2460 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2461 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2462 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2463 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2464 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2485 uint64_t
Address,
const void *Decoder) {
2488 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2489 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2490 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2506 uint64_t
Address,
const void *Decoder) {
2509 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2514 if (!FeatureBits[ARM::HasV8_1aOps] ||
2515 !FeatureBits[ARM::HasV8Ops])
2520 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2521 fieldFromInstruction(Insn, 4,4) != 0)
2523 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2524 fieldFromInstruction(Insn, 0,4) != 0)
2534 uint64_t
Address,
const void *Decoder) {
2537 unsigned add = fieldFromInstruction(Val, 12, 1);
2538 unsigned imm = fieldFromInstruction(Val, 0, 12);
2539 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2544 if (!add) imm *= -1;
2545 if (imm == 0 && !add) imm = INT32_MIN;
2554 uint64_t
Address,
const void *Decoder) {
2557 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2559 unsigned U = fieldFromInstruction(Val, 8, 1);
2560 unsigned imm = fieldFromInstruction(Val, 0, 8);
2574 uint64_t
Address,
const void *Decoder) {
2577 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2579 unsigned U = fieldFromInstruction(Val, 8, 1);
2580 unsigned imm = fieldFromInstruction(Val, 0, 8);
2594 uint64_t
Address,
const void *Decoder) {
2600 uint64_t
Address,
const void *Decoder) {
2609 unsigned S = fieldFromInstruction(Insn, 26, 1);
2610 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2611 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2612 unsigned I1 = !(J1 ^ S);
2613 unsigned I2 = !(J2 ^ S);
2614 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2615 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2616 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2617 int imm32 = SignExtend32<25>(tmp << 1);
2619 true, 4, Inst, Decoder))
2627 uint64_t
Address,
const void *Decoder) {
2630 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2631 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2635 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2637 true, 4, Inst, Decoder))
2643 true, 4, Inst, Decoder))
2652 uint64_t
Address,
const void *Decoder) {
2655 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2656 unsigned align = fieldFromInstruction(Val, 4, 2);
2669 uint64_t
Address,
const void *Decoder) {
2672 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2673 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2674 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2675 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2676 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2677 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2681 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2682 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2683 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2684 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2685 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2686 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2687 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2688 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2689 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2696 case ARM::VLD2b16wb_fixed:
2697 case ARM::VLD2b16wb_register:
2698 case ARM::VLD2b32wb_fixed:
2699 case ARM::VLD2b32wb_register:
2700 case ARM::VLD2b8wb_fixed:
2701 case ARM::VLD2b8wb_register:
2715 case ARM::VLD3d8_UPD:
2716 case ARM::VLD3d16_UPD:
2717 case ARM::VLD3d32_UPD:
2721 case ARM::VLD4d8_UPD:
2722 case ARM::VLD4d16_UPD:
2723 case ARM::VLD4d32_UPD:
2730 case ARM::VLD3q8_UPD:
2731 case ARM::VLD3q16_UPD:
2732 case ARM::VLD3q32_UPD:
2736 case ARM::VLD4q8_UPD:
2737 case ARM::VLD4q16_UPD:
2738 case ARM::VLD4q32_UPD:
2751 case ARM::VLD3d8_UPD:
2752 case ARM::VLD3d16_UPD:
2753 case ARM::VLD3d32_UPD:
2757 case ARM::VLD4d8_UPD:
2758 case ARM::VLD4d16_UPD:
2759 case ARM::VLD4d32_UPD:
2766 case ARM::VLD3q8_UPD:
2767 case ARM::VLD3q16_UPD:
2768 case ARM::VLD3q32_UPD:
2772 case ARM::VLD4q8_UPD:
2773 case ARM::VLD4q16_UPD:
2774 case ARM::VLD4q32_UPD:
2787 case ARM::VLD4d8_UPD:
2788 case ARM::VLD4d16_UPD:
2789 case ARM::VLD4d32_UPD:
2796 case ARM::VLD4q8_UPD:
2797 case ARM::VLD4q16_UPD:
2798 case ARM::VLD4q32_UPD:
2808 case ARM::VLD1d8wb_fixed:
2809 case ARM::VLD1d16wb_fixed:
2810 case ARM::VLD1d32wb_fixed:
2811 case ARM::VLD1d64wb_fixed:
2812 case ARM::VLD1d8wb_register:
2813 case ARM::VLD1d16wb_register:
2814 case ARM::VLD1d32wb_register:
2815 case ARM::VLD1d64wb_register:
2816 case ARM::VLD1q8wb_fixed:
2817 case ARM::VLD1q16wb_fixed:
2818 case ARM::VLD1q32wb_fixed:
2819 case ARM::VLD1q64wb_fixed:
2820 case ARM::VLD1q8wb_register:
2821 case ARM::VLD1q16wb_register:
2822 case ARM::VLD1q32wb_register:
2823 case ARM::VLD1q64wb_register:
2824 case ARM::VLD1d8Twb_fixed:
2825 case ARM::VLD1d8Twb_register:
2826 case ARM::VLD1d16Twb_fixed:
2827 case ARM::VLD1d16Twb_register:
2828 case ARM::VLD1d32Twb_fixed:
2829 case ARM::VLD1d32Twb_register:
2830 case ARM::VLD1d64Twb_fixed:
2831 case ARM::VLD1d64Twb_register:
2832 case ARM::VLD1d8Qwb_fixed:
2833 case ARM::VLD1d8Qwb_register:
2834 case ARM::VLD1d16Qwb_fixed:
2835 case ARM::VLD1d16Qwb_register:
2836 case ARM::VLD1d32Qwb_fixed:
2837 case ARM::VLD1d32Qwb_register:
2838 case ARM::VLD1d64Qwb_fixed:
2839 case ARM::VLD1d64Qwb_register:
2840 case ARM::VLD2d8wb_fixed:
2841 case ARM::VLD2d16wb_fixed:
2842 case ARM::VLD2d32wb_fixed:
2843 case ARM::VLD2q8wb_fixed:
2844 case ARM::VLD2q16wb_fixed:
2845 case ARM::VLD2q32wb_fixed:
2846 case ARM::VLD2d8wb_register:
2847 case ARM::VLD2d16wb_register:
2848 case ARM::VLD2d32wb_register:
2849 case ARM::VLD2q8wb_register:
2850 case ARM::VLD2q16wb_register:
2851 case ARM::VLD2q32wb_register:
2852 case ARM::VLD2b8wb_fixed:
2853 case ARM::VLD2b16wb_fixed:
2854 case ARM::VLD2b32wb_fixed:
2855 case ARM::VLD2b8wb_register:
2856 case ARM::VLD2b16wb_register:
2857 case ARM::VLD2b32wb_register:
2860 case ARM::VLD3d8_UPD:
2861 case ARM::VLD3d16_UPD:
2862 case ARM::VLD3d32_UPD:
2863 case ARM::VLD3q8_UPD:
2864 case ARM::VLD3q16_UPD:
2865 case ARM::VLD3q32_UPD:
2866 case ARM::VLD4d8_UPD:
2867 case ARM::VLD4d16_UPD:
2868 case ARM::VLD4d32_UPD:
2869 case ARM::VLD4q8_UPD:
2870 case ARM::VLD4q16_UPD:
2871 case ARM::VLD4q32_UPD:
2898 case ARM::VLD1d8wb_fixed:
2899 case ARM::VLD1d16wb_fixed:
2900 case ARM::VLD1d32wb_fixed:
2901 case ARM::VLD1d64wb_fixed:
2902 case ARM::VLD1d8Twb_fixed:
2903 case ARM::VLD1d16Twb_fixed:
2904 case ARM::VLD1d32Twb_fixed:
2905 case ARM::VLD1d64Twb_fixed:
2906 case ARM::VLD1d8Qwb_fixed:
2907 case ARM::VLD1d16Qwb_fixed:
2908 case ARM::VLD1d32Qwb_fixed:
2909 case ARM::VLD1d64Qwb_fixed:
2910 case ARM::VLD1d8wb_register:
2911 case ARM::VLD1d16wb_register:
2912 case ARM::VLD1d32wb_register:
2913 case ARM::VLD1d64wb_register:
2914 case ARM::VLD1q8wb_fixed:
2915 case ARM::VLD1q16wb_fixed:
2916 case ARM::VLD1q32wb_fixed:
2917 case ARM::VLD1q64wb_fixed:
2918 case ARM::VLD1q8wb_register:
2919 case ARM::VLD1q16wb_register:
2920 case ARM::VLD1q32wb_register:
2921 case ARM::VLD1q64wb_register:
2925 if (Rm != 0xD && Rm != 0xF &&
2929 case ARM::VLD2d8wb_fixed:
2930 case ARM::VLD2d16wb_fixed:
2931 case ARM::VLD2d32wb_fixed:
2932 case ARM::VLD2b8wb_fixed:
2933 case ARM::VLD2b16wb_fixed:
2934 case ARM::VLD2b32wb_fixed:
2935 case ARM::VLD2q8wb_fixed:
2936 case ARM::VLD2q16wb_fixed:
2937 case ARM::VLD2q32wb_fixed:
2945 uint64_t
Address,
const void *Decoder) {
2946 unsigned type = fieldFromInstruction(Insn, 8, 4);
2947 unsigned align = fieldFromInstruction(Insn, 4, 2);
2952 unsigned load = fieldFromInstruction(Insn, 21, 1);
2958 uint64_t
Address,
const void *Decoder) {
2959 unsigned size = fieldFromInstruction(Insn, 6, 2);
2962 unsigned type = fieldFromInstruction(Insn, 8, 4);
2963 unsigned align = fieldFromInstruction(Insn, 4, 2);
2967 unsigned load = fieldFromInstruction(Insn, 21, 1);
2973 uint64_t
Address,
const void *Decoder) {
2974 unsigned size = fieldFromInstruction(Insn, 6, 2);
2977 unsigned align = fieldFromInstruction(Insn, 4, 2);
2980 unsigned load = fieldFromInstruction(Insn, 21, 1);
2986 uint64_t
Address,
const void *Decoder) {
2987 unsigned size = fieldFromInstruction(Insn, 6, 2);
2990 unsigned load = fieldFromInstruction(Insn, 21, 1);
2996 uint64_t
Address,
const void *Decoder) {
2999 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3000 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3001 unsigned wb = fieldFromInstruction(Insn, 16, 4);
3002 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3003 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3004 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3008 case ARM::VST1d8wb_fixed:
3009 case ARM::VST1d16wb_fixed:
3010 case ARM::VST1d32wb_fixed:
3011 case ARM::VST1d64wb_fixed:
3012 case ARM::VST1d8wb_register:
3013 case ARM::VST1d16wb_register:
3014 case ARM::VST1d32wb_register:
3015 case ARM::VST1d64wb_register:
3016 case ARM::VST1q8wb_fixed:
3017 case ARM::VST1q16wb_fixed:
3018 case ARM::VST1q32wb_fixed:
3019 case ARM::VST1q64wb_fixed:
3020 case ARM::VST1q8wb_register:
3021 case ARM::VST1q16wb_register:
3022 case ARM::VST1q32wb_register:
3023 case ARM::VST1q64wb_register:
3024 case ARM::VST1d8Twb_fixed:
3025 case ARM::VST1d16Twb_fixed:
3026 case ARM::VST1d32Twb_fixed:
3027 case ARM::VST1d64Twb_fixed:
3028 case ARM::VST1d8Twb_register:
3029 case ARM::VST1d16Twb_register:
3030 case ARM::VST1d32Twb_register:
3031 case ARM::VST1d64Twb_register:
3032 case ARM::VST1d8Qwb_fixed:
3033 case ARM::VST1d16Qwb_fixed:
3034 case ARM::VST1d32Qwb_fixed:
3035 case ARM::VST1d64Qwb_fixed:
3036 case ARM::VST1d8Qwb_register:
3037 case ARM::VST1d16Qwb_register:
3038 case ARM::VST1d32Qwb_register:
3039 case ARM::VST1d64Qwb_register:
3040 case ARM::VST2d8wb_fixed:
3041 case ARM::VST2d16wb_fixed:
3042 case ARM::VST2d32wb_fixed:
3043 case ARM::VST2d8wb_register:
3044 case ARM::VST2d16wb_register:
3045 case ARM::VST2d32wb_register:
3046 case ARM::VST2q8wb_fixed:
3047 case ARM::VST2q16wb_fixed:
3048 case ARM::VST2q32wb_fixed:
3049 case ARM::VST2q8wb_register:
3050 case ARM::VST2q16wb_register:
3051 case ARM::VST2q32wb_register:
3052 case ARM::VST2b8wb_fixed:
3053 case ARM::VST2b16wb_fixed:
3054 case ARM::VST2b32wb_fixed:
3055 case ARM::VST2b8wb_register:
3056 case ARM::VST2b16wb_register:
3057 case ARM::VST2b32wb_register:
3062 case ARM::VST3d8_UPD:
3063 case ARM::VST3d16_UPD:
3064 case ARM::VST3d32_UPD:
3065 case ARM::VST3q8_UPD:
3066 case ARM::VST3q16_UPD:
3067 case ARM::VST3q32_UPD:
3068 case ARM::VST4d8_UPD:
3069 case ARM::VST4d16_UPD:
3070 case ARM::VST4d32_UPD:
3071 case ARM::VST4q8_UPD:
3072 case ARM::VST4q16_UPD:
3073 case ARM::VST4q32_UPD:
3090 else if (Rm != 0xF) {
3095 case ARM::VST1d8wb_fixed:
3096 case ARM::VST1d16wb_fixed:
3097 case ARM::VST1d32wb_fixed:
3098 case ARM::VST1d64wb_fixed:
3099 case ARM::VST1q8wb_fixed:
3100 case ARM::VST1q16wb_fixed:
3101 case ARM::VST1q32wb_fixed:
3102 case ARM::VST1q64wb_fixed:
3103 case ARM::VST1d8Twb_fixed:
3104 case ARM::VST1d16Twb_fixed:
3105 case ARM::VST1d32Twb_fixed:
3106 case ARM::VST1d64Twb_fixed:
3107 case ARM::VST1d8Qwb_fixed:
3108 case ARM::VST1d16Qwb_fixed:
3109 case ARM::VST1d32Qwb_fixed:
3110 case ARM::VST1d64Qwb_fixed:
3111 case ARM::VST2d8wb_fixed:
3112 case ARM::VST2d16wb_fixed:
3113 case ARM::VST2d32wb_fixed:
3114 case ARM::VST2q8wb_fixed:
3115 case ARM::VST2q16wb_fixed:
3116 case ARM::VST2q32wb_fixed:
3117 case ARM::VST2b8wb_fixed:
3118 case ARM::VST2b16wb_fixed:
3119 case ARM::VST2b32wb_fixed:
3129 case ARM::VST1q16wb_fixed:
3130 case ARM::VST1q16wb_register:
3131 case ARM::VST1q32wb_fixed:
3132 case ARM::VST1q32wb_register:
3133 case ARM::VST1q64wb_fixed:
3134 case ARM::VST1q64wb_register:
3135 case ARM::VST1q8wb_fixed:
3136 case ARM::VST1q8wb_register:
3140 case ARM::VST2d16wb_fixed:
3141 case ARM::VST2d16wb_register:
3142 case ARM::VST2d32wb_fixed:
3143 case ARM::VST2d32wb_register:
3144 case ARM::VST2d8wb_fixed:
3145 case ARM::VST2d8wb_register:
3152 case ARM::VST2b16wb_fixed:
3153 case ARM::VST2b16wb_register:
3154 case ARM::VST2b32wb_fixed:
3155 case ARM::VST2b32wb_register:
3156 case ARM::VST2b8wb_fixed:
3157 case ARM::VST2b8wb_register:
3171 case ARM::VST3d8_UPD:
3172 case ARM::VST3d16_UPD:
3173 case ARM::VST3d32_UPD:
3177 case ARM::VST4d8_UPD:
3178 case ARM::VST4d16_UPD:
3179 case ARM::VST4d32_UPD:
3186 case ARM::VST3q8_UPD:
3187 case ARM::VST3q16_UPD:
3188 case ARM::VST3q32_UPD:
3192 case ARM::VST4q8_UPD:
3193 case ARM::VST4q16_UPD:
3194 case ARM::VST4q32_UPD:
3207 case ARM::VST3d8_UPD:
3208 case ARM::VST3d16_UPD:
3209 case ARM::VST3d32_UPD:
3213 case ARM::VST4d8_UPD:
3214 case ARM::VST4d16_UPD:
3215 case ARM::VST4d32_UPD:
3222 case ARM::VST3q8_UPD:
3223 case ARM::VST3q16_UPD:
3224 case ARM::VST3q32_UPD:
3228 case ARM::VST4q8_UPD:
3229 case ARM::VST4q16_UPD:
3230 case ARM::VST4q32_UPD:
3243 case ARM::VST4d8_UPD:
3244 case ARM::VST4d16_UPD:
3245 case ARM::VST4d32_UPD:
3252 case ARM::VST4q8_UPD:
3253 case ARM::VST4q16_UPD:
3254 case ARM::VST4q32_UPD:
3266 uint64_t
Address,
const void *Decoder) {
3269 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3270 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3271 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3272 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3273 unsigned align = fieldFromInstruction(Insn, 4, 1);
3274 unsigned size = fieldFromInstruction(Insn, 6, 2);
3276 if (size == 0 && align == 1)
3278 align *= (1 <<
size);
3281 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
3282 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
3283 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
3284 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
3305 if (Rm != 0xD && Rm != 0xF &&
3313 uint64_t
Address,
const void *Decoder) {
3316 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3317 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3318 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3319 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3320 unsigned align = fieldFromInstruction(Insn, 4, 1);
3321 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3325 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
3326 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
3327 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
3328 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
3332 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
3333 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
3334 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
3335 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3352 if (Rm != 0xD && Rm != 0xF) {
3361 uint64_t
Address,
const void *Decoder) {
3364 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3365 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3366 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3367 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3368 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3387 else if (Rm != 0xF) {
3396 uint64_t
Address,
const void *Decoder) {
3399 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3400 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3401 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3402 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3403 unsigned size = fieldFromInstruction(Insn, 6, 2);
3404 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3405 unsigned align = fieldFromInstruction(Insn, 4, 1);
3439 else if (Rm != 0xF) {
3449 uint64_t
Address,
const void *Decoder) {
3452 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3453 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3454 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3455 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3456 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3457 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3458 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3459 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3472 case ARM::VORRiv4i16:
3473 case ARM::VORRiv2i32:
3474 case ARM::VBICiv4i16:
3475 case ARM::VBICiv2i32:
3479 case ARM::VORRiv8i16:
3480 case ARM::VORRiv4i32:
3481 case ARM::VBICiv8i16:
3482 case ARM::VBICiv4i32:
3495 uint64_t
Address,
const void *Decoder) {
3498 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3499 fieldFromInstruction(Insn, 13, 3));
3500 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3501 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3502 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3503 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3505 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3507 if (cmode == 0xF && Inst.
getOpcode() == ARM::MVE_VMVNimmi32)
3523 uint64_t
Address,
const void *Decoder) {
3526 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3527 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3532 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3533 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3536 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3537 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3540 if (!fieldFromInstruction(Insn, 12, 1))
3548 uint64_t
Address,
const void *Decoder) {
3551 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3552 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3553 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3554 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3555 unsigned size = fieldFromInstruction(Insn, 18, 2);
3567 uint64_t
Address,
const void *Decoder) {
3573 uint64_t
Address,
const void *Decoder) {
3579 uint64_t
Address,
const void *Decoder) {
3585 uint64_t
Address,
const void *Decoder) {
3591 uint64_t
Address,
const void *Decoder) {
3594 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3595 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3596 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3597 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3598 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3599 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3600 unsigned op = fieldFromInstruction(Insn, 6, 1);
3627 uint64_t
Address,
const void *Decoder) {
3630 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3631 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3651 uint64_t
Address,
const void *Decoder) {
3653 true, 2, Inst, Decoder))
3659 uint64_t
Address,
const void *Decoder) {
3661 true, 4, Inst, Decoder))
3667 uint64_t
Address,
const void *Decoder) {
3669 true, 2, Inst, Decoder))
3675 uint64_t
Address,
const void *Decoder) {
3678 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3679 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3690 uint64_t
Address,
const void *Decoder) {
3693 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3694 unsigned imm = fieldFromInstruction(Val, 3, 5);
3704 uint64_t
Address,
const void *Decoder) {
3705 unsigned imm = Val << 2;
3714 uint64_t
Address,
const void *Decoder) {
3722 uint64_t
Address,
const void *Decoder) {
3725 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3726 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3727 unsigned imm = fieldFromInstruction(Val, 0, 2);
3751 uint64_t
Address,
const void *Decoder) {
3754 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3755 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3758 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3760 bool hasMP = featureBits[ARM::FeatureMP];
3761 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3816 if (!hasV7Ops || !hasMP)
3824 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3825 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3826 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3834 uint64_t
Address,
const void* Decoder) {
3837 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3838 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3839 unsigned U = fieldFromInstruction(Insn, 9, 1);
3840 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3843 unsigned add = fieldFromInstruction(Insn, 9, 1);
3846 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3848 bool hasMP = featureBits[ARM::FeatureMP];
3849 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3859 case ARM::t2LDRSBi8:
3865 case ARM::t2LDRSHi8:
3882 case ARM::t2LDRSHi8:
3888 case ARM::t2LDRSBi8:
3904 if (!hasV7Ops || !hasMP)
3918 uint64_t
Address,
const void* Decoder) {
3921 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3922 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3923 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3927 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3929 bool hasMP = featureBits[ARM::FeatureMP];
3930 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3937 case ARM::t2LDRHi12:
3940 case ARM::t2LDRSHi12:
3943 case ARM::t2LDRBi12:
3946 case ARM::t2LDRSBi12:
3963 case ARM::t2LDRSHi12:
3965 case ARM::t2LDRHi12:
3968 case ARM::t2LDRSBi12:
3983 case ARM::t2PLDWi12:
3984 if (!hasV7Ops || !hasMP)
3998 uint64_t
Address,
const void* Decoder) {
4001 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4002 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4003 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4037 uint64_t
Address,
const void* Decoder) {
4040 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4041 unsigned U = fieldFromInstruction(Insn, 23, 1);
4042 int imm = fieldFromInstruction(Insn, 0, 12);
4045 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4047 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4051 case ARM::t2LDRBpci:
4052 case ARM::t2LDRHpci:
4055 case ARM::t2LDRSBpci:
4058 case ARM::t2LDRSHpci:
4090 uint64_t
Address,
const void *Decoder) {
4094 int imm = Val & 0xFF;
4096 if (!(Val & 0x100)) imm *= -1;
4104 const void *Decoder) {
4108 int imm = Val & 0x7F;
4119 uint64_t
Address,
const void *Decoder) {
4122 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4123 unsigned imm = fieldFromInstruction(Val, 0, 9);
4135 const void *Decoder) {
4138 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4139 unsigned imm = fieldFromInstruction(Val, 0, 8);
4150 uint64_t
Address,
const void *Decoder) {
4153 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4154 unsigned imm = fieldFromInstruction(Val, 0, 8);
4165 uint64_t
Address,
const void *Decoder) {
4166 int imm = Val & 0xFF;
4169 else if (!(Val & 0x100))
4178 uint64_t
Address,
const void *Decoder) {
4179 int imm = Val & 0x7F;
4182 else if (!(Val & 0x80))
4184 if (imm != INT32_MIN)
4185 imm *= (1U << shift);
4192 uint64_t
Address,
const void *Decoder) {
4195 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4196 unsigned imm = fieldFromInstruction(Val, 0, 9);
4240 const void *Decoder) {
4243 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4244 unsigned imm = fieldFromInstruction(Val, 0, 8);
4248 if (!
Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4254 template<
int shift,
int WriteBack>
4257 const void *Decoder) {
4260 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4261 unsigned imm = fieldFromInstruction(Val, 0, 8);
4267 if (!
Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4274 uint64_t
Address,
const void *Decoder) {
4277 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4278 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4279 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4280 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4282 unsigned load = fieldFromInstruction(Insn, 20, 1);
4286 case ARM::t2LDR_PRE:
4287 case ARM::t2LDR_POST:
4290 case ARM::t2LDRB_PRE:
4291 case ARM::t2LDRB_POST:
4294 case ARM::t2LDRH_PRE:
4295 case ARM::t2LDRH_POST:
4298 case ARM::t2LDRSB_PRE:
4299 case ARM::t2LDRSB_POST:
4305 case ARM::t2LDRSH_PRE:
4306 case ARM::t2LDRSH_POST:
4335 uint64_t
Address,
const void *Decoder) {
4338 unsigned Rn = fieldFromInstruction(Val, 13, 4);
4339 unsigned imm = fieldFromInstruction(Val, 0, 12);
4344 case ARM::t2STRBi12:
4345 case ARM::t2STRHi12:
4361 uint64_t
Address,
const void *Decoder) {
4362 unsigned imm = fieldFromInstruction(Insn, 0, 7);
4372 uint64_t
Address,
const void *Decoder) {
4376 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4377 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4384 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
4385 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4397 uint64_t
Address,
const void *Decoder) {
4398 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4399 unsigned flags = fieldFromInstruction(Insn, 0, 3);
4408 uint64_t
Address,
const void *Decoder) {
4410 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4411 unsigned add = fieldFromInstruction(Insn, 4, 1);
4421 uint64_t
Address,
const void *Decoder) {
4423 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4424 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4436 uint64_t
Address,
const void *Decoder) {
4438 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4439 int imm = fieldFromInstruction(Insn, 0, 7);
4444 if(!fieldFromInstruction(Insn, 7, 1)) {
4450 if (imm != INT32_MIN)
4451 imm *= (1U << shift);
4458 uint64_t
Address,
const void *Decoder) {
4466 unsigned S = (Val >> 23) & 1;
4467 unsigned J1 = (Val >> 22) & 1;
4468 unsigned J2 = (Val >> 21) & 1;
4469 unsigned I1 = !(J1 ^ S);
4470 unsigned I2 = !(J2 ^ S);
4471 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4472 int imm32 = SignExtend32<25>(tmp << 1);
4475 (Address & ~2u) + imm32 + 4,
4476 true, 4, Inst, Decoder))
4482 uint64_t
Address,
const void *Decoder) {
4483 if (Val == 0xA || Val == 0xB)
4487 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4498 uint64_t
Address,
const void *Decoder) {
4501 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4502 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4514 uint64_t
Address,
const void *Decoder) {
4517 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4518 if (pred == 0xE || pred == 0xF) {
4519 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4534 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4538 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4539 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4540 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4541 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4542 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4556 uint64_t
Address,
const void *Decoder) {
4557 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4559 unsigned byte = fieldFromInstruction(Val, 8, 2);
4560 unsigned imm = fieldFromInstruction(Val, 0, 8);
4577 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4578 unsigned rot = fieldFromInstruction(Val, 7, 5);
4579 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4588 uint64_t
Address,
const void *Decoder) {
4590 true, 2, Inst, Decoder))
4597 const void *Decoder) {
4605 unsigned S = (Val >> 23) & 1;
4606 unsigned J1 = (Val >> 22) & 1;
4607 unsigned J2 = (Val >> 21) & 1;
4608 unsigned I1 = !(J1 ^ S);
4609 unsigned I2 = !(J2 ^ S);
4610 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4611 int imm32 = SignExtend32<25>(tmp << 1);
4614 true, 4, Inst, Decoder))
4620 uint64_t
Address,
const void *Decoder) {
4629 uint64_t
Address,
const void *Decoder) {
4638 uint64_t
Address,
const void *Decoder) {
4641 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4643 if (FeatureBits[ARM::FeatureMClass]) {
4644 unsigned ValLow = Val & 0xff;
4663 if (!(FeatureBits[ARM::HasV7Ops]))
4671 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4681 if (!(FeatureBits[ARM::Feature8MSecExt]))
4691 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4692 if (!(FeatureBits[ARM::HasV7Ops])) {
4705 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4706 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4720 uint64_t
Address,
const void *Decoder) {
4721 unsigned R = fieldFromInstruction(Val, 5, 1);
4722 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4727 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4735 uint64_t
Address,
const void *Decoder) {
4738 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4739 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4740 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4757 const void *Decoder) {
4760 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4761 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4762 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4763 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4768 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4782 uint64_t
Address,
const void *Decoder) {
4785 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4786 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4787 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4788 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4789 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4790 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4807 uint64_t
Address,
const void *Decoder) {
4810 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4811 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4812 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4813 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4814 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4815 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4816 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4834 uint64_t
Address,
const void *Decoder) {
4837 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4838 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4839 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4840 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4841 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4842 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4859 uint64_t
Address,
const void *Decoder) {
4862 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4863 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4864 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4865 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4866 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4867 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4884 uint64_t
Address,
const void *Decoder) {
4887 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4888 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4889 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4890 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4891 unsigned size = fieldFromInstruction(Insn, 10, 2);
4899 if (fieldFromInstruction(Insn, 4, 1))
4901 index = fieldFromInstruction(Insn, 5, 3);
4904 if (fieldFromInstruction(Insn, 5, 1))
4906 index = fieldFromInstruction(Insn, 6, 2);
4907 if (fieldFromInstruction(Insn, 4, 1))
4911 if (fieldFromInstruction(Insn, 6, 1))
4913 index = fieldFromInstruction(Insn, 7, 1);
4915 switch (fieldFromInstruction(Insn, 4, 2)) {
4951 uint64_t
Address,
const void *Decoder) {
4954 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4955 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4956 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4957 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4958 unsigned size = fieldFromInstruction(Insn, 10, 2);
4966 if (fieldFromInstruction(Insn, 4, 1))
4968 index = fieldFromInstruction(Insn, 5, 3);
4971 if (fieldFromInstruction(Insn, 5, 1))
4973 index = fieldFromInstruction(Insn, 6, 2);
4974 if (fieldFromInstruction(Insn, 4, 1))
4978 if (fieldFromInstruction(Insn, 6, 1))
4980 index = fieldFromInstruction(Insn, 7, 1);
4982 switch (fieldFromInstruction(Insn, 4, 2)) {
5016 uint64_t
Address,
const void *Decoder) {
5019 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5020 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5021 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5022 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5023 unsigned size = fieldFromInstruction(Insn, 10, 2);
5032 index = fieldFromInstruction(Insn, 5, 3);
5033 if (fieldFromInstruction(Insn, 4, 1))
5037 index = fieldFromInstruction(Insn, 6, 2);
5038 if (fieldFromInstruction(Insn, 4, 1))
5040 if (fieldFromInstruction(Insn, 5, 1))
5044 if (fieldFromInstruction(Insn, 5, 1))
5046 index = fieldFromInstruction(Insn, 7, 1);
5047 if (fieldFromInstruction(Insn, 4, 1) != 0)
5049 if (fieldFromInstruction(Insn, 6, 1))
5083 uint64_t
Address,
const void *Decoder) {
5086 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5087 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5088 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5089 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5090 unsigned size = fieldFromInstruction(Insn, 10, 2);
5099 index = fieldFromInstruction(Insn, 5, 3);
5100 if (fieldFromInstruction(Insn, 4, 1))
5104 index = fieldFromInstruction(Insn, 6, 2);
5105 if (fieldFromInstruction(Insn, 4, 1))
5107 if (fieldFromInstruction(Insn, 5, 1))
5111 if (fieldFromInstruction(Insn, 5, 1))
5113 index = fieldFromInstruction(Insn, 7, 1);
5114 if (fieldFromInstruction(Insn, 4, 1) != 0)
5116 if (fieldFromInstruction(Insn, 6, 1))