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ARMDisassembler.cpp
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1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
13 #include "Utils/ARMBaseInfo.h"
14 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Support/Compiler.h"
26 #include <algorithm>
27 #include <cassert>
28 #include <cstdint>
29 #include <vector>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "arm-disassembler"
34 
36 
37 namespace {
38 
39  // Handles the condition code status of instructions in IT blocks
40  class ITStatus
41  {
42  public:
43  // Returns the condition code for instruction in IT block
44  unsigned getITCC() {
45  unsigned CC = ARMCC::AL;
46  if (instrInITBlock())
47  CC = ITStates.back();
48  return CC;
49  }
50 
51  // Advances the IT block state to the next T or E
52  void advanceITState() {
53  ITStates.pop_back();
54  }
55 
56  // Returns true if the current instruction is in an IT block
57  bool instrInITBlock() {
58  return !ITStates.empty();
59  }
60 
61  // Returns true if current instruction is the last instruction in an IT block
62  bool instrLastInITBlock() {
63  return ITStates.size() == 1;
64  }
65 
66  // Called when decoding an IT instruction. Sets the IT state for the following
67  // instructions that for the IT block. Firstcond and Mask correspond to the
68  // fields in the IT instruction encoding.
69  void setITState(char Firstcond, char Mask) {
70  // (3 - the number of trailing zeros) is the number of then / else.
71  unsigned CondBit0 = Firstcond & 1;
72  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
73  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
74  assert(NumTZ <= 3 && "Invalid IT mask!");
75  // push condition codes onto the stack the correct order for the pops
76  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
77  bool T = ((Mask >> Pos) & 1) == CondBit0;
78  if (T)
79  ITStates.push_back(CCBits);
80  else
81  ITStates.push_back(CCBits ^ 1);
82  }
83  ITStates.push_back(CCBits);
84  }
85 
86  private:
87  std::vector<unsigned char> ITStates;
88  };
89 
90 /// ARM disassembler for all ARM platforms.
91 class ARMDisassembler : public MCDisassembler {
92 public:
93  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94  MCDisassembler(STI, Ctx) {
95  }
96 
97  ~ARMDisassembler() override = default;
98 
99  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
100  ArrayRef<uint8_t> Bytes, uint64_t Address,
101  raw_ostream &VStream,
102  raw_ostream &CStream) const override;
103 };
104 
105 /// Thumb disassembler for all Thumb platforms.
106 class ThumbDisassembler : public MCDisassembler {
107 public:
108  ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
109  MCDisassembler(STI, Ctx) {
110  }
111 
112  ~ThumbDisassembler() override = default;
113 
114  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
115  ArrayRef<uint8_t> Bytes, uint64_t Address,
116  raw_ostream &VStream,
117  raw_ostream &CStream) const override;
118 
119 private:
120  mutable ITStatus ITBlock;
121 
122  DecodeStatus AddThumbPredicate(MCInst&) const;
123  void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
124 };
125 
126 } // end anonymous namespace
127 
128 static bool Check(DecodeStatus &Out, DecodeStatus In) {
129  switch (In) {
131  // Out stays the same.
132  return true;
134  Out = In;
135  return true;
137  Out = In;
138  return false;
139  }
140  llvm_unreachable("Invalid DecodeStatus!");
141 }
142 
143 // Forward declare these because the autogenerated code will reference them.
144 // Definitions are further down.
145 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
146  uint64_t Address, const void *Decoder);
148  unsigned RegNo, uint64_t Address,
149  const void *Decoder);
151  unsigned RegNo, uint64_t Address,
152  const void *Decoder);
153 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154  uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
156  uint64_t Address, const void *Decoder);
157 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
158  uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
160  uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
162  uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
164  uint64_t Address, const void *Decoder);
165 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
166  uint64_t Address, const void *Decoder);
167 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
168  uint64_t Address, const void *Decoder);
169 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
170  uint64_t Address, const void *Decoder);
172  unsigned RegNo,
173  uint64_t Address,
174  const void *Decoder);
175 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
176  uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
178  uint64_t Address, const void *Decoder);
180  unsigned RegNo, uint64_t Address,
181  const void *Decoder);
182 
183 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
184  uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
186  uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
188  uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
190  uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
192  uint64_t Address, const void *Decoder);
193 
194 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
195  uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
197  uint64_t Address, const void *Decoder);
199  unsigned Insn,
200  uint64_t Address,
201  const void *Decoder);
202 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
203  uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
205  uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
207  uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
209  uint64_t Address, const void *Decoder);
210 
212  unsigned Insn,
213  uint64_t Adddress,
214  const void *Decoder);
215 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
216  uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
218  uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
220  uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
222  uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
224  uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
226  uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
228  uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
230  uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
232  uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
234  uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
236  uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
238  uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
240  uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
242  uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
244  uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
246  uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
248  uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
250  uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
252  uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
254  uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
256  uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
258  uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
260  uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
262  uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
264  uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
266  uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
268  uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
270  uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
272  uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
274  uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
276  uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
278  uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
280  uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
282  uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
284  uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
286  uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
288  uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
290  uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
292  uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
294  uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
296  uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
298  uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
300  uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
302  uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
304  uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
306  uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
308  uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
310  uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
312  uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
314  uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
316  uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
318  uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
320  uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
322  uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
324  uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
326  uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
328  uint64_t Address, const void *Decoder);
330  unsigned Val,
331  uint64_t Address,
332  const void *Decoder);
333 
334 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
335  uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
337  uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
339  uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
341  uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
343  uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
345  uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
347  uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
349  uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
351  uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
353  uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
355  uint64_t Address, const void* Decoder);
356 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
357  uint64_t Address, const void* Decoder);
358 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
359  uint64_t Address, const void* Decoder);
360 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
361  uint64_t Address, const void* Decoder);
362 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
363  uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
365  uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
367  uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
369  uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
371  uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
373  uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
375  uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
377  uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
379  uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
381  uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
383  uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
385  uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
387  uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
389  uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
391  uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
393  uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
395  uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
397  uint64_t Address, const void *Decoder);
398 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
399  uint64_t Address, const void *Decoder);
400 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
401  uint64_t Address, const void *Decoder);
402 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
403  uint64_t Address, const void *Decoder);
404 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
405  uint64_t Address, const void *Decoder);
406 
407 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
408  uint64_t Address, const void *Decoder);
409 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
410  uint64_t Address, const void *Decoder);
411 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
412  uint64_t Address, const void *Decoder);
413 
414 #include "ARMGenDisassemblerTables.inc"
415 
417  const MCSubtargetInfo &STI,
418  MCContext &Ctx) {
419  return new ARMDisassembler(STI, Ctx);
420 }
421 
423  const MCSubtargetInfo &STI,
424  MCContext &Ctx) {
425  return new ThumbDisassembler(STI, Ctx);
426 }
427 
428 // Post-decoding checks
430  uint64_t Address, raw_ostream &OS,
431  raw_ostream &CS,
432  uint32_t Insn,
433  DecodeStatus Result) {
434  switch (MI.getOpcode()) {
435  case ARM::HVC: {
436  // HVC is undefined if condition = 0xf otherwise upredictable
437  // if condition != 0xe
438  uint32_t Cond = (Insn >> 28) & 0xF;
439  if (Cond == 0xF)
440  return MCDisassembler::Fail;
441  if (Cond != 0xE)
443  return Result;
444  }
445  case ARM::t2ADDri:
446  case ARM::t2ADDri12:
447  case ARM::t2ADDrr:
448  case ARM::t2ADDrs:
449  case ARM::t2SUBri:
450  case ARM::t2SUBri12:
451  case ARM::t2SUBrr:
452  case ARM::t2SUBrs:
453  if (MI.getOperand(0).getReg() == ARM::SP &&
454  MI.getOperand(1).getReg() != ARM::SP)
456  return Result;
457  default: return Result;
458  }
459 }
460 
461 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
462  ArrayRef<uint8_t> Bytes,
463  uint64_t Address, raw_ostream &OS,
464  raw_ostream &CS) const {
465  CommentStream = &CS;
466 
467  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
468  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
469  "mode!");
470 
471  // We want to read exactly 4 bytes of data.
472  if (Bytes.size() < 4) {
473  Size = 0;
474  return MCDisassembler::Fail;
475  }
476 
477  // Encoded as a small-endian 32-bit word in the stream.
478  uint32_t Insn =
479  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
480 
481  // Calling the auto-generated decoder function.
482  DecodeStatus Result =
483  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
484  if (Result != MCDisassembler::Fail) {
485  Size = 4;
486  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
487  }
488 
489  struct DecodeTable {
490  const uint8_t *P;
491  bool DecodePred;
492  };
493 
494  const DecodeTable Tables[] = {
495  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
496  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
497  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
498  {DecoderTablev8Crypto32, false},
499  };
500 
501  for (auto Table : Tables) {
502  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
503  if (Result != MCDisassembler::Fail) {
504  Size = 4;
505  // Add a fake predicate operand, because we share these instruction
506  // definitions with Thumb2 where these instructions are predicable.
507  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
508  return MCDisassembler::Fail;
509  return Result;
510  }
511  }
512 
513  Result =
514  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
515  if (Result != MCDisassembler::Fail) {
516  Size = 4;
517  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
518  }
519 
520  Size = 4;
521  return MCDisassembler::Fail;
522 }
523 
524 namespace llvm {
525 
526 extern const MCInstrDesc ARMInsts[];
527 
528 } // end namespace llvm
529 
530 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
531 /// immediate Value in the MCInst. The immediate Value has had any PC
532 /// adjustment made by the caller. If the instruction is a branch instruction
533 /// then isBranch is true, else false. If the getOpInfo() function was set as
534 /// part of the setupForSymbolicDisassembly() call then that function is called
535 /// to get any symbolic information at the Address for this instruction. If
536 /// that returns non-zero then the symbolic information it returns is used to
537 /// create an MCExpr and that is added as an operand to the MCInst. If
538 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
539 /// Value is done and if a symbol is found an MCExpr is created with that, else
540 /// an MCExpr with Value is created. This function returns true if it adds an
541 /// operand to the MCInst and false otherwise.
542 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
543  bool isBranch, uint64_t InstSize,
544  MCInst &MI, const void *Decoder) {
545  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
546  // FIXME: Does it make sense for value to be negative?
547  return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
548  /* Offset */ 0, InstSize);
549 }
550 
551 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
552 /// referenced by a load instruction with the base register that is the Pc.
553 /// These can often be values in a literal pool near the Address of the
554 /// instruction. The Address of the instruction and its immediate Value are
555 /// used as a possible literal pool entry. The SymbolLookUp call back will
556 /// return the name of a symbol referenced by the literal pool's entry if
557 /// the referenced address is that of a symbol. Or it will return a pointer to
558 /// a literal 'C' string if the referenced address of the literal pool's entry
559 /// is an address into a section with 'C' string literals.
561  const void *Decoder) {
562  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
563  Dis->tryAddingPcLoadReferenceComment(Value, Address);
564 }
565 
566 // Thumb1 instructions don't have explicit S bits. Rather, they
567 // implicitly set CPSR. Since it's not represented in the encoding, the
568 // auto-generated decoder won't inject the CPSR operand. We need to fix
569 // that as a post-pass.
570 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
571  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
572  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
573  MCInst::iterator I = MI.begin();
574  for (unsigned i = 0; i < NumOps; ++i, ++I) {
575  if (I == MI.end()) break;
576  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
577  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
578  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
579  return;
580  }
581  }
582 
583  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
584 }
585 
586 // Most Thumb instructions don't have explicit predicates in the
587 // encoding, but rather get their predicates from IT context. We need
588 // to fix up the predicate operands using this context information as a
589 // post-pass.
591 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
593 
594  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
595 
596  // A few instructions actually have predicates encoded in them. Don't
597  // try to overwrite it if we're seeing one of those.
598  switch (MI.getOpcode()) {
599  case ARM::tBcc:
600  case ARM::t2Bcc:
601  case ARM::tCBZ:
602  case ARM::tCBNZ:
603  case ARM::tCPS:
604  case ARM::t2CPS3p:
605  case ARM::t2CPS2p:
606  case ARM::t2CPS1p:
607  case ARM::tMOVSr:
608  case ARM::tSETEND:
609  // Some instructions (mostly conditional branches) are not
610  // allowed in IT blocks.
611  if (ITBlock.instrInITBlock())
612  S = SoftFail;
613  else
614  return Success;
615  break;
616  case ARM::t2HINT:
617  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
618  S = SoftFail;
619  break;
620  case ARM::tB:
621  case ARM::t2B:
622  case ARM::t2TBB:
623  case ARM::t2TBH:
624  // Some instructions (mostly unconditional branches) can
625  // only appears at the end of, or outside of, an IT.
626  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
627  S = SoftFail;
628  break;
629  default:
630  break;
631  }
632 
633  // If we're in an IT block, base the predicate on that. Otherwise,
634  // assume a predicate of AL.
635  unsigned CC;
636  CC = ITBlock.getITCC();
637  if (CC == 0xF)
638  CC = ARMCC::AL;
639  if (ITBlock.instrInITBlock())
640  ITBlock.advanceITState();
641 
642  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
643  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
644  MCInst::iterator I = MI.begin();
645  for (unsigned i = 0; i < NumOps; ++i, ++I) {
646  if (I == MI.end()) break;
647  if (OpInfo[i].isPredicate()) {
648  if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
649  Check(S, SoftFail);
650  I = MI.insert(I, MCOperand::createImm(CC));
651  ++I;
652  if (CC == ARMCC::AL)
653  MI.insert(I, MCOperand::createReg(0));
654  else
655  MI.insert(I, MCOperand::createReg(ARM::CPSR));
656  return S;
657  }
658  }
659 
660  I = MI.insert(I, MCOperand::createImm(CC));
661  ++I;
662  if (CC == ARMCC::AL)
663  MI.insert(I, MCOperand::createReg(0));
664  else
665  MI.insert(I, MCOperand::createReg(ARM::CPSR));
666 
667  return S;
668 }
669 
670 // Thumb VFP instructions are a special case. Because we share their
671 // encodings between ARM and Thumb modes, and they are predicable in ARM
672 // mode, the auto-generated decoder will give them an (incorrect)
673 // predicate operand. We need to rewrite these operands based on the IT
674 // context as a post-pass.
675 void ThumbDisassembler::UpdateThumbVFPPredicate(
676  DecodeStatus &S, MCInst &MI) const {
677  unsigned CC;
678  CC = ITBlock.getITCC();
679  if (CC == 0xF)
680  CC = ARMCC::AL;
681  if (ITBlock.instrInITBlock())
682  ITBlock.advanceITState();
683 
684  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
685  MCInst::iterator I = MI.begin();
686  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
687  for (unsigned i = 0; i < NumOps; ++i, ++I) {
688  if (OpInfo[i].isPredicate() ) {
689  if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
690  Check(S, SoftFail);
691  I->setImm(CC);
692  ++I;
693  if (CC == ARMCC::AL)
694  I->setReg(0);
695  else
696  I->setReg(ARM::CPSR);
697  return;
698  }
699  }
700 }
701 
702 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
703  ArrayRef<uint8_t> Bytes,
704  uint64_t Address,
705  raw_ostream &OS,
706  raw_ostream &CS) const {
707  CommentStream = &CS;
708 
709  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
710  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
711 
712  // We want to read exactly 2 bytes of data.
713  if (Bytes.size() < 2) {
714  Size = 0;
715  return MCDisassembler::Fail;
716  }
717 
718  uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
719  DecodeStatus Result =
720  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
721  if (Result != MCDisassembler::Fail) {
722  Size = 2;
723  Check(Result, AddThumbPredicate(MI));
724  return Result;
725  }
726 
727  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
728  STI);
729  if (Result) {
730  Size = 2;
731  bool InITBlock = ITBlock.instrInITBlock();
732  Check(Result, AddThumbPredicate(MI));
733  AddThumb1SBit(MI, InITBlock);
734  return Result;
735  }
736 
737  Result =
738  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
739  if (Result != MCDisassembler::Fail) {
740  Size = 2;
741 
742  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
743  // the Thumb predicate.
744  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
745  Result = MCDisassembler::SoftFail;
746 
747  Check(Result, AddThumbPredicate(MI));
748 
749  // If we find an IT instruction, we need to parse its condition
750  // code and mask operands so that we can apply them correctly
751  // to the subsequent instructions.
752  if (MI.getOpcode() == ARM::t2IT) {
753  unsigned Firstcond = MI.getOperand(0).getImm();
754  unsigned Mask = MI.getOperand(1).getImm();
755  ITBlock.setITState(Firstcond, Mask);
756 
757  // An IT instruction that would give a 'NV' predicate is unpredictable.
758  if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
759  CS << "unpredictable IT predicate sequence";
760  }
761 
762  return Result;
763  }
764 
765  // We want to read exactly 4 bytes of data.
766  if (Bytes.size() < 4) {
767  Size = 0;
768  return MCDisassembler::Fail;
769  }
770 
771  uint32_t Insn32 =
772  (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
773  Result =
774  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
775  if (Result != MCDisassembler::Fail) {
776  Size = 4;
777  bool InITBlock = ITBlock.instrInITBlock();
778  Check(Result, AddThumbPredicate(MI));
779  AddThumb1SBit(MI, InITBlock);
780  return Result;
781  }
782 
783  Result =
784  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
785  if (Result != MCDisassembler::Fail) {
786  Size = 4;
787  Check(Result, AddThumbPredicate(MI));
788  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result);
789  }
790 
791  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
792  Result =
793  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
794  if (Result != MCDisassembler::Fail) {
795  Size = 4;
796  UpdateThumbVFPPredicate(Result, MI);
797  return Result;
798  }
799  }
800 
801  Result =
802  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
803  if (Result != MCDisassembler::Fail) {
804  Size = 4;
805  return Result;
806  }
807 
808  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
809  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
810  STI);
811  if (Result != MCDisassembler::Fail) {
812  Size = 4;
813  Check(Result, AddThumbPredicate(MI));
814  return Result;
815  }
816  }
817 
818  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
819  uint32_t NEONLdStInsn = Insn32;
820  NEONLdStInsn &= 0xF0FFFFFF;
821  NEONLdStInsn |= 0x04000000;
822  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
823  Address, this, STI);
824  if (Result != MCDisassembler::Fail) {
825  Size = 4;
826  Check(Result, AddThumbPredicate(MI));
827  return Result;
828  }
829  }
830 
831  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
832  uint32_t NEONDataInsn = Insn32;
833  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
834  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
835  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
836  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
837  Address, this, STI);
838  if (Result != MCDisassembler::Fail) {
839  Size = 4;
840  Check(Result, AddThumbPredicate(MI));
841  return Result;
842  }
843 
844  uint32_t NEONCryptoInsn = Insn32;
845  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
846  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
847  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
848  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
849  Address, this, STI);
850  if (Result != MCDisassembler::Fail) {
851  Size = 4;
852  return Result;
853  }
854 
855  uint32_t NEONv8Insn = Insn32;
856  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
857  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
858  this, STI);
859  if (Result != MCDisassembler::Fail) {
860  Size = 4;
861  return Result;
862  }
863  }
864 
865  Result =
866  decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
867  if (Result != MCDisassembler::Fail) {
868  Size = 4;
869  Check(Result, AddThumbPredicate(MI));
870  return Result;
871  }
872 
873  Size = 0;
874  return MCDisassembler::Fail;
875 }
876 
877 extern "C" void LLVMInitializeARMDisassembler() {
886 }
887 
888 static const uint16_t GPRDecoderTable[] = {
889  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
890  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
891  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
892  ARM::R12, ARM::SP, ARM::LR, ARM::PC
893 };
894 
895 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
896  uint64_t Address, const void *Decoder) {
897  if (RegNo > 15)
898  return MCDisassembler::Fail;
899 
900  unsigned Register = GPRDecoderTable[RegNo];
901  Inst.addOperand(MCOperand::createReg(Register));
903 }
904 
905 static DecodeStatus
906 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
907  uint64_t Address, const void *Decoder) {
909 
910  if (RegNo == 15)
912 
913  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
914 
915  return S;
916 }
917 
918 static DecodeStatus
920  uint64_t Address, const void *Decoder) {
922 
923  if (RegNo == 15)
924  {
925  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
927  }
928 
929  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
930  return S;
931 }
932 
933 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
934  uint64_t Address, const void *Decoder) {
935  if (RegNo > 7)
936  return MCDisassembler::Fail;
937  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
938 }
939 
940 static const uint16_t GPRPairDecoderTable[] = {
941  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
942  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
943 };
944 
945 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
946  uint64_t Address, const void *Decoder) {
948 
949  if (RegNo > 13)
950  return MCDisassembler::Fail;
951 
952  if ((RegNo & 1) || RegNo == 0xe)
954 
955  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
956  Inst.addOperand(MCOperand::createReg(RegisterPair));
957  return S;
958 }
959 
960 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
961  uint64_t Address, const void *Decoder) {
962  unsigned Register = 0;
963  switch (RegNo) {
964  case 0:
965  Register = ARM::R0;
966  break;
967  case 1:
968  Register = ARM::R1;
969  break;
970  case 2:
971  Register = ARM::R2;
972  break;
973  case 3:
974  Register = ARM::R3;
975  break;
976  case 9:
977  Register = ARM::R9;
978  break;
979  case 12:
980  Register = ARM::R12;
981  break;
982  default:
983  return MCDisassembler::Fail;
984  }
985 
986  Inst.addOperand(MCOperand::createReg(Register));
988 }
989 
990 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
991  uint64_t Address, const void *Decoder) {
993 
994  const FeatureBitset &featureBits =
995  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
996 
997  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
999 
1000  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1001  return S;
1002 }
1003 
1004 static const uint16_t SPRDecoderTable[] = {
1005  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1006  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1007  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1008  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1009  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1010  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1011  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1012  ARM::S28, ARM::S29, ARM::S30, ARM::S31
1013 };
1014 
1015 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1016  uint64_t Address, const void *Decoder) {
1017  if (RegNo > 31)
1018  return MCDisassembler::Fail;
1019 
1020  unsigned Register = SPRDecoderTable[RegNo];
1021  Inst.addOperand(MCOperand::createReg(Register));
1022  return MCDisassembler::Success;
1023 }
1024 
1025 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1026  uint64_t Address, const void *Decoder) {
1027  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1028 }
1029 
1030 static const uint16_t DPRDecoderTable[] = {
1031  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1032  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1033  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1034  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1035  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1036  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1037  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1038  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1039 };
1040 
1041 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1042  uint64_t Address, const void *Decoder) {
1043  const FeatureBitset &featureBits =
1044  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1045 
1046  bool hasD16 = featureBits[ARM::FeatureD16];
1047 
1048  if (RegNo > 31 || (hasD16 && RegNo > 15))
1049  return MCDisassembler::Fail;
1050 
1051  unsigned Register = DPRDecoderTable[RegNo];
1052  Inst.addOperand(MCOperand::createReg(Register));
1053  return MCDisassembler::Success;
1054 }
1055 
1056 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1057  uint64_t Address, const void *Decoder) {
1058  if (RegNo > 7)
1059  return MCDisassembler::Fail;
1060  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1061 }
1062 
1063 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1064  uint64_t Address, const void *Decoder) {
1065  if (RegNo > 15)
1066  return MCDisassembler::Fail;
1067  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1068 }
1069 
1070 static DecodeStatus
1071 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1072  uint64_t Address, const void *Decoder) {
1073  if (RegNo > 15)
1074  return MCDisassembler::Fail;
1075  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1076 }
1077 
1078 static const uint16_t QPRDecoderTable[] = {
1079  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1080  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1081  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1082  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1083 };
1084 
1085 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1086  uint64_t Address, const void *Decoder) {
1087  if (RegNo > 31 || (RegNo & 1) != 0)
1088  return MCDisassembler::Fail;
1089  RegNo >>= 1;
1090 
1091  unsigned Register = QPRDecoderTable[RegNo];
1092  Inst.addOperand(MCOperand::createReg(Register));
1093  return MCDisassembler::Success;
1094 }
1095 
1096 static const uint16_t DPairDecoderTable[] = {
1097  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1098  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1099  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1100  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1101  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1102  ARM::Q15
1103 };
1104 
1105 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1106  uint64_t Address, const void *Decoder) {
1107  if (RegNo > 30)
1108  return MCDisassembler::Fail;
1109 
1110  unsigned Register = DPairDecoderTable[RegNo];
1111  Inst.addOperand(MCOperand::createReg(Register));
1112  return MCDisassembler::Success;
1113 }
1114 
1115 static const uint16_t DPairSpacedDecoderTable[] = {
1116  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1117  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1118  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1119  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1120  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1121  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1122  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1123  ARM::D28_D30, ARM::D29_D31
1124 };
1125 
1127  unsigned RegNo,
1128  uint64_t Address,
1129  const void *Decoder) {
1130  if (RegNo > 29)
1131  return MCDisassembler::Fail;
1132 
1133  unsigned Register = DPairSpacedDecoderTable[RegNo];
1134  Inst.addOperand(MCOperand::createReg(Register));
1135  return MCDisassembler::Success;
1136 }
1137 
1138 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1139  uint64_t Address, const void *Decoder) {
1141  if (Val == 0xF) return MCDisassembler::Fail;
1142  // AL predicate is not allowed on Thumb1 branches.
1143  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1144  return MCDisassembler::Fail;
1145  if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1147  Inst.addOperand(MCOperand::createImm(Val));
1148  if (Val == ARMCC::AL) {
1150  } else
1151  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1152  return S;
1153 }
1154 
1155 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1156  uint64_t Address, const void *Decoder) {
1157  if (Val)
1158  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1159  else
1161  return MCDisassembler::Success;
1162 }
1163 
1164 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1165  uint64_t Address, const void *Decoder) {
1167 
1168  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1169  unsigned type = fieldFromInstruction(Val, 5, 2);
1170  unsigned imm = fieldFromInstruction(Val, 7, 5);
1171 
1172  // Register-immediate
1173  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1174  return MCDisassembler::Fail;
1175 
1176  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1177  switch (type) {
1178  case 0:
1179  Shift = ARM_AM::lsl;
1180  break;
1181  case 1:
1182  Shift = ARM_AM::lsr;
1183  break;
1184  case 2:
1185  Shift = ARM_AM::asr;
1186  break;
1187  case 3:
1188  Shift = ARM_AM::ror;
1189  break;
1190  }
1191 
1192  if (Shift == ARM_AM::ror && imm == 0)
1193  Shift = ARM_AM::rrx;
1194 
1195  unsigned Op = Shift | (imm << 3);
1196  Inst.addOperand(MCOperand::createImm(Op));
1197 
1198  return S;
1199 }
1200 
1201 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1202  uint64_t Address, const void *Decoder) {
1204 
1205  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1206  unsigned type = fieldFromInstruction(Val, 5, 2);
1207  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1208 
1209  // Register-register
1210  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1211  return MCDisassembler::Fail;
1212  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1213  return MCDisassembler::Fail;
1214 
1215  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1216  switch (type) {
1217  case 0:
1218  Shift = ARM_AM::lsl;
1219  break;
1220  case 1:
1221  Shift = ARM_AM::lsr;
1222  break;
1223  case 2:
1224  Shift = ARM_AM::asr;
1225  break;
1226  case 3:
1227  Shift = ARM_AM::ror;
1228  break;
1229  }
1230 
1231  Inst.addOperand(MCOperand::createImm(Shift));
1232 
1233  return S;
1234 }
1235 
1236 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1237  uint64_t Address, const void *Decoder) {
1239 
1240  bool NeedDisjointWriteback = false;
1241  unsigned WritebackReg = 0;
1242  switch (Inst.getOpcode()) {
1243  default:
1244  break;
1245  case ARM::LDMIA_UPD:
1246  case ARM::LDMDB_UPD:
1247  case ARM::LDMIB_UPD:
1248  case ARM::LDMDA_UPD:
1249  case ARM::t2LDMIA_UPD:
1250  case ARM::t2LDMDB_UPD:
1251  case ARM::t2STMIA_UPD:
1252  case ARM::t2STMDB_UPD:
1253  NeedDisjointWriteback = true;
1254  WritebackReg = Inst.getOperand(0).getReg();
1255  break;
1256  }
1257 
1258  // Empty register lists are not allowed.
1259  if (Val == 0) return MCDisassembler::Fail;
1260  for (unsigned i = 0; i < 16; ++i) {
1261  if (Val & (1 << i)) {
1262  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1263  return MCDisassembler::Fail;
1264  // Writeback not allowed if Rn is in the target list.
1265  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1267  }
1268  }
1269 
1270  return S;
1271 }
1272 
1273 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1274  uint64_t Address, const void *Decoder) {
1276 
1277  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1278  unsigned regs = fieldFromInstruction(Val, 0, 8);
1279 
1280  // In case of unpredictable encoding, tweak the operands.
1281  if (regs == 0 || (Vd + regs) > 32) {
1282  regs = Vd + regs > 32 ? 32 - Vd : regs;
1283  regs = std::max( 1u, regs);
1285  }
1286 
1287  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1288  return MCDisassembler::Fail;
1289  for (unsigned i = 0; i < (regs - 1); ++i) {
1290  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1291  return MCDisassembler::Fail;
1292  }
1293 
1294  return S;
1295 }
1296 
1297 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1298  uint64_t Address, const void *Decoder) {
1300 
1301  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1302  unsigned regs = fieldFromInstruction(Val, 1, 7);
1303 
1304  // In case of unpredictable encoding, tweak the operands.
1305  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1306  regs = Vd + regs > 32 ? 32 - Vd : regs;
1307  regs = std::max( 1u, regs);
1308  regs = std::min(16u, regs);
1310  }
1311 
1312  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1313  return MCDisassembler::Fail;
1314  for (unsigned i = 0; i < (regs - 1); ++i) {
1315  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1316  return MCDisassembler::Fail;
1317  }
1318 
1319  return S;
1320 }
1321 
1322 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1323  uint64_t Address, const void *Decoder) {
1324  // This operand encodes a mask of contiguous zeros between a specified MSB
1325  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1326  // the mask of all bits LSB-and-lower, and then xor them to create
1327  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1328  // create the final mask.
1329  unsigned msb = fieldFromInstruction(Val, 5, 5);
1330  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1331 
1333  if (lsb > msb) {
1335  // The check above will cause the warning for the "potentially undefined
1336  // instruction encoding" but we can't build a bad MCOperand value here
1337  // with a lsb > msb or else printing the MCInst will cause a crash.
1338  lsb = msb;
1339  }
1340 
1341  uint32_t msb_mask = 0xFFFFFFFF;
1342  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1343  uint32_t lsb_mask = (1U << lsb) - 1;
1344 
1345  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1346  return S;
1347 }
1348 
1349 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1350  uint64_t Address, const void *Decoder) {
1352 
1353  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1354  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1355  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1356  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1357  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1358  unsigned U = fieldFromInstruction(Insn, 23, 1);
1359 
1360  switch (Inst.getOpcode()) {
1361  case ARM::LDC_OFFSET:
1362  case ARM::LDC_PRE:
1363  case ARM::LDC_POST:
1364  case ARM::LDC_OPTION:
1365  case ARM::LDCL_OFFSET:
1366  case ARM::LDCL_PRE:
1367  case ARM::LDCL_POST:
1368  case ARM::LDCL_OPTION:
1369  case ARM::STC_OFFSET:
1370  case ARM::STC_PRE:
1371  case ARM::STC_POST:
1372  case ARM::STC_OPTION:
1373  case ARM::STCL_OFFSET:
1374  case ARM::STCL_PRE:
1375  case ARM::STCL_POST:
1376  case ARM::STCL_OPTION:
1377  case ARM::t2LDC_OFFSET:
1378  case ARM::t2LDC_PRE:
1379  case ARM::t2LDC_POST:
1380  case ARM::t2LDC_OPTION:
1381  case ARM::t2LDCL_OFFSET:
1382  case ARM::t2LDCL_PRE:
1383  case ARM::t2LDCL_POST:
1384  case ARM::t2LDCL_OPTION:
1385  case ARM::t2STC_OFFSET:
1386  case ARM::t2STC_PRE:
1387  case ARM::t2STC_POST:
1388  case ARM::t2STC_OPTION:
1389  case ARM::t2STCL_OFFSET:
1390  case ARM::t2STCL_PRE:
1391  case ARM::t2STCL_POST:
1392  case ARM::t2STCL_OPTION:
1393  if (coproc == 0xA || coproc == 0xB)
1394  return MCDisassembler::Fail;
1395  break;
1396  default:
1397  break;
1398  }
1399 
1400  const FeatureBitset &featureBits =
1401  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1402  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1403  return MCDisassembler::Fail;
1404 
1405  Inst.addOperand(MCOperand::createImm(coproc));
1406  Inst.addOperand(MCOperand::createImm(CRd));
1407  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1408  return MCDisassembler::Fail;
1409 
1410  switch (Inst.getOpcode()) {
1411  case ARM::t2LDC2_OFFSET:
1412  case ARM::t2LDC2L_OFFSET:
1413  case ARM::t2LDC2_PRE:
1414  case ARM::t2LDC2L_PRE:
1415  case ARM::t2STC2_OFFSET:
1416  case ARM::t2STC2L_OFFSET:
1417  case ARM::t2STC2_PRE:
1418  case ARM::t2STC2L_PRE:
1419  case ARM::LDC2_OFFSET:
1420  case ARM::LDC2L_OFFSET:
1421  case ARM::LDC2_PRE:
1422  case ARM::LDC2L_PRE:
1423  case ARM::STC2_OFFSET:
1424  case ARM::STC2L_OFFSET:
1425  case ARM::STC2_PRE:
1426  case ARM::STC2L_PRE:
1427  case ARM::t2LDC_OFFSET:
1428  case ARM::t2LDCL_OFFSET:
1429  case ARM::t2LDC_PRE:
1430  case ARM::t2LDCL_PRE:
1431  case ARM::t2STC_OFFSET:
1432  case ARM::t2STCL_OFFSET:
1433  case ARM::t2STC_PRE:
1434  case ARM::t2STCL_PRE:
1435  case ARM::LDC_OFFSET:
1436  case ARM::LDCL_OFFSET:
1437  case ARM::LDC_PRE:
1438  case ARM::LDCL_PRE:
1439  case ARM::STC_OFFSET:
1440  case ARM::STCL_OFFSET:
1441  case ARM::STC_PRE:
1442  case ARM::STCL_PRE:
1443  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1444  Inst.addOperand(MCOperand::createImm(imm));
1445  break;
1446  case ARM::t2LDC2_POST:
1447  case ARM::t2LDC2L_POST:
1448  case ARM::t2STC2_POST:
1449  case ARM::t2STC2L_POST:
1450  case ARM::LDC2_POST:
1451  case ARM::LDC2L_POST:
1452  case ARM::STC2_POST:
1453  case ARM::STC2L_POST:
1454  case ARM::t2LDC_POST:
1455  case ARM::t2LDCL_POST:
1456  case ARM::t2STC_POST:
1457  case ARM::t2STCL_POST:
1458  case ARM::LDC_POST:
1459  case ARM::LDCL_POST:
1460  case ARM::STC_POST:
1461  case ARM::STCL_POST:
1462  imm |= U << 8;
1464  default:
1465  // The 'option' variant doesn't encode 'U' in the immediate since
1466  // the immediate is unsigned [0,255].
1467  Inst.addOperand(MCOperand::createImm(imm));
1468  break;
1469  }
1470 
1471  switch (Inst.getOpcode()) {
1472  case ARM::LDC_OFFSET:
1473  case ARM::LDC_PRE:
1474  case ARM::LDC_POST:
1475  case ARM::LDC_OPTION:
1476  case ARM::LDCL_OFFSET:
1477  case ARM::LDCL_PRE:
1478  case ARM::LDCL_POST:
1479  case ARM::LDCL_OPTION:
1480  case ARM::STC_OFFSET:
1481  case ARM::STC_PRE:
1482  case ARM::STC_POST:
1483  case ARM::STC_OPTION:
1484  case ARM::STCL_OFFSET:
1485  case ARM::STCL_PRE:
1486  case ARM::STCL_POST:
1487  case ARM::STCL_OPTION:
1488  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1489  return MCDisassembler::Fail;
1490  break;
1491  default:
1492  break;
1493  }
1494 
1495  return S;
1496 }
1497 
1498 static DecodeStatus
1500  uint64_t Address, const void *Decoder) {
1502 
1503  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1504  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1505  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1506  unsigned imm = fieldFromInstruction(Insn, 0, 12);
1507  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1508  unsigned reg = fieldFromInstruction(Insn, 25, 1);
1509  unsigned P = fieldFromInstruction(Insn, 24, 1);
1510  unsigned W = fieldFromInstruction(Insn, 21, 1);
1511 
1512  // On stores, the writeback operand precedes Rt.
1513  switch (Inst.getOpcode()) {
1514  case ARM::STR_POST_IMM:
1515  case ARM::STR_POST_REG:
1516  case ARM::STRB_POST_IMM:
1517  case ARM::STRB_POST_REG:
1518  case ARM::STRT_POST_REG:
1519  case ARM::STRT_POST_IMM:
1520  case ARM::STRBT_POST_REG:
1521  case ARM::STRBT_POST_IMM:
1522  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1523  return MCDisassembler::Fail;
1524  break;
1525  default:
1526  break;
1527  }
1528 
1529  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1530  return MCDisassembler::Fail;
1531 
1532  // On loads, the writeback operand comes after Rt.
1533  switch (Inst.getOpcode()) {
1534  case ARM::LDR_POST_IMM:
1535  case ARM::LDR_POST_REG:
1536  case ARM::LDRB_POST_IMM:
1537  case ARM::LDRB_POST_REG:
1538  case ARM::LDRBT_POST_REG:
1539  case ARM::LDRBT_POST_IMM:
1540  case ARM::LDRT_POST_REG:
1541  case ARM::LDRT_POST_IMM:
1542  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1543  return MCDisassembler::Fail;
1544  break;
1545  default:
1546  break;
1547  }
1548 
1549  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1550  return MCDisassembler::Fail;
1551 
1553  if (!fieldFromInstruction(Insn, 23, 1))
1554  Op = ARM_AM::sub;
1555 
1556  bool writeback = (P == 0) || (W == 1);
1557  unsigned idx_mode = 0;
1558  if (P && writeback)
1559  idx_mode = ARMII::IndexModePre;
1560  else if (!P && writeback)
1561  idx_mode = ARMII::IndexModePost;
1562 
1563  if (writeback && (Rn == 15 || Rn == Rt))
1564  S = MCDisassembler::SoftFail; // UNPREDICTABLE
1565 
1566  if (reg) {
1567  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1568  return MCDisassembler::Fail;
1570  switch( fieldFromInstruction(Insn, 5, 2)) {
1571  case 0:
1572  Opc = ARM_AM::lsl;
1573  break;
1574  case 1:
1575  Opc = ARM_AM::lsr;
1576  break;
1577  case 2:
1578  Opc = ARM_AM::asr;
1579  break;
1580  case 3:
1581  Opc = ARM_AM::ror;
1582  break;
1583  default:
1584  return MCDisassembler::Fail;
1585  }
1586  unsigned amt = fieldFromInstruction(Insn, 7, 5);
1587  if (Opc == ARM_AM::ror && amt == 0)
1588  Opc = ARM_AM::rrx;
1589  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1590 
1591  Inst.addOperand(MCOperand::createImm(imm));
1592  } else {
1594  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1595  Inst.addOperand(MCOperand::createImm(tmp));
1596  }
1597 
1598  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1599  return MCDisassembler::Fail;
1600 
1601  return S;
1602 }
1603 
1604 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1605  uint64_t Address, const void *Decoder) {
1607 
1608  unsigned Rn = fieldFromInstruction(Val, 13, 4);
1609  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1610  unsigned type = fieldFromInstruction(Val, 5, 2);
1611  unsigned imm = fieldFromInstruction(Val, 7, 5);
1612  unsigned U = fieldFromInstruction(Val, 12, 1);
1613 
1615  switch (type) {
1616  case 0:
1617  ShOp = ARM_AM::lsl;
1618  break;
1619  case 1:
1620  ShOp = ARM_AM::lsr;
1621  break;
1622  case 2:
1623  ShOp = ARM_AM::asr;
1624  break;
1625  case 3:
1626  ShOp = ARM_AM::ror;
1627  break;
1628  }
1629 
1630  if (ShOp == ARM_AM::ror && imm == 0)
1631  ShOp = ARM_AM::rrx;
1632 
1633  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1634  return MCDisassembler::Fail;
1635  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1636  return MCDisassembler::Fail;
1637  unsigned shift;
1638  if (U)
1639  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1640  else
1641  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1642  Inst.addOperand(MCOperand::createImm(shift));
1643 
1644  return S;
1645 }
1646 
1647 static DecodeStatus
1648 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1649  uint64_t Address, const void *Decoder) {
1651 
1652  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1653  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1654  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1655  unsigned type = fieldFromInstruction(Insn, 22, 1);
1656  unsigned imm = fieldFromInstruction(Insn, 8, 4);
1657  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1658  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1659  unsigned W = fieldFromInstruction(Insn, 21, 1);
1660  unsigned P = fieldFromInstruction(Insn, 24, 1);
1661  unsigned Rt2 = Rt + 1;
1662 
1663  bool writeback = (W == 1) | (P == 0);
1664 
1665  // For {LD,ST}RD, Rt must be even, else undefined.
1666  switch (Inst.getOpcode()) {
1667  case ARM::STRD:
1668  case ARM::STRD_PRE:
1669  case ARM::STRD_POST:
1670  case ARM::LDRD:
1671  case ARM::LDRD_PRE:
1672  case ARM::LDRD_POST:
1673  if (Rt & 0x1) S = MCDisassembler::SoftFail;
1674  break;
1675  default:
1676  break;
1677  }
1678  switch (Inst.getOpcode()) {
1679  case ARM::STRD:
1680  case ARM::STRD_PRE:
1681  case ARM::STRD_POST:
1682  if (P == 0 && W == 1)
1684 
1685  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1687  if (type && Rm == 15)
1689  if (Rt2 == 15)
1691  if (!type && fieldFromInstruction(Insn, 8, 4))
1693  break;
1694  case ARM::STRH:
1695  case ARM::STRH_PRE:
1696  case ARM::STRH_POST:
1697  if (Rt == 15)
1699  if (writeback && (Rn == 15 || Rn == Rt))
1701  if (!type && Rm == 15)
1703  break;
1704  case ARM::LDRD:
1705  case ARM::LDRD_PRE:
1706  case ARM::LDRD_POST:
1707  if (type && Rn == 15) {
1708  if (Rt2 == 15)
1710  break;
1711  }
1712  if (P == 0 && W == 1)
1714  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1716  if (!type && writeback && Rn == 15)
1718  if (writeback && (Rn == Rt || Rn == Rt2))
1720  break;
1721  case ARM::LDRH:
1722  case ARM::LDRH_PRE:
1723  case ARM::LDRH_POST:
1724  if (type && Rn == 15) {
1725  if (Rt == 15)
1727  break;
1728  }
1729  if (Rt == 15)
1731  if (!type && Rm == 15)
1733  if (!type && writeback && (Rn == 15 || Rn == Rt))
1735  break;
1736  case ARM::LDRSH:
1737  case ARM::LDRSH_PRE:
1738  case ARM::LDRSH_POST:
1739  case ARM::LDRSB:
1740  case ARM::LDRSB_PRE:
1741  case ARM::LDRSB_POST:
1742  if (type && Rn == 15) {
1743  if (Rt == 15)
1745  break;
1746  }
1747  if (type && (Rt == 15 || (writeback && Rn == Rt)))
1749  if (!type && (Rt == 15 || Rm == 15))
1751  if (!type && writeback && (Rn == 15 || Rn == Rt))
1753  break;
1754  default:
1755  break;
1756  }
1757 
1758  if (writeback) { // Writeback
1759  if (P)
1760  U |= ARMII::IndexModePre << 9;
1761  else
1762  U |= ARMII::IndexModePost << 9;
1763 
1764  // On stores, the writeback operand precedes Rt.
1765  switch (Inst.getOpcode()) {
1766  case ARM::STRD:
1767  case ARM::STRD_PRE:
1768  case ARM::STRD_POST:
1769  case ARM::STRH:
1770  case ARM::STRH_PRE:
1771  case ARM::STRH_POST:
1772  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1773  return MCDisassembler::Fail;
1774  break;
1775  default:
1776  break;
1777  }
1778  }
1779 
1780  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1781  return MCDisassembler::Fail;
1782  switch (Inst.getOpcode()) {
1783  case ARM::STRD:
1784  case ARM::STRD_PRE:
1785  case ARM::STRD_POST:
1786  case ARM::LDRD:
1787  case ARM::LDRD_PRE:
1788  case ARM::LDRD_POST:
1789  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1790  return MCDisassembler::Fail;
1791  break;
1792  default:
1793  break;
1794  }
1795 
1796  if (writeback) {
1797  // On loads, the writeback operand comes after Rt.
1798  switch (Inst.getOpcode()) {
1799  case ARM::LDRD:
1800  case ARM::LDRD_PRE:
1801  case ARM::LDRD_POST:
1802  case ARM::LDRH:
1803  case ARM::LDRH_PRE:
1804  case ARM::LDRH_POST:
1805  case ARM::LDRSH:
1806  case ARM::LDRSH_PRE:
1807  case ARM::LDRSH_POST:
1808  case ARM::LDRSB:
1809  case ARM::LDRSB_PRE:
1810  case ARM::LDRSB_POST:
1811  case ARM::LDRHTr:
1812  case ARM::LDRSBTr:
1813  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1814  return MCDisassembler::Fail;
1815  break;
1816  default:
1817  break;
1818  }
1819  }
1820 
1821  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1822  return MCDisassembler::Fail;
1823 
1824  if (type) {
1826  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1827  } else {
1828  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1829  return MCDisassembler::Fail;
1831  }
1832 
1833  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1834  return MCDisassembler::Fail;
1835 
1836  return S;
1837 }
1838 
1839 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1840  uint64_t Address, const void *Decoder) {
1842 
1843  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1844  unsigned mode = fieldFromInstruction(Insn, 23, 2);
1845 
1846  switch (mode) {
1847  case 0:
1848  mode = ARM_AM::da;
1849  break;
1850  case 1:
1851  mode = ARM_AM::ia;
1852  break;
1853  case 2:
1854  mode = ARM_AM::db;
1855  break;
1856  case 3:
1857  mode = ARM_AM::ib;
1858  break;
1859  }
1860 
1861  Inst.addOperand(MCOperand::createImm(mode));
1862  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1863  return MCDisassembler::Fail;
1864 
1865  return S;
1866 }
1867 
1868 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1869  uint64_t Address, const void *Decoder) {
1871 
1872  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1873  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1874  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1875  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1876 
1877  if (pred == 0xF)
1878  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1879 
1880  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1881  return MCDisassembler::Fail;
1882  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1883  return MCDisassembler::Fail;
1884  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1885  return MCDisassembler::Fail;
1886  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1887  return MCDisassembler::Fail;
1888  return S;
1889 }
1890 
1892  unsigned Insn,
1893  uint64_t Address, const void *Decoder) {
1895 
1896  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1897  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1898  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1899 
1900  if (pred == 0xF) {
1901  // Ambiguous with RFE and SRS
1902  switch (Inst.getOpcode()) {
1903  case ARM::LDMDA:
1904  Inst.setOpcode(ARM::RFEDA);
1905  break;
1906  case ARM::LDMDA_UPD:
1907  Inst.setOpcode(ARM::RFEDA_UPD);
1908  break;
1909  case ARM::LDMDB:
1910  Inst.setOpcode(ARM::RFEDB);
1911  break;
1912  case ARM::LDMDB_UPD:
1913  Inst.setOpcode(ARM::RFEDB_UPD);
1914  break;
1915  case ARM::LDMIA:
1916  Inst.setOpcode(ARM::RFEIA);
1917  break;
1918  case ARM::LDMIA_UPD:
1919  Inst.setOpcode(ARM::RFEIA_UPD);
1920  break;
1921  case ARM::LDMIB:
1922  Inst.setOpcode(ARM::RFEIB);
1923  break;
1924  case ARM::LDMIB_UPD:
1925  Inst.setOpcode(ARM::RFEIB_UPD);
1926  break;
1927  case ARM::STMDA:
1928  Inst.setOpcode(ARM::SRSDA);
1929  break;
1930  case ARM::STMDA_UPD:
1931  Inst.setOpcode(ARM::SRSDA_UPD);
1932  break;
1933  case ARM::STMDB:
1934  Inst.setOpcode(ARM::SRSDB);
1935  break;
1936  case ARM::STMDB_UPD:
1937  Inst.setOpcode(ARM::SRSDB_UPD);
1938  break;
1939  case ARM::STMIA:
1940  Inst.setOpcode(ARM::SRSIA);
1941  break;
1942  case ARM::STMIA_UPD:
1943  Inst.setOpcode(ARM::SRSIA_UPD);
1944  break;
1945  case ARM::STMIB:
1946  Inst.setOpcode(ARM::SRSIB);
1947  break;
1948  case ARM::STMIB_UPD:
1949  Inst.setOpcode(ARM::SRSIB_UPD);
1950  break;
1951  default:
1952  return MCDisassembler::Fail;
1953  }
1954 
1955  // For stores (which become SRS's, the only operand is the mode.
1956  if (fieldFromInstruction(Insn, 20, 1) == 0) {
1957  // Check SRS encoding constraints
1958  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1959  fieldFromInstruction(Insn, 20, 1) == 0))
1960  return MCDisassembler::Fail;
1961 
1962  Inst.addOperand(
1963  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1964  return S;
1965  }
1966 
1967  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1968  }
1969 
1970  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1971  return MCDisassembler::Fail;
1972  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1973  return MCDisassembler::Fail; // Tied
1974  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1975  return MCDisassembler::Fail;
1976  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1977  return MCDisassembler::Fail;
1978 
1979  return S;
1980 }
1981 
1982 // Check for UNPREDICTABLE predicated ESB instruction
1983 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1984  uint64_t Address, const void *Decoder) {
1985  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1986  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1987  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1988  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1989 
1991 
1992  Inst.addOperand(MCOperand::createImm(imm8));
1993 
1994  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1995  return MCDisassembler::Fail;
1996 
1997  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1998  // so all predicates should be allowed.
1999  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2001 
2002  return S;
2003 }
2004 
2005 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2006  uint64_t Address, const void *Decoder) {
2007  unsigned imod = fieldFromInstruction(Insn, 18, 2);
2008  unsigned M = fieldFromInstruction(Insn, 17, 1);
2009  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2010  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2011 
2013 
2014  // This decoder is called from multiple location that do not check
2015  // the full encoding is valid before they do.
2016  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2017  fieldFromInstruction(Insn, 16, 1) != 0 ||
2018  fieldFromInstruction(Insn, 20, 8) != 0x10)
2019  return MCDisassembler::Fail;
2020 
2021  // imod == '01' --> UNPREDICTABLE
2022  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2023  // return failure here. The '01' imod value is unprintable, so there's
2024  // nothing useful we could do even if we returned UNPREDICTABLE.
2025 
2026  if (imod == 1) return MCDisassembler::Fail;
2027 
2028  if (imod && M) {
2029  Inst.setOpcode(ARM::CPS3p);
2030  Inst.addOperand(MCOperand::createImm(imod));
2031  Inst.addOperand(MCOperand::createImm(iflags));
2032  Inst.addOperand(MCOperand::createImm(mode));
2033  } else if (imod && !M) {
2034  Inst.setOpcode(ARM::CPS2p);
2035  Inst.addOperand(MCOperand::createImm(imod));
2036  Inst.addOperand(MCOperand::createImm(iflags));
2037  if (mode) S = MCDisassembler::SoftFail;
2038  } else if (!imod && M) {
2039  Inst.setOpcode(ARM::CPS1p);
2040  Inst.addOperand(MCOperand::createImm(mode));
2041  if (iflags) S = MCDisassembler::SoftFail;
2042  } else {
2043  // imod == '00' && M == '0' --> UNPREDICTABLE
2044  Inst.setOpcode(ARM::CPS1p);
2045  Inst.addOperand(MCOperand::createImm(mode));
2047  }
2048 
2049  return S;
2050 }
2051 
2052 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2053  uint64_t Address, const void *Decoder) {
2054  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2055  unsigned M = fieldFromInstruction(Insn, 8, 1);
2056  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2057  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2058 
2060 
2061  // imod == '01' --> UNPREDICTABLE
2062  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2063  // return failure here. The '01' imod value is unprintable, so there's
2064  // nothing useful we could do even if we returned UNPREDICTABLE.
2065 
2066  if (imod == 1) return MCDisassembler::Fail;
2067 
2068  if (imod && M) {
2069  Inst.setOpcode(ARM::t2CPS3p);
2070  Inst.addOperand(MCOperand::createImm(imod));
2071  Inst.addOperand(MCOperand::createImm(iflags));
2072  Inst.addOperand(MCOperand::createImm(mode));
2073  } else if (imod && !M) {
2074  Inst.setOpcode(ARM::t2CPS2p);
2075  Inst.addOperand(MCOperand::createImm(imod));
2076  Inst.addOperand(MCOperand::createImm(iflags));
2077  if (mode) S = MCDisassembler::SoftFail;
2078  } else if (!imod && M) {
2079  Inst.setOpcode(ARM::t2CPS1p);
2080  Inst.addOperand(MCOperand::createImm(mode));
2081  if (iflags) S = MCDisassembler::SoftFail;
2082  } else {
2083  // imod == '00' && M == '0' --> this is a HINT instruction
2084  int imm = fieldFromInstruction(Insn, 0, 8);
2085  // HINT are defined only for immediate in [0..4]
2086  if(imm > 4) return MCDisassembler::Fail;
2087  Inst.setOpcode(ARM::t2HINT);
2088  Inst.addOperand(MCOperand::createImm(imm));
2089  }
2090 
2091  return S;
2092 }
2093 
2094 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2095  uint64_t Address, const void *Decoder) {
2097 
2098  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2099  unsigned imm = 0;
2100 
2101  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2102  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2103  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2104  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2105 
2106  if (Inst.getOpcode() == ARM::t2MOVTi16)
2107  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2108  return MCDisassembler::Fail;
2109  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2110  return MCDisassembler::Fail;
2111 
2112  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2113  Inst.addOperand(MCOperand::createImm(imm));
2114 
2115  return S;
2116 }
2117 
2118 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2119  uint64_t Address, const void *Decoder) {
2121 
2122  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2123  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2124  unsigned imm = 0;
2125 
2126  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2127  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2128 
2129  if (Inst.getOpcode() == ARM::MOVTi16)
2130  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2131  return MCDisassembler::Fail;
2132 
2133  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2134  return MCDisassembler::Fail;
2135 
2136  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2137  Inst.addOperand(MCOperand::createImm(imm));
2138 
2139  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2140  return MCDisassembler::Fail;
2141 
2142  return S;
2143 }
2144 
2145 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2146  uint64_t Address, const void *Decoder) {
2148 
2149  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2150  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2151  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2152  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2153  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2154 
2155  if (pred == 0xF)
2156  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2157 
2158  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2159  return MCDisassembler::Fail;
2160  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2161  return MCDisassembler::Fail;
2162  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2163  return MCDisassembler::Fail;
2164  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2165  return MCDisassembler::Fail;
2166 
2167  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2168  return MCDisassembler::Fail;
2169 
2170  return S;
2171 }
2172 
2173 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2174  uint64_t Address, const void *Decoder) {
2176 
2177  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2178  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2179  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2180 
2181  if (Pred == 0xF)
2182  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2183 
2184  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2185  return MCDisassembler::Fail;
2186  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2187  return MCDisassembler::Fail;
2188  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2189  return MCDisassembler::Fail;
2190 
2191  return S;
2192 }
2193 
2194 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2195  uint64_t Address, const void *Decoder) {
2197 
2198  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2199 
2200  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2201  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2202 
2203  if (!FeatureBits[ARM::HasV8_1aOps] ||
2204  !FeatureBits[ARM::HasV8Ops])
2205  return MCDisassembler::Fail;
2206 
2207  // Decoder can be called from DecodeTST, which does not check the full
2208  // encoding is valid.
2209  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2210  fieldFromInstruction(Insn, 4,4) != 0)
2211  return MCDisassembler::Fail;
2212  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2213  fieldFromInstruction(Insn, 0,4) != 0)
2215 
2216  Inst.setOpcode(ARM::SETPAN);
2217  Inst.addOperand(MCOperand::createImm(Imm));
2218 
2219  return S;
2220 }
2221 
2223  uint64_t Address, const void *Decoder) {
2225 
2226  unsigned add = fieldFromInstruction(Val, 12, 1);
2227  unsigned imm = fieldFromInstruction(Val, 0, 12);
2228  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2229 
2230  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2231  return MCDisassembler::Fail;
2232 
2233  if (!add) imm *= -1;
2234  if (imm == 0 && !add) imm = INT32_MIN;
2235  Inst.addOperand(MCOperand::createImm(imm));
2236  if (Rn == 15)
2237  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2238 
2239  return S;
2240 }
2241 
2242 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2243  uint64_t Address, const void *Decoder) {
2245 
2246  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2247  // U == 1 to add imm, 0 to subtract it.
2248  unsigned U = fieldFromInstruction(Val, 8, 1);
2249  unsigned imm = fieldFromInstruction(Val, 0, 8);
2250 
2251  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2252  return MCDisassembler::Fail;
2253 
2254  if (U)
2256  else
2258 
2259  return S;
2260 }
2261 
2263  uint64_t Address, const void *Decoder) {
2265 
2266  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2267  // U == 1 to add imm, 0 to subtract it.
2268  unsigned U = fieldFromInstruction(Val, 8, 1);
2269  unsigned imm = fieldFromInstruction(Val, 0, 8);
2270 
2271  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2272  return MCDisassembler::Fail;
2273 
2274  if (U)
2276  else
2278 
2279  return S;
2280 }
2281 
2282 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2283  uint64_t Address, const void *Decoder) {
2284  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2285 }
2286 
2287 static DecodeStatus
2288 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2289  uint64_t Address, const void *Decoder) {
2291 
2292  // Note the J1 and J2 values are from the encoded instruction. So here
2293  // change them to I1 and I2 values via as documented:
2294  // I1 = NOT(J1 EOR S);
2295  // I2 = NOT(J2 EOR S);
2296  // and build the imm32 with one trailing zero as documented:
2297  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2298  unsigned S = fieldFromInstruction(Insn, 26, 1);
2299  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2300  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2301  unsigned I1 = !(J1 ^ S);
2302  unsigned I2 = !(J2 ^ S);
2303  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2304  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2305  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2306  int imm32 = SignExtend32<25>(tmp << 1);
2307  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2308  true, 4, Inst, Decoder))
2309  Inst.addOperand(MCOperand::createImm(imm32));
2310 
2311  return Status;
2312 }
2313 
2314 static DecodeStatus
2315 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2316  uint64_t Address, const void *Decoder) {
2318 
2319  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2320  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2321 
2322  if (pred == 0xF) {
2323  Inst.setOpcode(ARM::BLXi);
2324  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2325  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2326  true, 4, Inst, Decoder))
2327  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2328  return S;
2329  }
2330 
2331  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2332  true, 4, Inst, Decoder))
2333  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2334  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2335  return MCDisassembler::Fail;
2336 
2337  return S;
2338 }
2339 
2340 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2341  uint64_t Address, const void *Decoder) {
2343 
2344  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2345  unsigned align = fieldFromInstruction(Val, 4, 2);
2346 
2347  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2348  return MCDisassembler::Fail;
2349  if (!align)
2351  else
2352  Inst.addOperand(MCOperand::createImm(4 << align));
2353 
2354  return S;
2355 }
2356 
2357 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2358  uint64_t Address, const void *Decoder) {
2360 
2361  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2362  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2363  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2364  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2365  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2366  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2367 
2368  // First output register
2369  switch (Inst.getOpcode()) {
2370  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2371  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2372  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2373  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2374  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2375  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2376  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2377  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2378  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2379  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2380  return MCDisassembler::Fail;
2381  break;
2382  case ARM::VLD2b16:
2383  case ARM::VLD2b32:
2384  case ARM::VLD2b8:
2385  case ARM::VLD2b16wb_fixed:
2386  case ARM::VLD2b16wb_register:
2387  case ARM::VLD2b32wb_fixed:
2388  case ARM::VLD2b32wb_register:
2389  case ARM::VLD2b8wb_fixed:
2390  case ARM::VLD2b8wb_register:
2391  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2392  return MCDisassembler::Fail;
2393  break;
2394  default:
2395  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2396  return MCDisassembler::Fail;
2397  }
2398 
2399  // Second output register
2400  switch (Inst.getOpcode()) {
2401  case ARM::VLD3d8:
2402  case ARM::VLD3d16:
2403  case ARM::VLD3d32:
2404  case ARM::VLD3d8_UPD:
2405  case ARM::VLD3d16_UPD:
2406  case ARM::VLD3d32_UPD:
2407  case ARM::VLD4d8:
2408  case ARM::VLD4d16:
2409  case ARM::VLD4d32:
2410  case ARM::VLD4d8_UPD:
2411  case ARM::VLD4d16_UPD:
2412  case ARM::VLD4d32_UPD:
2413  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2414  return MCDisassembler::Fail;
2415  break;
2416  case ARM::VLD3q8:
2417  case ARM::VLD3q16:
2418  case ARM::VLD3q32:
2419  case ARM::VLD3q8_UPD:
2420  case ARM::VLD3q16_UPD:
2421  case ARM::VLD3q32_UPD:
2422  case ARM::VLD4q8:
2423  case ARM::VLD4q16:
2424  case ARM::VLD4q32:
2425  case ARM::VLD4q8_UPD:
2426  case ARM::VLD4q16_UPD:
2427  case ARM::VLD4q32_UPD:
2428  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2429  return MCDisassembler::Fail;
2430  break;
2431  default:
2432  break;
2433  }
2434 
2435  // Third output register
2436  switch(Inst.getOpcode()) {
2437  case ARM::VLD3d8:
2438  case ARM::VLD3d16:
2439  case ARM::VLD3d32:
2440  case ARM::VLD3d8_UPD:
2441  case ARM::VLD3d16_UPD:
2442  case ARM::VLD3d32_UPD:
2443  case ARM::VLD4d8:
2444  case ARM::VLD4d16:
2445  case ARM::VLD4d32:
2446  case ARM::VLD4d8_UPD:
2447  case ARM::VLD4d16_UPD:
2448  case ARM::VLD4d32_UPD:
2449  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2450  return MCDisassembler::Fail;
2451  break;
2452  case ARM::VLD3q8:
2453  case ARM::VLD3q16:
2454  case ARM::VLD3q32:
2455  case ARM::VLD3q8_UPD:
2456  case ARM::VLD3q16_UPD:
2457  case ARM::VLD3q32_UPD:
2458  case ARM::VLD4q8:
2459  case ARM::VLD4q16:
2460  case ARM::VLD4q32:
2461  case ARM::VLD4q8_UPD:
2462  case ARM::VLD4q16_UPD:
2463  case ARM::VLD4q32_UPD:
2464  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2465  return MCDisassembler::Fail;
2466  break;
2467  default:
2468  break;
2469  }
2470 
2471  // Fourth output register
2472  switch (Inst.getOpcode()) {
2473  case ARM::VLD4d8:
2474  case ARM::VLD4d16:
2475  case ARM::VLD4d32:
2476  case ARM::VLD4d8_UPD:
2477  case ARM::VLD4d16_UPD:
2478  case ARM::VLD4d32_UPD:
2479  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2480  return MCDisassembler::Fail;
2481  break;
2482  case ARM::VLD4q8:
2483  case ARM::VLD4q16:
2484  case ARM::VLD4q32:
2485  case ARM::VLD4q8_UPD:
2486  case ARM::VLD4q16_UPD:
2487  case ARM::VLD4q32_UPD:
2488  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2489  return MCDisassembler::Fail;
2490  break;
2491  default:
2492  break;
2493  }
2494 
2495  // Writeback operand
2496  switch (Inst.getOpcode()) {
2497  case ARM::VLD1d8wb_fixed:
2498  case ARM::VLD1d16wb_fixed:
2499  case ARM::VLD1d32wb_fixed:
2500  case ARM::VLD1d64wb_fixed:
2501  case ARM::VLD1d8wb_register:
2502  case ARM::VLD1d16wb_register:
2503  case ARM::VLD1d32wb_register:
2504  case ARM::VLD1d64wb_register:
2505  case ARM::VLD1q8wb_fixed:
2506  case ARM::VLD1q16wb_fixed:
2507  case ARM::VLD1q32wb_fixed:
2508  case ARM::VLD1q64wb_fixed:
2509  case ARM::VLD1q8wb_register:
2510  case ARM::VLD1q16wb_register:
2511  case ARM::VLD1q32wb_register:
2512  case ARM::VLD1q64wb_register:
2513  case ARM::VLD1d8Twb_fixed:
2514  case ARM::VLD1d8Twb_register:
2515  case ARM::VLD1d16Twb_fixed:
2516  case ARM::VLD1d16Twb_register:
2517  case ARM::VLD1d32Twb_fixed:
2518  case ARM::VLD1d32Twb_register:
2519  case ARM::VLD1d64Twb_fixed:
2520  case ARM::VLD1d64Twb_register:
2521  case ARM::VLD1d8Qwb_fixed:
2522  case ARM::VLD1d8Qwb_register:
2523  case ARM::VLD1d16Qwb_fixed:
2524  case ARM::VLD1d16Qwb_register:
2525  case ARM::VLD1d32Qwb_fixed:
2526  case ARM::VLD1d32Qwb_register:
2527  case ARM::VLD1d64Qwb_fixed:
2528  case ARM::VLD1d64Qwb_register:
2529  case ARM::VLD2d8wb_fixed:
2530  case ARM::VLD2d16wb_fixed:
2531  case ARM::VLD2d32wb_fixed:
2532  case ARM::VLD2q8wb_fixed:
2533  case ARM::VLD2q16wb_fixed:
2534  case ARM::VLD2q32wb_fixed:
2535  case ARM::VLD2d8wb_register:
2536  case ARM::VLD2d16wb_register:
2537  case ARM::VLD2d32wb_register:
2538  case ARM::VLD2q8wb_register:
2539  case ARM::VLD2q16wb_register:
2540  case ARM::VLD2q32wb_register:
2541  case ARM::VLD2b8wb_fixed:
2542  case ARM::VLD2b16wb_fixed:
2543  case ARM::VLD2b32wb_fixed:
2544  case ARM::VLD2b8wb_register:
2545  case ARM::VLD2b16wb_register:
2546  case ARM::VLD2b32wb_register:
2548  break;
2549  case ARM::VLD3d8_UPD:
2550  case ARM::VLD3d16_UPD:
2551  case ARM::VLD3d32_UPD:
2552  case ARM::VLD3q8_UPD:
2553  case ARM::VLD3q16_UPD:
2554  case ARM::VLD3q32_UPD:
2555  case ARM::VLD4d8_UPD:
2556  case ARM::VLD4d16_UPD:
2557  case ARM::VLD4d32_UPD:
2558  case ARM::VLD4q8_UPD:
2559  case ARM::VLD4q16_UPD:
2560  case ARM::VLD4q32_UPD:
2561  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2562  return MCDisassembler::Fail;
2563  break;
2564  default:
2565  break;
2566  }
2567 
2568  // AddrMode6 Base (register+alignment)
2569  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2570  return MCDisassembler::Fail;
2571 
2572  // AddrMode6 Offset (register)
2573  switch (Inst.getOpcode()) {
2574  default:
2575  // The below have been updated to have explicit am6offset split
2576  // between fixed and register offset. For those instructions not
2577  // yet updated, we need to add an additional reg0 operand for the
2578  // fixed variant.
2579  //
2580  // The fixed offset encodes as Rm == 0xd, so we check for that.
2581  if (Rm == 0xd) {
2583  break;
2584  }
2585  // Fall through to handle the register offset variant.
2587  case ARM::VLD1d8wb_fixed:
2588  case ARM::VLD1d16wb_fixed:
2589  case ARM::VLD1d32wb_fixed:
2590  case ARM::VLD1d64wb_fixed:
2591  case ARM::VLD1d8Twb_fixed:
2592  case ARM::VLD1d16Twb_fixed:
2593  case ARM::VLD1d32Twb_fixed:
2594  case ARM::VLD1d64Twb_fixed:
2595  case ARM::VLD1d8Qwb_fixed:
2596  case ARM::VLD1d16Qwb_fixed:
2597  case ARM::VLD1d32Qwb_fixed:
2598  case ARM::VLD1d64Qwb_fixed:
2599  case ARM::VLD1d8wb_register:
2600  case ARM::VLD1d16wb_register:
2601  case ARM::VLD1d32wb_register:
2602  case ARM::VLD1d64wb_register:
2603  case ARM::VLD1q8wb_fixed:
2604  case ARM::VLD1q16wb_fixed:
2605  case ARM::VLD1q32wb_fixed:
2606  case ARM::VLD1q64wb_fixed:
2607  case ARM::VLD1q8wb_register:
2608  case ARM::VLD1q16wb_register:
2609  case ARM::VLD1q32wb_register:
2610  case ARM::VLD1q64wb_register:
2611  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2612  // variant encodes Rm == 0xf. Anything else is a register offset post-
2613  // increment and we need to add the register operand to the instruction.
2614  if (Rm != 0xD && Rm != 0xF &&
2615  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2616  return MCDisassembler::Fail;
2617  break;
2618  case ARM::VLD2d8wb_fixed:
2619  case ARM::VLD2d16wb_fixed:
2620  case ARM::VLD2d32wb_fixed:
2621  case ARM::VLD2b8wb_fixed:
2622  case ARM::VLD2b16wb_fixed:
2623  case ARM::VLD2b32wb_fixed:
2624  case ARM::VLD2q8wb_fixed:
2625  case ARM::VLD2q16wb_fixed:
2626  case ARM::VLD2q32wb_fixed:
2627  break;
2628  }
2629 
2630  return S;
2631 }
2632 
2633 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2634  uint64_t Address, const void *Decoder) {
2635  unsigned type = fieldFromInstruction(Insn, 8, 4);
2636  unsigned align = fieldFromInstruction(Insn, 4, 2);
2637  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2638  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2639  if (type == 10 && align == 3) return MCDisassembler::Fail;
2640 
2641  unsigned load = fieldFromInstruction(Insn, 21, 1);
2642  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2643  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2644 }
2645 
2646 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2647  uint64_t Address, const void *Decoder) {
2648  unsigned size = fieldFromInstruction(Insn, 6, 2);
2649  if (size == 3) return MCDisassembler::Fail;
2650 
2651  unsigned type = fieldFromInstruction(Insn, 8, 4);
2652  unsigned align = fieldFromInstruction(Insn, 4, 2);
2653  if (type == 8 && align == 3) return MCDisassembler::Fail;
2654  if (type == 9 && align == 3) return MCDisassembler::Fail;
2655 
2656  unsigned load = fieldFromInstruction(Insn, 21, 1);
2657  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2658  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2659 }
2660 
2661 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2662  uint64_t Address, const void *Decoder) {
2663  unsigned size = fieldFromInstruction(Insn, 6, 2);
2664  if (size == 3) return MCDisassembler::Fail;
2665 
2666  unsigned align = fieldFromInstruction(Insn, 4, 2);
2667  if (align & 2) return MCDisassembler::Fail;
2668 
2669  unsigned load = fieldFromInstruction(Insn, 21, 1);
2670  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2671  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2672 }
2673 
2674 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2675  uint64_t Address, const void *Decoder) {
2676  unsigned size = fieldFromInstruction(Insn, 6, 2);
2677  if (size == 3) return MCDisassembler::Fail;
2678 
2679  unsigned load = fieldFromInstruction(Insn, 21, 1);
2680  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2681  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2682 }
2683 
2684 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2685  uint64_t Address, const void *Decoder) {
2687 
2688  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2689  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2690  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2691  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2692  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2693  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2694 
2695  // Writeback Operand
2696  switch (Inst.getOpcode()) {
2697  case ARM::VST1d8wb_fixed:
2698  case ARM::VST1d16wb_fixed:
2699  case ARM::VST1d32wb_fixed:
2700  case ARM::VST1d64wb_fixed:
2701  case ARM::VST1d8wb_register:
2702  case ARM::VST1d16wb_register:
2703  case ARM::VST1d32wb_register:
2704  case ARM::VST1d64wb_register:
2705  case ARM::VST1q8wb_fixed:
2706  case ARM::VST1q16wb_fixed:
2707  case ARM::VST1q32wb_fixed:
2708  case ARM::VST1q64wb_fixed:
2709  case ARM::VST1q8wb_register:
2710  case ARM::VST1q16wb_register:
2711  case ARM::VST1q32wb_register:
2712  case ARM::VST1q64wb_register:
2713  case ARM::VST1d8Twb_fixed:
2714  case ARM::VST1d16Twb_fixed:
2715  case ARM::VST1d32Twb_fixed:
2716  case ARM::VST1d64Twb_fixed:
2717  case ARM::VST1d8Twb_register:
2718  case ARM::VST1d16Twb_register:
2719  case ARM::VST1d32Twb_register:
2720  case ARM::VST1d64Twb_register:
2721  case ARM::VST1d8Qwb_fixed:
2722  case ARM::VST1d16Qwb_fixed:
2723  case ARM::VST1d32Qwb_fixed:
2724  case ARM::VST1d64Qwb_fixed:
2725  case ARM::VST1d8Qwb_register:
2726  case ARM::VST1d16Qwb_register:
2727  case ARM::VST1d32Qwb_register:
2728  case ARM::VST1d64Qwb_register:
2729  case ARM::VST2d8wb_fixed:
2730  case ARM::VST2d16wb_fixed:
2731  case ARM::VST2d32wb_fixed:
2732  case ARM::VST2d8wb_register:
2733  case ARM::VST2d16wb_register:
2734  case ARM::VST2d32wb_register:
2735  case ARM::VST2q8wb_fixed:
2736  case ARM::VST2q16wb_fixed:
2737  case ARM::VST2q32wb_fixed:
2738  case ARM::VST2q8wb_register:
2739  case ARM::VST2q16wb_register:
2740  case ARM::VST2q32wb_register:
2741  case ARM::VST2b8wb_fixed:
2742  case ARM::VST2b16wb_fixed:
2743  case ARM::VST2b32wb_fixed:
2744  case ARM::VST2b8wb_register:
2745  case ARM::VST2b16wb_register:
2746  case ARM::VST2b32wb_register:
2747  if (Rm == 0xF)
2748  return MCDisassembler::Fail;
2750  break;
2751  case ARM::VST3d8_UPD:
2752  case ARM::VST3d16_UPD:
2753  case ARM::VST3d32_UPD:
2754  case ARM::VST3q8_UPD:
2755  case ARM::VST3q16_UPD:
2756  case ARM::VST3q32_UPD:
2757  case ARM::VST4d8_UPD:
2758  case ARM::VST4d16_UPD:
2759  case ARM::VST4d32_UPD:
2760  case ARM::VST4q8_UPD:
2761  case ARM::VST4q16_UPD:
2762  case ARM::VST4q32_UPD:
2763  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2764  return MCDisassembler::Fail;
2765  break;
2766  default:
2767  break;
2768  }
2769 
2770  // AddrMode6 Base (register+alignment)
2771  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2772  return MCDisassembler::Fail;
2773 
2774  // AddrMode6 Offset (register)
2775  switch (Inst.getOpcode()) {
2776  default:
2777  if (Rm == 0xD)
2779  else if (Rm != 0xF) {
2780  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2781  return MCDisassembler::Fail;
2782  }
2783  break;
2784  case ARM::VST1d8wb_fixed:
2785  case ARM::VST1d16wb_fixed:
2786  case ARM::VST1d32wb_fixed:
2787  case ARM::VST1d64wb_fixed:
2788  case ARM::VST1q8wb_fixed:
2789  case ARM::VST1q16wb_fixed:
2790  case ARM::VST1q32wb_fixed:
2791  case ARM::VST1q64wb_fixed:
2792  case ARM::VST1d8Twb_fixed:
2793  case ARM::VST1d16Twb_fixed:
2794  case ARM::VST1d32Twb_fixed:
2795  case ARM::VST1d64Twb_fixed:
2796  case ARM::VST1d8Qwb_fixed:
2797  case ARM::VST1d16Qwb_fixed:
2798  case ARM::VST1d32Qwb_fixed:
2799  case ARM::VST1d64Qwb_fixed:
2800  case ARM::VST2d8wb_fixed:
2801  case ARM::VST2d16wb_fixed:
2802  case ARM::VST2d32wb_fixed:
2803  case ARM::VST2q8wb_fixed:
2804  case ARM::VST2q16wb_fixed:
2805  case ARM::VST2q32wb_fixed:
2806  case ARM::VST2b8wb_fixed:
2807  case ARM::VST2b16wb_fixed:
2808  case ARM::VST2b32wb_fixed:
2809  break;
2810  }
2811 
2812  // First input register
2813  switch (Inst.getOpcode()) {
2814  case ARM::VST1q16:
2815  case ARM::VST1q32:
2816  case ARM::VST1q64:
2817  case ARM::VST1q8:
2818  case ARM::VST1q16wb_fixed:
2819  case ARM::VST1q16wb_register:
2820  case ARM::VST1q32wb_fixed:
2821  case ARM::VST1q32wb_register:
2822  case ARM::VST1q64wb_fixed:
2823  case ARM::VST1q64wb_register:
2824  case ARM::VST1q8wb_fixed:
2825  case ARM::VST1q8wb_register:
2826  case ARM::VST2d16:
2827  case ARM::VST2d32:
2828  case ARM::VST2d8:
2829  case ARM::VST2d16wb_fixed:
2830  case ARM::VST2d16wb_register:
2831  case ARM::VST2d32wb_fixed:
2832  case ARM::VST2d32wb_register:
2833  case ARM::VST2d8wb_fixed:
2834  case ARM::VST2d8wb_register:
2835  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2836  return MCDisassembler::Fail;
2837  break;
2838  case ARM::VST2b16:
2839  case ARM::VST2b32:
2840  case ARM::VST2b8:
2841  case ARM::VST2b16wb_fixed:
2842  case ARM::VST2b16wb_register:
2843  case ARM::VST2b32wb_fixed:
2844  case ARM::VST2b32wb_register:
2845  case ARM::VST2b8wb_fixed:
2846  case ARM::VST2b8wb_register:
2847  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2848  return MCDisassembler::Fail;
2849  break;
2850  default:
2851  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2852  return MCDisassembler::Fail;
2853  }
2854 
2855  // Second input register
2856  switch (Inst.getOpcode()) {
2857  case ARM::VST3d8:
2858  case ARM::VST3d16:
2859  case ARM::VST3d32:
2860  case ARM::VST3d8_UPD:
2861  case ARM::VST3d16_UPD:
2862  case ARM::VST3d32_UPD:
2863  case ARM::VST4d8:
2864  case ARM::VST4d16:
2865  case ARM::VST4d32:
2866  case ARM::VST4d8_UPD:
2867  case ARM::VST4d16_UPD:
2868  case ARM::VST4d32_UPD:
2869  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2870  return MCDisassembler::Fail;
2871  break;
2872  case ARM::VST3q8:
2873  case ARM::VST3q16:
2874  case ARM::VST3q32:
2875  case ARM::VST3q8_UPD:
2876  case ARM::VST3q16_UPD:
2877  case ARM::VST3q32_UPD:
2878  case ARM::VST4q8:
2879  case ARM::VST4q16:
2880  case ARM::VST4q32:
2881  case ARM::VST4q8_UPD:
2882  case ARM::VST4q16_UPD:
2883  case ARM::VST4q32_UPD:
2884  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2885  return MCDisassembler::Fail;
2886  break;
2887  default:
2888  break;
2889  }
2890 
2891  // Third input register
2892  switch (Inst.getOpcode()) {
2893  case ARM::VST3d8:
2894  case ARM::VST3d16:
2895  case ARM::VST3d32:
2896  case ARM::VST3d8_UPD:
2897  case ARM::VST3d16_UPD:
2898  case ARM::VST3d32_UPD:
2899  case ARM::VST4d8:
2900  case ARM::VST4d16:
2901  case ARM::VST4d32:
2902  case ARM::VST4d8_UPD:
2903  case ARM::VST4d16_UPD:
2904  case ARM::VST4d32_UPD:
2905  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2906  return MCDisassembler::Fail;
2907  break;
2908  case ARM::VST3q8:
2909  case ARM::VST3q16:
2910  case ARM::VST3q32:
2911  case ARM::VST3q8_UPD:
2912  case ARM::VST3q16_UPD:
2913  case ARM::VST3q32_UPD:
2914  case ARM::VST4q8:
2915  case ARM::VST4q16:
2916  case ARM::VST4q32:
2917  case ARM::VST4q8_UPD:
2918  case ARM::VST4q16_UPD:
2919  case ARM::VST4q32_UPD:
2920  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2921  return MCDisassembler::Fail;
2922  break;
2923  default:
2924  break;
2925  }
2926 
2927  // Fourth input register
2928  switch (Inst.getOpcode()) {
2929  case ARM::VST4d8:
2930  case ARM::VST4d16:
2931  case ARM::VST4d32:
2932  case ARM::VST4d8_UPD:
2933  case ARM::VST4d16_UPD:
2934  case ARM::VST4d32_UPD:
2935  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2936  return MCDisassembler::Fail;
2937  break;
2938  case ARM::VST4q8:
2939  case ARM::VST4q16:
2940  case ARM::VST4q32:
2941  case ARM::VST4q8_UPD:
2942  case ARM::VST4q16_UPD:
2943  case ARM::VST4q32_UPD:
2944  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2945  return MCDisassembler::Fail;
2946  break;
2947  default:
2948  break;
2949  }
2950 
2951  return S;
2952 }
2953 
2954 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2955  uint64_t Address, const void *Decoder) {
2957 
2958  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2959  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2960  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2961  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2962  unsigned align = fieldFromInstruction(Insn, 4, 1);
2963  unsigned size = fieldFromInstruction(Insn, 6, 2);
2964 
2965  if (size == 0 && align == 1)
2966  return MCDisassembler::Fail;
2967  align *= (1 << size);
2968 
2969  switch (Inst.getOpcode()) {
2970  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2971  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2972  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2973  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2974  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2975  return MCDisassembler::Fail;
2976  break;
2977  default:
2978  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2979  return MCDisassembler::Fail;
2980  break;
2981  }
2982  if (Rm != 0xF) {
2983  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2984  return MCDisassembler::Fail;
2985  }
2986 
2987  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2988  return MCDisassembler::Fail;
2989  Inst.addOperand(MCOperand::createImm(align));
2990 
2991  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2992  // variant encodes Rm == 0xf. Anything else is a register offset post-
2993  // increment and we need to add the register operand to the instruction.
2994  if (Rm != 0xD && Rm != 0xF &&
2995  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2996  return MCDisassembler::Fail;
2997 
2998  return S;
2999 }
3000 
3001 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3002  uint64_t Address, const void *Decoder) {
3004 
3005  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3006  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3007  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3008  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3009  unsigned align = fieldFromInstruction(Insn, 4, 1);
3010  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3011  align *= 2*size;
3012 
3013  switch (Inst.getOpcode()) {
3014  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3015  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3016  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3017  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3018  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3019  return MCDisassembler::Fail;
3020  break;
3021  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3022  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3023  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3024  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3025  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3026  return MCDisassembler::Fail;
3027  break;
3028  default:
3029  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3030  return MCDisassembler::Fail;
3031  break;
3032  }
3033 
3034  if (Rm != 0xF)
3036 
3037  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3038  return MCDisassembler::Fail;
3039  Inst.addOperand(MCOperand::createImm(align));
3040 
3041  if (Rm != 0xD && Rm != 0xF) {
3042  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3043  return MCDisassembler::Fail;
3044  }
3045 
3046  return S;
3047 }
3048 
3049 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3050  uint64_t Address, const void *Decoder) {
3052 
3053  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3054  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3055  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3056  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3057  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3058 
3059  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3060  return MCDisassembler::Fail;
3061  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3062  return MCDisassembler::Fail;
3063  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3064  return MCDisassembler::Fail;
3065  if (Rm != 0xF) {
3066  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3067  return MCDisassembler::Fail;
3068  }
3069 
3070  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3071  return MCDisassembler::Fail;
3073 
3074  if (Rm == 0xD)
3076  else if (Rm != 0xF) {
3077  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3078  return MCDisassembler::Fail;
3079  }
3080 
3081  return S;
3082 }
3083 
3084 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3085  uint64_t Address, const void *Decoder) {
3087 
3088  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3089  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3090  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3091  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3092  unsigned size = fieldFromInstruction(Insn, 6, 2);
3093  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3094  unsigned align = fieldFromInstruction(Insn, 4, 1);
3095 
3096  if (size == 0x3) {
3097  if (align == 0)
3098  return MCDisassembler::Fail;
3099  align = 16;
3100  } else {
3101  if (size == 2) {
3102  align *= 8;
3103  } else {
3104  size = 1 << size;
3105  align *= 4*size;
3106  }
3107  }
3108 
3109  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3110  return MCDisassembler::Fail;
3111  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3112  return MCDisassembler::Fail;
3113  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3114  return MCDisassembler::Fail;
3115  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3116  return MCDisassembler::Fail;
3117  if (Rm != 0xF) {
3118  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3119  return MCDisassembler::Fail;
3120  }
3121 
3122  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3123  return MCDisassembler::Fail;
3124  Inst.addOperand(MCOperand::createImm(align));
3125 
3126  if (Rm == 0xD)
3128  else if (Rm != 0xF) {
3129  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3130  return MCDisassembler::Fail;
3131  }
3132 
3133  return S;
3134 }
3135 
3136 static DecodeStatus
3138  uint64_t Address, const void *Decoder) {
3140 
3141  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3142  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3143  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3144  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3145  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3146  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3147  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3148  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3149 
3150  if (Q) {
3151  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3152  return MCDisassembler::Fail;
3153  } else {
3154  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3155  return MCDisassembler::Fail;
3156  }
3157 
3158  Inst.addOperand(MCOperand::createImm(imm));
3159 
3160  switch (Inst.getOpcode()) {
3161  case ARM::VORRiv4i16:
3162  case ARM::VORRiv2i32:
3163  case ARM::VBICiv4i16:
3164  case ARM::VBICiv2i32:
3165  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3166  return MCDisassembler::Fail;
3167  break;
3168  case ARM::VORRiv8i16:
3169  case ARM::VORRiv4i32:
3170  case ARM::VBICiv8i16:
3171  case ARM::VBICiv4i32:
3172  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3173  return MCDisassembler::Fail;
3174  break;
3175  default:
3176  break;
3177  }
3178 
3179  return S;
3180 }
3181 
3182 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3183  uint64_t Address, const void *Decoder) {
3185 
3186  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3187  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3188  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3189  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3190  unsigned size = fieldFromInstruction(Insn, 18, 2);
3191 
3192  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3193  return MCDisassembler::Fail;
3194  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3195  return MCDisassembler::Fail;
3196  Inst.addOperand(MCOperand::createImm(8 << size));
3197 
3198  return S;
3199 }
3200 
3201 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3202  uint64_t Address, const void *Decoder) {
3203  Inst.addOperand(MCOperand::createImm(8 - Val));
3204  return MCDisassembler::Success;
3205 }
3206 
3207 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3208  uint64_t Address, const void *Decoder) {
3209  Inst.addOperand(MCOperand::createImm(16 - Val));
3210  return MCDisassembler::Success;
3211 }
3212 
3213 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3214  uint64_t Address, const void *Decoder) {
3215  Inst.addOperand(MCOperand::createImm(32 - Val));
3216  return MCDisassembler::Success;
3217 }
3218 
3219 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3220  uint64_t Address, const void *Decoder) {
3221  Inst.addOperand(MCOperand::createImm(64 - Val));
3222  return MCDisassembler::Success;
3223 }
3224 
3225 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3226  uint64_t Address, const void *Decoder) {
3228 
3229  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3230  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3231  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3232  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3233  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3234  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3235  unsigned op = fieldFromInstruction(Insn, 6, 1);
3236 
3237  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3238  return MCDisassembler::Fail;
3239  if (op) {
3240  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3241  return MCDisassembler::Fail; // Writeback
3242  }
3243 
3244  switch (Inst.getOpcode()) {
3245  case ARM::VTBL2:
3246  case ARM::VTBX2:
3247  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3248  return MCDisassembler::Fail;
3249  break;
3250  default:
3251  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3252  return MCDisassembler::Fail;
3253  }
3254 
3255  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3256  return MCDisassembler::Fail;
3257 
3258  return S;
3259 }
3260 
3261 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3262  uint64_t Address, const void *Decoder) {
3264 
3265  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3266  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3267 
3268  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3269  return MCDisassembler::Fail;
3270 
3271  switch(Inst.getOpcode()) {
3272  default:
3273  return MCDisassembler::Fail;
3274  case ARM::tADR:
3275  break; // tADR does not explicitly represent the PC as an operand.
3276  case ARM::tADDrSPi:
3277  Inst.addOperand(MCOperand::createReg(ARM::SP));
3278  break;
3279  }
3280 
3281  Inst.addOperand(MCOperand::createImm(imm));
3282  return S;
3283 }
3284 
3285 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3286  uint64_t Address, const void *Decoder) {
3287  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3288  true, 2, Inst, Decoder))
3289  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3290  return MCDisassembler::Success;
3291 }
3292 
3293 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3294  uint64_t Address, const void *Decoder) {
3295  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3296  true, 4, Inst, Decoder))
3297  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3298  return MCDisassembler::Success;
3299 }
3300 
3301 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3302  uint64_t Address, const void *Decoder) {
3303  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3304  true, 2, Inst, Decoder))
3305  Inst.addOperand(MCOperand::createImm(Val << 1));
3306  return MCDisassembler::Success;
3307 }
3308 
3309 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3310  uint64_t Address, const void *Decoder) {
3312 
3313  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3314  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3315 
3316  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3317  return MCDisassembler::Fail;
3318  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3319  return MCDisassembler::Fail;
3320 
3321  return S;
3322 }
3323 
3324 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3325  uint64_t Address, const void *Decoder) {
3327 
3328  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3329  unsigned imm = fieldFromInstruction(Val, 3, 5);
3330 
3331  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332  return MCDisassembler::Fail;
3333  Inst.addOperand(MCOperand::createImm(imm));
3334 
3335  return S;
3336 }
3337 
3338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3339  uint64_t Address, const void *Decoder) {
3340  unsigned imm = Val << 2;
3341 
3342  Inst.addOperand(MCOperand::createImm(imm));
3343  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3344 
3345  return MCDisassembler::Success;
3346 }
3347 
3348 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3349  uint64_t Address, const void *Decoder) {
3350  Inst.addOperand(MCOperand::createReg(ARM::SP));
3351  Inst.addOperand(MCOperand::createImm(Val));
3352 
3353  return MCDisassembler::Success;
3354 }
3355 
3356 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3357  uint64_t Address, const void *Decoder) {
3359 
3360  unsigned Rn = fieldFromInstruction(Val, 6, 4);
3361  unsigned Rm = fieldFromInstruction(Val, 2, 4);
3362  unsigned imm = fieldFromInstruction(Val, 0, 2);
3363 
3364  // Thumb stores cannot use PC as dest register.
3365  switch (Inst.getOpcode()) {
3366  case ARM::t2STRHs:
3367  case ARM::t2STRBs:
3368  case ARM::t2STRs:
3369  if (Rn == 15)
3370  return MCDisassembler::Fail;
3371  break;
3372  default:
3373  break;
3374  }
3375 
3376  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3377  return MCDisassembler::Fail;
3378  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3379  return MCDisassembler::Fail;
3380  Inst.addOperand(MCOperand::createImm(imm));
3381 
3382  return S;
3383 }
3384 
3385 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3386  uint64_t Address, const void *Decoder) {
3388 
3389  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3390  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3391 
3392  const FeatureBitset &featureBits =
3393  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3394 
3395  bool hasMP = featureBits[ARM::FeatureMP];
3396  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3397 
3398  if (Rn == 15) {
3399  switch (Inst.getOpcode()) {
3400  case ARM::t2LDRBs:
3401  Inst.setOpcode(ARM::t2LDRBpci);
3402  break;
3403  case ARM::t2LDRHs:
3404  Inst.setOpcode(ARM::t2LDRHpci);
3405  break;
3406  case ARM::t2LDRSHs:
3407  Inst.setOpcode(ARM::t2LDRSHpci);
3408  break;
3409  case ARM::t2LDRSBs:
3410  Inst.setOpcode(ARM::t2LDRSBpci);
3411  break;
3412  case ARM::t2LDRs:
3413  Inst.setOpcode(ARM::t2LDRpci);
3414  break;
3415  case ARM::t2PLDs:
3416  Inst.setOpcode(ARM::t2PLDpci);
3417  break;
3418  case ARM::t2PLIs:
3419  Inst.setOpcode(ARM::t2PLIpci);
3420  break;
3421  default:
3422  return MCDisassembler::Fail;
3423  }
3424 
3425  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3426  }
3427 
3428  if (Rt == 15) {
3429  switch (Inst.getOpcode()) {
3430  case ARM::t2LDRSHs:
3431  return MCDisassembler::Fail;
3432  case ARM::t2LDRHs:
3433  Inst.setOpcode(ARM::t2PLDWs);
3434  break;
3435  case ARM::t2LDRSBs:
3436  Inst.setOpcode(ARM::t2PLIs);
3437  break;
3438  default:
3439  break;
3440  }
3441  }
3442 
3443  switch (Inst.getOpcode()) {
3444  case ARM::t2PLDs:
3445  break;
3446  case ARM::t2PLIs:
3447  if (!hasV7Ops)
3448  return MCDisassembler::Fail;
3449  break;
3450  case ARM::t2PLDWs:
3451  if (!hasV7Ops || !hasMP)
3452  return MCDisassembler::Fail;
3453  break;
3454  default:
3455  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3456  return MCDisassembler::Fail;
3457  }
3458 
3459  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3460  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3461  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3462  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3463  return MCDisassembler::Fail;
3464 
3465  return S;
3466 }
3467 
3468 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3469  uint64_t Address, const void* Decoder) {
3471 
3472  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3473  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3474  unsigned U = fieldFromInstruction(Insn, 9, 1);
3475  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3476  imm |= (U << 8);
3477  imm |= (Rn << 9);
3478  unsigned add = fieldFromInstruction(Insn, 9, 1);
3479 
3480  const FeatureBitset &featureBits =
3481  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3482 
3483  bool hasMP = featureBits[ARM::FeatureMP];
3484  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3485 
3486  if (Rn == 15) {
3487  switch (Inst.getOpcode()) {
3488  case ARM::t2LDRi8:
3489  Inst.setOpcode(ARM::t2LDRpci);
3490  break;
3491  case ARM::t2LDRBi8:
3492  Inst.setOpcode(ARM::t2LDRBpci);
3493  break;
3494  case ARM::t2LDRSBi8:
3495  Inst.setOpcode(ARM::t2LDRSBpci);
3496  break;
3497  case ARM::t2LDRHi8:
3498  Inst.setOpcode(ARM::t2LDRHpci);
3499  break;
3500  case ARM::t2LDRSHi8:
3501  Inst.setOpcode(ARM::t2LDRSHpci);
3502  break;
3503  case ARM::t2PLDi8:
3504  Inst.setOpcode(ARM::t2PLDpci);
3505  break;
3506  case ARM::t2PLIi8:
3507  Inst.setOpcode(ARM::t2PLIpci);
3508  break;
3509  default:
3510  return MCDisassembler::Fail;
3511  }
3512  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3513  }
3514 
3515  if (Rt == 15) {
3516  switch (Inst.getOpcode()) {
3517  case ARM::t2LDRSHi8:
3518  return MCDisassembler::Fail;
3519  case ARM::t2LDRHi8:
3520  if (!add)
3521  Inst.setOpcode(ARM::t2PLDWi8);
3522  break;
3523  case ARM::t2LDRSBi8:
3524  Inst.setOpcode(ARM::t2PLIi8);
3525  break;
3526  default:
3527  break;
3528  }
3529  }
3530 
3531  switch (Inst.getOpcode()) {
3532  case ARM::t2PLDi8:
3533  break;
3534  case ARM::t2PLIi8:
3535  if (!hasV7Ops)
3536  return MCDisassembler::Fail;
3537  break;
3538  case ARM::t2PLDWi8:
3539  if (!hasV7Ops || !hasMP)
3540  return MCDisassembler::Fail;
3541  break;
3542  default:
3543  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3544  return MCDisassembler::Fail;
3545  }
3546 
3547  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3548  return MCDisassembler::Fail;
3549  return S;
3550 }
3551 
3552 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3553  uint64_t Address, const void* Decoder) {
3555 
3556  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3557  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3558  unsigned imm = fieldFromInstruction(Insn, 0, 12);
3559  imm |= (Rn << 13);
3560 
3561  const FeatureBitset &featureBits =
3562  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3563 
3564  bool hasMP = featureBits[ARM::FeatureMP];
3565  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3566 
3567  if (Rn == 15) {
3568  switch (Inst.getOpcode()) {
3569  case ARM::t2LDRi12:
3570  Inst.setOpcode(ARM::t2LDRpci);
3571  break;
3572  case ARM::t2LDRHi12:
3573  Inst.setOpcode(ARM::t2LDRHpci);
3574  break;
3575  case ARM::t2LDRSHi12:
3576  Inst.setOpcode(ARM::t2LDRSHpci);
3577  break;
3578  case ARM::t2LDRBi12:
3579  Inst.setOpcode(ARM::t2LDRBpci);
3580  break;
3581  case ARM::t2LDRSBi12:
3582  Inst.setOpcode(ARM::t2LDRSBpci);
3583  break;
3584  case ARM::t2PLDi12:
3585  Inst.setOpcode(ARM::t2PLDpci);
3586  break;
3587  case ARM::t2PLIi12:
3588  Inst.setOpcode(ARM::t2PLIpci);
3589  break;
3590  default:
3591  return MCDisassembler::Fail;
3592  }
3593  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3594  }
3595 
3596  if (Rt == 15) {
3597  switch (Inst.getOpcode()) {
3598  case ARM::t2LDRSHi12:
3599  return MCDisassembler::Fail;
3600  case ARM::t2LDRHi12:
3601  Inst.setOpcode(ARM::t2PLDWi12);
3602  break;
3603  case ARM::t2LDRSBi12:
3604  Inst.setOpcode(ARM::t2PLIi12);
3605  break;
3606  default:
3607  break;
3608  }
3609  }
3610 
3611  switch (Inst.getOpcode()) {
3612  case ARM::t2PLDi12:
3613  break;
3614  case ARM::t2PLIi12:
3615  if (!hasV7Ops)
3616  return MCDisassembler::Fail;
3617  break;
3618  case ARM::t2PLDWi12:
3619  if (!hasV7Ops || !hasMP)
3620  return MCDisassembler::Fail;
3621  break;
3622  default:
3623  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3624  return MCDisassembler::Fail;
3625  }
3626 
3627  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3628  return MCDisassembler::Fail;
3629  return S;
3630 }
3631 
3632 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3633  uint64_t Address, const void* Decoder) {
3635 
3636  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3637  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3638  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3639  imm |= (Rn << 9);
3640 
3641  if (Rn == 15) {
3642  switch (Inst.getOpcode()) {
3643  case ARM::t2LDRT:
3644  Inst.setOpcode(ARM::t2LDRpci);
3645  break;
3646  case ARM::t2LDRBT:
3647  Inst.setOpcode(ARM::t2LDRBpci);
3648  break;
3649  case ARM::t2LDRHT:
3650  Inst.setOpcode(ARM::t2LDRHpci);
3651  break;
3652  case ARM::t2LDRSBT:
3653  Inst.setOpcode(ARM::t2LDRSBpci);
3654  break;
3655  case ARM::t2LDRSHT:
3656  Inst.setOpcode(ARM::t2LDRSHpci);
3657  break;
3658  default:
3659  return MCDisassembler::Fail;
3660  }
3661  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3662  }
3663 
3664  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3665  return MCDisassembler::Fail;
3666  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3667  return MCDisassembler::Fail;
3668  return S;
3669 }
3670 
3671 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3672  uint64_t Address, const void* Decoder) {
3674 
3675  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3676  unsigned U = fieldFromInstruction(Insn, 23, 1);
3677  int imm = fieldFromInstruction(Insn, 0, 12);
3678 
3679  const FeatureBitset &featureBits =
3680  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3681 
3682  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3683 
3684  if (Rt == 15) {
3685  switch (Inst.getOpcode()) {
3686  case ARM::t2LDRBpci:
3687  case ARM::t2LDRHpci:
3688  Inst.setOpcode(ARM::t2PLDpci);
3689  break;
3690  case ARM::t2LDRSBpci:
3691  Inst.setOpcode(ARM::t2PLIpci);
3692  break;
3693  case ARM::t2LDRSHpci:
3694  return MCDisassembler::Fail;
3695  default:
3696  break;
3697  }
3698  }
3699 
3700  switch(Inst.getOpcode()) {
3701  case ARM::t2PLDpci:
3702  break;
3703  case ARM::t2PLIpci:
3704  if (!hasV7Ops)
3705  return MCDisassembler::Fail;
3706  break;
3707  default:
3708  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3709  return MCDisassembler::Fail;
3710  }
3711 
3712  if (!U) {
3713  // Special case for #-0.
3714  if (imm == 0)
3715  imm = INT32_MIN;
3716  else
3717  imm = -imm;
3718  }
3719  Inst.addOperand(MCOperand::createImm(imm));
3720 
3721  return S;
3722 }
3723 
3724 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3725  uint64_t Address, const void *Decoder) {
3726  if (Val == 0)
3727  Inst.addOperand(MCOperand::createImm(INT32_MIN));
3728  else {
3729  int imm = Val & 0xFF;
3730 
3731  if (!(Val & 0x100)) imm *= -1;
3732  Inst.addOperand(MCOperand::createImm(imm * 4));
3733  }
3734 
3735  return MCDisassembler::Success;
3736 }
3737 
3738 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3739  uint64_t Address, const void *Decoder) {
3741 
3742  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3743  unsigned imm = fieldFromInstruction(Val, 0, 9);
3744 
3745  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3746  return MCDisassembler::Fail;
3747  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3748  return MCDisassembler::Fail;
3749 
3750  return S;
3751 }
3752 
3754  uint64_t Address, const void *Decoder) {
3756 
3757  unsigned Rn = fieldFromInstruction(Val, 8, 4);
3758  unsigned imm = fieldFromInstruction(Val, 0, 8);
3759 
3760  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3761  return MCDisassembler::Fail;
3762 
3763  Inst.addOperand(MCOperand::createImm(imm));
3764 
3765  return S;
3766 }
3767 
3768 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3769  uint64_t Address, const void *Decoder) {
3770  int imm = Val & 0xFF;
3771  if (Val == 0)
3772  imm = INT32_MIN;
3773  else if (!(Val & 0x100))
3774  imm *= -1;
3775  Inst.addOperand(MCOperand::createImm(imm));
3776 
3777  return MCDisassembler::Success;
3778 }
3779 
3780 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3781  uint64_t Address, const void *Decoder) {
3783 
3784  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3785  unsigned imm = fieldFromInstruction(Val, 0, 9);
3786 
3787  // Thumb stores cannot use PC as dest register.
3788  switch (Inst.getOpcode()) {
3789  case ARM::t2STRT:
3790  case ARM::t2STRBT:
3791  case ARM::t2STRHT:
3792  case ARM::t2STRi8:
3793  case ARM::t2STRHi8:
3794  case ARM::t2STRBi8:
3795  if (Rn == 15)
3796  return MCDisassembler::Fail;
3797  break;
3798  default:
3799  break;
3800  }
3801 
3802  // Some instructions always use an additive offset.
3803  switch (Inst.getOpcode()) {
3804  case ARM::t2LDRT:
3805  case ARM::t2LDRBT:
3806  case ARM::t2LDRHT:
3807  case ARM::t2LDRSBT:
3808  case ARM::t2LDRSHT:
3809  case ARM::t2STRT:
3810  case ARM::t2STRBT:
3811  case ARM::t2STRHT:
3812  imm |= 0x100;
3813  break;
3814  default:
3815  break;
3816  }
3817 
3818  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3819  return MCDisassembler::Fail;
3820  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3821  return MCDisassembler::Fail;
3822 
3823  return S;
3824 }
3825 
3826 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3827  uint64_t Address, const void *Decoder) {
3829 
3830  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3831  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3832  unsigned addr = fieldFromInstruction(Insn, 0, 8);
3833  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3834  addr |= Rn << 9;
3835  unsigned load = fieldFromInstruction(Insn, 20, 1);
3836 
3837  if (Rn == 15) {
3838  switch (Inst.getOpcode()) {
3839  case ARM::t2LDR_PRE:
3840  case ARM::t2LDR_POST:
3841  Inst.setOpcode(ARM::t2LDRpci);
3842  break;
3843  case ARM::t2LDRB_PRE:
3844  case ARM::t2LDRB_POST:
3845  Inst.setOpcode(ARM::t2LDRBpci);
3846  break;
3847  case ARM::t2LDRH_PRE:
3848  case ARM::t2LDRH_POST:
3849  Inst.setOpcode(ARM::t2LDRHpci);
3850  break;
3851  case ARM::t2LDRSB_PRE:
3852  case ARM::t2LDRSB_POST:
3853  if (Rt == 15)
3854  Inst.setOpcode(ARM::t2PLIpci);
3855  else
3856  Inst.setOpcode(ARM::t2LDRSBpci);
3857  break;
3858  case ARM::t2LDRSH_PRE:
3859  case ARM::t2LDRSH_POST:
3860  Inst.setOpcode(ARM::t2LDRSHpci);
3861  break;
3862  default:
3863  return MCDisassembler::Fail;
3864  }
3865  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3866  }
3867 
3868  if (!load) {
3869  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3870  return MCDisassembler::Fail;
3871  }
3872 
3873  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3874  return MCDisassembler::Fail;
3875 
3876  if (load) {
3877  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3878  return MCDisassembler::Fail;
3879  }
3880 
3881  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3882  return MCDisassembler::Fail;
3883 
3884  return S;
3885 }
3886 
3887 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3888  uint64_t Address, const void *Decoder) {
3890 
3891  unsigned Rn = fieldFromInstruction(Val, 13, 4);
3892  unsigned imm = fieldFromInstruction(Val, 0, 12);
3893 
3894  // Thumb stores cannot use PC as dest register.
3895  switch (Inst.getOpcode()) {
3896  case ARM::t2STRi12:
3897  case ARM::t2STRBi12:
3898  case ARM::t2STRHi12:
3899  if (Rn == 15)
3900  return MCDisassembler::Fail;
3901  break;
3902  default:
3903  break;
3904  }
3905 
3906  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3907  return MCDisassembler::Fail;
3908  Inst.addOperand(MCOperand::createImm(imm));
3909 
3910  return S;
3911 }
3912 
3913 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3914  uint64_t Address, const void *Decoder) {
3915  unsigned imm = fieldFromInstruction(Insn, 0, 7);
3916 
3917  Inst.addOperand(MCOperand::createReg(ARM::SP));
3918  Inst.addOperand(MCOperand::createReg(ARM::SP));
3919  Inst.addOperand(MCOperand::createImm(imm));
3920 
3921  return MCDisassembler::Success;
3922 }
3923 
3924 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3925  uint64_t Address, const void *Decoder) {
3927 
3928  if (Inst.getOpcode() == ARM::tADDrSP) {
3929  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3930  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3931 
3932  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3933  return MCDisassembler::Fail;
3934  Inst.addOperand(MCOperand::createReg(ARM::SP));
3935  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3936  return MCDisassembler::Fail;
3937  } else if (Inst.getOpcode() == ARM::tADDspr) {
3938  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3939 
3940  Inst.addOperand(MCOperand::createReg(ARM::SP));
3941  Inst.addOperand(MCOperand::createReg(ARM::SP));
3942  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3943  return MCDisassembler::Fail;
3944  }
3945 
3946  return S;
3947 }
3948 
3949 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3950  uint64_t Address, const void *Decoder) {
3951  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3952  unsigned flags = fieldFromInstruction(Insn, 0, 3);
3953 
3954  Inst.addOperand(MCOperand::createImm(imod));
3955  Inst.addOperand(MCOperand::createImm(flags));
3956 
3957  return MCDisassembler::Success;
3958 }
3959 
3960 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3961  uint64_t Address, const void *Decoder) {
3963  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3964  unsigned add = fieldFromInstruction(Insn, 4, 1);
3965 
3966  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3967  return MCDisassembler::Fail;
3968  Inst.addOperand(MCOperand::createImm(add));
3969 
3970  return S;
3971 }
3972 
3973 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3974  uint64_t Address, const void *Decoder) {
3975  // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3976  // Note only one trailing zero not two. Also the J1 and J2 values are from
3977  // the encoded instruction. So here change to I1 and I2 values via:
3978  // I1 = NOT(J1 EOR S);
3979  // I2 = NOT(J2 EOR S);
3980  // and build the imm32 with two trailing zeros as documented:
3981  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3982  unsigned S = (Val >> 23) & 1;
3983  unsigned J1 = (Val >> 22) & 1;
3984  unsigned J2 = (Val >> 21) & 1;
3985  unsigned I1 = !(J1 ^ S);
3986  unsigned I2 = !(J2 ^ S);
3987  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3988  int imm32 = SignExtend32<25>(tmp << 1);
3989 
3990  if (!tryAddingSymbolicOperand(Address,
3991  (Address & ~2u) + imm32 + 4,
3992  true, 4, Inst, Decoder))
3993  Inst.addOperand(MCOperand::createImm(imm32));
3994  return MCDisassembler::Success;
3995 }
3996 
3997 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3998  uint64_t Address, const void *Decoder) {
3999  if (Val == 0xA || Val == 0xB)
4000  return MCDisassembler::Fail;
4001 
4002  const FeatureBitset &featureBits =
4003  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4004 
4005  if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
4006  return MCDisassembler::Fail;
4007 
4008  Inst.addOperand(MCOperand::createImm(Val));
4009  return MCDisassembler::Success;
4010 }
4011 
4012 static DecodeStatus
4013 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4014  uint64_t Address, const void *Decoder) {
4016 
4017  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4018  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4019 
4020  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
4021  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4022  return MCDisassembler::Fail;
4023  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4024  return MCDisassembler::Fail;
4025  return S;
4026 }
4027 
4028 static DecodeStatus
4029 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4030  uint64_t Address, const void *Decoder) {
4032 
4033  unsigned pred = fieldFromInstruction(Insn, 22, 4);
4034  if (pred == 0xE || pred == 0xF) {
4035  unsigned opc = fieldFromInstruction(Insn, 4, 28);
4036  switch (opc) {
4037  default:
4038  return MCDisassembler::Fail;
4039  case 0xf3bf8f4:
4040  Inst.setOpcode(ARM::t2DSB);
4041  break;
4042  case 0xf3bf8f5:
4043  Inst.setOpcode(ARM::t2DMB);
4044  break;
4045  case 0xf3bf8f6:
4046  Inst.setOpcode(ARM::t2ISB);
4047  break;
4048  }
4049 
4050  unsigned imm = fieldFromInstruction(Insn, 0, 4);
4051  return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4052  }
4053 
4054  unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4055  brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4056  brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4057  brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4058  brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4059 
4060  if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4061  return MCDisassembler::Fail;
4062  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4063  return MCDisassembler::Fail;
4064 
4065  return S;
4066 }
4067 
4068 // Decode a shifted immediate operand. These basically consist
4069 // of an 8-bit value, and a 4-bit directive that specifies either
4070 // a splat operation or a rotation.
4071 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4072  uint64_t Address, const void *Decoder) {
4073  unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4074  if (ctrl == 0) {
4075  unsigned byte = fieldFromInstruction(Val, 8, 2);
4076  unsigned imm = fieldFromInstruction(Val, 0, 8);
4077  switch (byte) {
4078  case 0:
4079  Inst.addOperand(MCOperand::createImm(imm));
4080  break;
4081  case 1:
4082  Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4083  break;
4084  case 2:
4085  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4086  break;
4087  case 3:
4088  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4089  (imm << 8) | imm));
4090  break;
4091  }
4092  } else {
4093  unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4094  unsigned rot = fieldFromInstruction(Val, 7, 5);
4095  unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4096  Inst.addOperand(MCOperand::createImm(imm));
4097  }
4098 
4099  return MCDisassembler::Success;
4100 }
4101 
4102 static DecodeStatus
4104  uint64_t Address, const void *Decoder) {
4105  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4106  true, 2, Inst, Decoder))
4107  Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4108  return MCDisassembler::Success;
4109 }
4110 
4112  uint64_t Address,
4113  const void *Decoder) {
4114  // Val is passed in as S:J1:J2:imm10:imm11
4115  // Note no trailing zero after imm11. Also the J1 and J2 values are from
4116  // the encoded instruction. So here change to I1 and I2 values via:
4117  // I1 = NOT(J1 EOR S);
4118  // I2 = NOT(J2 EOR S);
4119  // and build the imm32 with one trailing zero as documented:
4120  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4121  unsigned S = (Val >> 23) & 1;
4122  unsigned J1 = (Val >> 22) & 1;
4123  unsigned J2 = (Val >> 21) & 1;
4124  unsigned I1 = !(J1 ^ S);
4125  unsigned I2 = !(J2 ^ S);
4126  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4127  int imm32 = SignExtend32<25>(tmp << 1);
4128 
4129  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4130  true, 4, Inst, Decoder))
4131  Inst.addOperand(MCOperand::createImm(imm32));
4132  return MCDisassembler::Success;
4133 }
4134 
4135 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4136  uint64_t Address, const void *Decoder) {
4137  if (Val & ~0xf)
4138  return MCDisassembler::Fail;
4139 
4140  Inst.addOperand(MCOperand::createImm(Val));
4141  return MCDisassembler::Success;
4142 }
4143 
4145  uint64_t Address, const void *Decoder) {
4146  if (Val & ~0xf)
4147  return MCDisassembler::Fail;
4148 
4149  Inst.addOperand(MCOperand::createImm(Val));
4150  return MCDisassembler::Success;
4151 }
4152 
4153 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4154  uint64_t Address, const void *Decoder) {
4156  const FeatureBitset &FeatureBits =
4157  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4158 
4159  if (FeatureBits[ARM::FeatureMClass]) {
4160  unsigned ValLow = Val & 0xff;
4161 
4162  // Validate the SYSm value first.
4163  switch (ValLow) {
4164  case 0: // apsr
4165  case 1: // iapsr
4166  case 2: // eapsr
4167  case 3: // xpsr
4168  case 5: // ipsr
4169  case 6: // epsr
4170  case 7: // iepsr
4171  case 8: // msp
4172  case 9: // psp
4173  case 16: // primask
4174  case 20: // control
4175  break;
4176  case 17: // basepri
4177  case 18: // basepri_max
4178  case 19: // faultmask
4179  if (!(FeatureBits[ARM::HasV7Ops]))
4180  // Values basepri, basepri_max and faultmask are only valid for v7m.
4181  return MCDisassembler::Fail;
4182  break;
4183  case 0x8a: // msplim_ns
4184  case 0x8b: // psplim_ns
4185  case 0x91: // basepri_ns
4186  case 0x93: // faultmask_ns
4187  if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4188  return MCDisassembler::Fail;
4190  case 10: // msplim
4191  case 11: // psplim
4192  case 0x88: // msp_ns
4193  case 0x89: // psp_ns
4194  case 0x90: // primask_ns
4195  case 0x94: // control_ns
4196  case 0x98: // sp_ns
4197  if (!(FeatureBits[ARM::Feature8MSecExt]))
4198  return MCDisassembler::Fail;
4199  break;
4200  default:
4201  // Architecturally defined as unpredictable
4203  break;
4204  }
4205 
4206  if (Inst.getOpcode() == ARM::t2MSR_M) {
4207  unsigned Mask = fieldFromInstruction(Val, 10, 2);
4208  if (!(FeatureBits[ARM::HasV7Ops])) {
4209  // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4210  // unpredictable.
4211  if (Mask != 2)
4213  }
4214  else {
4215  // The ARMv7-M architecture stores an additional 2-bit mask value in
4216  // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4217  // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4218  // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4219  // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4220  // only if the processor includes the DSP extension.
4221  if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4222  (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4224  }
4225  }
4226  } else {
4227  // A/R class
4228  if (Val == 0)
4229  return MCDisassembler::Fail;
4230  }
4231  Inst.addOperand(MCOperand::createImm(Val));
4232  return S;
4233 }
4234 
4235 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4236  uint64_t Address, const void *Decoder) {
4237  unsigned R = fieldFromInstruction(Val, 5, 1);
4238  unsigned SysM = fieldFromInstruction(Val, 0, 5);
4239 
4240  // The table of encodings for these banked registers comes from B9.2.3 of the
4241  // ARM ARM. There are patterns, but nothing regular enough to make this logic
4242  // neater. So by fiat, these values are UNPREDICTABLE:
4243  if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4244  return MCDisassembler::Fail;
4245 
4246  Inst.addOperand(MCOperand::createImm(Val));
4247  return MCDisassembler::Success;
4248 }
4249 
4250 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4251  uint64_t Address, const void *Decoder) {
4253 
4254  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4255  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4256  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4257 
4258  if (Rn == 0xF)
4260 
4261  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4262  return MCDisassembler::Fail;
4263  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4264  return MCDisassembler::Fail;
4265  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4266  return MCDisassembler::Fail;
4267 
4268  return S;
4269 }
4270 
4271 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4272  uint64_t Address,
4273  const void *Decoder) {
4275 
4276  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4277  unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4278  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4279  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4280 
4281  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4282  return MCDisassembler::Fail;
4283 
4284  if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4286 
4287  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4288  return MCDisassembler::Fail;
4289  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4290  return MCDisassembler::Fail;
4291  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4292  return MCDisassembler::Fail;
4293 
4294  return S;
4295 }
4296 
4297 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4298  uint64_t Address, const void *Decoder) {
4300 
4301  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4302  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4303  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4304  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4305  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4306  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4307 
4308  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4309 
4310  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4311  return MCDisassembler::Fail;
4312  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4313  return MCDisassembler::Fail;
4314  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4315  return MCDisassembler::Fail;
4316  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4317  return MCDisassembler::Fail;
4318 
4319  return S;
4320 }
4321 
4322 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4323  uint64_t Address, const void *Decoder) {
4325 
4326  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4327  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4328  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4329  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4330  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4331  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4332  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4333 
4334  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4335  if (Rm == 0xF) S = MCDisassembler::SoftFail;
4336 
4337  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4338  return MCDisassembler::Fail;
4339  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4340  return MCDisassembler::Fail;
4341  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4342  return MCDisassembler::Fail;
4343  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4344  return MCDisassembler::Fail;
4345 
4346  return S;
4347 }
4348 
4349 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4350  uint64_t Address, const void *Decoder) {
4352 
4353  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4354  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4355  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4356  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4357  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4358  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4359 
4360  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4361 
4362  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4363  return MCDisassembler::Fail;
4364  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4365  return MCDisassembler::Fail;
4366  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4367  return MCDisassembler::Fail;
4368  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4369  return MCDisassembler::Fail;
4370 
4371  return S;
4372 }
4373 
4374 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4375  uint64_t Address, const void *Decoder) {
4377 
4378  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4379  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4380  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4381  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4382  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4383  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4384 
4385  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4386 
4387  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4388  return MCDisassembler::Fail;
4389  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4390  return MCDisassembler::Fail;
4391  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4392  return MCDisassembler::Fail;
4393  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4394  return MCDisassembler::Fail;
4395 
4396  return S;
4397 }
4398 
4399 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4400  uint64_t Address, const void *Decoder) {
4402 
4403  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4404  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4405  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4406  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4407  unsigned size = fieldFromInstruction(Insn, 10, 2);
4408 
4409  unsigned align = 0;
4410  unsigned index = 0;
4411  switch (size) {
4412  default:
4413  return MCDisassembler::Fail;
4414  case 0:
4415  if (fieldFromInstruction(Insn, 4, 1))
4416  return MCDisassembler::Fail; // UNDEFINED
4417  index = fieldFromInstruction(Insn, 5, 3);
4418  break;
4419  case 1:
4420  if (fieldFromInstruction(Insn, 5, 1))
4421  return MCDisassembler::Fail; // UNDEFINED
4422  index = fieldFromInstruction(Insn, 6, 2);
4423  if (fieldFromInstruction(Insn, 4, 1))
4424  align = 2;
4425  break;
4426  case 2:
4427  if (fieldFromInstruction(Insn, 6, 1))
4428  return MCDisassembler::Fail; // UNDEFINED
4429  index = fieldFromInstruction(Insn, 7, 1);
4430 
4431  switch (fieldFromInstruction(Insn, 4, 2)) {
4432  case 0 :
4433  align = 0; break;
4434  case 3:
4435  align = 4; break;
4436  default:
4437  return MCDisassembler::Fail;
4438  }
4439  break;
4440  }
4441 
4442  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4443  return MCDisassembler::Fail;
4444  if (Rm != 0xF) { // Writeback
4445  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4446  return MCDisassembler::Fail;
4447  }
4448  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4449  return MCDisassembler::Fail;
4450  Inst.addOperand(MCOperand::createImm(align));
4451  if (Rm != 0xF) {
4452  if (Rm != 0xD) {
4453  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4454  return MCDisassembler::Fail;
4455  } else
4457  }
4458 
4459  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4460  return MCDisassembler::Fail;
4461  Inst.addOperand(MCOperand::createImm(index));
4462 
4463  return S;
4464 }
4465 
4466 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4467  uint64_t Address, const void *Decoder) {
4469 
4470  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4471  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4472  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4473  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4474  unsigned size = fieldFromInstruction(Insn, 10, 2);
4475 
4476  unsigned align = 0;
4477  unsigned index = 0;
4478  switch (size) {
4479  default:
4480  return MCDisassembler::Fail;
4481  case 0:
4482  if (fieldFromInstruction(Insn, 4, 1))
4483  return MCDisassembler::Fail; // UNDEFINED
4484  index = fieldFromInstruction(Insn, 5, 3);
4485  break;
4486  case 1:
4487  if (fieldFromInstruction(Insn, 5, 1))
4488  return MCDisassembler::Fail; // UNDEFINED
4489  index = fieldFromInstruction(Insn, 6, 2);
4490  if (fieldFromInstruction(Insn, 4, 1))
4491  align = 2;
4492  break;
4493  case 2:
4494  if (fieldFromInstruction(Insn, 6, 1))
4495  return MCDisassembler::Fail; // UNDEFINED
4496  index = fieldFromInstruction(Insn, 7, 1);
4497 
4498  switch (fieldFromInstruction(Insn, 4, 2)) {
4499  case 0:
4500  align = 0; break;
4501  case 3:
4502  align = 4; break;
4503  default:
4504  return MCDisassembler::Fail;
4505  }
4506  break;
4507  }
4508 
4509  if (Rm != 0xF) { // Writeback
4510  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4511  return MCDisassembler::Fail;
4512  }
4513  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4514  return MCDisassembler::Fail;
4515  Inst.addOperand(MCOperand::createImm(align));
4516  if (Rm != 0xF) {
4517  if (Rm != 0xD) {
4518  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4519  return MCDisassembler::Fail;
4520  } else
4522  }
4523 
4524  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4525  return MCDisassembler::Fail;
4526  Inst.addOperand(MCOperand::createImm(index));
4527 
4528  return S;
4529 }
4530 
4531 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4532  uint64_t Address, const void *Decoder) {
4534 
4535  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4536  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4537  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4538  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4539  unsigned size = fieldFromInstruction(Insn, 10, 2);
4540 
4541  unsigned align = 0;
4542  unsigned index = 0;
4543  unsigned inc = 1;
4544  switch (size) {
4545  default:
4546  return MCDisassembler::Fail;
4547  case 0:
4548  index = fieldFromInstruction(Insn, 5, 3);
4549  if (fieldFromInstruction(Insn, 4, 1))
4550  align = 2;
4551  break;
4552  case 1:
4553  index = fieldFromInstruction(Insn, 6, 2);
4554  if (fieldFromInstruction(Insn, 4, 1))
4555  align = 4;
4556  if (fieldFromInstruction(Insn, 5, 1))
4557  inc = 2;
4558  break;
4559  case 2:
4560  if (fieldFromInstruction(Insn, 5, 1))
4561  return MCDisassembler::Fail; // UNDEFINED
4562  index = fieldFromInstruction(Insn, 7, 1);
4563  if (fieldFromInstruction(Insn, 4, 1) != 0)
4564  align = 8;
4565  if (fieldFromInstruction(Insn, 6, 1))
4566  inc = 2;
4567  break;
4568  }
4569 
4570  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4571  return MCDisassembler::Fail;
4572  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4573  return MCDisassembler::Fail;
4574  if (Rm != 0xF) { // Writeback
4575  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4576  return MCDisassembler::Fail;
4577  }
4578  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4579  return MCDisassembler::Fail;
4580  Inst.addOperand(MCOperand::createImm(align));
4581  if (Rm != 0xF) {
4582  if (Rm != 0xD) {
4583  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4584  return MCDisassembler::Fail;
4585  } else
4587  }
4588 
4589  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4590  return MCDisassembler::Fail;
4591  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4592  return MCDisassembler::Fail;
4593  Inst.addOperand(MCOperand::createImm(index));
4594 
4595  return S;
4596 }
4597 
4598 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4599  uint64_t Address, const void *Decoder) {
4601 
4602  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4603  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4604  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4605  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4606  unsigned size = fieldFromInstruction(Insn, 10, 2);
4607 
4608  unsigned align = 0;
4609  unsigned index = 0;
4610  unsigned inc = 1;
4611  switch (size) {
4612  default:
4613  return MCDisassembler::Fail;
4614  case 0:
4615  index = fieldFromInstruction(Insn, 5, 3);
4616  if (fieldFromInstruction(Insn, 4, 1))
4617  align = 2;
4618  break;
4619  case 1:
4620  index = fieldFromInstruction(Insn, 6, 2);
4621  if (fieldFromInstruction(Insn, 4, 1))
4622  align = 4;
4623  if (fieldFromInstruction(Insn, 5, 1))
4624  inc = 2;
4625  break;
4626  case 2:
4627  if (fieldFromInstruction(Insn, 5, 1))
4628  return MCDisassembler::Fail; // UNDEFINED
4629  index = fieldFromInstruction(Insn, 7, 1);
4630  if (fieldFromInstruction(Insn, 4, 1) != 0)
4631  align = 8;
4632  if (fieldFromInstruction(Insn, 6, 1))
4633  inc = 2;
4634  break;
4635  }
4636 
4637  if (Rm != 0xF) { // Writeback
4638  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4639  return MCDisassembler::Fail;
4640  }
4641  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4642  return MCDisassembler::Fail;
4643  Inst.addOperand(MCOperand::createImm(align));
4644  if (Rm != 0xF) {
4645  if (Rm != 0xD) {
4646  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4647  return MCDisassembler::Fail;
4648  } else
4650  }
4651 
4652  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4653  return MCDisassembler::Fail;
4654  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4655  return MCDisassembler::Fail;
4656  Inst.addOperand(MCOperand::createImm(index));
4657 
4658  return S;
4659 }
4660 
4661 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4662  uint64_t Address, const void *Decoder) {
4664 
4665  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4666  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4667  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4668  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4669  unsigned size = fieldFromInstruction(Insn, 10, 2);
4670 
4671  unsigned align = 0;
4672  unsigned index = 0;
4673  unsigned inc = 1;
4674  switch (size) {
4675  default:
4676  return MCDisassembler::Fail;
4677  case 0:
4678  if (fieldFromInstruction(Insn, 4, 1))
4679  return MCDisassembler::Fail; // UNDEFINED
4680  index = fieldFromInstruction(Insn, 5, 3);
4681  break;
4682  case 1:
4683  if (fieldFromInstruction(Insn, 4, 1))
4684  return MCDisassembler::Fail; // UNDEFINED
4685  index = fieldFromInstruction(Insn, 6, 2);
4686  if (fieldFromInstruction(Insn, 5, 1))
4687  inc = 2;
4688  break;
4689  case 2:
4690  if (fieldFromInstruction(Insn, 4, 2))
4691  return MCDisassembler::Fail; // UNDEFINED
4692  index = fieldFromInstruction(Insn, 7, 1);
4693  if (fieldFromInstruction(Insn, 6, 1))
4694  inc = 2;
4695  break;
4696  }
4697 
4698  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4699  return MCDisassembler::Fail;
4700  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4701  return MCDisassembler::Fail;
4702  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4703  return MCDisassembler::Fail;
4704 
4705  if (Rm != 0xF) { // Writeback
4706  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4707  return MCDisassembler::Fail;
4708  }
4709  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4710  return MCDisassembler::Fail;
4711  Inst.addOperand(MCOperand::createImm(align));
4712  if (Rm != 0xF) {
4713  if (Rm != 0xD) {
4714  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4715  return MCDisassembler::Fail;
4716  } else
4718  }
4719 
4720  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4721  return MCDisassembler::Fail;
4722  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4723  return MCDisassembler::Fail;
4724  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4725  return MCDisassembler::Fail;
4726  Inst.addOperand(MCOperand::createImm(index));
4727 
4728  return S;
4729 }
4730 
4731 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4732  uint64_t Address, const void *Decoder) {
4734 
4735  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4736  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4737  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4738  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4739  unsigned size = fieldFromInstruction(Insn, 10, 2);
4740 
4741  unsigned align = 0;
4742  unsigned index = 0;
4743  unsigned inc = 1;
4744  switch (size) {
4745  default:
4746  return MCDisassembler::Fail;
4747  case 0:
4748  if (fieldFromInstruction(Insn, 4, 1))
4749  return MCDisassembler::Fail; // UNDEFINED
4750  index = fieldFromInstruction(Insn, 5, 3);
4751  break;
4752  case 1:
4753  if (fieldFromInstruction(Insn, 4, 1))
4754  return MCDisassembler::Fail; // UNDEFINED
4755  index = fieldFromInstruction(Insn, 6, 2);
4756  if (fieldFromInstruction(Insn, 5, 1))
4757  inc = 2;
4758  break;
4759  case 2:
4760  if (fieldFromInstruction(Insn, 4, 2))
4761  return MCDisassembler::Fail; // UNDEFINED
4762  index = fieldFromInstruction(Insn, 7, 1);
4763  if (fieldFromInstruction(Insn, 6, 1))
4764  inc = 2;
4765  break;
4766  }
4767 
4768  if (Rm != 0xF) { // Writeback
4769  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4770  return MCDisassembler::Fail;
4771  }
4772  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4773  return MCDisassembler::Fail;
4774  Inst.addOperand(MCOperand::createImm(align));
4775  if (Rm != 0xF) {
4776  if (Rm != 0xD) {
4777  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4778  return MCDisassembler::Fail;
4779  } else
4781  }
4782 
4783  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4784  return MCDisassembler::Fail;
4785  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4786  return MCDisassembler::Fail;
4787  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4788  return MCDisassembler::Fail;
4789  Inst.addOperand(MCOperand::createImm(index));
4790 
4791  return S;
4792 }
4793 
4794 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4795  uint64_t Address, const void *Decoder) {
4797 
4798  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4799  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4800  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4801  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4802  unsigned size = fieldFromInstruction(Insn, 10, 2);
4803 
4804  unsigned align = 0;
4805  unsigned index = 0;
4806  unsigned inc = 1;
4807  switch (size) {
4808  default:
4809  return MCDisassembler::Fail;
4810  case 0:
4811  if (fieldFromInstruction(Insn, 4, 1))
4812  align = 4;
4813  index = fieldFromInstruction(Insn, 5, 3);
4814  break;
4815  case 1:
4816  if (fieldFromInstruction(Insn, 4, 1))
4817  align = 8;
4818  index = fieldFromInstruction(Insn, 6, 2);
4819  if (fieldFromInstruction(Insn, 5, 1))
4820  inc = 2;
4821  break;
4822  case 2:
4823  switch (fieldFromInstruction(Insn, 4, 2)) {
4824  case 0:
4825  align = 0; break;
4826  case 3:
4827  return MCDisassembler::Fail;
4828  default:
4829  align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4830  }
4831 
4832  index = fieldFromInstruction(Insn, 7, 1);
4833  if (fieldFromInstruction(Insn, 6, 1))
4834  inc = 2;
4835  break;
4836  }
4837 
4838  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4839  return MCDisassembler::Fail;
4840  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4841  return MCDisassembler::Fail;
4842  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4843  return MCDisassembler::Fail;
4844  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4845  return MCDisassembler::Fail;
4846 
4847  if (Rm != 0xF) { // Writeback
4848  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4849  return MCDisassembler::Fail;
4850  }
4851  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4852  return MCDisassembler::Fail;
4853  Inst.addOperand(MCOperand::createImm(align));
4854  if (Rm != 0xF) {
4855  if (Rm != 0xD) {
4856  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4857  return MCDisassembler::Fail;
4858  } else
4860  }
4861 
4862  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4863  return MCDisassembler::Fail;
4864  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4865  return MCDisassembler::Fail;
4866  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4867  return MCDisassembler::Fail;
4868  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4869  return MCDisassembler::Fail;
4870  Inst.addOperand(MCOperand::createImm(index));
4871 
4872  return S;
4873 }
4874 
4875 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4876  uint64_t Address, const void *Decoder) {
4878 
4879  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4880  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4881  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4882  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4883  unsigned size = fieldFromInstruction(Insn, 10, 2);
4884 
4885  unsigned align = 0;
4886  unsigned index = 0;
4887  unsigned inc = 1;
4888  switch (size) {
4889  default:
4890  return MCDisassembler::Fail;
4891  case 0:
4892  if (fieldFromInstruction(Insn, 4, 1))
4893  align = 4;
4894  index = fieldFromInstruction(Insn, 5, 3);
4895  break;
4896  case 1:
4897  if (fieldFromInstruction(Insn, 4, 1))
4898  align = 8;
4899  index = fieldFromInstruction(Insn, 6, 2);
4900  if (fieldFromInstruction(Insn, 5, 1))
4901  inc = 2;
4902  break;
4903  case 2:
4904  switch (fieldFromInstruction(Insn, 4, 2)) {
4905  case 0:
4906  align = 0; break;
4907  case 3:
4908  return MCDisassembler::Fail;
4909  default:
4910  align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4911  }
4912 
4913  index = fieldFromInstruction(Insn, 7, 1);
4914  if (fieldFromInstruction(Insn, 6, 1))
4915  inc = 2;
4916  break;
4917  }
4918 
4919  if (Rm != 0xF) { // Writeback
4920  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4921  return MCDisassembler::Fail;
4922  }
4923  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4924  return MCDisassembler::Fail;
4925  Inst.addOperand(MCOperand::createImm(align));
4926  if (Rm != 0xF) {
4927  if (Rm != 0xD) {
4928  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4929  return MCDisassembler::Fail;
4930  } else
4932  }
4933 
4934  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4935  return MCDisassembler::Fail;
4936  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4937  return MCDisassembler::Fail;
4938  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4939  return MCDisassembler::Fail;
4940  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4941  return MCDisassembler::Fail;
4942  Inst.addOperand(MCOperand::createImm(index));
4943 
4944  return S;
4945 }
4946 
4947 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4948  uint64_t Address, const void *Decoder) {
4950  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4951  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4952  unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4953  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4954  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4955 
4956  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4958 
4959  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4960  return MCDisassembler::Fail;
4961  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4962  return MCDisassembler::Fail;
4963  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4964  return MCDisassembler::Fail;
4965  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4966  return MCDisassembler::Fail;
4967  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4968  return MCDisassembler::Fail;
4969 
4970  return S;
4971 }
4972 
4973 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4974  uint64_t Address, const void *Decoder) {
4976  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4977  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4978  unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4979  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4980  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4981 
4982  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4984 
4985  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4986  return MCDisassembler::Fail;
4987  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4988  return MCDisassembler::Fail;
4989  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4990  return MCDisassembler::Fail;
4991  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4992  return MCDisassembler::Fail;
4993  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4994  return MCDisassembler::Fail;
4995 
4996  return S;
4997 }
4998 
4999 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
5000  uint64_t Address, const void *Decoder) {
5002  unsigned pred = fieldFromInstruction(Insn, 4, 4);
5003  unsigned mask = fieldFromInstruction(Insn, 0, 4);
5004 
5005  if (pred == 0xF) {
5006  pred = 0xE;
5008  }
5009 
5010  if (mask == 0x0)
5011  return MCDisassembler::Fail;
5012 
5013  Inst.addOperand(MCOperand::createImm(pred));
5014  Inst.addOperand(MCOperand::createImm(mask));
5015  return S;
5016 }
5017 
5018 static DecodeStatus
5019 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5020  uint64_t Address, const void *Decoder) {
5022 
5023  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5024  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5025  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5026  unsigned addr = fieldFromInstruction(Insn, 0, 8);
5027  unsigned W = fieldFromInstruction(Insn, 21, 1);
5028  unsigned U = fieldFromInstruction(Insn, 23, 1);
5029  unsigned P = fieldFromInstruction(Insn, 24, 1);
5030  bool writeback = (W == 1) | (P == 0);
5031 
5032  addr |= (U << 8) | (Rn << 9);
5033 
5034  if (writeback && (Rn == Rt || Rn == Rt2))
5036  if (Rt == Rt2)
5038 
5039  // Rt
5040  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5041  return MCDisassembler::Fail;
5042  // Rt2
5043  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5044  return MCDisassembler::Fail;
5045  // Writeback operand
5046  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5047  return MCDisassembler::Fail;
5048  // addr
5049  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5050  return MCDisassembler::Fail;
5051 
5052  return S;
5053 }
5054 
5055 static DecodeStatus
5056 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5057  uint64_t Address, const void *Decoder) {
5059 
5060  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5061  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5062  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5063  unsigned addr = fieldFromInstruction(Insn, 0, 8);
5064  unsigned W = fieldFromInstruction(Insn, 21, 1);
5065  unsigned U = fieldFromInstruction(Insn, 23, 1);
5066  unsigned P = fieldFromInstruction(Insn, 24, 1);
5067  bool writeback = (W == 1) | (P == 0);
5068 
5069  addr |= (U << 8) | (Rn << 9);
5070 
5071  if (writeback && (Rn == Rt || Rn == Rt2))
5073 
5074  // Writeback operand
5075  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5076  return MCDisassembler::Fail;
5077  // Rt
5078  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5079  return MCDisassembler::Fail;
5080  // Rt2
5081  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5082  return MCDisassembler::Fail;
5083  // addr
5084  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5085  return MCDisassembler::Fail;
5086 
5087  return S;
5088 }
5089 
5091  uint64_t Address, const void *Decoder) {
5092  unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5093  unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5094  if (sign1 != sign2) return MCDisassembler::Fail;
5095 
5096  unsigned Val = fieldFromInstruction(Insn, 0, 8);
5097  Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5098  Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5099  Val |= sign1 << 12;
5100  Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5101 
5102  return MCDisassembler::Success;
5103 }
5104 
5106  uint64_t Address,
5107  const void *Decoder) {
5109 
5110  // Shift of "asr #32" is not allowed in Thumb2 mode.
5111  if (Val == 0x20) S = MCDisassembler::Fail;
5112  Inst.addOperand(MCOperand::createImm(Val));
5113  return S;
5114 }
5115 
5116 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5117  uint64_t Address, const void *Decoder) {
5118  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5119  unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5120  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5121  unsigned pred = fieldFromInstruction(Insn, 28, 4);
5122 
5123  if (pred == 0xF)
5124  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5125 
5127 
5128  if (Rt == Rn || Rn == Rt2)
5130 
5131  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5132  return MCDisassembler::Fail;
5133  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5134  return MCDisassembler::Fail;
5135  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5136  return MCDisassembler::Fail;
5137  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5138  return MCDisassembler::Fail;
5139 
5140  return S;
5141 }
5142 
5143 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5144  uint64_t Address, const void *Decoder) {
5145  const FeatureBitset &featureBits =
5146  ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5147  bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5148 
5149  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5150  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5151  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5152  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5153  unsigned imm = fieldFromInstruction(Insn, 16, 6);
5154  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5155  unsigned op = fieldFromInstruction(Insn, 5, 1);
5156 
5158 
5159  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5160  if (!(imm & 0x38)) {
5161  if (cmode == 0xF) {
5162  if (op == 1) return MCDisassembler::Fail;
5163  Inst.setOpcode(ARM::VMOVv2f32);
5164  }
5165  if (hasFullFP16) {
5166  if (cmode == 0xE) {
5167  if (op == 1) {
5168  Inst.setOpcode(ARM::VMOVv1i64);
5169  } else {
5170  Inst.setOpcode(ARM::VMOVv8i8);
5171  }
5172  }
5173  if (cmode == 0xD) {
5174  if (op == 1) {
5175  Inst.setOpcode(ARM::VMVNv2i32);
5176  } else {
5177  Inst.setOpcode(ARM::VMOVv2i32);
5178  }
5179  }
5180  if (cmode == 0xC) {
5181  if (op == 1) {
5182  Inst.setOpcode(ARM::VMVNv2i32);
5183  } else {
5184  Inst.setOpcode(ARM::VMOVv2i32);
5185  }
5186  }
5187  }
5188  return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5189  }
5190 
5191  if (!(imm & 0x20)) return MCDisassembler::Fail;
5192 
5193  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5194  return