34 #define DEBUG_TYPE "arm-disassembler"
53 void advanceITState() {
58 bool instrInITBlock() {
59 return !ITStates.empty();
63 bool instrLastInITBlock() {
64 return ITStates.size() == 1;
71 void setITState(
char Firstcond,
char Mask) {
73 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
74 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
75 assert(NumTZ <= 3 &&
"Invalid IT mask!");
77 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
79 ITStates.push_back(CCBits ^
Else);
81 ITStates.push_back(CCBits);
85 std::vector<unsigned char> ITStates;
91 unsigned getVPTPred() {
93 if (instrInVPTBlock())
94 Pred = VPTStates.back();
98 void advanceVPTState() {
102 bool instrInVPTBlock() {
103 return !VPTStates.empty();
106 bool instrLastInVPTBlock() {
107 return VPTStates.size() == 1;
110 void setVPTState(
char Mask) {
112 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
113 assert(NumTZ <= 3 &&
"Invalid VPT mask!");
115 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116 bool T = ((
Mask >> Pos) & 1) == 0;
136 ~ARMDisassembler()
override =
default;
151 mutable ITStatus ITBlock;
152 mutable VPTStatus VPTBlock;
178 uint64_t Address,
const void *Decoder);
180 uint64_t Address,
const void *Decoder);
182 uint64_t Address,
const void *Decoder);
184 uint64_t Address,
const void *Decoder);
187 uint64_t Address,
const void *Decoder);
190 const void *Decoder);
193 const void *Decoder);
196 const void *Decoder);
198 MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
200 uint64_t Address,
const void *Decoder);
202 uint64_t Address,
const void *Decoder);
204 uint64_t Address,
const void *Decoder);
206 uint64_t Address,
const void *Decoder);
208 uint64_t Address,
const void *Decoder);
211 const void *Decoder);
213 uint64_t Address,
const void *Decoder);
215 uint64_t Address,
const void *Decoder);
217 uint64_t Address,
const void *Decoder);
219 uint64_t Address,
const void *Decoder);
221 uint64_t Address,
const void *Decoder);
225 const void *Decoder);
227 uint64_t Address,
const void *Decoder);
229 uint64_t Address,
const void *Decoder);
232 const void *Decoder);
235 const void *Decoder);
237 uint64_t Address,
const void *Decoder);
240 const void *Decoder);
243 uint64_t Address,
const void *Decoder);
245 uint64_t Address,
const void *Decoder);
247 uint64_t Address,
const void *Decoder);
249 uint64_t Address,
const void *Decoder);
251 uint64_t Address,
const void *Decoder);
254 uint64_t Address,
const void *Decoder);
256 uint64_t Address,
const void *Decoder);
260 const void *Decoder);
262 uint64_t Address,
const void *Decoder);
264 uint64_t Address,
const void *Decoder);
266 uint64_t Address,
const void *Decoder);
268 uint64_t Address,
const void *Decoder);
273 const void *Decoder);
275 uint64_t Address,
const void *Decoder);
277 uint64_t Address,
const void *Decoder);
279 uint64_t Address,
const void *Decoder);
281 uint64_t Address,
const void *Decoder);
283 uint64_t Address,
const void *Decoder);
285 uint64_t Address,
const void *Decoder);
287 uint64_t Address,
const void *Decoder);
289 uint64_t Address,
const void *Decoder);
291 uint64_t Address,
const void *Decoder);
293 uint64_t Address,
const void *Decoder);
295 uint64_t Address,
const void *Decoder);
297 uint64_t Address,
const void *Decoder);
299 uint64_t Address,
const void *Decoder);
301 uint64_t Address,
const void *Decoder);
303 uint64_t Address,
const void *Decoder);
305 uint64_t Address,
const void *Decoder);
307 uint64_t Address,
const void *Decoder);
309 uint64_t Address,
const void *Decoder);
311 uint64_t Address,
const void *Decoder);
313 uint64_t Address,
const void *Decoder);
315 uint64_t Address,
const void *Decoder);
317 uint64_t Address,
const void *Decoder);
319 uint64_t Address,
const void *Decoder);
321 uint64_t Address,
const void *Decoder);
323 uint64_t Address,
const void *Decoder);
325 uint64_t Address,
const void *Decoder);
327 uint64_t Address,
const void *Decoder);
329 uint64_t Address,
const void *Decoder);
331 uint64_t Address,
const void *Decoder);
333 uint64_t Address,
const void *Decoder);
335 uint64_t Address,
const void *Decoder);
337 uint64_t Address,
const void *Decoder);
339 uint64_t Address,
const void *Decoder);
341 uint64_t Address,
const void *Decoder);
343 uint64_t Address,
const void *Decoder);
345 uint64_t Address,
const void *Decoder);
348 uint64_t Address,
const void *Decoder);
350 uint64_t Address,
const void *Decoder);
352 uint64_t Address,
const void *Decoder);
354 uint64_t Address,
const void *Decoder);
356 uint64_t Address,
const void *Decoder);
358 uint64_t Address,
const void *Decoder);
360 uint64_t Address,
const void *Decoder);
362 uint64_t Address,
const void *Decoder);
364 uint64_t Address,
const void *Decoder);
366 uint64_t Address,
const void *Decoder);
368 uint64_t Address,
const void *Decoder);
370 uint64_t Address,
const void *Decoder);
372 uint64_t Address,
const void *Decoder);
374 uint64_t Address,
const void *Decoder);
376 uint64_t Address,
const void *Decoder);
378 uint64_t Address,
const void *Decoder);
380 uint64_t Address,
const void *Decoder);
382 uint64_t Address,
const void *Decoder);
384 uint64_t Address,
const void *Decoder);
386 uint64_t Address,
const void *Decoder);
388 uint64_t Address,
const void *Decoder);
390 uint64_t Address,
const void *Decoder);
392 uint64_t Address,
const void *Decoder);
394 uint64_t Address,
const void *Decoder);
396 uint64_t Address,
const void *Decoder);
398 uint64_t Address,
const void *Decoder);
402 const void *Decoder);
405 uint64_t Address,
const void *Decoder);
407 uint64_t Address,
const void *Decoder);
409 uint64_t Address,
const void *Decoder);
411 uint64_t Address,
const void *Decoder);
413 uint64_t Address,
const void *Decoder);
415 uint64_t Address,
const void *Decoder);
417 uint64_t Address,
const void *Decoder);
419 uint64_t Address,
const void *Decoder);
421 uint64_t Address,
const void *Decoder);
423 uint64_t Address,
const void *Decoder);
425 uint64_t Address,
const void* Decoder);
427 uint64_t Address,
const void* Decoder);
429 uint64_t Address,
const void* Decoder);
431 uint64_t Address,
const void* Decoder);
433 uint64_t Address,
const void *Decoder);
435 uint64_t Address,
const void *Decoder);
437 uint64_t Address,
const void *Decoder);
440 const void *Decoder);
442 uint64_t Address,
const void *Decoder);
444 uint64_t Address,
const void *Decoder);
447 uint64_t Address,
const void *Decoder);
449 uint64_t Address,
const void *Decoder);
452 uint64_t Address,
const void *Decoder);
453 template<
int shift,
int WriteBack>
455 uint64_t Address,
const void *Decoder);
457 uint64_t Address,
const void *Decoder);
459 uint64_t Address,
const void *Decoder);
461 uint64_t Address,
const void *Decoder);
463 uint64_t Address,
const void *Decoder);
465 uint64_t Address,
const void *Decoder);
467 uint64_t Address,
const void *Decoder);
469 uint64_t Address,
const void *Decoder);
471 uint64_t Address,
const void *Decoder);
473 uint64_t Address,
const void *Decoder);
475 uint64_t Address,
const void *Decoder);
477 uint64_t Address,
const void *Decoder);
479 uint64_t Address,
const void *Decoder);
481 uint64_t Address,
const void *Decoder);
483 uint64_t Address,
const void *Decoder);
485 uint64_t Address,
const void *Decoder);
487 uint64_t Address,
const void *Decoder);
489 uint64_t Address,
const void *Decoder);
492 uint64_t Address,
const void *Decoder);
494 uint64_t Address,
const void *Decoder);
496 uint64_t Address,
const void *Decoder);
498 template <
bool isSigned,
bool isNeg,
bool zeroPermitted,
int size>
500 uint64_t Address,
const void *Decoder);
503 const void *Decoder);
506 const void *Decoder);
508 const void *Decoder);
511 const void *Decoder);
513 const void *Decoder);
515 uint64_t Address,
const void *Decoder);
517 uint64_t Address,
const void *Decoder);
520 const void *Decoder);
523 const void *Decoder);
526 const void *Decoder);
530 const void *Decoder);
531 template<
bool Writeback>
534 const void *Decoder);
537 uint64_t Address,
const void *Decoder);
540 uint64_t Address,
const void *Decoder);
543 uint64_t Address,
const void *Decoder);
544 template<
unsigned MinLog,
unsigned MaxLog>
547 const void *Decoder);
548 template<
unsigned start>
551 const void *Decoder);
554 const void *Decoder);
557 const void *Decoder);
559 uint64_t Address,
const void *Decoder);
561 uint64_t Address,
const void *Decoder);
562 template<
bool scalar, OperandDecoder predicate_decoder>
564 uint64_t Address,
const void *Decoder);
566 uint64_t Address,
const void *Decoder);
568 uint64_t Address,
const void *Decoder);
571 const void *Decoder);
573 uint64_t Address,
const void *Decoder);
575 #include "ARMGenDisassemblerTables.inc"
580 return new ARMDisassembler(STI, Ctx);
588 switch (
MI.getOpcode()) {
607 if (
MI.getOperand(0).getReg() == ARM::SP &&
608 MI.getOperand(1).getReg() != ARM::SP)
611 default:
return Result;
619 if (STI.getFeatureBits()[ARM::ModeThumb])
620 return getThumbInstruction(
MI,
Size, Bytes, Address, CS);
621 return getARMInstruction(
MI,
Size, Bytes, Address, CS);
630 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
631 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
635 if (Bytes.
size() < 4) {
642 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
646 decodeInstruction(DecoderTableARM32,
MI, Insn, Address,
this, STI);
657 const DecodeTable Tables[] = {
658 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
659 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
660 {DecoderTableNEONDup32,
true}, {DecoderTablev8NEON32,
false},
661 {DecoderTablev8Crypto32,
false},
664 for (
auto Table : Tables) {
665 Result = decodeInstruction(Table.P,
MI, Insn, Address,
this, STI);
677 decodeInstruction(DecoderTableCoProc32,
MI, Insn, Address,
this, STI);
724 const void *Decoder) {
737 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
738 if (
I ==
MI.end())
break;
739 if (OpInfo[
i].isOptionalDef() && OpInfo[
i].RegClass == ARM::CCRRegClassID) {
740 if (
i > 0 && OpInfo[
i-1].isPredicate())
continue;
752 for (
unsigned i = 0;
i < NumOps; ++
i) {
764 ARMDisassembler::AddThumbPredicate(
MCInst &
MI)
const {
767 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
771 switch (
MI.getOpcode()) {
788 if (ITBlock.instrInITBlock())
794 if (
MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
803 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
820 if (ITBlock.instrInITBlock()) {
821 CC = ITBlock.getITCC();
822 ITBlock.advanceITState();
823 }
else if (VPTBlock.instrInVPTBlock()) {
824 VCC = VPTBlock.getVPTPred();
825 VPTBlock.advanceVPTState();
832 for (
unsigned i = 0;
i < NumOps; ++
i, ++CCI) {
833 if (OpInfo[
i].isPredicate() || CCI ==
MI.end())
break;
849 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
867 "Inactive register in vpred_r is not tied to an output!");
883 void ARMDisassembler::UpdateThumbVFPPredicate(
886 CC = ITBlock.getITCC();
889 if (ITBlock.instrInITBlock())
890 ITBlock.advanceITState();
891 else if (VPTBlock.instrInVPTBlock()) {
892 CC = VPTBlock.getVPTPred();
893 VPTBlock.advanceVPTState();
899 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
900 if (OpInfo[
i].isPredicate() ) {
908 I->setReg(ARM::CPSR);
920 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
921 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
924 if (Bytes.
size() < 2) {
929 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
931 decodeInstruction(DecoderTableThumb16,
MI, Insn16, Address,
this, STI);
934 Check(Result, AddThumbPredicate(
MI));
938 Result = decodeInstruction(DecoderTableThumbSBit16,
MI, Insn16, Address,
this,
942 bool InITBlock = ITBlock.instrInITBlock();
943 Check(Result, AddThumbPredicate(
MI));
949 decodeInstruction(DecoderTableThumb216,
MI, Insn16, Address,
this, STI);
955 if (
MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
958 Check(Result, AddThumbPredicate(
MI));
963 if (
MI.getOpcode() == ARM::t2IT) {
964 unsigned Firstcond =
MI.getOperand(0).getImm();
965 unsigned Mask =
MI.getOperand(1).getImm();
966 ITBlock.setITState(Firstcond,
Mask);
970 CS <<
"unpredictable IT predicate sequence";
977 if (Bytes.
size() < 4) {
983 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
986 decodeInstruction(DecoderTableMVE32,
MI, Insn32, Address,
this, STI);
992 if (
isVPTOpcode(
MI.getOpcode()) && VPTBlock.instrInVPTBlock())
995 Check(Result, AddThumbPredicate(
MI));
998 unsigned Mask =
MI.getOperand(0).getImm();
999 VPTBlock.setVPTState(
Mask);
1006 decodeInstruction(DecoderTableThumb32,
MI, Insn32, Address,
this, STI);
1009 bool InITBlock = ITBlock.instrInITBlock();
1010 Check(Result, AddThumbPredicate(
MI));
1016 decodeInstruction(DecoderTableThumb232,
MI, Insn32, Address,
this, STI);
1019 Check(Result, AddThumbPredicate(
MI));
1023 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1025 decodeInstruction(DecoderTableVFP32,
MI, Insn32, Address,
this, STI);
1028 UpdateThumbVFPPredicate(Result,
MI);
1034 decodeInstruction(DecoderTableVFPV832,
MI, Insn32, Address,
this, STI);
1040 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1041 Result = decodeInstruction(DecoderTableNEONDup32,
MI, Insn32, Address,
this,
1045 Check(Result, AddThumbPredicate(
MI));
1050 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1052 NEONLdStInsn &= 0xF0FFFFFF;
1053 NEONLdStInsn |= 0x04000000;
1054 Result = decodeInstruction(DecoderTableNEONLoadStore32,
MI, NEONLdStInsn,
1055 Address,
this, STI);
1058 Check(Result, AddThumbPredicate(
MI));
1063 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1065 NEONDataInsn &= 0xF0FFFFFF;
1066 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
1067 NEONDataInsn |= 0x12000000;
1068 Result = decodeInstruction(DecoderTableNEONData32,
MI, NEONDataInsn,
1069 Address,
this, STI);
1072 Check(Result, AddThumbPredicate(
MI));
1077 NEONCryptoInsn &= 0xF0FFFFFF;
1078 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
1079 NEONCryptoInsn |= 0x12000000;
1080 Result = decodeInstruction(DecoderTablev8Crypto32,
MI, NEONCryptoInsn,
1081 Address,
this, STI);
1088 NEONv8Insn &= 0xF3FFFFFF;
1089 Result = decodeInstruction(DecoderTablev8NEON32,
MI, NEONv8Insn, Address,
1097 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1099 ? DecoderTableThumb2CDE32
1100 : DecoderTableThumb2CoProc32;
1102 decodeInstruction(DecoderTable,
MI, Insn32, Address,
this, STI);
1105 Check(Result, AddThumbPredicate(
MI));
1125 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1127 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1128 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1132 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
1134 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1135 ARM::R12, 0, ARM::LR, ARM::APSR
1139 uint64_t Address,
const void *Decoder) {
1150 const void *Decoder) {
1164 uint64_t Address,
const void *Decoder) {
1177 uint64_t Address,
const void *Decoder) {
1192 uint64_t Address,
const void *Decoder) {
1210 uint64_t Address,
const void *Decoder) {
1219 uint64_t Address,
const void *Decoder) {
1226 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1227 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1231 uint64_t Address,
const void *Decoder) {
1248 uint64_t Address,
const void *Decoder) {
1255 if ((RegNo & 1) || RegNo > 10)
1262 const void *Decoder) {
1272 uint64_t Address,
const void *Decoder) {
1302 uint64_t Address,
const void *Decoder) {
1306 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1308 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1316 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1317 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1318 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1319 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1320 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1321 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1322 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1323 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1327 uint64_t Address,
const void *Decoder) {
1337 uint64_t Address,
const void *Decoder) {
1342 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1343 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1344 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1345 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1346 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1347 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1348 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1349 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1353 uint64_t Address,
const void *Decoder) {
1355 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1357 bool hasD32 = featureBits[ARM::FeatureD32];
1359 if (RegNo > 31 || (!hasD32 && RegNo > 15))
1368 uint64_t Address,
const void *Decoder) {
1375 uint64_t Address,
const void *Decoder) {
1383 uint64_t Address,
const void *Decoder) {
1390 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1391 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1392 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1393 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1397 uint64_t Address,
const void *Decoder) {
1398 if (RegNo > 31 || (RegNo & 1) != 0)
1408 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1409 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1410 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1411 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1412 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1417 uint64_t Address,
const void *Decoder) {
1427 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1428 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1429 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1430 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1431 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1432 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1433 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1434 ARM::D28_D30, ARM::D29_D31
1440 const void *Decoder) {
1450 uint64_t Address,
const void *Decoder) {
1454 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1467 uint64_t Address,
const void *Decoder) {
1476 uint64_t Address,
const void *Decoder) {
1479 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1480 unsigned type = fieldFromInstruction(Val, 5, 2);
1481 unsigned imm = fieldFromInstruction(Val, 7, 5);
1506 unsigned Op =
Shift | (imm << 3);
1513 uint64_t Address,
const void *Decoder) {
1516 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1517 unsigned type = fieldFromInstruction(Val, 5, 2);
1518 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1548 uint64_t Address,
const void *Decoder) {
1551 bool NeedDisjointWriteback =
false;
1552 unsigned WritebackReg = 0;
1557 case ARM::LDMIA_UPD:
1558 case ARM::LDMDB_UPD:
1559 case ARM::LDMIB_UPD:
1560 case ARM::LDMDA_UPD:
1561 case ARM::t2LDMIA_UPD:
1562 case ARM::t2LDMDB_UPD:
1563 case ARM::t2STMIA_UPD:
1564 case ARM::t2STMDB_UPD:
1565 NeedDisjointWriteback =
true;
1575 for (
unsigned i = 0;
i < 16; ++
i) {
1576 if (Val & (1 <<
i)) {
1585 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1595 uint64_t Address,
const void *Decoder) {
1598 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1599 unsigned regs = fieldFromInstruction(Val, 0, 8);
1602 if (regs == 0 || (Vd + regs) > 32) {
1603 regs = Vd + regs > 32 ? 32 - Vd : regs;
1610 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1619 uint64_t Address,
const void *Decoder) {
1622 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1623 unsigned regs = fieldFromInstruction(Val, 1, 7);
1626 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1627 regs = Vd + regs > 32 ? 32 - Vd : regs;
1635 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1644 uint64_t Address,
const void *Decoder) {
1650 unsigned msb = fieldFromInstruction(Val, 5, 5);
1651 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1663 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1664 uint32_t lsb_mask = (1U << lsb) - 1;
1671 uint64_t Address,
const void *Decoder) {
1674 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1675 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1676 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1677 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1678 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1679 unsigned U = fieldFromInstruction(Insn, 23, 1);
1681 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1684 case ARM::LDC_OFFSET:
1687 case ARM::LDC_OPTION:
1688 case ARM::LDCL_OFFSET:
1690 case ARM::LDCL_POST:
1691 case ARM::LDCL_OPTION:
1692 case ARM::STC_OFFSET:
1695 case ARM::STC_OPTION:
1696 case ARM::STCL_OFFSET:
1698 case ARM::STCL_POST:
1699 case ARM::STCL_OPTION:
1700 case ARM::t2LDC_OFFSET:
1701 case ARM::t2LDC_PRE:
1702 case ARM::t2LDC_POST:
1703 case ARM::t2LDC_OPTION:
1704 case ARM::t2LDCL_OFFSET:
1705 case ARM::t2LDCL_PRE:
1706 case ARM::t2LDCL_POST:
1707 case ARM::t2LDCL_OPTION:
1708 case ARM::t2STC_OFFSET:
1709 case ARM::t2STC_PRE:
1710 case ARM::t2STC_POST:
1711 case ARM::t2STC_OPTION:
1712 case ARM::t2STCL_OFFSET:
1713 case ARM::t2STCL_PRE:
1714 case ARM::t2STCL_POST:
1715 case ARM::t2STCL_OPTION:
1716 case ARM::t2LDC2_OFFSET:
1717 case ARM::t2LDC2L_OFFSET:
1718 case ARM::t2LDC2_PRE:
1719 case ARM::t2LDC2L_PRE:
1720 case ARM::t2STC2_OFFSET:
1721 case ARM::t2STC2L_OFFSET:
1722 case ARM::t2STC2_PRE:
1723 case ARM::t2STC2L_PRE:
1724 case ARM::LDC2_OFFSET:
1725 case ARM::LDC2L_OFFSET:
1727 case ARM::LDC2L_PRE:
1728 case ARM::STC2_OFFSET:
1729 case ARM::STC2L_OFFSET:
1731 case ARM::STC2L_PRE:
1732 case ARM::t2LDC2_OPTION:
1733 case ARM::t2STC2_OPTION:
1734 case ARM::t2LDC2_POST:
1735 case ARM::t2LDC2L_POST:
1736 case ARM::t2STC2_POST:
1737 case ARM::t2STC2L_POST:
1738 case ARM::LDC2_POST:
1739 case ARM::LDC2L_POST:
1740 case ARM::STC2_POST:
1741 case ARM::STC2L_POST:
1742 if (coproc == 0xA || coproc == 0xB ||
1743 (featureBits[ARM::HasV8_1MMainlineOps] &&
1744 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1745 coproc == 0xE || coproc == 0xF)))
1752 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1761 case ARM::t2LDC2_OFFSET:
1762 case ARM::t2LDC2L_OFFSET:
1763 case ARM::t2LDC2_PRE:
1764 case ARM::t2LDC2L_PRE:
1765 case ARM::t2STC2_OFFSET:
1766 case ARM::t2STC2L_OFFSET:
1767 case ARM::t2STC2_PRE:
1768 case ARM::t2STC2L_PRE:
1769 case ARM::LDC2_OFFSET:
1770 case ARM::LDC2L_OFFSET:
1772 case ARM::LDC2L_PRE:
1773 case ARM::STC2_OFFSET:
1774 case ARM::STC2L_OFFSET:
1776 case ARM::STC2L_PRE:
1777 case ARM::t2LDC_OFFSET:
1778 case ARM::t2LDCL_OFFSET:
1779 case ARM::t2LDC_PRE:
1780 case ARM::t2LDCL_PRE:
1781 case ARM::t2STC_OFFSET:
1782 case ARM::t2STCL_OFFSET:
1783 case ARM::t2STC_PRE:
1784 case ARM::t2STCL_PRE:
1785 case ARM::LDC_OFFSET:
1786 case ARM::LDCL_OFFSET:
1789 case ARM::STC_OFFSET:
1790 case ARM::STCL_OFFSET:
1796 case ARM::t2LDC2_POST:
1797 case ARM::t2LDC2L_POST:
1798 case ARM::t2STC2_POST:
1799 case ARM::t2STC2L_POST:
1800 case ARM::LDC2_POST:
1801 case ARM::LDC2L_POST:
1802 case ARM::STC2_POST:
1803 case ARM::STC2L_POST:
1804 case ARM::t2LDC_POST:
1805 case ARM::t2LDCL_POST:
1806 case ARM::t2STC_POST:
1807 case ARM::t2STCL_POST:
1809 case ARM::LDCL_POST:
1811 case ARM::STCL_POST:
1822 case ARM::LDC_OFFSET:
1825 case ARM::LDC_OPTION:
1826 case ARM::LDCL_OFFSET:
1828 case ARM::LDCL_POST:
1829 case ARM::LDCL_OPTION:
1830 case ARM::STC_OFFSET:
1833 case ARM::STC_OPTION:
1834 case ARM::STCL_OFFSET:
1836 case ARM::STCL_POST:
1837 case ARM::STCL_OPTION:
1850 uint64_t Address,
const void *Decoder) {
1853 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1854 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1855 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1856 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1857 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1858 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1859 unsigned P = fieldFromInstruction(Insn, 24, 1);
1860 unsigned W = fieldFromInstruction(Insn, 21, 1);
1864 case ARM::STR_POST_IMM:
1865 case ARM::STR_POST_REG:
1866 case ARM::STRB_POST_IMM:
1867 case ARM::STRB_POST_REG:
1868 case ARM::STRT_POST_REG:
1869 case ARM::STRT_POST_IMM:
1870 case ARM::STRBT_POST_REG:
1871 case ARM::STRBT_POST_IMM:
1884 case ARM::LDR_POST_IMM:
1885 case ARM::LDR_POST_REG:
1886 case ARM::LDRB_POST_IMM:
1887 case ARM::LDRB_POST_REG:
1888 case ARM::LDRBT_POST_REG:
1889 case ARM::LDRBT_POST_IMM:
1890 case ARM::LDRT_POST_REG:
1891 case ARM::LDRT_POST_IMM:
1903 if (!fieldFromInstruction(Insn, 23, 1))
1906 bool writeback = (
P == 0) || (
W == 1);
1907 unsigned idx_mode = 0;
1910 else if (!
P && writeback)
1913 if (writeback && (Rn == 15 || Rn == Rt))
1920 switch( fieldFromInstruction(Insn, 5, 2)) {
1936 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1955 uint64_t Address,
const void *Decoder) {
1958 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1959 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1960 unsigned type = fieldFromInstruction(Val, 5, 2);
1961 unsigned imm = fieldFromInstruction(Val, 7, 5);
1962 unsigned U = fieldFromInstruction(Val, 12, 1);
1999 uint64_t Address,
const void *Decoder) {
2002 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2003 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2004 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2005 unsigned type = fieldFromInstruction(Insn, 22, 1);
2006 unsigned imm = fieldFromInstruction(Insn, 8, 4);
2007 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2008 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2009 unsigned W = fieldFromInstruction(Insn, 21, 1);
2010 unsigned P = fieldFromInstruction(Insn, 24, 1);
2011 unsigned Rt2 = Rt + 1;
2013 bool writeback = (
W == 1) | (
P == 0);
2019 case ARM::STRD_POST:
2022 case ARM::LDRD_POST:
2031 case ARM::STRD_POST:
2032 if (
P == 0 &&
W == 1)
2035 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2037 if (
type && Rm == 15)
2041 if (!
type && fieldFromInstruction(Insn, 8, 4))
2046 case ARM::STRH_POST:
2049 if (writeback && (Rn == 15 || Rn == Rt))
2051 if (!
type && Rm == 15)
2056 case ARM::LDRD_POST:
2057 if (
type && Rn == 15) {
2062 if (
P == 0 &&
W == 1)
2064 if (!
type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2066 if (!
type && writeback && Rn == 15)
2068 if (writeback && (Rn == Rt || Rn == Rt2))
2073 case ARM::LDRH_POST:
2074 if (
type && Rn == 15) {
2081 if (!
type && Rm == 15)
2083 if (!
type && writeback && (Rn == 15 || Rn == Rt))
2087 case ARM::LDRSH_PRE:
2088 case ARM::LDRSH_POST:
2090 case ARM::LDRSB_PRE:
2091 case ARM::LDRSB_POST:
2092 if (
type && Rn == 15) {
2097 if (
type && (Rt == 15 || (writeback && Rn == Rt)))
2099 if (!
type && (Rt == 15 || Rm == 15))
2101 if (!
type && writeback && (Rn == 15 || Rn == Rt))
2118 case ARM::STRD_POST:
2121 case ARM::STRH_POST:
2135 case ARM::STRD_POST:
2138 case ARM::LDRD_POST:
2151 case ARM::LDRD_POST:
2154 case ARM::LDRH_POST:
2156 case ARM::LDRSH_PRE:
2157 case ARM::LDRSH_POST:
2159 case ARM::LDRSB_PRE:
2160 case ARM::LDRSB_POST:
2190 uint64_t Address,
const void *Decoder) {
2193 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2194 unsigned mode = fieldFromInstruction(Insn, 23, 2);
2219 uint64_t Address,
const void *Decoder) {
2222 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2223 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2224 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2225 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2243 uint64_t Address,
const void *Decoder) {
2246 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2247 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2248 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2256 case ARM::LDMDA_UPD:
2262 case ARM::LDMDB_UPD:
2268 case ARM::LDMIA_UPD:
2274 case ARM::LDMIB_UPD:
2280 case ARM::STMDA_UPD:
2286 case ARM::STMDB_UPD:
2292 case ARM::STMIA_UPD:
2298 case ARM::STMIB_UPD:
2306 if (fieldFromInstruction(Insn, 20, 1) == 0) {
2308 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2309 fieldFromInstruction(Insn, 20, 1) == 0))
2334 uint64_t Address,
const void *Decoder) {
2335 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2336 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2349 if (imm8 == 0x10 &&
pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2356 uint64_t Address,
const void *Decoder) {
2357 unsigned imod = fieldFromInstruction(Insn, 18, 2);
2358 unsigned M = fieldFromInstruction(Insn, 17, 1);
2359 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2360 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2366 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2367 fieldFromInstruction(Insn, 16, 1) != 0 ||
2368 fieldFromInstruction(Insn, 20, 8) != 0x10)
2383 }
else if (imod && !
M) {
2388 }
else if (!imod &&
M) {
2403 uint64_t Address,
const void *Decoder) {
2404 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2405 unsigned M = fieldFromInstruction(Insn, 8, 1);
2406 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2407 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2423 }
else if (imod && !
M) {
2428 }
else if (!imod &&
M) {
2434 int imm = fieldFromInstruction(Insn, 0, 8);
2445 uint64_t Address,
const void *Decoder) {
2448 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2451 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2452 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2453 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2454 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2469 uint64_t Address,
const void *Decoder) {
2472 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2473 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2476 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2477 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2496 uint64_t Address,
const void *Decoder) {
2499 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2500 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2501 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2502 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2503 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2524 uint64_t Address,
const void *Decoder) {
2527 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2528 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2529 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2545 uint64_t Address,
const void *Decoder) {
2548 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2553 if (!FeatureBits[ARM::HasV8_1aOps] ||
2554 !FeatureBits[ARM::HasV8Ops])
2559 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2560 fieldFromInstruction(Insn, 4,4) != 0)
2562 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2563 fieldFromInstruction(Insn, 0,4) != 0)
2573 uint64_t Address,
const void *Decoder) {
2576 unsigned add = fieldFromInstruction(Val, 12, 1);
2577 unsigned imm = fieldFromInstruction(Val, 0, 12);
2578 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2583 if (!
add) imm *= -1;
2584 if (imm == 0 && !
add) imm = INT32_MIN;
2593 uint64_t Address,
const void *Decoder) {
2596 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2598 unsigned U = fieldFromInstruction(Val, 8, 1);
2599 unsigned imm = fieldFromInstruction(Val, 0, 8);
2613 uint64_t Address,
const void *Decoder) {
2616 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2618 unsigned U = fieldFromInstruction(Val, 8, 1);
2619 unsigned imm = fieldFromInstruction(Val, 0, 8);
2633 uint64_t Address,
const void *Decoder) {
2639 uint64_t Address,
const void *Decoder) {
2648 unsigned S = fieldFromInstruction(Insn, 26, 1);
2649 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2650 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2651 unsigned I1 = !(J1 ^
S);
2652 unsigned I2 = !(J2 ^
S);
2653 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2654 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2655 unsigned tmp = (
S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2656 int imm32 = SignExtend32<25>(
tmp << 1);
2658 true, 4, Inst, Decoder))
2666 uint64_t Address,
const void *Decoder) {
2669 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2670 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2674 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2676 true, 4, Inst, Decoder))
2682 true, 4, Inst, Decoder))
2695 uint64_t Address,
const void *Decoder) {
2698 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2699 unsigned align = fieldFromInstruction(Val, 4, 2);
2712 uint64_t Address,
const void *Decoder) {
2715 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2716 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2717 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2718 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2719 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2720 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2724 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2725 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2726 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2727 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2728 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2729 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2730 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2731 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2732 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2739 case ARM::VLD2b16wb_fixed:
2740 case ARM::VLD2b16wb_register:
2741 case ARM::VLD2b32wb_fixed:
2742 case ARM::VLD2b32wb_register:
2743 case ARM::VLD2b8wb_fixed:
2744 case ARM::VLD2b8wb_register:
2758 case ARM::VLD3d8_UPD:
2759 case ARM::VLD3d16_UPD:
2760 case ARM::VLD3d32_UPD:
2764 case ARM::VLD4d8_UPD:
2765 case ARM::VLD4d16_UPD:
2766 case ARM::VLD4d32_UPD:
2773 case ARM::VLD3q8_UPD:
2774 case ARM::VLD3q16_UPD:
2775 case ARM::VLD3q32_UPD:
2779 case ARM::VLD4q8_UPD:
2780 case ARM::VLD4q16_UPD:
2781 case ARM::VLD4q32_UPD:
2794 case ARM::VLD3d8_UPD:
2795 case ARM::VLD3d16_UPD:
2796 case ARM::VLD3d32_UPD:
2800 case ARM::VLD4d8_UPD:
2801 case ARM::VLD4d16_UPD:
2802 case ARM::VLD4d32_UPD:
2809 case ARM::VLD3q8_UPD:
2810 case ARM::VLD3q16_UPD:
2811 case ARM::VLD3q32_UPD:
2815 case ARM::VLD4q8_UPD:
2816 case ARM::VLD4q16_UPD:
2817 case ARM::VLD4q32_UPD:
2830 case ARM::VLD4d8_UPD:
2831 case ARM::VLD4d16_UPD:
2832 case ARM::VLD4d32_UPD:
2839 case ARM::VLD4q8_UPD:
2840 case ARM::VLD4q16_UPD:
2841 case ARM::VLD4q32_UPD:
2851 case ARM::VLD1d8wb_fixed:
2852 case ARM::VLD1d16wb_fixed:
2853 case ARM::VLD1d32wb_fixed:
2854 case ARM::VLD1d64wb_fixed:
2855 case ARM::VLD1d8wb_register:
2856 case ARM::VLD1d16wb_register:
2857 case ARM::VLD1d32wb_register:
2858 case ARM::VLD1d64wb_register:
2859 case ARM::VLD1q8wb_fixed:
2860 case ARM::VLD1q16wb_fixed:
2861 case ARM::VLD1q32wb_fixed:
2862 case ARM::VLD1q64wb_fixed:
2863 case ARM::VLD1q8wb_register:
2864 case ARM::VLD1q16wb_register:
2865 case ARM::VLD1q32wb_register:
2866 case ARM::VLD1q64wb_register:
2867 case ARM::VLD1d8Twb_fixed:
2868 case ARM::VLD1d8Twb_register:
2869 case ARM::VLD1d16Twb_fixed:
2870 case ARM::VLD1d16Twb_register:
2871 case ARM::VLD1d32Twb_fixed:
2872 case ARM::VLD1d32Twb_register:
2873 case ARM::VLD1d64Twb_fixed:
2874 case ARM::VLD1d64Twb_register:
2875 case ARM::VLD1d8Qwb_fixed:
2876 case ARM::VLD1d8Qwb_register:
2877 case ARM::VLD1d16Qwb_fixed:
2878 case ARM::VLD1d16Qwb_register:
2879 case ARM::VLD1d32Qwb_fixed:
2880 case ARM::VLD1d32Qwb_register:
2881 case ARM::VLD1d64Qwb_fixed:
2882 case ARM::VLD1d64Qwb_register:
2883 case ARM::VLD2d8wb_fixed:
2884 case ARM::VLD2d16wb_fixed:
2885 case ARM::VLD2d32wb_fixed:
2886 case ARM::VLD2q8wb_fixed:
2887 case ARM::VLD2q16wb_fixed:
2888 case ARM::VLD2q32wb_fixed:
2889 case ARM::VLD2d8wb_register:
2890 case ARM::VLD2d16wb_register:
2891 case ARM::VLD2d32wb_register:
2892 case ARM::VLD2q8wb_register:
2893 case ARM::VLD2q16wb_register:
2894 case ARM::VLD2q32wb_register:
2895 case ARM::VLD2b8wb_fixed:
2896 case ARM::VLD2b16wb_fixed:
2897 case ARM::VLD2b32wb_fixed:
2898 case ARM::VLD2b8wb_register:
2899 case ARM::VLD2b16wb_register:
2900 case ARM::VLD2b32wb_register:
2903 case ARM::VLD3d8_UPD:
2904 case ARM::VLD3d16_UPD:
2905 case ARM::VLD3d32_UPD:
2906 case ARM::VLD3q8_UPD:
2907 case ARM::VLD3q16_UPD:
2908 case ARM::VLD3q32_UPD:
2909 case ARM::VLD4d8_UPD:
2910 case ARM::VLD4d16_UPD:
2911 case ARM::VLD4d32_UPD:
2912 case ARM::VLD4q8_UPD:
2913 case ARM::VLD4q16_UPD:
2914 case ARM::VLD4q32_UPD:
2941 case ARM::VLD1d8wb_fixed:
2942 case ARM::VLD1d16wb_fixed:
2943 case ARM::VLD1d32wb_fixed:
2944 case ARM::VLD1d64wb_fixed:
2945 case ARM::VLD1d8Twb_fixed:
2946 case ARM::VLD1d16Twb_fixed:
2947 case ARM::VLD1d32Twb_fixed:
2948 case ARM::VLD1d64Twb_fixed:
2949 case ARM::VLD1d8Qwb_fixed:
2950 case ARM::VLD1d16Qwb_fixed:
2951 case ARM::VLD1d32Qwb_fixed:
2952 case ARM::VLD1d64Qwb_fixed:
2953 case ARM::VLD1d8wb_register:
2954 case ARM::VLD1d16wb_register:
2955 case ARM::VLD1d32wb_register:
2956 case ARM::VLD1d64wb_register:
2957 case ARM::VLD1q8wb_fixed:
2958 case ARM::VLD1q16wb_fixed:
2959 case ARM::VLD1q32wb_fixed:
2960 case ARM::VLD1q64wb_fixed:
2961 case ARM::VLD1q8wb_register:
2962 case ARM::VLD1q16wb_register:
2963 case ARM::VLD1q32wb_register:
2964 case ARM::VLD1q64wb_register:
2968 if (Rm != 0xD && Rm != 0xF &&
2972 case ARM::VLD2d8wb_fixed:
2973 case ARM::VLD2d16wb_fixed:
2974 case ARM::VLD2d32wb_fixed:
2975 case ARM::VLD2b8wb_fixed:
2976 case ARM::VLD2b16wb_fixed:
2977 case ARM::VLD2b32wb_fixed:
2978 case ARM::VLD2q8wb_fixed:
2979 case ARM::VLD2q16wb_fixed:
2980 case ARM::VLD2q32wb_fixed:
2988 uint64_t Address,
const void *Decoder) {
2989 unsigned type = fieldFromInstruction(Insn, 8, 4);
2990 unsigned align = fieldFromInstruction(Insn, 4, 2);
2995 unsigned load = fieldFromInstruction(Insn, 21, 1);
3001 uint64_t Address,
const void *Decoder) {
3002 unsigned size = fieldFromInstruction(Insn, 6, 2);
3005 unsigned type = fieldFromInstruction(Insn, 8, 4);
3006 unsigned align = fieldFromInstruction(Insn, 4, 2);
3010 unsigned load = fieldFromInstruction(Insn, 21, 1);
3016 uint64_t Address,
const void *Decoder) {
3017 unsigned size = fieldFromInstruction(Insn, 6, 2);
3020 unsigned align = fieldFromInstruction(Insn, 4, 2);
3023 unsigned load = fieldFromInstruction(Insn, 21, 1);
3029 uint64_t Address,
const void *Decoder) {
3030 unsigned size = fieldFromInstruction(Insn, 6, 2);
3033 unsigned load = fieldFromInstruction(Insn, 21, 1);
3039 uint64_t Address,
const void *Decoder) {
3042 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3043 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3044 unsigned wb = fieldFromInstruction(Insn, 16, 4);
3045 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3046 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3047 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3051 case ARM::VST1d8wb_fixed:
3052 case ARM::VST1d16wb_fixed:
3053 case ARM::VST1d32wb_fixed:
3054 case ARM::VST1d64wb_fixed:
3055 case ARM::VST1d8wb_register:
3056 case ARM::VST1d16wb_register:
3057 case ARM::VST1d32wb_register:
3058 case ARM::VST1d64wb_register:
3059 case ARM::VST1q8wb_fixed:
3060 case ARM::VST1q16wb_fixed:
3061 case ARM::VST1q32wb_fixed:
3062 case ARM::VST1q64wb_fixed:
3063 case ARM::VST1q8wb_register:
3064 case ARM::VST1q16wb_register:
3065 case ARM::VST1q32wb_register:
3066 case ARM::VST1q64wb_register:
3067 case ARM::VST1d8Twb_fixed:
3068 case ARM::VST1d16Twb_fixed:
3069 case ARM::VST1d32Twb_fixed:
3070 case ARM::VST1d64Twb_fixed:
3071 case ARM::VST1d8Twb_register:
3072 case ARM::VST1d16Twb_register:
3073 case ARM::VST1d32Twb_register:
3074 case ARM::VST1d64Twb_register:
3075 case ARM::VST1d8Qwb_fixed:
3076 case ARM::VST1d16Qwb_fixed:
3077 case ARM::VST1d32Qwb_fixed:
3078 case ARM::VST1d64Qwb_fixed:
3079 case ARM::VST1d8Qwb_register:
3080 case ARM::VST1d16Qwb_register:
3081 case ARM::VST1d32Qwb_register:
3082 case ARM::VST1d64Qwb_register:
3083 case ARM::VST2d8wb_fixed:
3084 case ARM::VST2d16wb_fixed:
3085 case ARM::VST2d32wb_fixed:
3086 case ARM::VST2d8wb_register:
3087 case ARM::VST2d16wb_register:
3088 case ARM::VST2d32wb_register:
3089 case ARM::VST2q8wb_fixed:
3090 case ARM::VST2q16wb_fixed:
3091 case ARM::VST2q32wb_fixed:
3092 case ARM::VST2q8wb_register:
3093 case ARM::VST2q16wb_register:
3094 case ARM::VST2q32wb_register:
3095 case ARM::VST2b8wb_fixed:
3096 case ARM::VST2b16wb_fixed:
3097 case ARM::VST2b32wb_fixed:
3098 case ARM::VST2b8wb_register:
3099 case ARM::VST2b16wb_register:
3100 case ARM::VST2b32wb_register:
3105 case ARM::VST3d8_UPD:
3106 case ARM::VST3d16_UPD:
3107 case ARM::VST3d32_UPD:
3108 case ARM::VST3q8_UPD:
3109 case ARM::VST3q16_UPD:
3110 case ARM::VST3q32_UPD:
3111 case ARM::VST4d8_UPD:
3112 case ARM::VST4d16_UPD:
3113 case ARM::VST4d32_UPD:
3114 case ARM::VST4q8_UPD:
3115 case ARM::VST4q16_UPD:
3116 case ARM::VST4q32_UPD:
3133 else if (Rm != 0xF) {
3138 case ARM::VST1d8wb_fixed:
3139 case ARM::VST1d16wb_fixed:
3140 case ARM::VST1d32wb_fixed:
3141 case ARM::VST1d64wb_fixed:
3142 case ARM::VST1q8wb_fixed:
3143 case ARM::VST1q16wb_fixed:
3144 case ARM::VST1q32wb_fixed:
3145 case ARM::VST1q64wb_fixed:
3146 case ARM::VST1d8Twb_fixed:
3147 case ARM::VST1d16Twb_fixed:
3148 case ARM::VST1d32Twb_fixed:
3149 case ARM::VST1d64Twb_fixed:
3150 case ARM::VST1d8Qwb_fixed:
3151 case ARM::VST1d16Qwb_fixed:
3152 case ARM::VST1d32Qwb_fixed:
3153 case ARM::VST1d64Qwb_fixed:
3154 case ARM::VST2d8wb_fixed:
3155 case ARM::VST2d16wb_fixed:
3156 case ARM::VST2d32wb_fixed:
3157 case ARM::VST2q8wb_fixed:
3158 case ARM::VST2q16wb_fixed:
3159 case ARM::VST2q32wb_fixed:
3160 case ARM::VST2b8wb_fixed:
3161 case ARM::VST2b16wb_fixed:
3162 case ARM::VST2b32wb_fixed:
3172 case ARM::VST1q16wb_fixed:
3173 case ARM::VST1q16wb_register:
3174 case ARM::VST1q32wb_fixed:
3175 case ARM::VST1q32wb_register:
3176 case ARM::VST1q64wb_fixed:
3177 case ARM::VST1q64wb_register:
3178 case ARM::VST1q8wb_fixed:
3179 case ARM::VST1q8wb_register:
3183 case ARM::VST2d16wb_fixed:
3184 case ARM::VST2d16wb_register:
3185 case ARM::VST2d32wb_fixed:
3186 case ARM::VST2d32wb_register:
3187 case ARM::VST2d8wb_fixed:
3188 case ARM::VST2d8wb_register:
3195 case ARM::VST2b16wb_fixed:
3196 case ARM::VST2b16wb_register:
3197 case ARM::VST2b32wb_fixed:
3198 case ARM::VST2b32wb_register:
3199 case ARM::VST2b8wb_fixed:
3200 case ARM::VST2b8wb_register:
3214 case ARM::VST3d8_UPD:
3215 case ARM::VST3d16_UPD:
3216 case ARM::VST3d32_UPD:
3220 case ARM::VST4d8_UPD:
3221 case ARM::VST4d16_UPD:
3222 case ARM::VST4d32_UPD:
3229 case ARM::VST3q8_UPD:
3230 case ARM::VST3q16_UPD:
3231 case ARM::VST3q32_UPD:
3235 case ARM::VST4q8_UPD:
3236 case ARM::VST4q16_UPD:
3237 case ARM::VST4q32_UPD:
3250 case ARM::VST3d8_UPD:
3251 case ARM::VST3d16_UPD:
3252 case ARM::VST3d32_UPD:
3256 case ARM::VST4d8_UPD:
3257 case ARM::VST4d16_UPD:
3258 case ARM::VST4d32_UPD:
3265 case ARM::VST3q8_UPD:
3266 case ARM::VST3q16_UPD:
3267 case ARM::VST3q32_UPD:
3271 case ARM::VST4q8_UPD:
3272 case ARM::VST4q16_UPD:
3273 case ARM::VST4q32_UPD:
3286 case ARM::VST4d8_UPD:
3287 case ARM::VST4d16_UPD:
3288 case ARM::VST4d32_UPD:
3295 case ARM::VST4q8_UPD:
3296 case ARM::VST4q16_UPD:
3297 case ARM::VST4q32_UPD:
3309 uint64_t Address,
const void *Decoder) {
3312 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3313 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3314 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3315 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3316 unsigned align = fieldFromInstruction(Insn, 4, 1);
3317 unsigned size = fieldFromInstruction(Insn, 6, 2);
3324 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
3325 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
3326 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
3327 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
3348 if (Rm != 0xD && Rm != 0xF &&
3356 uint64_t Address,
const void *Decoder) {
3359 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3360 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3361 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3362 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3363 unsigned align = fieldFromInstruction(Insn, 4, 1);
3364 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3368 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
3369 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
3370 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
3371 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
3375 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
3376 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
3377 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
3378 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3395 if (Rm != 0xD && Rm != 0xF) {
3404 uint64_t Address,
const void *Decoder) {
3407 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3408 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3409 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3410 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3411 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3430 else if (Rm != 0xF) {
3439 uint64_t Address,
const void *Decoder) {
3442 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3443 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3444 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3445 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3446 unsigned size = fieldFromInstruction(Insn, 6, 2);
3447 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3448 unsigned align = fieldFromInstruction(Insn, 4, 1);
3482 else if (Rm != 0xF) {
3492 uint64_t Address,
const void *Decoder) {
3495 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3496 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3497 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3498 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3499 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3500 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3501 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3502 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3515 case ARM::VORRiv4i16:
3516 case ARM::VORRiv2i32:
3517 case ARM::VBICiv4i16:
3518 case ARM::VBICiv2i32:
3522 case ARM::VORRiv8i16:
3523 case ARM::VORRiv4i32:
3524 case ARM::VBICiv8i16:
3525 case ARM::VBICiv4i32:
3538 uint64_t Address,
const void *Decoder) {
3541 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3542 fieldFromInstruction(Insn, 13, 3));
3543 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3544 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3545 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3546 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3548 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3550 if (cmode == 0xF && Inst.
getOpcode() == ARM::MVE_VMVNimmi32)
3566 uint64_t Address,
const void *Decoder) {
3569 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3570 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3575 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3576 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3579 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3580 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3583 if (!fieldFromInstruction(Insn, 12, 1))
3591 uint64_t Address,
const void *Decoder) {
3594 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3595 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3596 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3597 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3598 unsigned size = fieldFromInstruction(Insn, 18, 2);
3610 uint64_t Address,
const void *Decoder) {
3616 uint64_t Address,
const void *Decoder) {
3622 uint64_t Address,
const void *Decoder) {
3628 uint64_t Address,
const void *Decoder) {
3634 uint64_t Address,
const void *Decoder) {
3637 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3638 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3639 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3640 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3641 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3642 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3643 unsigned op = fieldFromInstruction(Insn, 6, 1);
3670 uint64_t Address,
const void *Decoder) {
3673 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3674 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3694 uint64_t Address,
const void *Decoder) {
3696 true, 2, Inst, Decoder))
3702 uint64_t Address,
const void *Decoder) {
3704 true, 4, Inst, Decoder))
3710 uint64_t Address,
const void *Decoder) {
3712 true, 2, Inst, Decoder))
3718 uint64_t Address,
const void *Decoder) {
3721 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3722 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3733 uint64_t Address,
const void *Decoder) {
3736 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3737 unsigned imm = fieldFromInstruction(Val, 3, 5);
3747 uint64_t Address,
const void *Decoder) {
3748 unsigned imm = Val << 2;
3757 uint64_t Address,
const void *Decoder) {
3765 uint64_t Address,
const void *Decoder) {
3768 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3769 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3770 unsigned imm = fieldFromInstruction(Val, 0, 2);
3794 uint64_t Address,
const void *Decoder) {
3797 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3798 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3801 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3803 bool hasMP = featureBits[ARM::FeatureMP];
3804 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3859 if (!hasV7Ops || !hasMP)
3867 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3868 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3869 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3877 uint64_t Address,
const void* Decoder) {
3880 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3881 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3882 unsigned U = fieldFromInstruction(Insn, 9, 1);
3883 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3886 unsigned add = fieldFromInstruction(Insn, 9, 1);
3889 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3891 bool hasMP = featureBits[ARM::FeatureMP];
3892 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3902 case ARM::t2LDRSBi8:
3908 case ARM::t2LDRSHi8:
3925 case ARM::t2LDRSHi8:
3931 case ARM::t2LDRSBi8:
3947 if (!hasV7Ops || !hasMP)
3961 uint64_t Address,
const void* Decoder) {
3964 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3965 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3966 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3970 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3972 bool hasMP = featureBits[ARM::FeatureMP];
3973 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3980 case ARM::t2LDRHi12:
3983 case ARM::t2LDRSHi12:
3986 case ARM::t2LDRBi12:
3989 case ARM::t2LDRSBi12:
4006 case ARM::t2LDRSHi12:
4008 case ARM::t2LDRHi12:
4011 case ARM::t2LDRSBi12:
4026 case ARM::t2PLDWi12:
4027 if (!hasV7Ops || !hasMP)
4041 uint64_t Address,
const void* Decoder) {
4044 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4045 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4046 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4080 uint64_t Address,
const void* Decoder) {
4083 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4084 unsigned U = fieldFromInstruction(Insn, 23, 1);
4085 int imm = fieldFromInstruction(Insn, 0, 12);
4088 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4090 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4094 case ARM::t2LDRBpci:
4095 case ARM::t2LDRHpci:
4098 case ARM::t2LDRSBpci:
4101 case ARM::t2LDRSHpci:
4133 uint64_t Address,
const void *Decoder) {
4137 int imm = Val & 0xFF;
4139 if (!(Val & 0x100)) imm *= -1;
4147 const void *Decoder) {
4151 int imm = Val & 0x7F;
4162 uint64_t Address,
const void *Decoder) {
4165 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4166 unsigned imm = fieldFromInstruction(Val, 0, 9);
4178 const void *Decoder) {
4181 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4182 unsigned imm = fieldFromInstruction(Val, 0, 8);
4193 uint64_t Address,
const void *Decoder) {
4196 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4197 unsigned imm = fieldFromInstruction(Val, 0, 8);
4208 uint64_t Address,
const void *Decoder) {
4209 int imm = Val & 0xFF;
4212 else if (!(Val & 0x100))
4221 uint64_t Address,
const void *Decoder) {
4222 int imm = Val & 0x7F;
4225 else if (!(Val & 0x80))
4227 if (imm != INT32_MIN)
4228 imm *= (1U <<
shift);
4235 uint64_t Address,
const void *Decoder) {
4238 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4239 unsigned imm = fieldFromInstruction(Val, 0, 9);
4283 const void *Decoder) {
4286 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4287 unsigned imm = fieldFromInstruction(Val, 0, 8);
4291 if (!
Check(
S, DecodeT2Imm7<shift>(Inst, imm,
Address, Decoder)))
4297 template<
int shift,
int WriteBack>
4300 const void *Decoder) {
4303 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4304 unsigned imm = fieldFromInstruction(Val, 0, 8);
4310 if (!
Check(
S, DecodeT2Imm7<shift>(Inst, imm,
Address, Decoder)))
4317 uint64_t Address,
const void *Decoder) {
4320 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4321 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4322 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4323 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4325 unsigned load = fieldFromInstruction(Insn, 20, 1);
4329 case ARM::t2LDR_PRE:
4330 case ARM::t2LDR_POST:
4333 case ARM::t2LDRB_PRE:
4334 case ARM::t2LDRB_POST:
4337 case ARM::t2LDRH_PRE:
4338 case ARM::t2LDRH_POST:
4341 case ARM::t2LDRSB_PRE:
4342 case ARM::t2LDRSB_POST:
4348 case ARM::t2LDRSH_PRE:
4349 case ARM::t2LDRSH_POST:
4378 uint64_t Address,
const void *Decoder) {
4381 unsigned Rn = fieldFromInstruction(Val, 13, 4);
4382 unsigned imm = fieldFromInstruction(Val, 0, 12);
4387 case ARM::t2STRBi12:
4388 case ARM::t2STRHi12:
4404 uint64_t Address,
const void *Decoder) {
4405 unsigned imm = fieldFromInstruction(Insn, 0, 7);
4415 uint64_t Address,
const void *Decoder) {
4419 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4420 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4427 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
4428 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4440 uint64_t Address,
const void *Decoder) {
4441 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4442 unsigned flags = fieldFromInstruction(Insn, 0, 3);
4451 uint64_t Address,
const void *Decoder) {
4453 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4454 unsigned add = fieldFromInstruction(Insn, 4, 1);
4464 uint64_t Address,
const void *Decoder) {
4466 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4467 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4479 uint64_t Address,
const void *Decoder) {
4481 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4482 int imm = fieldFromInstruction(Insn, 0, 7);
4487 if(!fieldFromInstruction(Insn, 7, 1)) {
4493 if (imm != INT32_MIN)
4494 imm *= (1U <<
shift);
4501 uint64_t Address,
const void *Decoder) {
4509 unsigned S = (Val >> 23) & 1;
4510 unsigned J1 = (Val >> 22) & 1;
4511 unsigned J2 = (Val >> 21) & 1;
4512 unsigned I1 = !(J1 ^
S);
4513 unsigned I2 = !(J2 ^
S);
4514 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4515 int imm32 = SignExtend32<25>(
tmp << 1);
4519 true, 4, Inst, Decoder))
4525 uint64_t Address,
const void *Decoder) {
4526 if (Val == 0xA || Val == 0xB)
4530 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4541 uint64_t Address,
const void *Decoder) {
4543 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4546 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4547 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4559 uint64_t Address,
const void *Decoder) {
4562 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4564 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4579 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4583 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4584 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4585 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4586 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4587 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4601 uint64_t Address,
const void *Decoder) {
4602 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4604 unsigned byte = fieldFromInstruction(Val, 8, 2);
4605 unsigned imm = fieldFromInstruction(Val, 0, 8);
4622 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4623 unsigned rot = fieldFromInstruction(Val, 7, 5);
4624 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4633 uint64_t Address,
const void *Decoder) {
4635 true, 2, Inst, Decoder))
4642 const void *Decoder) {
4650 unsigned S = (Val >> 23) & 1;
4651 unsigned J1 = (Val >> 22) & 1;
4652 unsigned J2 = (Val >> 21) & 1;
4653 unsigned I1 = !(J1 ^
S);
4654 unsigned I2 = !(J2 ^
S);
4655 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4656 int imm32 = SignExtend32<25>(
tmp << 1);
4659 true, 4, Inst, Decoder))
4665 uint64_t Address,
const void *Decoder) {
4674 uint64_t Address,
const void *Decoder) {
4683 uint64_t Address,
const void *Decoder) {
4686 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4688 if (FeatureBits[ARM::FeatureMClass]) {
4689 unsigned ValLow = Val & 0xff;
4708 if (!(FeatureBits[ARM::HasV7Ops]))
4716 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4726 if (!(FeatureBits[ARM::Feature8MSecExt]))
4736 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4737 if (!(FeatureBits[ARM::HasV7Ops])) {
4750 if (
Mask == 0 || (
Mask != 2 && ValLow > 3) ||
4751 (!(FeatureBits[ARM::FeatureDSP]) && (
Mask & 1)))