LLVM  9.0.0svn
ARMDisassembler.cpp
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1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMBaseInstrInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/Compiler.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arm-disassembler"
35 
37 
38 namespace {
39 
40  // Handles the condition code status of instructions in IT blocks
41  class ITStatus
42  {
43  public:
44  // Returns the condition code for instruction in IT block
45  unsigned getITCC() {
46  unsigned CC = ARMCC::AL;
47  if (instrInITBlock())
48  CC = ITStates.back();
49  return CC;
50  }
51 
52  // Advances the IT block state to the next T or E
53  void advanceITState() {
54  ITStates.pop_back();
55  }
56 
57  // Returns true if the current instruction is in an IT block
58  bool instrInITBlock() {
59  return !ITStates.empty();
60  }
61 
62  // Returns true if current instruction is the last instruction in an IT block
63  bool instrLastInITBlock() {
64  return ITStates.size() == 1;
65  }
66 
67  // Called when decoding an IT instruction. Sets the IT state for
68  // the following instructions that for the IT block. Firstcond
69  // corresponds to the field in the IT instruction encoding; Mask
70  // is in the MCOperand format in which 1 means 'else' and 0 'then'.
71  void setITState(char Firstcond, char Mask) {
72  // (3 - the number of trailing zeros) is the number of then / else.
73  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75  assert(NumTZ <= 3 && "Invalid IT mask!");
76  // push condition codes onto the stack the correct order for the pops
77  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78  unsigned Else = (Mask >> Pos) & 1;
79  ITStates.push_back(CCBits ^ Else);
80  }
81  ITStates.push_back(CCBits);
82  }
83 
84  private:
85  std::vector<unsigned char> ITStates;
86  };
87 
88  class VPTStatus
89  {
90  public:
91  unsigned getVPTPred() {
92  unsigned Pred = ARMVCC::None;
93  if (instrInVPTBlock())
94  Pred = VPTStates.back();
95  return Pred;
96  }
97 
98  void advanceVPTState() {
99  VPTStates.pop_back();
100  }
101 
102  bool instrInVPTBlock() {
103  return !VPTStates.empty();
104  }
105 
106  bool instrLastInVPTBlock() {
107  return VPTStates.size() == 1;
108  }
109 
110  void setVPTState(char Mask) {
111  // (3 - the number of trailing zeros) is the number of then / else.
112  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113  assert(NumTZ <= 3 && "Invalid VPT mask!");
114  // push predicates onto the stack the correct order for the pops
115  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116  bool T = ((Mask >> Pos) & 1) == 0;
117  if (T)
118  VPTStates.push_back(ARMVCC::Then);
119  else
120  VPTStates.push_back(ARMVCC::Else);
121  }
122  VPTStates.push_back(ARMVCC::Then);
123  }
124 
125  private:
127  };
128 
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
132  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133  MCDisassembler(STI, Ctx) {
134  }
135 
136  ~ARMDisassembler() override = default;
137 
138  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
139  ArrayRef<uint8_t> Bytes, uint64_t Address,
140  raw_ostream &VStream,
141  raw_ostream &CStream) const override;
142 
143 private:
144  DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
145  ArrayRef<uint8_t> Bytes, uint64_t Address,
146  raw_ostream &VStream,
147  raw_ostream &CStream) const;
148 
149  DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
150  ArrayRef<uint8_t> Bytes, uint64_t Address,
151  raw_ostream &VStream,
152  raw_ostream &CStream) const;
153 
154  mutable ITStatus ITBlock;
155  mutable VPTStatus VPTBlock;
156 
157  DecodeStatus AddThumbPredicate(MCInst&) const;
158  void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
159 };
160 
161 } // end anonymous namespace
162 
163 static bool Check(DecodeStatus &Out, DecodeStatus In) {
164  switch (In) {
166  // Out stays the same.
167  return true;
169  Out = In;
170  return true;
172  Out = In;
173  return false;
174  }
175  llvm_unreachable("Invalid DecodeStatus!");
176 }
177 
178 // Forward declare these because the autogenerated code will reference them.
179 // Definitions are further down.
180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
181  uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
183  uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
185  uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
187  uint64_t Address, const void *Decoder);
189  unsigned RegNo, uint64_t Address,
190  const void *Decoder);
192  unsigned RegNo, uint64_t Address,
193  const void *Decoder);
195  unsigned RegNo, uint64_t Address,
196  const void *Decoder);
198  MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
200  uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
202  uint64_t Address, const void *Decoder);
203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
204  uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
206  uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
208  uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
210  uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
212  uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
214  uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
216  uint64_t Address, const void *Decoder);
218  unsigned RegNo,
219  uint64_t Address,
220  const void *Decoder);
221 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
222  uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
224  uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
226  uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
228  uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
230  uint64_t Address, const void *Decoder);
232  unsigned RegNo, uint64_t Address,
233  const void *Decoder);
234 
235 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
236  uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
238  uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
240  uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
242  uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
244  uint64_t Address, const void *Decoder);
245 
246 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
247  uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
249  uint64_t Address, const void *Decoder);
251  unsigned Insn,
252  uint64_t Address,
253  const void *Decoder);
254 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
255  uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
257  uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
259  uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
261  uint64_t Address, const void *Decoder);
262 
264  unsigned Insn,
265  uint64_t Adddress,
266  const void *Decoder);
267 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
268  uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
270  uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
272  uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
274  uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
276  uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
278  uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
280  uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
282  uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
284  uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
286  uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
288  uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
290  uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
292  uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
294  uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
296  uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
298  uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
300  uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
302  uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
304  uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
306  uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
308  uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
310  uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
312  uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
314  uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
316  uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
318  uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
320  uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
322  uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
324  uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
326  uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
328  uint64_t Address, const void *Decoder);
329 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
330  uint64_t Address, const void *Decoder);
331 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
332  uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
334  uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
336  uint64_t Address, const void *Decoder);
337 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
338  uint64_t Address, const void *Decoder);
339 template<int shift>
340 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
341  uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
343  uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
345  uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
347  uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
349  uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
351  uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
353  uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
355  uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
357  uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
359  uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
361  uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
363  uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
365  uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
367  uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
369  uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
371  uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
373  uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
375  uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
377  uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
379  uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
381  uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
383  uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
385  uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
387  uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
389  uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
391  uint64_t Address, const void *Decoder);
393  unsigned Val,
394  uint64_t Address,
395  const void *Decoder);
396 
397 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
398  uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
400  uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
402  uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
404  uint64_t Address, const void *Decoder);
405 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
406  uint64_t Address, const void *Decoder);
407 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
408  uint64_t Address, const void *Decoder);
409 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
410  uint64_t Address, const void *Decoder);
411 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
412  uint64_t Address, const void *Decoder);
413 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
414  uint64_t Address, const void *Decoder);
415 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
416  uint64_t Address, const void *Decoder);
417 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
418  uint64_t Address, const void* Decoder);
419 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
420  uint64_t Address, const void* Decoder);
421 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
422  uint64_t Address, const void* Decoder);
423 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
424  uint64_t Address, const void* Decoder);
425 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
426  uint64_t Address, const void *Decoder);
427 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
428  uint64_t Address, const void *Decoder);
429 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
430  uint64_t Address, const void *Decoder);
431 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
432  uint64_t Address,
433  const void *Decoder);
434 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
435  uint64_t Address, const void *Decoder);
436 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
437  uint64_t Address, const void *Decoder);
438 template<int shift>
439 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
440  uint64_t Address, const void *Decoder);
441 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
442  uint64_t Address, const void *Decoder);
443 template<int shift>
444 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
445  uint64_t Address, const void *Decoder);
446 template<int shift, int WriteBack>
447 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
448  uint64_t Address, const void *Decoder);
449 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
450  uint64_t Address, const void *Decoder);
451 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
452  uint64_t Address, const void *Decoder);
453 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
454  uint64_t Address, const void *Decoder);
455 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
456  uint64_t Address, const void *Decoder);
457 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
458  uint64_t Address, const void *Decoder);
459 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
460  uint64_t Address, const void *Decoder);
461 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
462  uint64_t Address, const void *Decoder);
463 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
464  uint64_t Address, const void *Decoder);
465 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
466  uint64_t Address, const void *Decoder);
467 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
468  uint64_t Address, const void *Decoder);
469 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
470  uint64_t Address, const void *Decoder);
471 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
472  uint64_t Address, const void *Decoder);
473 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
474  uint64_t Address, const void *Decoder);
475 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
476  uint64_t Address, const void *Decoder);
477 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
478  uint64_t Address, const void *Decoder);
479 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
480  uint64_t Address, const void *Decoder);
481 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
482  uint64_t Address, const void *Decoder);
483 
484 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
485  uint64_t Address, const void *Decoder);
486 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
487  uint64_t Address, const void *Decoder);
488 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
489  uint64_t Address, const void *Decoder);
490 
491 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
492 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
493  uint64_t Address, const void *Decoder);
494 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
495  uint64_t Address,
496  const void *Decoder);
497 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
498  uint64_t Address,
499  const void *Decoder);
500 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
501  const void *Decoder);
502 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
503  uint64_t Address,
504  const void *Decoder);
505 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
506  const void *Decoder);
507 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
508  uint64_t Address, const void *Decoder);
509 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
510  uint64_t Address, const void *Decoder);
511 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
512  uint64_t Address,
513  const void *Decoder);
514 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
515  uint64_t Address,
516  const void *Decoder);
517 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
518  uint64_t Address,
519  const void *Decoder);
521  unsigned Val,
522  uint64_t Address,
523  const void *Decoder);
524 template<bool Writeback>
525 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
526  uint64_t Address,
527  const void *Decoder);
528 template<int shift>
529 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
530  uint64_t Address, const void *Decoder);
531 template<int shift>
532 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
533  uint64_t Address, const void *Decoder);
534 template<int shift>
535 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
536  uint64_t Address, const void *Decoder);
537 template<unsigned MinLog, unsigned MaxLog>
538 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
539  uint64_t Address,
540  const void *Decoder);
541 template <int shift>
542 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
543  uint64_t Address,
544  const void *Decoder);
545 template<unsigned start>
546 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
547  uint64_t Address,
548  const void *Decoder);
549 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
550  uint64_t Address,
551  const void *Decoder);
552 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
553  uint64_t Address,
554  const void *Decoder);
555 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
556  uint64_t Address, const void *Decoder);
557 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
558  uint64_t Address, const void *Decoder);
559 template<bool scalar, OperandDecoder predicate_decoder>
560 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
561  uint64_t Address, const void *Decoder);
562 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
563  uint64_t Address, const void *Decoder);
564 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
565  uint64_t Address,
566  const void *Decoder);
567 #include "ARMGenDisassemblerTables.inc"
568 
570  const MCSubtargetInfo &STI,
571  MCContext &Ctx) {
572  return new ARMDisassembler(STI, Ctx);
573 }
574 
575 // Post-decoding checks
577  uint64_t Address, raw_ostream &OS,
578  raw_ostream &CS,
579  uint32_t Insn,
580  DecodeStatus Result) {
581  switch (MI.getOpcode()) {
582  case ARM::HVC: {
583  // HVC is undefined if condition = 0xf otherwise upredictable
584  // if condition != 0xe
585  uint32_t Cond = (Insn >> 28) & 0xF;
586  if (Cond == 0xF)
587  return MCDisassembler::Fail;
588  if (Cond != 0xE)
590  return Result;
591  }
592  case ARM::t2ADDri:
593  case ARM::t2ADDri12:
594  case ARM::t2ADDrr:
595  case ARM::t2ADDrs:
596  case ARM::t2SUBri:
597  case ARM::t2SUBri12:
598  case ARM::t2SUBrr:
599  case ARM::t2SUBrs:
600  if (MI.getOperand(0).getReg() == ARM::SP &&
601  MI.getOperand(1).getReg() != ARM::SP)
603  return Result;
604  default: return Result;
605  }
606 }
607 
608 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
609  ArrayRef<uint8_t> Bytes,
610  uint64_t Address, raw_ostream &OS,
611  raw_ostream &CS) const {
612  if (STI.getFeatureBits()[ARM::ModeThumb])
613  return getThumbInstruction(MI, Size, Bytes, Address, OS, CS);
614  return getARMInstruction(MI, Size, Bytes, Address, OS, CS);
615 }
616 
617 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
618  ArrayRef<uint8_t> Bytes,
619  uint64_t Address,
620  raw_ostream &OS,
621  raw_ostream &CS) const {
622  CommentStream = &CS;
623 
624  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
625  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
626  "mode!");
627 
628  // We want to read exactly 4 bytes of data.
629  if (Bytes.size() < 4) {
630  Size = 0;
631  return MCDisassembler::Fail;
632  }
633 
634  // Encoded as a small-endian 32-bit word in the stream.
635  uint32_t Insn =
636  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
637 
638  // Calling the auto-generated decoder function.
639  DecodeStatus Result =
640  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
641  if (Result != MCDisassembler::Fail) {
642  Size = 4;
643  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
644  }
645 
646  struct DecodeTable {
647  const uint8_t *P;
648  bool DecodePred;
649  };
650 
651  const DecodeTable Tables[] = {
652  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
653  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
654  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
655  {DecoderTablev8Crypto32, false},
656  };
657 
658  for (auto Table : Tables) {
659  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
660  if (Result != MCDisassembler::Fail) {
661  Size = 4;
662  // Add a fake predicate operand, because we share these instruction
663  // definitions with Thumb2 where these instructions are predicable.
664  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
665  return MCDisassembler::Fail;
666  return Result;
667  }
668  }
669 
670  Result =
671  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
672  if (Result != MCDisassembler::Fail) {
673  Size = 4;
674  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
675  }
676 
677  Size = 4;
678  return MCDisassembler::Fail;
679 }
680 
681 namespace llvm {
682 
683 extern const MCInstrDesc ARMInsts[];
684 
685 } // end namespace llvm
686 
687 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
688 /// immediate Value in the MCInst. The immediate Value has had any PC
689 /// adjustment made by the caller. If the instruction is a branch instruction
690 /// then isBranch is true, else false. If the getOpInfo() function was set as
691 /// part of the setupForSymbolicDisassembly() call then that function is called
692 /// to get any symbolic information at the Address for this instruction. If
693 /// that returns non-zero then the symbolic information it returns is used to
694 /// create an MCExpr and that is added as an operand to the MCInst. If
695 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
696 /// Value is done and if a symbol is found an MCExpr is created with that, else
697 /// an MCExpr with Value is created. This function returns true if it adds an
698 /// operand to the MCInst and false otherwise.
699 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
700  bool isBranch, uint64_t InstSize,
701  MCInst &MI, const void *Decoder) {
702  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
703  // FIXME: Does it make sense for value to be negative?
704  return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
705  /* Offset */ 0, InstSize);
706 }
707 
708 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
709 /// referenced by a load instruction with the base register that is the Pc.
710 /// These can often be values in a literal pool near the Address of the
711 /// instruction. The Address of the instruction and its immediate Value are
712 /// used as a possible literal pool entry. The SymbolLookUp call back will
713 /// return the name of a symbol referenced by the literal pool's entry if
714 /// the referenced address is that of a symbol. Or it will return a pointer to
715 /// a literal 'C' string if the referenced address of the literal pool's entry
716 /// is an address into a section with 'C' string literals.
718  const void *Decoder) {
719  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
720  Dis->tryAddingPcLoadReferenceComment(Value, Address);
721 }
722 
723 // Thumb1 instructions don't have explicit S bits. Rather, they
724 // implicitly set CPSR. Since it's not represented in the encoding, the
725 // auto-generated decoder won't inject the CPSR operand. We need to fix
726 // that as a post-pass.
727 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
728  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
729  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
730  MCInst::iterator I = MI.begin();
731  for (unsigned i = 0; i < NumOps; ++i, ++I) {
732  if (I == MI.end()) break;
733  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
734  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
735  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
736  return;
737  }
738  }
739 
740  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
741 }
742 
743 static bool isVectorPredicable(unsigned Opcode) {
744  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
745  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
746  for (unsigned i = 0; i < NumOps; ++i) {
747  if (ARM::isVpred(OpInfo[i].OperandType))
748  return true;
749  }
750  return false;
751 }
752 
753 // Most Thumb instructions don't have explicit predicates in the
754 // encoding, but rather get their predicates from IT context. We need
755 // to fix up the predicate operands using this context information as a
756 // post-pass.
758 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
760 
761  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
762 
763  // A few instructions actually have predicates encoded in them. Don't
764  // try to overwrite it if we're seeing one of those.
765  switch (MI.getOpcode()) {
766  case ARM::tBcc:
767  case ARM::t2Bcc:
768  case ARM::tCBZ:
769  case ARM::tCBNZ:
770  case ARM::tCPS:
771  case ARM::t2CPS3p:
772  case ARM::t2CPS2p:
773  case ARM::t2CPS1p:
774  case ARM::t2CSEL:
775  case ARM::t2CSINC:
776  case ARM::t2CSINV:
777  case ARM::t2CSNEG:
778  case ARM::tMOVSr:
779  case ARM::tSETEND:
780  // Some instructions (mostly conditional branches) are not
781  // allowed in IT blocks.
782  if (ITBlock.instrInITBlock())
783  S = SoftFail;
784  else
785  return Success;
786  break;
787  case ARM::t2HINT:
788  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
789  S = SoftFail;
790  break;
791  case ARM::tB:
792  case ARM::t2B:
793  case ARM::t2TBB:
794  case ARM::t2TBH:
795  // Some instructions (mostly unconditional branches) can
796  // only appears at the end of, or outside of, an IT.
797  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
798  S = SoftFail;
799  break;
800  default:
801  break;
802  }
803 
804  // Warn on non-VPT predicable instruction in a VPT block and a VPT
805  // predicable instruction in an IT block
806  if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
807  (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
808  S = SoftFail;
809 
810  // If we're in an IT/VPT block, base the predicate on that. Otherwise,
811  // assume a predicate of AL.
812  unsigned CC = ARMCC::AL;
813  unsigned VCC = ARMVCC::None;
814  if (ITBlock.instrInITBlock()) {
815  CC = ITBlock.getITCC();
816  ITBlock.advanceITState();
817  } else if (VPTBlock.instrInVPTBlock()) {
818  VCC = VPTBlock.getVPTPred();
819  VPTBlock.advanceVPTState();
820  }
821 
822  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
823  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
824 
825  MCInst::iterator CCI = MI.begin();
826  for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
827  if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
828  }
829 
830  if (ARMInsts[MI.getOpcode()].isPredicable()) {
831  CCI = MI.insert(CCI, MCOperand::createImm(CC));
832  ++CCI;
833  if (CC == ARMCC::AL)
834  MI.insert(CCI, MCOperand::createReg(0));
835  else
836  MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
837  } else if (CC != ARMCC::AL) {
838  Check(S, SoftFail);
839  }
840 
841  MCInst::iterator VCCI = MI.begin();
842  unsigned VCCPos;
843  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
844  if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
845  }
846 
847  if (isVectorPredicable(MI.getOpcode())) {
848  VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
849  ++VCCI;
850  if (VCC == ARMVCC::None)
851  MI.insert(VCCI, MCOperand::createReg(0));
852  else
853  MI.insert(VCCI, MCOperand::createReg(ARM::P0));
854  if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
855  int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
856  VCCPos + 2, MCOI::TIED_TO);
857  assert(TiedOp >= 0 &&
858  "Inactive register in vpred_r is not tied to an output!");
859  MI.insert(VCCI, MI.getOperand(TiedOp));
860  }
861  } else if (VCC != ARMVCC::None) {
862  Check(S, SoftFail);
863  }
864 
865  return S;
866 }
867 
868 // Thumb VFP instructions are a special case. Because we share their
869 // encodings between ARM and Thumb modes, and they are predicable in ARM
870 // mode, the auto-generated decoder will give them an (incorrect)
871 // predicate operand. We need to rewrite these operands based on the IT
872 // context as a post-pass.
873 void ARMDisassembler::UpdateThumbVFPPredicate(
874  DecodeStatus &S, MCInst &MI) const {
875  unsigned CC;
876  CC = ITBlock.getITCC();
877  if (CC == 0xF)
878  CC = ARMCC::AL;
879  if (ITBlock.instrInITBlock())
880  ITBlock.advanceITState();
881  else if (VPTBlock.instrInVPTBlock()) {
882  CC = VPTBlock.getVPTPred();
883  VPTBlock.advanceVPTState();
884  }
885 
886  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
887  MCInst::iterator I = MI.begin();
888  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
889  for (unsigned i = 0; i < NumOps; ++i, ++I) {
890  if (OpInfo[i].isPredicate() ) {
891  if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
892  Check(S, SoftFail);
893  I->setImm(CC);
894  ++I;
895  if (CC == ARMCC::AL)
896  I->setReg(0);
897  else
898  I->setReg(ARM::CPSR);
899  return;
900  }
901  }
902 }
903 
904 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
905  ArrayRef<uint8_t> Bytes,
906  uint64_t Address,
907  raw_ostream &OS,
908  raw_ostream &CS) const {
909  CommentStream = &CS;
910 
911  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
912  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
913 
914  // We want to read exactly 2 bytes of data.
915  if (Bytes.size() < 2) {
916  Size = 0;
917  return MCDisassembler::Fail;
918  }
919 
920  uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
921  DecodeStatus Result =
922  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
923  if (Result != MCDisassembler::Fail) {
924  Size = 2;
925  Check(Result, AddThumbPredicate(MI));
926  return Result;
927  }
928 
929  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
930  STI);
931  if (Result) {
932  Size = 2;
933  bool InITBlock = ITBlock.instrInITBlock();
934  Check(Result, AddThumbPredicate(MI));
935  AddThumb1SBit(MI, InITBlock);
936  return Result;
937  }
938 
939  Result =
940  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
941  if (Result != MCDisassembler::Fail) {
942  Size = 2;
943 
944  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
945  // the Thumb predicate.
946  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
947  Result = MCDisassembler::SoftFail;
948 
949  Check(Result, AddThumbPredicate(MI));
950 
951  // If we find an IT instruction, we need to parse its condition
952  // code and mask operands so that we can apply them correctly
953  // to the subsequent instructions.
954  if (MI.getOpcode() == ARM::t2IT) {
955  unsigned Firstcond = MI.getOperand(0).getImm();
956  unsigned Mask = MI.getOperand(1).getImm();
957  ITBlock.setITState(Firstcond, Mask);
958 
959  // An IT instruction that would give a 'NV' predicate is unpredictable.
960  if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
961  CS << "unpredictable IT predicate sequence";
962  }
963 
964  return Result;
965  }
966 
967  // We want to read exactly 4 bytes of data.
968  if (Bytes.size() < 4) {
969  Size = 0;
970  return MCDisassembler::Fail;
971  }
972 
973  uint32_t Insn32 =
974  (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
975 
976  Result =
977  decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
978  if (Result != MCDisassembler::Fail) {
979  Size = 4;
980 
981  // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
982  // the VPT predicate.
983  if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
984  Result = MCDisassembler::SoftFail;
985 
986  Check(Result, AddThumbPredicate(MI));
987 
988  if (isVPTOpcode(MI.getOpcode())) {
989  unsigned Mask = MI.getOperand(0).getImm();
990  VPTBlock.setVPTState(Mask);
991  }
992 
993  return Result;
994  }
995 
996  Result =
997  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
998  if (Result != MCDisassembler::Fail) {
999  Size = 4;
1000  bool InITBlock = ITBlock.instrInITBlock();
1001  Check(Result, AddThumbPredicate(MI));
1002  AddThumb1SBit(MI, InITBlock);
1003  return Result;
1004  }
1005 
1006  Result =
1007  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1008  if (Result != MCDisassembler::Fail) {
1009  Size = 4;
1010  Check(Result, AddThumbPredicate(MI));
1011  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result);
1012  }
1013 
1014  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1015  Result =
1016  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1017  if (Result != MCDisassembler::Fail) {
1018  Size = 4;
1019  UpdateThumbVFPPredicate(Result, MI);
1020  return Result;
1021  }
1022  }
1023 
1024  Result =
1025  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1026  if (Result != MCDisassembler::Fail) {
1027  Size = 4;
1028  return Result;
1029  }
1030 
1031  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1032  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1033  STI);
1034  if (Result != MCDisassembler::Fail) {
1035  Size = 4;
1036  Check(Result, AddThumbPredicate(MI));
1037  return Result;
1038  }
1039  }
1040 
1041  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1042  uint32_t NEONLdStInsn = Insn32;
1043  NEONLdStInsn &= 0xF0FFFFFF;
1044  NEONLdStInsn |= 0x04000000;
1045  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1046  Address, this, STI);
1047  if (Result != MCDisassembler::Fail) {
1048  Size = 4;
1049  Check(Result, AddThumbPredicate(MI));
1050  return Result;
1051  }
1052  }
1053 
1054  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1055  uint32_t NEONDataInsn = Insn32;
1056  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1057  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1058  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1059  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1060  Address, this, STI);
1061  if (Result != MCDisassembler::Fail) {
1062  Size = 4;
1063  Check(Result, AddThumbPredicate(MI));
1064  return Result;
1065  }
1066 
1067  uint32_t NEONCryptoInsn = Insn32;
1068  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1069  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1070  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1071  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1072  Address, this, STI);
1073  if (Result != MCDisassembler::Fail) {
1074  Size = 4;
1075  return Result;
1076  }
1077 
1078  uint32_t NEONv8Insn = Insn32;
1079  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1080  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1081  this, STI);
1082  if (Result != MCDisassembler::Fail) {
1083  Size = 4;
1084  return Result;
1085  }
1086  }
1087 
1088  Result =
1089  decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
1090  if (Result != MCDisassembler::Fail) {
1091  Size = 4;
1092  Check(Result, AddThumbPredicate(MI));
1093  return Result;
1094  }
1095 
1096  Size = 0;
1097  return MCDisassembler::Fail;
1098 }
1099 
1109 }
1110 
1111 static const uint16_t GPRDecoderTable[] = {
1112  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1113  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1114  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1115  ARM::R12, ARM::SP, ARM::LR, ARM::PC
1116 };
1117 
1118 static const uint16_t CLRMGPRDecoderTable[] = {
1119  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1120  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1121  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1122  ARM::R12, 0, ARM::LR, ARM::APSR
1123 };
1124 
1125 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1126  uint64_t Address, const void *Decoder) {
1127  if (RegNo > 15)
1128  return MCDisassembler::Fail;
1129 
1130  unsigned Register = GPRDecoderTable[RegNo];
1131  Inst.addOperand(MCOperand::createReg(Register));
1132  return MCDisassembler::Success;
1133 }
1134 
1135 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1136  uint64_t Address,
1137  const void *Decoder) {
1138  if (RegNo > 15)
1139  return MCDisassembler::Fail;
1140 
1141  unsigned Register = CLRMGPRDecoderTable[RegNo];
1142  if (Register == 0)
1143  return MCDisassembler::Fail;
1144 
1145  Inst.addOperand(MCOperand::createReg(Register));
1146  return MCDisassembler::Success;
1147 }
1148 
1149 static DecodeStatus
1150 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1151  uint64_t Address, const void *Decoder) {
1153 
1154  if (RegNo == 15)
1156 
1157  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1158 
1159  return S;
1160 }
1161 
1162 static DecodeStatus
1164  uint64_t Address, const void *Decoder) {
1166 
1167  if (RegNo == 15)
1168  {
1169  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1170  return MCDisassembler::Success;
1171  }
1172 
1173  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1174  return S;
1175 }
1176 
1177 static DecodeStatus
1178 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
1179  uint64_t Address, const void *Decoder) {
1181 
1182  if (RegNo == 15)
1183  {
1184  Inst.addOperand(MCOperand::createReg(ARM::ZR));
1185  return MCDisassembler::Success;
1186  }
1187 
1188  if (RegNo == 13)
1190 
1191  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1192  return S;
1193 }
1194 
1195 static DecodeStatus
1197  uint64_t Address, const void *Decoder) {
1199  if (RegNo == 13)
1200  return MCDisassembler::Fail;
1201  Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1202  return S;
1203 }
1204 
1205 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1206  uint64_t Address, const void *Decoder) {
1207  if (RegNo > 7)
1208  return MCDisassembler::Fail;
1209  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1210 }
1211 
1212 static const uint16_t GPRPairDecoderTable[] = {
1213  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1214  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1215 };
1216 
1217 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1218  uint64_t Address, const void *Decoder) {
1220 
1221  if (RegNo > 13)
1222  return MCDisassembler::Fail;
1223 
1224  if ((RegNo & 1) || RegNo == 0xe)
1226 
1227  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1228  Inst.addOperand(MCOperand::createReg(RegisterPair));
1229  return S;
1230 }
1231 
1232 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1233  uint64_t Address, const void *Decoder) {
1234  unsigned Register = 0;
1235  switch (RegNo) {
1236  case 0:
1237  Register = ARM::R0;
1238  break;
1239  case 1:
1240  Register = ARM::R1;
1241  break;
1242  case 2:
1243  Register = ARM::R2;
1244  break;
1245  case 3:
1246  Register = ARM::R3;
1247  break;
1248  case 9:
1249  Register = ARM::R9;
1250  break;
1251  case 12:
1252  Register = ARM::R12;
1253  break;
1254  default:
1255  return MCDisassembler::Fail;
1256  }
1257 
1258  Inst.addOperand(MCOperand::createReg(Register));
1259  return MCDisassembler::Success;
1260 }
1261 
1262 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1263  uint64_t Address, const void *Decoder) {
1265 
1266  const FeatureBitset &featureBits =
1267  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1268 
1269  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1271 
1272  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1273  return S;
1274 }
1275 
1276 static const uint16_t SPRDecoderTable[] = {
1277  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1278  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1279  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1280  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1281  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1282  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1283  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1284  ARM::S28, ARM::S29, ARM::S30, ARM::S31
1285 };
1286 
1287 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1288  uint64_t Address, const void *Decoder) {
1289  if (RegNo > 31)
1290  return MCDisassembler::Fail;
1291 
1292  unsigned Register = SPRDecoderTable[RegNo];
1293  Inst.addOperand(MCOperand::createReg(Register));
1294  return MCDisassembler::Success;
1295 }
1296 
1297 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1298  uint64_t Address, const void *Decoder) {
1299  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1300 }
1301 
1302 static const uint16_t DPRDecoderTable[] = {
1303  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1304  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1305  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1306  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1307  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1308  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1309  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1310  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1311 };
1312 
1313 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1314  uint64_t Address, const void *Decoder) {
1315  const FeatureBitset &featureBits =
1316  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1317 
1318  bool hasD32 = featureBits[ARM::FeatureD32];
1319 
1320  if (RegNo > 31 || (!hasD32 && RegNo > 15))
1321  return MCDisassembler::Fail;
1322 
1323  unsigned Register = DPRDecoderTable[RegNo];
1324  Inst.addOperand(MCOperand::createReg(Register));
1325  return MCDisassembler::Success;
1326 }
1327 
1328 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1329  uint64_t Address, const void *Decoder) {
1330  if (RegNo > 7)
1331  return MCDisassembler::Fail;
1332  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1333 }
1334 
1335 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1336  uint64_t Address, const void *Decoder) {
1337  if (RegNo > 15)
1338  return MCDisassembler::Fail;
1339  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1340 }
1341 
1342 static DecodeStatus
1343 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1344  uint64_t Address, const void *Decoder) {
1345  if (RegNo > 15)
1346  return MCDisassembler::Fail;
1347  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1348 }
1349 
1350 static const uint16_t QPRDecoderTable[] = {
1351  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1352  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1353  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1354  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1355 };
1356 
1357 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1358  uint64_t Address, const void *Decoder) {
1359  if (RegNo > 31 || (RegNo & 1) != 0)
1360  return MCDisassembler::Fail;
1361  RegNo >>= 1;
1362 
1363  unsigned Register = QPRDecoderTable[RegNo];
1364  Inst.addOperand(MCOperand::createReg(Register));
1365  return MCDisassembler::Success;
1366 }
1367 
1368 static const uint16_t DPairDecoderTable[] = {
1369  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1370  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1371  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1372  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1373  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1374  ARM::Q15
1375 };
1376 
1377 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1378  uint64_t Address, const void *Decoder) {
1379  if (RegNo > 30)
1380  return MCDisassembler::Fail;
1381 
1382  unsigned Register = DPairDecoderTable[RegNo];
1383  Inst.addOperand(MCOperand::createReg(Register));
1384  return MCDisassembler::Success;
1385 }
1386 
1387 static const uint16_t DPairSpacedDecoderTable[] = {
1388  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1389  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1390  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1391  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1392  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1393  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1394  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1395  ARM::D28_D30, ARM::D29_D31
1396 };
1397 
1399  unsigned RegNo,
1400  uint64_t Address,
1401  const void *Decoder) {
1402  if (RegNo > 29)
1403  return MCDisassembler::Fail;
1404 
1405  unsigned Register = DPairSpacedDecoderTable[RegNo];
1406  Inst.addOperand(MCOperand::createReg(Register));
1407  return MCDisassembler::Success;
1408 }
1409 
1410 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1411  uint64_t Address, const void *Decoder) {
1413  if (Val == 0xF) return MCDisassembler::Fail;
1414  // AL predicate is not allowed on Thumb1 branches.
1415  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1416  return MCDisassembler::Fail;
1417  if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1419  Inst.addOperand(MCOperand::createImm(Val));
1420  if (Val == ARMCC::AL) {
1422  } else
1423  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1424  return S;
1425 }
1426 
1427 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1428  uint64_t Address, const void *Decoder) {
1429  if (Val)
1430  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1431  else
1433  return MCDisassembler::Success;
1434 }
1435 
1436 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1437  uint64_t Address, const void *Decoder) {
1439 
1440  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1441  unsigned type = fieldFromInstruction(Val, 5, 2);
1442  unsigned imm = fieldFromInstruction(Val, 7, 5);
1443 
1444  // Register-immediate
1445  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1446  return MCDisassembler::Fail;
1447 
1448  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1449  switch (type) {
1450  case 0:
1451  Shift = ARM_AM::lsl;
1452  break;
1453  case 1:
1454  Shift = ARM_AM::lsr;
1455  break;
1456  case 2:
1457  Shift = ARM_AM::asr;
1458  break;
1459  case 3:
1460  Shift = ARM_AM::ror;
1461  break;
1462  }
1463 
1464  if (Shift == ARM_AM::ror && imm == 0)
1465  Shift = ARM_AM::rrx;
1466 
1467  unsigned Op = Shift | (imm << 3);
1468  Inst.addOperand(MCOperand::createImm(Op));
1469 
1470  return S;
1471 }
1472 
1473 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1474  uint64_t Address, const void *Decoder) {
1476 
1477  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1478  unsigned type = fieldFromInstruction(Val, 5, 2);
1479  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1480 
1481  // Register-register
1482  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1483  return MCDisassembler::Fail;
1484  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1485  return MCDisassembler::Fail;
1486 
1487  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1488  switch (type) {
1489  case 0:
1490  Shift = ARM_AM::lsl;
1491  break;
1492  case 1:
1493  Shift = ARM_AM::lsr;
1494  break;
1495  case 2:
1496  Shift = ARM_AM::asr;
1497  break;
1498  case 3:
1499  Shift = ARM_AM::ror;
1500  break;
1501  }
1502 
1503  Inst.addOperand(MCOperand::createImm(Shift));
1504 
1505  return S;
1506 }
1507 
1508 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1509  uint64_t Address, const void *Decoder) {
1511 
1512  bool NeedDisjointWriteback = false;
1513  unsigned WritebackReg = 0;
1514  bool CLRM = false;
1515  switch (Inst.getOpcode()) {
1516  default:
1517  break;
1518  case ARM::LDMIA_UPD:
1519  case ARM::LDMDB_UPD:
1520  case ARM::LDMIB_UPD:
1521  case ARM::LDMDA_UPD:
1522  case ARM::t2LDMIA_UPD:
1523  case ARM::t2LDMDB_UPD:
1524  case ARM::t2STMIA_UPD:
1525  case ARM::t2STMDB_UPD:
1526  NeedDisjointWriteback = true;
1527  WritebackReg = Inst.getOperand(0).getReg();
1528  break;
1529  case ARM::t2CLRM:
1530  CLRM = true;
1531  break;
1532  }
1533 
1534  // Empty register lists are not allowed.
1535  if (Val == 0) return MCDisassembler::Fail;
1536  for (unsigned i = 0; i < 16; ++i) {
1537  if (Val & (1 << i)) {
1538  if (CLRM) {
1539  if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1540  return MCDisassembler::Fail;
1541  }
1542  } else {
1543  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1544  return MCDisassembler::Fail;
1545  // Writeback not allowed if Rn is in the target list.
1546  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1548  }
1549  }
1550  }
1551 
1552  return S;
1553 }
1554 
1555 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1556  uint64_t Address, const void *Decoder) {
1558 
1559  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1560  unsigned regs = fieldFromInstruction(Val, 0, 8);
1561 
1562  // In case of unpredictable encoding, tweak the operands.
1563  if (regs == 0 || (Vd + regs) > 32) {
1564  regs = Vd + regs > 32 ? 32 - Vd : regs;
1565  regs = std::max( 1u, regs);
1567  }
1568 
1569  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1570  return MCDisassembler::Fail;
1571  for (unsigned i = 0; i < (regs - 1); ++i) {
1572  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1573  return MCDisassembler::Fail;
1574  }
1575 
1576  return S;
1577 }
1578 
1579 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1580  uint64_t Address, const void *Decoder) {
1582 
1583  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1584  unsigned regs = fieldFromInstruction(Val, 1, 7);
1585 
1586  // In case of unpredictable encoding, tweak the operands.
1587  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1588  regs = Vd + regs > 32 ? 32 - Vd : regs;
1589  regs = std::max( 1u, regs);
1590  regs = std::min(16u, regs);
1592  }
1593 
1594  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1595  return MCDisassembler::Fail;
1596  for (unsigned i = 0; i < (regs - 1); ++i) {
1597  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1598  return MCDisassembler::Fail;
1599  }
1600 
1601  return S;
1602 }
1603 
1604 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1605  uint64_t Address, const void *Decoder) {
1606  // This operand encodes a mask of contiguous zeros between a specified MSB
1607  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1608  // the mask of all bits LSB-and-lower, and then xor them to create
1609  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1610  // create the final mask.
1611  unsigned msb = fieldFromInstruction(Val, 5, 5);
1612  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1613 
1615  if (lsb > msb) {
1617  // The check above will cause the warning for the "potentially undefined
1618  // instruction encoding" but we can't build a bad MCOperand value here
1619  // with a lsb > msb or else printing the MCInst will cause a crash.
1620  lsb = msb;
1621  }
1622 
1623  uint32_t msb_mask = 0xFFFFFFFF;
1624  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1625  uint32_t lsb_mask = (1U << lsb) - 1;
1626 
1627  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1628  return S;
1629 }
1630 
1631 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1632  uint64_t Address, const void *Decoder) {
1634 
1635  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1636  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1637  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1638  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1639  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1640  unsigned U = fieldFromInstruction(Insn, 23, 1);
1641  const FeatureBitset &featureBits =
1642  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1643 
1644  switch (Inst.getOpcode()) {
1645  case ARM::LDC_OFFSET:
1646  case ARM::LDC_PRE:
1647  case ARM::LDC_POST:
1648  case ARM::LDC_OPTION:
1649  case ARM::LDCL_OFFSET:
1650  case ARM::LDCL_PRE:
1651  case ARM::LDCL_POST:
1652  case ARM::LDCL_OPTION:
1653  case ARM::STC_OFFSET:
1654  case ARM::STC_PRE:
1655  case ARM::STC_POST:
1656  case ARM::STC_OPTION:
1657  case ARM::STCL_OFFSET:
1658  case ARM::STCL_PRE:
1659  case ARM::STCL_POST:
1660  case ARM::STCL_OPTION:
1661  case ARM::t2LDC_OFFSET:
1662  case ARM::t2LDC_PRE:
1663  case ARM::t2LDC_POST:
1664  case ARM::t2LDC_OPTION:
1665  case ARM::t2LDCL_OFFSET:
1666  case ARM::t2LDCL_PRE:
1667  case ARM::t2LDCL_POST:
1668  case ARM::t2LDCL_OPTION:
1669  case ARM::t2STC_OFFSET:
1670  case ARM::t2STC_PRE:
1671  case ARM::t2STC_POST:
1672  case ARM::t2STC_OPTION:
1673  case ARM::t2STCL_OFFSET:
1674  case ARM::t2STCL_PRE:
1675  case ARM::t2STCL_POST:
1676  case ARM::t2STCL_OPTION:
1677  case ARM::t2LDC2_OFFSET:
1678  case ARM::t2LDC2L_OFFSET:
1679  case ARM::t2LDC2_PRE:
1680  case ARM::t2LDC2L_PRE:
1681  case ARM::t2STC2_OFFSET:
1682  case ARM::t2STC2L_OFFSET:
1683  case ARM::t2STC2_PRE:
1684  case ARM::t2STC2L_PRE:
1685  case ARM::LDC2_OFFSET:
1686  case ARM::LDC2L_OFFSET:
1687  case ARM::LDC2_PRE:
1688  case ARM::LDC2L_PRE:
1689  case ARM::STC2_OFFSET:
1690  case ARM::STC2L_OFFSET:
1691  case ARM::STC2_PRE:
1692  case ARM::STC2L_PRE:
1693  case ARM::t2LDC2_OPTION:
1694  case ARM::t2STC2_OPTION:
1695  case ARM::t2LDC2_POST:
1696  case ARM::t2LDC2L_POST:
1697  case ARM::t2STC2_POST:
1698  case ARM::t2STC2L_POST:
1699  case ARM::LDC2_POST:
1700  case ARM::LDC2L_POST:
1701  case ARM::STC2_POST:
1702  case ARM::STC2L_POST:
1703  if (coproc == 0xA || coproc == 0xB ||
1704  (featureBits[ARM::HasV8_1MMainlineOps] &&
1705  (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1706  coproc == 0xE || coproc == 0xF)))
1707  return MCDisassembler::Fail;
1708  break;
1709  default:
1710  break;
1711  }
1712 
1713  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1714  return MCDisassembler::Fail;
1715 
1716  Inst.addOperand(MCOperand::createImm(coproc));
1717  Inst.addOperand(MCOperand::createImm(CRd));
1718  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1719  return MCDisassembler::Fail;
1720 
1721  switch (Inst.getOpcode()) {
1722  case ARM::t2LDC2_OFFSET:
1723  case ARM::t2LDC2L_OFFSET:
1724  case ARM::t2LDC2_PRE:
1725  case ARM::t2LDC2L_PRE:
1726  case ARM::t2STC2_OFFSET:
1727  case ARM::t2STC2L_OFFSET:
1728  case ARM::t2STC2_PRE:
1729  case ARM::t2STC2L_PRE:
1730  case ARM::LDC2_OFFSET:
1731  case ARM::LDC2L_OFFSET:
1732  case ARM::LDC2_PRE:
1733  case ARM::LDC2L_PRE:
1734  case ARM::STC2_OFFSET:
1735  case ARM::STC2L_OFFSET:
1736  case ARM::STC2_PRE:
1737  case ARM::STC2L_PRE:
1738  case ARM::t2LDC_OFFSET:
1739  case ARM::t2LDCL_OFFSET:
1740  case ARM::t2LDC_PRE:
1741  case ARM::t2LDCL_PRE:
1742  case ARM::t2STC_OFFSET:
1743  case ARM::t2STCL_OFFSET:
1744  case ARM::t2STC_PRE:
1745  case ARM::t2STCL_PRE:
1746  case ARM::LDC_OFFSET:
1747  case ARM::LDCL_OFFSET:
1748  case ARM::LDC_PRE:
1749  case ARM::LDCL_PRE:
1750  case ARM::STC_OFFSET:
1751  case ARM::STCL_OFFSET:
1752  case ARM::STC_PRE:
1753  case ARM::STCL_PRE:
1754  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1755  Inst.addOperand(MCOperand::createImm(imm));
1756  break;
1757  case ARM::t2LDC2_POST:
1758  case ARM::t2LDC2L_POST:
1759  case ARM::t2STC2_POST:
1760  case ARM::t2STC2L_POST:
1761  case ARM::LDC2_POST:
1762  case ARM::LDC2L_POST:
1763  case ARM::STC2_POST:
1764  case ARM::STC2L_POST:
1765  case ARM::t2LDC_POST:
1766  case ARM::t2LDCL_POST:
1767  case ARM::t2STC_POST:
1768  case ARM::t2STCL_POST:
1769  case ARM::LDC_POST:
1770  case ARM::LDCL_POST:
1771  case ARM::STC_POST:
1772  case ARM::STCL_POST:
1773  imm |= U << 8;
1775  default:
1776  // The 'option' variant doesn't encode 'U' in the immediate since
1777  // the immediate is unsigned [0,255].
1778  Inst.addOperand(MCOperand::createImm(imm));
1779  break;
1780  }
1781 
1782  switch (Inst.getOpcode()) {
1783  case ARM::LDC_OFFSET:
1784  case ARM::LDC_PRE:
1785  case ARM::LDC_POST:
1786  case ARM::LDC_OPTION:
1787  case ARM::LDCL_OFFSET:
1788  case ARM::LDCL_PRE:
1789  case ARM::LDCL_POST:
1790  case ARM::LDCL_OPTION:
1791  case ARM::STC_OFFSET:
1792  case ARM::STC_PRE:
1793  case ARM::STC_POST:
1794  case ARM::STC_OPTION:
1795  case ARM::STCL_OFFSET:
1796  case ARM::STCL_PRE:
1797  case ARM::STCL_POST:
1798  case ARM::STCL_OPTION:
1799  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1800  return MCDisassembler::Fail;
1801  break;
1802  default:
1803  break;
1804  }
1805 
1806  return S;
1807 }
1808 
1809 static DecodeStatus
1811  uint64_t Address, const void *Decoder) {
1813 
1814  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1815  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1816  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1817  unsigned imm = fieldFromInstruction(Insn, 0, 12);
1818  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1819  unsigned reg = fieldFromInstruction(Insn, 25, 1);
1820  unsigned P = fieldFromInstruction(Insn, 24, 1);
1821  unsigned W = fieldFromInstruction(Insn, 21, 1);
1822 
1823  // On stores, the writeback operand precedes Rt.
1824  switch (Inst.getOpcode()) {
1825  case ARM::STR_POST_IMM:
1826  case ARM::STR_POST_REG:
1827  case ARM::STRB_POST_IMM:
1828  case ARM::STRB_POST_REG:
1829  case ARM::STRT_POST_REG:
1830  case ARM::STRT_POST_IMM:
1831  case ARM::STRBT_POST_REG:
1832  case ARM::STRBT_POST_IMM:
1833  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1834  return MCDisassembler::Fail;
1835  break;
1836  default:
1837  break;
1838  }
1839 
1840  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1841  return MCDisassembler::Fail;
1842 
1843  // On loads, the writeback operand comes after Rt.
1844  switch (Inst.getOpcode()) {
1845  case ARM::LDR_POST_IMM:
1846  case ARM::LDR_POST_REG:
1847  case ARM::LDRB_POST_IMM:
1848  case ARM::LDRB_POST_REG:
1849  case ARM::LDRBT_POST_REG:
1850  case ARM::LDRBT_POST_IMM:
1851  case ARM::LDRT_POST_REG:
1852  case ARM::LDRT_POST_IMM:
1853  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1854  return MCDisassembler::Fail;
1855  break;
1856  default:
1857  break;
1858  }
1859 
1860  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1861  return MCDisassembler::Fail;
1862 
1864  if (!fieldFromInstruction(Insn, 23, 1))
1865  Op = ARM_AM::sub;
1866 
1867  bool writeback = (P == 0) || (W == 1);
1868  unsigned idx_mode = 0;
1869  if (P && writeback)
1870  idx_mode = ARMII::IndexModePre;
1871  else if (!P && writeback)
1872  idx_mode = ARMII::IndexModePost;
1873 
1874  if (writeback && (Rn == 15 || Rn == Rt))
1875  S = MCDisassembler::SoftFail; // UNPREDICTABLE
1876 
1877  if (reg) {
1878  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1879  return MCDisassembler::Fail;
1881  switch( fieldFromInstruction(Insn, 5, 2)) {
1882  case 0:
1883  Opc = ARM_AM::lsl;
1884  break;
1885  case 1:
1886  Opc = ARM_AM::lsr;
1887  break;
1888  case 2:
1889  Opc = ARM_AM::asr;
1890  break;
1891  case 3:
1892  Opc = ARM_AM::ror;
1893  break;
1894  default:
1895  return MCDisassembler::Fail;
1896  }
1897  unsigned amt = fieldFromInstruction(Insn, 7, 5);
1898  if (Opc == ARM_AM::ror && amt == 0)
1899  Opc = ARM_AM::rrx;
1900  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1901 
1902  Inst.addOperand(MCOperand::createImm(imm));
1903  } else {
1905  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1906  Inst.addOperand(MCOperand::createImm(tmp));
1907  }
1908 
1909  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1910  return MCDisassembler::Fail;
1911 
1912  return S;
1913 }
1914 
1915 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1916  uint64_t Address, const void *Decoder) {
1918 
1919  unsigned Rn = fieldFromInstruction(Val, 13, 4);
1920  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1921  unsigned type = fieldFromInstruction(Val, 5, 2);
1922  unsigned imm = fieldFromInstruction(Val, 7, 5);
1923  unsigned U = fieldFromInstruction(Val, 12, 1);
1924 
1926  switch (type) {
1927  case 0:
1928  ShOp = ARM_AM::lsl;
1929  break;
1930  case 1:
1931  ShOp = ARM_AM::lsr;
1932  break;
1933  case 2:
1934  ShOp = ARM_AM::asr;
1935  break;
1936  case 3:
1937  ShOp = ARM_AM::ror;
1938  break;
1939  }
1940 
1941  if (ShOp == ARM_AM::ror && imm == 0)
1942  ShOp = ARM_AM::rrx;
1943 
1944  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1945  return MCDisassembler::Fail;
1946  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1947  return MCDisassembler::Fail;
1948  unsigned shift;
1949  if (U)
1950  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1951  else
1952  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1953  Inst.addOperand(MCOperand::createImm(shift));
1954 
1955  return S;
1956 }
1957 
1958 static DecodeStatus
1959 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1960  uint64_t Address, const void *Decoder) {
1962 
1963  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1964  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1965  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1966  unsigned type = fieldFromInstruction(Insn, 22, 1);
1967  unsigned imm = fieldFromInstruction(Insn, 8, 4);
1968  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1969  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1970  unsigned W = fieldFromInstruction(Insn, 21, 1);
1971  unsigned P = fieldFromInstruction(Insn, 24, 1);
1972  unsigned Rt2 = Rt + 1;
1973 
1974  bool writeback = (W == 1) | (P == 0);
1975 
1976  // For {LD,ST}RD, Rt must be even, else undefined.
1977  switch (Inst.getOpcode()) {
1978  case ARM::STRD:
1979  case ARM::STRD_PRE:
1980  case ARM::STRD_POST:
1981  case ARM::LDRD:
1982  case ARM::LDRD_PRE:
1983  case ARM::LDRD_POST:
1984  if (Rt & 0x1) S = MCDisassembler::SoftFail;
1985  break;
1986  default:
1987  break;
1988  }
1989  switch (Inst.getOpcode()) {
1990  case ARM::STRD:
1991  case ARM::STRD_PRE:
1992  case ARM::STRD_POST:
1993  if (P == 0 && W == 1)
1995 
1996  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1998  if (type && Rm == 15)
2000  if (Rt2 == 15)
2002  if (!type && fieldFromInstruction(Insn, 8, 4))
2004  break;
2005  case ARM::STRH:
2006  case ARM::STRH_PRE:
2007  case ARM::STRH_POST:
2008  if (Rt == 15)
2010  if (writeback && (Rn == 15 || Rn == Rt))
2012  if (!type && Rm == 15)
2014  break;
2015  case ARM::LDRD:
2016  case ARM::LDRD_PRE:
2017  case ARM::LDRD_POST:
2018  if (type && Rn == 15) {
2019  if (Rt2 == 15)
2021  break;
2022  }
2023  if (P == 0 && W == 1)
2025  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2027  if (!type && writeback && Rn == 15)
2029  if (writeback && (Rn == Rt || Rn == Rt2))
2031  break;
2032  case ARM::LDRH:
2033  case ARM::LDRH_PRE:
2034  case ARM::LDRH_POST:
2035  if (type && Rn == 15) {
2036  if (Rt == 15)
2038  break;
2039  }
2040  if (Rt == 15)
2042  if (!type && Rm == 15)
2044  if (!type && writeback && (Rn == 15 || Rn == Rt))
2046  break;
2047  case ARM::LDRSH:
2048  case ARM::LDRSH_PRE:
2049  case ARM::LDRSH_POST:
2050  case ARM::LDRSB:
2051  case ARM::LDRSB_PRE:
2052  case ARM::LDRSB_POST:
2053  if (type && Rn == 15) {
2054  if (Rt == 15)
2056  break;
2057  }
2058  if (type && (Rt == 15 || (writeback && Rn == Rt)))
2060  if (!type && (Rt == 15 || Rm == 15))
2062  if (!type && writeback && (Rn == 15 || Rn == Rt))
2064  break;
2065  default:
2066  break;
2067  }
2068 
2069  if (writeback) { // Writeback
2070  if (P)
2071  U |= ARMII::IndexModePre << 9;
2072  else
2073  U |= ARMII::IndexModePost << 9;
2074 
2075  // On stores, the writeback operand precedes Rt.
2076  switch (Inst.getOpcode()) {
2077  case ARM::STRD:
2078  case ARM::STRD_PRE:
2079  case ARM::STRD_POST:
2080  case ARM::STRH:
2081  case ARM::STRH_PRE:
2082  case ARM::STRH_POST:
2083  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2084  return MCDisassembler::Fail;
2085  break;
2086  default:
2087  break;
2088  }
2089  }
2090 
2091  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2092  return MCDisassembler::Fail;
2093  switch (Inst.getOpcode()) {
2094  case ARM::STRD:
2095  case ARM::STRD_PRE:
2096  case ARM::STRD_POST:
2097  case ARM::LDRD:
2098  case ARM::LDRD_PRE:
2099  case ARM::LDRD_POST:
2100  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2101  return MCDisassembler::Fail;
2102  break;
2103  default:
2104  break;
2105  }
2106 
2107  if (writeback) {
2108  // On loads, the writeback operand comes after Rt.
2109  switch (Inst.getOpcode()) {
2110  case ARM::LDRD:
2111  case ARM::LDRD_PRE:
2112  case ARM::LDRD_POST:
2113  case ARM::LDRH:
2114  case ARM::LDRH_PRE:
2115  case ARM::LDRH_POST:
2116  case ARM::LDRSH:
2117  case ARM::LDRSH_PRE:
2118  case ARM::LDRSH_POST:
2119  case ARM::LDRSB:
2120  case ARM::LDRSB_PRE:
2121  case ARM::LDRSB_POST:
2122  case ARM::LDRHTr:
2123  case ARM::LDRSBTr:
2124  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2125  return MCDisassembler::Fail;
2126  break;
2127  default:
2128  break;
2129  }
2130  }
2131 
2132  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2133  return MCDisassembler::Fail;
2134 
2135  if (type) {
2137  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2138  } else {
2139  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2140  return MCDisassembler::Fail;
2142  }
2143 
2144  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2145  return MCDisassembler::Fail;
2146 
2147  return S;
2148 }
2149 
2150 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2151  uint64_t Address, const void *Decoder) {
2153 
2154  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2155  unsigned mode = fieldFromInstruction(Insn, 23, 2);
2156 
2157  switch (mode) {
2158  case 0:
2159  mode = ARM_AM::da;
2160  break;
2161  case 1:
2162  mode = ARM_AM::ia;
2163  break;
2164  case 2:
2165  mode = ARM_AM::db;
2166  break;
2167  case 3:
2168  mode = ARM_AM::ib;
2169  break;
2170  }
2171 
2172  Inst.addOperand(MCOperand::createImm(mode));
2173  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2174  return MCDisassembler::Fail;
2175 
2176  return S;
2177 }
2178 
2179 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2180  uint64_t Address, const void *Decoder) {
2182 
2183  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2184  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2185  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2186  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2187 
2188  if (pred == 0xF)
2189  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2190 
2191  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2192  return MCDisassembler::Fail;
2193  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2194  return MCDisassembler::Fail;
2195  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2196  return MCDisassembler::Fail;
2197  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2198  return MCDisassembler::Fail;
2199  return S;
2200 }
2201 
2203  unsigned Insn,
2204  uint64_t Address, const void *Decoder) {
2206 
2207  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2208  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2209  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2210 
2211  if (pred == 0xF) {
2212  // Ambiguous with RFE and SRS
2213  switch (Inst.getOpcode()) {
2214  case ARM::LDMDA:
2215  Inst.setOpcode(ARM::RFEDA);
2216  break;
2217  case ARM::LDMDA_UPD:
2218  Inst.setOpcode(ARM::RFEDA_UPD);
2219  break;
2220  case ARM::LDMDB:
2221  Inst.setOpcode(ARM::RFEDB);
2222  break;
2223  case ARM::LDMDB_UPD:
2224  Inst.setOpcode(ARM::RFEDB_UPD);
2225  break;
2226  case ARM::LDMIA:
2227  Inst.setOpcode(ARM::RFEIA);
2228  break;
2229  case ARM::LDMIA_UPD:
2230  Inst.setOpcode(ARM::RFEIA_UPD);
2231  break;
2232  case ARM::LDMIB:
2233  Inst.setOpcode(ARM::RFEIB);
2234  break;
2235  case ARM::LDMIB_UPD:
2236  Inst.setOpcode(ARM::RFEIB_UPD);
2237  break;
2238  case ARM::STMDA:
2239  Inst.setOpcode(ARM::SRSDA);
2240  break;
2241  case ARM::STMDA_UPD:
2242  Inst.setOpcode(ARM::SRSDA_UPD);
2243  break;
2244  case ARM::STMDB:
2245  Inst.setOpcode(ARM::SRSDB);
2246  break;
2247  case ARM::STMDB_UPD:
2248  Inst.setOpcode(ARM::SRSDB_UPD);
2249  break;
2250  case ARM::STMIA:
2251  Inst.setOpcode(ARM::SRSIA);
2252  break;
2253  case ARM::STMIA_UPD:
2254  Inst.setOpcode(ARM::SRSIA_UPD);
2255  break;
2256  case ARM::STMIB:
2257  Inst.setOpcode(ARM::SRSIB);
2258  break;
2259  case ARM::STMIB_UPD:
2260  Inst.setOpcode(ARM::SRSIB_UPD);
2261  break;
2262  default:
2263  return MCDisassembler::Fail;
2264  }
2265 
2266  // For stores (which become SRS's, the only operand is the mode.
2267  if (fieldFromInstruction(Insn, 20, 1) == 0) {
2268  // Check SRS encoding constraints
2269  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2270  fieldFromInstruction(Insn, 20, 1) == 0))
2271  return MCDisassembler::Fail;
2272 
2273  Inst.addOperand(
2274  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2275  return S;
2276  }
2277 
2278  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2279  }
2280 
2281  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2282  return MCDisassembler::Fail;
2283  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2284  return MCDisassembler::Fail; // Tied
2285  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2286  return MCDisassembler::Fail;
2287  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2288  return MCDisassembler::Fail;
2289 
2290  return S;
2291 }
2292 
2293 // Check for UNPREDICTABLE predicated ESB instruction
2294 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2295  uint64_t Address, const void *Decoder) {
2296  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2297  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2298  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2299  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2300 
2302 
2303  Inst.addOperand(MCOperand::createImm(imm8));
2304 
2305  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2306  return MCDisassembler::Fail;
2307 
2308  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2309  // so all predicates should be allowed.
2310  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2312 
2313  return S;
2314 }
2315 
2316 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2317  uint64_t Address, const void *Decoder) {
2318  unsigned imod = fieldFromInstruction(Insn, 18, 2);
2319  unsigned M = fieldFromInstruction(Insn, 17, 1);
2320  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2321  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2322 
2324 
2325  // This decoder is called from multiple location that do not check
2326  // the full encoding is valid before they do.
2327  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2328  fieldFromInstruction(Insn, 16, 1) != 0 ||
2329  fieldFromInstruction(Insn, 20, 8) != 0x10)
2330  return MCDisassembler::Fail;
2331 
2332  // imod == '01' --> UNPREDICTABLE
2333  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2334  // return failure here. The '01' imod value is unprintable, so there's
2335  // nothing useful we could do even if we returned UNPREDICTABLE.
2336 
2337  if (imod == 1) return MCDisassembler::Fail;
2338 
2339  if (imod && M) {
2340  Inst.setOpcode(ARM::CPS3p);
2341  Inst.addOperand(MCOperand::createImm(imod));
2342  Inst.addOperand(MCOperand::createImm(iflags));
2343  Inst.addOperand(MCOperand::createImm(mode));
2344  } else if (imod && !M) {
2345  Inst.setOpcode(ARM::CPS2p);
2346  Inst.addOperand(MCOperand::createImm(imod));
2347  Inst.addOperand(MCOperand::createImm(iflags));
2348  if (mode) S = MCDisassembler::SoftFail;
2349  } else if (!imod && M) {
2350  Inst.setOpcode(ARM::CPS1p);
2351  Inst.addOperand(MCOperand::createImm(mode));
2352  if (iflags) S = MCDisassembler::SoftFail;
2353  } else {
2354  // imod == '00' && M == '0' --> UNPREDICTABLE
2355  Inst.setOpcode(ARM::CPS1p);
2356  Inst.addOperand(MCOperand::createImm(mode));
2358  }
2359 
2360  return S;
2361 }
2362 
2363 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2364  uint64_t Address, const void *Decoder) {
2365  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2366  unsigned M = fieldFromInstruction(Insn, 8, 1);
2367  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2368  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2369 
2371 
2372  // imod == '01' --> UNPREDICTABLE
2373  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2374  // return failure here. The '01' imod value is unprintable, so there's
2375  // nothing useful we could do even if we returned UNPREDICTABLE.
2376 
2377  if (imod == 1) return MCDisassembler::Fail;
2378 
2379  if (imod && M) {
2380  Inst.setOpcode(ARM::t2CPS3p);
2381  Inst.addOperand(MCOperand::createImm(imod));
2382  Inst.addOperand(MCOperand::createImm(iflags));
2383  Inst.addOperand(MCOperand::createImm(mode));
2384  } else if (imod && !M) {
2385  Inst.setOpcode(ARM::t2CPS2p);
2386  Inst.addOperand(MCOperand::createImm(imod));
2387  Inst.addOperand(MCOperand::createImm(iflags));
2388  if (mode) S = MCDisassembler::SoftFail;
2389  } else if (!imod && M) {
2390  Inst.setOpcode(ARM::t2CPS1p);
2391  Inst.addOperand(MCOperand::createImm(mode));
2392  if (iflags) S = MCDisassembler::SoftFail;
2393  } else {
2394  // imod == '00' && M == '0' --> this is a HINT instruction
2395  int imm = fieldFromInstruction(Insn, 0, 8);
2396  // HINT are defined only for immediate in [0..4]
2397  if(imm > 4) return MCDisassembler::Fail;
2398  Inst.setOpcode(ARM::t2HINT);
2399  Inst.addOperand(MCOperand::createImm(imm));
2400  }
2401 
2402  return S;
2403 }
2404 
2405 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2406  uint64_t Address, const void *Decoder) {
2408 
2409  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2410  unsigned imm = 0;
2411 
2412  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2413  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2414  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2415  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2416 
2417  if (Inst.getOpcode() == ARM::t2MOVTi16)
2418  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2419  return MCDisassembler::Fail;
2420  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2421  return MCDisassembler::Fail;
2422 
2423  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2424  Inst.addOperand(MCOperand::createImm(imm));
2425 
2426  return S;
2427 }
2428 
2429 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2430  uint64_t Address, const void *Decoder) {
2432 
2433  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2434  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2435  unsigned imm = 0;
2436 
2437  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2438  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2439 
2440  if (Inst.getOpcode() == ARM::MOVTi16)
2441  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2442  return MCDisassembler::Fail;
2443 
2444  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2445  return MCDisassembler::Fail;
2446 
2447  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2448  Inst.addOperand(MCOperand::createImm(imm));
2449 
2450  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2451  return MCDisassembler::Fail;
2452 
2453  return S;
2454 }
2455 
2456 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2457  uint64_t Address, const void *Decoder) {
2459 
2460  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2461  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2462  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2463  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2464  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2465 
2466  if (pred == 0xF)
2467  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2468 
2469  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2470  return MCDisassembler::Fail;
2471  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2472  return MCDisassembler::Fail;
2473  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2474  return MCDisassembler::Fail;
2475  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2476  return MCDisassembler::Fail;
2477 
2478  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2479  return MCDisassembler::Fail;
2480 
2481  return S;
2482 }
2483 
2484 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2485  uint64_t Address, const void *Decoder) {
2487 
2488  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2489  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2490  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2491 
2492  if (Pred == 0xF)
2493  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2494 
2495  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2496  return MCDisassembler::Fail;
2497  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2498  return MCDisassembler::Fail;
2499  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2500  return MCDisassembler::Fail;
2501 
2502  return S;
2503 }
2504 
2505 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2506  uint64_t Address, const void *Decoder) {
2508 
2509  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2510 
2511  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2512  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2513 
2514  if (!FeatureBits[ARM::HasV8_1aOps] ||
2515  !FeatureBits[ARM::HasV8Ops])
2516  return MCDisassembler::Fail;
2517 
2518  // Decoder can be called from DecodeTST, which does not check the full
2519  // encoding is valid.
2520  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2521  fieldFromInstruction(Insn, 4,4) != 0)
2522  return MCDisassembler::Fail;
2523  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2524  fieldFromInstruction(Insn, 0,4) != 0)
2526 
2527  Inst.setOpcode(ARM::SETPAN);
2528  Inst.addOperand(MCOperand::createImm(Imm));
2529 
2530  return S;
2531 }
2532 
2534  uint64_t Address, const void *Decoder) {
2536 
2537  unsigned add = fieldFromInstruction(Val, 12, 1);
2538  unsigned imm = fieldFromInstruction(Val, 0, 12);
2539  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2540 
2541  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2542  return MCDisassembler::Fail;
2543 
2544  if (!add) imm *= -1;
2545  if (imm == 0 && !add) imm = INT32_MIN;
2546  Inst.addOperand(MCOperand::createImm(imm));
2547  if (Rn == 15)
2548  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2549 
2550  return S;
2551 }
2552 
2553 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2554  uint64_t Address, const void *Decoder) {
2556 
2557  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2558  // U == 1 to add imm, 0 to subtract it.
2559  unsigned U = fieldFromInstruction(Val, 8, 1);
2560  unsigned imm = fieldFromInstruction(Val, 0, 8);
2561 
2562  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2563  return MCDisassembler::Fail;
2564 
2565  if (U)
2567  else
2569 
2570  return S;
2571 }
2572 
2574  uint64_t Address, const void *Decoder) {
2576 
2577  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2578  // U == 1 to add imm, 0 to subtract it.
2579  unsigned U = fieldFromInstruction(Val, 8, 1);
2580  unsigned imm = fieldFromInstruction(Val, 0, 8);
2581 
2582  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2583  return MCDisassembler::Fail;
2584 
2585  if (U)
2587  else
2589 
2590  return S;
2591 }
2592 
2593 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2594  uint64_t Address, const void *Decoder) {
2595  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2596 }
2597 
2598 static DecodeStatus
2599 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2600  uint64_t Address, const void *Decoder) {
2602 
2603  // Note the J1 and J2 values are from the encoded instruction. So here
2604  // change them to I1 and I2 values via as documented:
2605  // I1 = NOT(J1 EOR S);
2606  // I2 = NOT(J2 EOR S);
2607  // and build the imm32 with one trailing zero as documented:
2608  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2609  unsigned S = fieldFromInstruction(Insn, 26, 1);
2610  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2611  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2612  unsigned I1 = !(J1 ^ S);
2613  unsigned I2 = !(J2 ^ S);
2614  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2615  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2616  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2617  int imm32 = SignExtend32<25>(tmp << 1);
2618  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2619  true, 4, Inst, Decoder))
2620  Inst.addOperand(MCOperand::createImm(imm32));
2621 
2622  return Status;
2623 }
2624 
2625 static DecodeStatus
2626 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2627  uint64_t Address, const void *Decoder) {
2629 
2630  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2631  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2632 
2633  if (pred == 0xF) {
2634  Inst.setOpcode(ARM::BLXi);
2635  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2636  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2637  true, 4, Inst, Decoder))
2638  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2639  return S;
2640  }
2641 
2642  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2643  true, 4, Inst, Decoder))
2644  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2645  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2646  return MCDisassembler::Fail;
2647 
2648  return S;
2649 }
2650 
2651 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2652  uint64_t Address, const void *Decoder) {
2654 
2655  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2656  unsigned align = fieldFromInstruction(Val, 4, 2);
2657 
2658  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2659  return MCDisassembler::Fail;
2660  if (!align)
2662  else
2663  Inst.addOperand(MCOperand::createImm(4 << align));
2664 
2665  return S;
2666 }
2667 
2668 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2669  uint64_t Address, const void *Decoder) {
2671 
2672  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2673  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2674  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2675  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2676  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2677  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2678 
2679  // First output register
2680  switch (Inst.getOpcode()) {
2681  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2682  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2683  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2684  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2685  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2686  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2687  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2688  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2689  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2690  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2691  return MCDisassembler::Fail;
2692  break;
2693  case ARM::VLD2b16:
2694  case ARM::VLD2b32:
2695  case ARM::VLD2b8:
2696  case ARM::VLD2b16wb_fixed:
2697  case ARM::VLD2b16wb_register:
2698  case ARM::VLD2b32wb_fixed:
2699  case ARM::VLD2b32wb_register:
2700  case ARM::VLD2b8wb_fixed:
2701  case ARM::VLD2b8wb_register:
2702  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2703  return MCDisassembler::Fail;
2704  break;
2705  default:
2706  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2707  return MCDisassembler::Fail;
2708  }
2709 
2710  // Second output register
2711  switch (Inst.getOpcode()) {
2712  case ARM::VLD3d8:
2713  case ARM::VLD3d16:
2714  case ARM::VLD3d32:
2715  case ARM::VLD3d8_UPD:
2716  case ARM::VLD3d16_UPD:
2717  case ARM::VLD3d32_UPD:
2718  case ARM::VLD4d8:
2719  case ARM::VLD4d16:
2720  case ARM::VLD4d32:
2721  case ARM::VLD4d8_UPD:
2722  case ARM::VLD4d16_UPD:
2723  case ARM::VLD4d32_UPD:
2724  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2725  return MCDisassembler::Fail;
2726  break;
2727  case ARM::VLD3q8:
2728  case ARM::VLD3q16:
2729  case ARM::VLD3q32:
2730  case ARM::VLD3q8_UPD:
2731  case ARM::VLD3q16_UPD:
2732  case ARM::VLD3q32_UPD:
2733  case ARM::VLD4q8:
2734  case ARM::VLD4q16:
2735  case ARM::VLD4q32:
2736  case ARM::VLD4q8_UPD:
2737  case ARM::VLD4q16_UPD:
2738  case ARM::VLD4q32_UPD:
2739  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2740  return MCDisassembler::Fail;
2741  break;
2742  default:
2743  break;
2744  }
2745 
2746  // Third output register
2747  switch(Inst.getOpcode()) {
2748  case ARM::VLD3d8:
2749  case ARM::VLD3d16:
2750  case ARM::VLD3d32:
2751  case ARM::VLD3d8_UPD:
2752  case ARM::VLD3d16_UPD:
2753  case ARM::VLD3d32_UPD:
2754  case ARM::VLD4d8:
2755  case ARM::VLD4d16:
2756  case ARM::VLD4d32:
2757  case ARM::VLD4d8_UPD:
2758  case ARM::VLD4d16_UPD:
2759  case ARM::VLD4d32_UPD:
2760  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2761  return MCDisassembler::Fail;
2762  break;
2763  case ARM::VLD3q8:
2764  case ARM::VLD3q16:
2765  case ARM::VLD3q32:
2766  case ARM::VLD3q8_UPD:
2767  case ARM::VLD3q16_UPD:
2768  case ARM::VLD3q32_UPD:
2769  case ARM::VLD4q8:
2770  case ARM::VLD4q16:
2771  case ARM::VLD4q32:
2772  case ARM::VLD4q8_UPD:
2773  case ARM::VLD4q16_UPD:
2774  case ARM::VLD4q32_UPD:
2775  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2776  return MCDisassembler::Fail;
2777  break;
2778  default:
2779  break;
2780  }
2781 
2782  // Fourth output register
2783  switch (Inst.getOpcode()) {
2784  case ARM::VLD4d8:
2785  case ARM::VLD4d16:
2786  case ARM::VLD4d32:
2787  case ARM::VLD4d8_UPD:
2788  case ARM::VLD4d16_UPD:
2789  case ARM::VLD4d32_UPD:
2790  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2791  return MCDisassembler::Fail;
2792  break;
2793  case ARM::VLD4q8:
2794  case ARM::VLD4q16:
2795  case ARM::VLD4q32:
2796  case ARM::VLD4q8_UPD:
2797  case ARM::VLD4q16_UPD:
2798  case ARM::VLD4q32_UPD:
2799  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2800  return MCDisassembler::Fail;
2801  break;
2802  default:
2803  break;
2804  }
2805 
2806  // Writeback operand
2807  switch (Inst.getOpcode()) {
2808  case ARM::VLD1d8wb_fixed:
2809  case ARM::VLD1d16wb_fixed:
2810  case ARM::VLD1d32wb_fixed:
2811  case ARM::VLD1d64wb_fixed:
2812  case ARM::VLD1d8wb_register:
2813  case ARM::VLD1d16wb_register:
2814  case ARM::VLD1d32wb_register:
2815  case ARM::VLD1d64wb_register:
2816  case ARM::VLD1q8wb_fixed:
2817  case ARM::VLD1q16wb_fixed:
2818  case ARM::VLD1q32wb_fixed:
2819  case ARM::VLD1q64wb_fixed:
2820  case ARM::VLD1q8wb_register:
2821  case ARM::VLD1q16wb_register:
2822  case ARM::VLD1q32wb_register:
2823  case ARM::VLD1q64wb_register:
2824  case ARM::VLD1d8Twb_fixed:
2825  case ARM::VLD1d8Twb_register:
2826  case ARM::VLD1d16Twb_fixed:
2827  case ARM::VLD1d16Twb_register:
2828  case ARM::VLD1d32Twb_fixed:
2829  case ARM::VLD1d32Twb_register:
2830  case ARM::VLD1d64Twb_fixed:
2831  case ARM::VLD1d64Twb_register:
2832  case ARM::VLD1d8Qwb_fixed:
2833  case ARM::VLD1d8Qwb_register:
2834  case ARM::VLD1d16Qwb_fixed:
2835  case ARM::VLD1d16Qwb_register:
2836  case ARM::VLD1d32Qwb_fixed:
2837  case ARM::VLD1d32Qwb_register:
2838  case ARM::VLD1d64Qwb_fixed:
2839  case ARM::VLD1d64Qwb_register:
2840  case ARM::VLD2d8wb_fixed:
2841  case ARM::VLD2d16wb_fixed:
2842  case ARM::VLD2d32wb_fixed:
2843  case ARM::VLD2q8wb_fixed:
2844  case ARM::VLD2q16wb_fixed:
2845  case ARM::VLD2q32wb_fixed:
2846  case ARM::VLD2d8wb_register:
2847  case ARM::VLD2d16wb_register:
2848  case ARM::VLD2d32wb_register:
2849  case ARM::VLD2q8wb_register:
2850  case ARM::VLD2q16wb_register:
2851  case ARM::VLD2q32wb_register:
2852  case ARM::VLD2b8wb_fixed:
2853  case ARM::VLD2b16wb_fixed:
2854  case ARM::VLD2b32wb_fixed:
2855  case ARM::VLD2b8wb_register:
2856  case ARM::VLD2b16wb_register:
2857  case ARM::VLD2b32wb_register:
2859  break;
2860  case ARM::VLD3d8_UPD:
2861  case ARM::VLD3d16_UPD:
2862  case ARM::VLD3d32_UPD:
2863  case ARM::VLD3q8_UPD:
2864  case ARM::VLD3q16_UPD:
2865  case ARM::VLD3q32_UPD:
2866  case ARM::VLD4d8_UPD:
2867  case ARM::VLD4d16_UPD:
2868  case ARM::VLD4d32_UPD:
2869  case ARM::VLD4q8_UPD:
2870  case ARM::VLD4q16_UPD:
2871  case ARM::VLD4q32_UPD:
2872  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2873  return MCDisassembler::Fail;
2874  break;
2875  default:
2876  break;
2877  }
2878 
2879  // AddrMode6 Base (register+alignment)
2880  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2881  return MCDisassembler::Fail;
2882 
2883  // AddrMode6 Offset (register)
2884  switch (Inst.getOpcode()) {
2885  default:
2886  // The below have been updated to have explicit am6offset split
2887  // between fixed and register offset. For those instructions not
2888  // yet updated, we need to add an additional reg0 operand for the
2889  // fixed variant.
2890  //
2891  // The fixed offset encodes as Rm == 0xd, so we check for that.
2892  if (Rm == 0xd) {
2894  break;
2895  }
2896  // Fall through to handle the register offset variant.
2898  case ARM::VLD1d8wb_fixed:
2899  case ARM::VLD1d16wb_fixed:
2900  case ARM::VLD1d32wb_fixed:
2901  case ARM::VLD1d64wb_fixed:
2902  case ARM::VLD1d8Twb_fixed:
2903  case ARM::VLD1d16Twb_fixed:
2904  case ARM::VLD1d32Twb_fixed:
2905  case ARM::VLD1d64Twb_fixed:
2906  case ARM::VLD1d8Qwb_fixed:
2907  case ARM::VLD1d16Qwb_fixed:
2908  case ARM::VLD1d32Qwb_fixed:
2909  case ARM::VLD1d64Qwb_fixed:
2910  case ARM::VLD1d8wb_register:
2911  case ARM::VLD1d16wb_register:
2912  case ARM::VLD1d32wb_register:
2913  case ARM::VLD1d64wb_register:
2914  case ARM::VLD1q8wb_fixed:
2915  case ARM::VLD1q16wb_fixed:
2916  case ARM::VLD1q32wb_fixed:
2917  case ARM::VLD1q64wb_fixed:
2918  case ARM::VLD1q8wb_register:
2919  case ARM::VLD1q16wb_register:
2920  case ARM::VLD1q32wb_register:
2921  case ARM::VLD1q64wb_register:
2922  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2923  // variant encodes Rm == 0xf. Anything else is a register offset post-
2924  // increment and we need to add the register operand to the instruction.
2925  if (Rm != 0xD && Rm != 0xF &&
2926  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2927  return MCDisassembler::Fail;
2928  break;
2929  case ARM::VLD2d8wb_fixed:
2930  case ARM::VLD2d16wb_fixed:
2931  case ARM::VLD2d32wb_fixed:
2932  case ARM::VLD2b8wb_fixed:
2933  case ARM::VLD2b16wb_fixed:
2934  case ARM::VLD2b32wb_fixed:
2935  case ARM::VLD2q8wb_fixed:
2936  case ARM::VLD2q16wb_fixed:
2937  case ARM::VLD2q32wb_fixed:
2938  break;
2939  }
2940 
2941  return S;
2942 }
2943 
2944 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2945  uint64_t Address, const void *Decoder) {
2946  unsigned type = fieldFromInstruction(Insn, 8, 4);
2947  unsigned align = fieldFromInstruction(Insn, 4, 2);
2948  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2949  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2950  if (type == 10 && align == 3) return MCDisassembler::Fail;
2951 
2952  unsigned load = fieldFromInstruction(Insn, 21, 1);
2953  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2954  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2955 }
2956 
2957 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2958  uint64_t Address, const void *Decoder) {
2959  unsigned size = fieldFromInstruction(Insn, 6, 2);
2960  if (size == 3) return MCDisassembler::Fail;
2961 
2962  unsigned type = fieldFromInstruction(Insn, 8, 4);
2963  unsigned align = fieldFromInstruction(Insn, 4, 2);
2964  if (type == 8 && align == 3) return MCDisassembler::Fail;
2965  if (type == 9 && align == 3) return MCDisassembler::Fail;
2966 
2967  unsigned load = fieldFromInstruction(Insn, 21, 1);
2968  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2969  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2970 }
2971 
2972 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2973  uint64_t Address, const void *Decoder) {
2974  unsigned size = fieldFromInstruction(Insn, 6, 2);
2975  if (size == 3) return MCDisassembler::Fail;
2976 
2977  unsigned align = fieldFromInstruction(Insn, 4, 2);
2978  if (align & 2) return MCDisassembler::Fail;
2979 
2980  unsigned load = fieldFromInstruction(Insn, 21, 1);
2981  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2982  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2983 }
2984 
2985 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2986  uint64_t Address, const void *Decoder) {
2987  unsigned size = fieldFromInstruction(Insn, 6, 2);
2988  if (size == 3) return MCDisassembler::Fail;
2989 
2990  unsigned load = fieldFromInstruction(Insn, 21, 1);
2991  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2992  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2993 }
2994 
2995 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2996  uint64_t Address, const void *Decoder) {
2998 
2999  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3000  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3001  unsigned wb = fieldFromInstruction(Insn, 16, 4);
3002  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3003  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3004  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3005 
3006  // Writeback Operand
3007  switch (Inst.getOpcode()) {
3008  case ARM::VST1d8wb_fixed:
3009  case ARM::VST1d16wb_fixed:
3010  case ARM::VST1d32wb_fixed:
3011  case ARM::VST1d64wb_fixed:
3012  case ARM::VST1d8wb_register:
3013  case ARM::VST1d16wb_register:
3014  case ARM::VST1d32wb_register:
3015  case ARM::VST1d64wb_register:
3016  case ARM::VST1q8wb_fixed:
3017  case ARM::VST1q16wb_fixed:
3018  case ARM::VST1q32wb_fixed:
3019  case ARM::VST1q64wb_fixed:
3020  case ARM::VST1q8wb_register:
3021  case ARM::VST1q16wb_register:
3022  case ARM::VST1q32wb_register:
3023  case ARM::VST1q64wb_register:
3024  case ARM::VST1d8Twb_fixed:
3025  case ARM::VST1d16Twb_fixed:
3026  case ARM::VST1d32Twb_fixed:
3027  case ARM::VST1d64Twb_fixed:
3028  case ARM::VST1d8Twb_register:
3029  case ARM::VST1d16Twb_register:
3030  case ARM::VST1d32Twb_register:
3031  case ARM::VST1d64Twb_register:
3032  case ARM::VST1d8Qwb_fixed:
3033  case ARM::VST1d16Qwb_fixed:
3034  case ARM::VST1d32Qwb_fixed:
3035  case ARM::VST1d64Qwb_fixed:
3036  case ARM::VST1d8Qwb_register:
3037  case ARM::VST1d16Qwb_register:
3038  case ARM::VST1d32Qwb_register:
3039  case ARM::VST1d64Qwb_register:
3040  case ARM::VST2d8wb_fixed:
3041  case ARM::VST2d16wb_fixed:
3042  case ARM::VST2d32wb_fixed:
3043  case ARM::VST2d8wb_register:
3044  case ARM::VST2d16wb_register:
3045  case ARM::VST2d32wb_register:
3046  case ARM::VST2q8wb_fixed:
3047  case ARM::VST2q16wb_fixed:
3048  case ARM::VST2q32wb_fixed:
3049  case ARM::VST2q8wb_register:
3050  case ARM::VST2q16wb_register:
3051  case ARM::VST2q32wb_register:
3052  case ARM::VST2b8wb_fixed:
3053  case ARM::VST2b16wb_fixed:
3054  case ARM::VST2b32wb_fixed:
3055  case ARM::VST2b8wb_register:
3056  case ARM::VST2b16wb_register:
3057  case ARM::VST2b32wb_register:
3058  if (Rm == 0xF)
3059  return MCDisassembler::Fail;
3061  break;
3062  case ARM::VST3d8_UPD:
3063  case ARM::VST3d16_UPD:
3064  case ARM::VST3d32_UPD:
3065  case ARM::VST3q8_UPD:
3066  case ARM::VST3q16_UPD:
3067  case ARM::VST3q32_UPD:
3068  case ARM::VST4d8_UPD:
3069  case ARM::VST4d16_UPD:
3070  case ARM::VST4d32_UPD:
3071  case ARM::VST4q8_UPD:
3072  case ARM::VST4q16_UPD:
3073  case ARM::VST4q32_UPD:
3074  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3075  return MCDisassembler::Fail;
3076  break;
3077  default:
3078  break;
3079  }
3080 
3081  // AddrMode6 Base (register+alignment)
3082  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3083  return MCDisassembler::Fail;
3084 
3085  // AddrMode6 Offset (register)
3086  switch (Inst.getOpcode()) {
3087  default:
3088  if (Rm == 0xD)
3090  else if (Rm != 0xF) {
3091  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3092  return MCDisassembler::Fail;
3093  }
3094  break;
3095  case ARM::VST1d8wb_fixed:
3096  case ARM::VST1d16wb_fixed:
3097  case ARM::VST1d32wb_fixed:
3098  case ARM::VST1d64wb_fixed:
3099  case ARM::VST1q8wb_fixed:
3100  case ARM::VST1q16wb_fixed:
3101  case ARM::VST1q32wb_fixed:
3102  case ARM::VST1q64wb_fixed:
3103  case ARM::VST1d8Twb_fixed:
3104  case ARM::VST1d16Twb_fixed:
3105  case ARM::VST1d32Twb_fixed:
3106  case ARM::VST1d64Twb_fixed:
3107  case ARM::VST1d8Qwb_fixed:
3108  case ARM::VST1d16Qwb_fixed:
3109  case ARM::VST1d32Qwb_fixed:
3110  case ARM::VST1d64Qwb_fixed:
3111  case ARM::VST2d8wb_fixed:
3112  case ARM::VST2d16wb_fixed:
3113  case ARM::VST2d32wb_fixed:
3114  case ARM::VST2q8wb_fixed:
3115  case ARM::VST2q16wb_fixed:
3116  case ARM::VST2q32wb_fixed:
3117  case ARM::VST2b8wb_fixed:
3118  case ARM::VST2b16wb_fixed:
3119  case ARM::VST2b32wb_fixed:
3120  break;
3121  }
3122 
3123  // First input register
3124  switch (Inst.getOpcode()) {
3125  case ARM::VST1q16:
3126  case ARM::VST1q32:
3127  case ARM::VST1q64:
3128  case ARM::VST1q8:
3129  case ARM::VST1q16wb_fixed:
3130  case ARM::VST1q16wb_register:
3131  case ARM::VST1q32wb_fixed:
3132  case ARM::VST1q32wb_register:
3133  case ARM::VST1q64wb_fixed:
3134  case ARM::VST1q64wb_register:
3135  case ARM::VST1q8wb_fixed:
3136  case ARM::VST1q8wb_register:
3137  case ARM::VST2d16:
3138  case ARM::VST2d32:
3139  case ARM::VST2d8:
3140  case ARM::VST2d16wb_fixed:
3141  case ARM::VST2d16wb_register:
3142  case ARM::VST2d32wb_fixed:
3143  case ARM::VST2d32wb_register:
3144  case ARM::VST2d8wb_fixed:
3145  case ARM::VST2d8wb_register:
3146  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3147  return MCDisassembler::Fail;
3148  break;
3149  case ARM::VST2b16:
3150  case ARM::VST2b32:
3151  case ARM::VST2b8:
3152  case ARM::VST2b16wb_fixed:
3153  case ARM::VST2b16wb_register:
3154  case ARM::VST2b32wb_fixed:
3155  case ARM::VST2b32wb_register:
3156  case ARM::VST2b8wb_fixed:
3157  case ARM::VST2b8wb_register:
3158  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3159  return MCDisassembler::Fail;
3160  break;
3161  default:
3162  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3163  return MCDisassembler::Fail;
3164  }
3165 
3166  // Second input register
3167  switch (Inst.getOpcode()) {
3168  case ARM::VST3d8:
3169  case ARM::VST3d16:
3170  case ARM::VST3d32:
3171  case ARM::VST3d8_UPD:
3172  case ARM::VST3d16_UPD:
3173  case ARM::VST3d32_UPD:
3174  case ARM::VST4d8:
3175  case ARM::VST4d16:
3176  case ARM::VST4d32:
3177  case ARM::VST4d8_UPD:
3178  case ARM::VST4d16_UPD:
3179  case ARM::VST4d32_UPD:
3180  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3181  return MCDisassembler::Fail;
3182  break;
3183  case ARM::VST3q8:
3184  case ARM::VST3q16:
3185  case ARM::VST3q32:
3186  case ARM::VST3q8_UPD:
3187  case ARM::VST3q16_UPD:
3188  case ARM::VST3q32_UPD:
3189  case ARM::VST4q8:
3190  case ARM::VST4q16:
3191  case ARM::VST4q32:
3192  case ARM::VST4q8_UPD:
3193  case ARM::VST4q16_UPD:
3194  case ARM::VST4q32_UPD:
3195  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3196  return MCDisassembler::Fail;
3197  break;
3198  default:
3199  break;
3200  }
3201 
3202  // Third input register
3203  switch (Inst.getOpcode()) {
3204  case ARM::VST3d8:
3205  case ARM::VST3d16:
3206  case ARM::VST3d32:
3207  case ARM::VST3d8_UPD:
3208  case ARM::VST3d16_UPD:
3209  case ARM::VST3d32_UPD:
3210  case ARM::VST4d8:
3211  case ARM::VST4d16:
3212  case ARM::VST4d32:
3213  case ARM::VST4d8_UPD:
3214  case ARM::VST4d16_UPD:
3215  case ARM::VST4d32_UPD:
3216  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3217  return MCDisassembler::Fail;
3218  break;
3219  case ARM::VST3q8:
3220  case ARM::VST3q16:
3221  case ARM::VST3q32:
3222  case ARM::VST3q8_UPD:
3223  case ARM::VST3q16_UPD:
3224  case ARM::VST3q32_UPD:
3225  case ARM::VST4q8:
3226  case ARM::VST4q16:
3227  case ARM::VST4q32:
3228  case ARM::VST4q8_UPD:
3229  case ARM::VST4q16_UPD:
3230  case ARM::VST4q32_UPD:
3231  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3232  return MCDisassembler::Fail;
3233  break;
3234  default:
3235  break;
3236  }
3237 
3238  // Fourth input register
3239  switch (Inst.getOpcode()) {
3240  case ARM::VST4d8:
3241  case ARM::VST4d16:
3242  case ARM::VST4d32:
3243  case ARM::VST4d8_UPD:
3244  case ARM::VST4d16_UPD:
3245  case ARM::VST4d32_UPD:
3246  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3247  return MCDisassembler::Fail;
3248  break;
3249  case ARM::VST4q8:
3250  case ARM::VST4q16:
3251  case ARM::VST4q32:
3252  case ARM::VST4q8_UPD:
3253  case ARM::VST4q16_UPD:
3254  case ARM::VST4q32_UPD:
3255  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3256  return MCDisassembler::Fail;
3257  break;
3258  default:
3259  break;
3260  }
3261 
3262  return S;
3263 }
3264 
3265 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3266  uint64_t Address, const void *Decoder) {
3268 
3269  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3270  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3271  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3272  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3273  unsigned align = fieldFromInstruction(Insn, 4, 1);
3274  unsigned size = fieldFromInstruction(Insn, 6, 2);
3275 
3276  if (size == 0 && align == 1)
3277  return MCDisassembler::Fail;
3278  align *= (1 << size);
3279 
3280  switch (Inst.getOpcode()) {
3281  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3282  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3283  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3284  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3285  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3286  return MCDisassembler::Fail;
3287  break;
3288  default:
3289  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3290  return MCDisassembler::Fail;
3291  break;
3292  }
3293  if (Rm != 0xF) {
3294  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3295  return MCDisassembler::Fail;
3296  }
3297 
3298  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3299  return MCDisassembler::Fail;
3300  Inst.addOperand(MCOperand::createImm(align));
3301 
3302  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3303  // variant encodes Rm == 0xf. Anything else is a register offset post-
3304  // increment and we need to add the register operand to the instruction.
3305  if (Rm != 0xD && Rm != 0xF &&
3306  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3307  return MCDisassembler::Fail;
3308 
3309  return S;
3310 }
3311 
3312 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3313  uint64_t Address, const void *Decoder) {
3315 
3316  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3317  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3318  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3319  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3320  unsigned align = fieldFromInstruction(Insn, 4, 1);
3321  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3322  align *= 2*size;
3323 
3324  switch (Inst.getOpcode()) {
3325  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3326  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3327  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3328  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3329  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3330  return MCDisassembler::Fail;
3331  break;
3332  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3333  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3334  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3335  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3336  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3337  return MCDisassembler::Fail;
3338  break;
3339  default:
3340  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3341  return MCDisassembler::Fail;
3342  break;
3343  }
3344 
3345  if (Rm != 0xF)
3347 
3348  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3349  return MCDisassembler::Fail;
3350  Inst.addOperand(MCOperand::createImm(align));
3351 
3352  if (Rm != 0xD && Rm != 0xF) {
3353  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3354  return MCDisassembler::Fail;
3355  }
3356 
3357  return S;
3358 }
3359 
3360 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3361  uint64_t Address, const void *Decoder) {
3363 
3364  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3365  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3366  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3367  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3368  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3369 
3370  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3371  return MCDisassembler::Fail;
3372  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3373  return MCDisassembler::Fail;
3374  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3375  return MCDisassembler::Fail;
3376  if (Rm != 0xF) {
3377  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3378  return MCDisassembler::Fail;
3379  }
3380 
3381  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3382  return MCDisassembler::Fail;
3384 
3385  if (Rm == 0xD)
3387  else if (Rm != 0xF) {
3388  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3389  return MCDisassembler::Fail;
3390  }
3391 
3392  return S;
3393 }
3394 
3395 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3396  uint64_t Address, const void *Decoder) {
3398 
3399  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3400  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3401  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3402  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3403  unsigned size = fieldFromInstruction(Insn, 6, 2);
3404  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3405  unsigned align = fieldFromInstruction(Insn, 4, 1);
3406 
3407  if (size == 0x3) {
3408  if (align == 0)
3409  return MCDisassembler::Fail;
3410  align = 16;
3411  } else {
3412  if (size == 2) {
3413  align *= 8;
3414  } else {
3415  size = 1 << size;
3416  align *= 4*size;
3417  }
3418  }
3419 
3420  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3421  return MCDisassembler::Fail;
3422  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3423  return MCDisassembler::Fail;
3424  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3425  return MCDisassembler::Fail;
3426  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3427  return MCDisassembler::Fail;
3428  if (Rm != 0xF) {
3429  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3430  return MCDisassembler::Fail;
3431  }
3432 
3433  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3434  return MCDisassembler::Fail;
3435  Inst.addOperand(MCOperand::createImm(align));
3436 
3437  if (Rm == 0xD)
3439  else if (Rm != 0xF) {
3440  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3441  return MCDisassembler::Fail;
3442  }
3443 
3444  return S;
3445 }
3446 
3447 static DecodeStatus
3449  uint64_t Address, const void *Decoder) {
3451 
3452  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3453  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3454  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3455  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3456  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3457  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3458  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3459  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3460 
3461  if (Q) {
3462  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3463  return MCDisassembler::Fail;
3464  } else {
3465  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3466  return MCDisassembler::Fail;
3467  }
3468 
3469  Inst.addOperand(MCOperand::createImm(imm));
3470 
3471  switch (Inst.getOpcode()) {
3472  case ARM::VORRiv4i16:
3473  case ARM::VORRiv2i32:
3474  case ARM::VBICiv4i16:
3475  case ARM::VBICiv2i32:
3476  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3477  return MCDisassembler::Fail;
3478  break;
3479  case ARM::VORRiv8i16:
3480  case ARM::VORRiv4i32:
3481  case ARM::VBICiv8i16:
3482  case ARM::VBICiv4i32:
3483  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3484  return MCDisassembler::Fail;
3485  break;
3486  default:
3487  break;
3488  }
3489 
3490  return S;
3491 }
3492 
3493 static DecodeStatus
3494 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3495  uint64_t Address, const void *Decoder) {
3497 
3498  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3499  fieldFromInstruction(Insn, 13, 3));
3500  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3501  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3502  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3503  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3504  imm |= cmode << 8;
3505  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3506 
3507  if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3508  return MCDisassembler::Fail;
3509 
3510  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3511  return MCDisassembler::Fail;
3512 
3513  Inst.addOperand(MCOperand::createImm(imm));
3514 
3518 
3519  return S;
3520 }
3521 
3522 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3523  uint64_t Address, const void *Decoder) {
3525 
3526  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3527  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3528  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3529  return MCDisassembler::Fail;
3530  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3531 
3532  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3533  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3534  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3535  return MCDisassembler::Fail;
3536  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3537  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3538  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3539  return MCDisassembler::Fail;
3540  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3541  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3542  Inst.addOperand(MCOperand::createImm(Qd));
3543 
3544  return S;
3545 }
3546 
3547 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3548  uint64_t Address, const void *Decoder) {
3550 
3551  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3552  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3553  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3554  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3555  unsigned size = fieldFromInstruction(Insn, 18, 2);
3556 
3557  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3558  return MCDisassembler::Fail;
3559  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3560  return MCDisassembler::Fail;
3561  Inst.addOperand(MCOperand::createImm(8 << size));
3562 
3563  return S;
3564 }
3565 
3566 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3567  uint64_t Address, const void *Decoder) {
3568  Inst.addOperand(MCOperand::createImm(8 - Val));
3569  return MCDisassembler::Success;
3570 }
3571 
3572 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3573  uint64_t Address, const void *Decoder) {
3574  Inst.addOperand(MCOperand::createImm(16 - Val));
3575  return MCDisassembler::Success;
3576 }
3577 
3578 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3579  uint64_t Address, const void *Decoder) {
3580  Inst.addOperand(MCOperand::createImm(32 - Val));
3581  return MCDisassembler::Success;
3582 }
3583 
3584 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3585  uint64_t Address, const void *Decoder) {
3586  Inst.addOperand(MCOperand::createImm(64 - Val));
3587  return MCDisassembler::Success;
3588 }
3589 
3590 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3591  uint64_t Address, const void *Decoder) {
3593 
3594  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3595  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3596  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3597  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3598  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3599  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3600  unsigned op = fieldFromInstruction(Insn, 6, 1);
3601 
3602  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3603  return MCDisassembler::Fail;
3604  if (op) {
3605  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3606  return MCDisassembler::Fail; // Writeback
3607  }
3608 
3609  switch (Inst.getOpcode()) {
3610  case ARM::VTBL2:
3611  case ARM::VTBX2:
3612  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3613  return MCDisassembler::Fail;
3614  break;
3615  default:
3616  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3617  return MCDisassembler::Fail;
3618  }
3619 
3620  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3621  return MCDisassembler::Fail;
3622 
3623  return S;
3624 }
3625 
3626 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3627  uint64_t Address, const void *Decoder) {
3629 
3630  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3631  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3632 
3633  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3634  return MCDisassembler::Fail;
3635 
3636  switch(Inst.getOpcode()) {
3637  default:
3638  return MCDisassembler::Fail;
3639  case ARM::tADR:
3640  break; // tADR does not explicitly represent the PC as an operand.
3641  case ARM::tADDrSPi:
3642  Inst.addOperand(MCOperand::createReg(ARM::SP));
3643  break;
3644  }
3645 
3646  Inst.addOperand(MCOperand::createImm(imm));
3647  return S;
3648 }
3649 
3650 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3651  uint64_t Address, const void *Decoder) {
3652  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3653  true, 2, Inst, Decoder))
3654  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3655  return MCDisassembler::Success;
3656 }
3657 
3658 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3659  uint64_t Address, const void *Decoder) {
3660  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3661  true, 4, Inst, Decoder))
3662  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3663  return MCDisassembler::Success;
3664 }
3665 
3666 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3667  uint64_t Address, const void *Decoder) {
3668  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3669  true, 2, Inst, Decoder))
3670  Inst.addOperand(MCOperand::createImm(Val << 1));
3671  return MCDisassembler::Success;
3672 }
3673 
3674 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3675  uint64_t Address, const void *Decoder) {
3677 
3678  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3679  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3680 
3681  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3682  return MCDisassembler::Fail;
3683  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3684  return MCDisassembler::Fail;
3685 
3686  return S;
3687 }
3688 
3689 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3690  uint64_t Address, const void *Decoder) {
3692 
3693  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3694  unsigned imm = fieldFromInstruction(Val, 3, 5);
3695 
3696  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3697  return MCDisassembler::Fail;
3698  Inst.addOperand(MCOperand::createImm(imm));
3699 
3700  return S;
3701 }
3702 
3703 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3704  uint64_t Address, const void *Decoder) {
3705  unsigned imm = Val << 2;
3706 
3707  Inst.addOperand(MCOperand::createImm(imm));
3708  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3709 
3710  return MCDisassembler::Success;
3711 }
3712 
3713 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3714  uint64_t Address, const void *Decoder) {
3715  Inst.addOperand(MCOperand::createReg(ARM::SP));
3716  Inst.addOperand(MCOperand::createImm(Val));
3717 
3718  return MCDisassembler::Success;
3719 }
3720 
3721 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3722  uint64_t Address, const void *Decoder) {
3724 
3725  unsigned Rn = fieldFromInstruction(Val, 6, 4);
3726  unsigned Rm = fieldFromInstruction(Val, 2, 4);
3727  unsigned imm = fieldFromInstruction(Val, 0, 2);
3728 
3729  // Thumb stores cannot use PC as dest register.
3730  switch (Inst.getOpcode()) {
3731  case ARM::t2STRHs:
3732  case ARM::t2STRBs:
3733  case ARM::t2STRs:
3734  if (Rn == 15)
3735  return MCDisassembler::Fail;
3736  break;
3737  default:
3738  break;
3739  }
3740 
3741  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742  return MCDisassembler::Fail;
3743  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3744  return MCDisassembler::Fail;
3745  Inst.addOperand(MCOperand::createImm(imm));
3746 
3747  return S;
3748 }
3749 
3750 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3751  uint64_t Address, const void *Decoder) {
3753 
3754  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3755  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3756 
3757  const FeatureBitset &featureBits =
3758  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3759 
3760  bool hasMP = featureBits[ARM::FeatureMP];
3761  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3762 
3763  if (Rn == 15) {
3764  switch (Inst.getOpcode()) {
3765  case ARM::t2LDRBs:
3766  Inst.setOpcode(ARM::t2LDRBpci);
3767  break;
3768  case ARM::t2LDRHs:
3769  Inst.setOpcode(ARM::t2LDRHpci);
3770  break;
3771  case ARM::t2LDRSHs:
3772  Inst.setOpcode(ARM::t2LDRSHpci);
3773  break;
3774  case ARM::t2LDRSBs:
3775  Inst.setOpcode(ARM::t2LDRSBpci);
3776  break;
3777  case ARM::t2LDRs:
3778  Inst.setOpcode(ARM::t2LDRpci);
3779  break;
3780  case ARM::t2PLDs:
3781  Inst.setOpcode(ARM::t2PLDpci);
3782  break;
3783  case ARM::t2PLIs:
3784  Inst.setOpcode(ARM::t2PLIpci);
3785  break;
3786  default:
3787  return MCDisassembler::Fail;
3788  }
3789 
3790  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3791  }
3792 
3793  if (Rt == 15) {
3794  switch (Inst.getOpcode()) {
3795  case ARM::t2LDRSHs:
3796  return MCDisassembler::Fail;
3797  case ARM::t2LDRHs:
3798  Inst.setOpcode(ARM::t2PLDWs);
3799  break;
3800  case ARM::t2LDRSBs:
3801  Inst.setOpcode(ARM::t2PLIs);
3802  break;
3803  default:
3804  break;
3805  }
3806  }
3807 
3808  switch (Inst.getOpcode()) {
3809  case ARM::t2PLDs:
3810  break;
3811  case ARM::t2PLIs:
3812  if (!hasV7Ops)
3813  return MCDisassembler::Fail;
3814  break;
3815  case ARM::t2PLDWs:
3816  if (!hasV7Ops || !hasMP)
3817  return MCDisassembler::Fail;
3818  break;
3819  default:
3820  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3821  return MCDisassembler::Fail;
3822  }
3823 
3824  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3825  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3826  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3827  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3828  return MCDisassembler::Fail;
3829 
3830  return S;
3831 }
3832 
3833 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3834  uint64_t Address, const void* Decoder) {
3836 
3837  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3838  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3839  unsigned U = fieldFromInstruction(Insn, 9, 1);
3840  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3841  imm |= (U << 8);
3842  imm |= (Rn << 9);
3843  unsigned add = fieldFromInstruction(Insn, 9, 1);
3844 
3845  const FeatureBitset &featureBits =
3846  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3847 
3848  bool hasMP = featureBits[ARM::FeatureMP];
3849  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3850 
3851  if (Rn == 15) {
3852  switch (Inst.getOpcode()) {
3853  case ARM::t2LDRi8:
3854  Inst.setOpcode(ARM::t2LDRpci);
3855  break;
3856  case ARM::t2LDRBi8:
3857  Inst.setOpcode(ARM::t2LDRBpci);
3858  break;
3859  case ARM::t2LDRSBi8:
3860  Inst.setOpcode(ARM::t2LDRSBpci);
3861  break;
3862  case ARM::t2LDRHi8:
3863  Inst.setOpcode(ARM::t2LDRHpci);
3864  break;
3865  case ARM::t2LDRSHi8:
3866  Inst.setOpcode(ARM::t2LDRSHpci);
3867  break;
3868  case ARM::t2PLDi8:
3869  Inst.setOpcode(ARM::t2PLDpci);
3870  break;
3871  case ARM::t2PLIi8:
3872  Inst.setOpcode(ARM::t2PLIpci);
3873  break;
3874  default:
3875  return MCDisassembler::Fail;
3876  }
3877  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3878  }
3879 
3880  if (Rt == 15) {
3881  switch (Inst.getOpcode()) {
3882  case ARM::t2LDRSHi8:
3883  return MCDisassembler::Fail;
3884  case ARM::t2LDRHi8:
3885  if (!add)
3886  Inst.setOpcode(ARM::t2PLDWi8);
3887  break;
3888  case ARM::t2LDRSBi8:
3889  Inst.setOpcode(ARM::t2PLIi8);
3890  break;
3891  default:
3892  break;
3893  }
3894  }
3895 
3896  switch (Inst.getOpcode()) {
3897  case ARM::t2PLDi8:
3898  break;
3899  case ARM::t2PLIi8:
3900  if (!hasV7Ops)
3901  return MCDisassembler::Fail;
3902  break;
3903  case ARM::t2PLDWi8:
3904  if (!hasV7Ops || !hasMP)
3905  return MCDisassembler::Fail;
3906  break;
3907  default:
3908  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3909  return MCDisassembler::Fail;
3910  }
3911 
3912  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3913  return MCDisassembler::Fail;
3914  return S;
3915 }
3916 
3917 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3918  uint64_t Address, const void* Decoder) {
3920 
3921  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3922  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3923  unsigned imm = fieldFromInstruction(Insn, 0, 12);
3924  imm |= (Rn << 13);
3925 
3926  const FeatureBitset &featureBits =
3927  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3928 
3929  bool hasMP = featureBits[ARM::FeatureMP];
3930  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3931 
3932  if (Rn == 15) {
3933  switch (Inst.getOpcode()) {
3934  case ARM::t2LDRi12:
3935  Inst.setOpcode(ARM::t2LDRpci);
3936  break;
3937  case ARM::t2LDRHi12:
3938  Inst.setOpcode(ARM::t2LDRHpci);
3939  break;
3940  case ARM::t2LDRSHi12:
3941  Inst.setOpcode(ARM::t2LDRSHpci);
3942  break;
3943  case ARM::t2LDRBi12:
3944  Inst.setOpcode(ARM::t2LDRBpci);
3945  break;
3946  case ARM::t2LDRSBi12:
3947  Inst.setOpcode(ARM::t2LDRSBpci);
3948  break;
3949  case ARM::t2PLDi12:
3950  Inst.setOpcode(ARM::t2PLDpci);
3951  break;
3952  case ARM::t2PLIi12:
3953  Inst.setOpcode(ARM::t2PLIpci);
3954  break;
3955  default:
3956  return MCDisassembler::Fail;
3957  }
3958  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3959  }
3960 
3961  if (Rt == 15) {
3962  switch (Inst.getOpcode()) {
3963  case ARM::t2LDRSHi12:
3964  return MCDisassembler::Fail;
3965  case ARM::t2LDRHi12:
3966  Inst.setOpcode(ARM::t2PLDWi12);
3967  break;
3968  case ARM::t2LDRSBi12:
3969  Inst.setOpcode(ARM::t2PLIi12);
3970  break;
3971  default:
3972  break;
3973  }
3974  }
3975 
3976  switch (Inst.getOpcode()) {
3977  case ARM::t2PLDi12:
3978  break;
3979  case ARM::t2PLIi12:
3980  if (!hasV7Ops)
3981  return MCDisassembler::Fail;
3982  break;
3983  case ARM::t2PLDWi12:
3984  if (!hasV7Ops || !hasMP)
3985  return MCDisassembler::Fail;
3986  break;
3987  default:
3988  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3989  return MCDisassembler::Fail;
3990  }
3991 
3992  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3993  return MCDisassembler::Fail;
3994  return S;
3995 }
3996 
3997 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3998  uint64_t Address, const void* Decoder) {
4000 
4001  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4002  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4003  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4004  imm |= (Rn << 9);
4005 
4006  if (Rn == 15) {
4007  switch (Inst.getOpcode()) {
4008  case ARM::t2LDRT:
4009  Inst.setOpcode(ARM::t2LDRpci);
4010  break;
4011  case ARM::t2LDRBT:
4012  Inst.setOpcode(ARM::t2LDRBpci);
4013  break;
4014  case ARM::t2LDRHT:
4015  Inst.setOpcode(ARM::t2LDRHpci);
4016  break;
4017  case ARM::t2LDRSBT:
4018  Inst.setOpcode(ARM::t2LDRSBpci);
4019  break;
4020  case ARM::t2LDRSHT:
4021  Inst.setOpcode(ARM::t2LDRSHpci);
4022  break;
4023  default:
4024  return MCDisassembler::Fail;
4025  }
4026  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4027  }
4028 
4029  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4030  return MCDisassembler::Fail;
4031  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4032  return MCDisassembler::Fail;
4033  return S;
4034 }
4035 
4036 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4037  uint64_t Address, const void* Decoder) {
4039 
4040  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4041  unsigned U = fieldFromInstruction(Insn, 23, 1);
4042  int imm = fieldFromInstruction(Insn, 0, 12);
4043 
4044  const FeatureBitset &featureBits =
4045  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4046 
4047  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4048 
4049  if (Rt == 15) {
4050  switch (Inst.getOpcode()) {
4051  case ARM::t2LDRBpci:
4052  case ARM::t2LDRHpci:
4053  Inst.setOpcode(ARM::t2PLDpci);
4054  break;
4055  case ARM::t2LDRSBpci:
4056  Inst.setOpcode(ARM::t2PLIpci);
4057  break;
4058  case ARM::t2LDRSHpci:
4059  return MCDisassembler::Fail;
4060  default:
4061  break;
4062  }
4063  }
4064 
4065  switch(Inst.getOpcode()) {
4066  case ARM::t2PLDpci:
4067  break;
4068  case ARM::t2PLIpci:
4069  if (!hasV7Ops)
4070  return MCDisassembler::Fail;
4071  break;
4072  default:
4073  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4074  return MCDisassembler::Fail;
4075  }
4076 
4077  if (!U) {
4078  // Special case for #-0.
4079  if (imm == 0)
4080  imm = INT32_MIN;
4081  else
4082  imm = -imm;
4083  }
4084  Inst.addOperand(MCOperand::createImm(imm));
4085 
4086  return S;
4087 }
4088 
4089 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
4090  uint64_t Address, const void *Decoder) {
4091  if (Val == 0)
4092  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4093  else {
4094  int imm = Val & 0xFF;
4095 
4096  if (!(Val & 0x100)) imm *= -1;
4097  Inst.addOperand(MCOperand::createImm(imm * 4));
4098  }
4099 
4100  return MCDisassembler::Success;
4101 }
4102 
4103 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4104  const void *Decoder) {
4105  if (Val == 0)
4106  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4107  else {
4108  int imm = Val & 0x7F;
4109 
4110  if (!(Val & 0x80))
4111  imm *= -1;
4112  Inst.addOperand(MCOperand::createImm(imm * 4));
4113  }
4114 
4115  return MCDisassembler::Success;
4116 }
4117 
4118 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4119  uint64_t Address, const void *Decoder) {
4121 
4122  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4123  unsigned imm = fieldFromInstruction(Val, 0, 9);
4124 
4125  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4126  return MCDisassembler::Fail;
4127  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4128  return MCDisassembler::Fail;
4129 
4130  return S;
4131 }
4132 
4133 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4134  uint64_t Address,
4135  const void *Decoder) {
4137 
4138  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4139  unsigned imm = fieldFromInstruction(Val, 0, 8);
4140 
4141  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4142  return MCDisassembler::Fail;
4143  if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4144  return MCDisassembler::Fail;
4145 
4146  return S;
4147 }
4148 
4150  uint64_t Address, const void *Decoder) {
4152 
4153  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4154  unsigned imm = fieldFromInstruction(Val, 0, 8);
4155 
4156  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4157  return MCDisassembler::Fail;
4158 
4159  Inst.addOperand(MCOperand::createImm(imm));
4160 
4161  return S;
4162 }
4163 
4164 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
4165  uint64_t Address, const void *Decoder) {
4166  int imm = Val & 0xFF;
4167  if (Val == 0)
4168  imm = INT32_MIN;
4169  else if (!(Val & 0x100))
4170  imm *= -1;
4171  Inst.addOperand(MCOperand::createImm(imm));
4172 
4173  return MCDisassembler::Success;
4174 }
4175 
4176 template<int shift>
4177 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
4178  uint64_t Address, const void *Decoder) {
4179  int imm = Val & 0x7F;
4180  if (Val == 0)
4181  imm = INT32_MIN;
4182  else if (!(Val & 0x80))
4183  imm *= -1;
4184  if (imm != INT32_MIN)
4185  imm *= (1U << shift);
4186  Inst.addOperand(MCOperand::createImm(imm));
4187 
4188  return MCDisassembler::Success;
4189 }
4190 
4191 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4192  uint64_t Address, const void *Decoder) {
4194 
4195  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4196  unsigned imm = fieldFromInstruction(Val, 0, 9);
4197 
4198  // Thumb stores cannot use PC as dest register.
4199  switch (Inst.getOpcode()) {
4200  case ARM::t2STRT:
4201  case ARM::t2STRBT:
4202  case ARM::t2STRHT:
4203  case ARM::t2STRi8:
4204  case ARM::t2STRHi8:
4205  case ARM::t2STRBi8:
4206  if (Rn == 15)
4207  return MCDisassembler::Fail;
4208  break;
4209  default:
4210  break;
4211  }
4212 
4213  // Some instructions always use an additive offset.
4214  switch (Inst.getOpcode()) {
4215  case ARM::t2LDRT:
4216  case ARM::t2LDRBT:
4217  case ARM::t2LDRHT:
4218  case ARM::t2LDRSBT:
4219  case ARM::t2LDRSHT:
4220  case ARM::t2STRT:
4221  case ARM::t2STRBT:
4222  case ARM::t2STRHT:
4223  imm |= 0x100;
4224  break;
4225  default:
4226  break;
4227  }
4228 
4229  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4230  return MCDisassembler::Fail;
4231  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4232  return MCDisassembler::Fail;
4233 
4234  return S;
4235 }
4236 
4237 template<int shift>
4238 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4239  uint64_t Address,
4240  const void *Decoder) {
4242 
4243  unsigned Rn = fieldFromInstruction(Val, 8, 3);
4244  unsigned imm = fieldFromInstruction(Val, 0, 8);
4245 
4246  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4247  return MCDisassembler::Fail;
4248  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4249  return MCDisassembler::Fail;
4250 
4251  return S;
4252 }
4253 
4254 template<int shift, int WriteBack>
4255 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4256  uint64_t Address,
4257  const void *Decoder) {
4259 
4260  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4261  unsigned imm = fieldFromInstruction(Val, 0, 8);
4262  if (WriteBack) {
4263  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4264  return MCDisassembler::Fail;
4265  } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4266  return MCDisassembler::Fail;
4267  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4268  return MCDisassembler::Fail;
4269 
4270  return S;
4271 }
4272 
4273 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4274  uint64_t Address, const void *Decoder) {
4276 
4277  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4278  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4279  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4280  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4281  addr |= Rn << 9;
4282  unsigned load = fieldFromInstruction(Insn, 20, 1);
4283 
4284  if (Rn == 15) {
4285  switch (Inst.getOpcode()) {
4286  case ARM::t2LDR_PRE:
4287  case ARM::t2LDR_POST:
4288  Inst.setOpcode(ARM::t2LDRpci);
4289  break;
4290  case ARM::t2LDRB_PRE:
4291  case ARM::t2LDRB_POST:
4292  Inst.setOpcode(ARM::t2LDRBpci);
4293  break;
4294  case ARM::t2LDRH_PRE:
4295  case ARM::t2LDRH_POST:
4296  Inst.setOpcode(ARM::t2LDRHpci);
4297  break;
4298  case ARM::t2LDRSB_PRE:
4299  case ARM::t2LDRSB_POST:
4300  if (Rt == 15)
4301  Inst.setOpcode(ARM::t2PLIpci);
4302  else
4303  Inst.setOpcode(ARM::t2LDRSBpci);
4304  break;
4305  case ARM::t2LDRSH_PRE:
4306  case ARM::t2LDRSH_POST:
4307  Inst.setOpcode(ARM::t2LDRSHpci);
4308  break;
4309  default:
4310  return MCDisassembler::Fail;
4311  }
4312  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4313  }
4314 
4315  if (!load) {
4316  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4317  return MCDisassembler::Fail;
4318  }
4319 
4320  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4321  return MCDisassembler::Fail;
4322 
4323  if (load) {
4324  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4325  return MCDisassembler::Fail;
4326  }
4327 
4328  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4329  return MCDisassembler::Fail;
4330 
4331  return S;
4332 }
4333 
4334 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4335  uint64_t Address, const void *Decoder) {
4337 
4338  unsigned Rn = fieldFromInstruction(Val, 13, 4);
4339  unsigned imm = fieldFromInstruction(Val, 0, 12);
4340 
4341  // Thumb stores cannot use PC as dest register.
4342  switch (Inst.getOpcode()) {
4343  case ARM::t2STRi12:
4344  case ARM::t2STRBi12:
4345  case ARM::t2STRHi12:
4346  if (Rn == 15)
4347  return MCDisassembler::Fail;
4348  break;
4349  default:
4350  break;
4351  }
4352 
4353  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4354  return MCDisassembler::Fail;
4355  Inst.addOperand(MCOperand::createImm(imm));
4356 
4357  return S;
4358 }
4359 
4360 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4361  uint64_t Address, const void *Decoder) {
4362  unsigned imm = fieldFromInstruction(Insn, 0, 7);
4363 
4364  Inst.addOperand(MCOperand::createReg(ARM::SP));
4365  Inst.addOperand(MCOperand::createReg(ARM::SP));
4366  Inst.addOperand(MCOperand::createImm(imm));
4367 
4368  return MCDisassembler::Success;
4369 }
4370 
4371 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4372  uint64_t Address, const void *Decoder) {
4374 
4375  if (Inst.getOpcode() == ARM::tADDrSP) {
4376  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4377  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4378 
4379  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4380  return MCDisassembler::Fail;
4381  Inst.addOperand(MCOperand::createReg(ARM::SP));
4382  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4383  return MCDisassembler::Fail;
4384  } else if (Inst.getOpcode() == ARM::tADDspr) {
4385  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4386 
4387  Inst.addOperand(MCOperand::createReg(ARM::SP));
4388  Inst.addOperand(MCOperand::createReg(ARM::SP));
4389  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4390  return MCDisassembler::Fail;
4391  }
4392 
4393  return S;
4394 }
4395 
4396 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4397  uint64_t Address, const void *Decoder) {
4398  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4399  unsigned flags = fieldFromInstruction(Insn, 0, 3);
4400 
4401  Inst.addOperand(MCOperand::createImm(imod));
4402  Inst.addOperand(MCOperand::createImm(flags));
4403 
4404  return MCDisassembler::Success;
4405 }
4406 
4407 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4408  uint64_t Address, const void *Decoder) {
4410  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4411  unsigned add = fieldFromInstruction(Insn, 4, 1);
4412 
4413  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4414  return MCDisassembler::Fail;
4415  Inst.addOperand(MCOperand::createImm(add));
4416 
4417  return S;
4418 }
4419 
4420 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4421  uint64_t Address, const void *Decoder) {
4423  unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4424  unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4425 
4426  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4427  return MCDisassembler::Fail;
4428  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4429  return MCDisassembler::Fail;
4430 
4431  return S;
4432 }
4433 
4434 template<int shift>
4435 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4436  uint64_t Address, const void *Decoder) {
4438  unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4439  int imm = fieldFromInstruction(Insn, 0, 7);
4440 
4441  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4442  return MCDisassembler::Fail;
4443 
4444  if(!fieldFromInstruction(Insn, 7, 1)) {
4445  if (imm == 0)
4446  imm = INT32_MIN; // indicate -0
4447  else
4448  imm *= -1;
4449  }
4450  if (imm != INT32_MIN)
4451  imm *= (1U << shift);
4452  Inst.addOperand(MCOperand::createImm(imm));
4453 
4454  return S;
4455 }
4456 
4457 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4458  uint64_t Address, const void *Decoder) {
4459  // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4460  // Note only one trailing zero not two. Also the J1 and J2 values are from
4461  // the encoded instruction. So here change to I1 and I2 values via:
4462  // I1 = NOT(J1 EOR S);
4463  // I2 = NOT(J2 EOR S);
4464  // and build the imm32 with two trailing zeros as documented:
4465  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4466  unsigned S = (Val >> 23) & 1;
4467  unsigned J1 = (Val >> 22) & 1;
4468  unsigned J2 = (Val >> 21) & 1;
4469  unsigned I1 = !(J1 ^ S);
4470  unsigned I2 = !(J2 ^ S);
4471  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4472  int imm32 = SignExtend32<25>(tmp << 1);
4473 
4474  if (!tryAddingSymbolicOperand(Address,
4475  (Address & ~2u) + imm32 + 4,
4476  true, 4, Inst, Decoder))
4477  Inst.addOperand(MCOperand::createImm(imm32));
4478  return MCDisassembler::Success;
4479 }
4480 
4481 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4482  uint64_t Address, const void *Decoder) {
4483  if (Val == 0xA || Val == 0xB)
4484  return MCDisassembler::Fail;
4485 
4486  const FeatureBitset &featureBits =
4487  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4488 
4489  if (!isValidCoprocessorNumber(Val, featureBits))
4490  return MCDisassembler::Fail;
4491 
4492  Inst.addOperand(MCOperand::createImm(Val));
4493  return MCDisassembler::Success;
4494 }
4495 
4496 static DecodeStatus
4497 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4498  uint64_t Address, const void *Decoder) {
4500 
4501  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4502  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4503 
4504  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
4505  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4506  return MCDisassembler::Fail;
4507  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4508  return MCDisassembler::Fail;
4509  return S;
4510 }
4511 
4512 static DecodeStatus
4513 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4514  uint64_t Address, const void *Decoder) {
4516 
4517  unsigned pred = fieldFromInstruction(Insn, 22, 4);
4518  if (pred == 0xE || pred == 0xF) {
4519  unsigned opc = fieldFromInstruction(Insn, 4, 28);
4520  switch (opc) {
4521  default:
4522  return MCDisassembler::Fail;
4523  case 0xf3bf8f4:
4524  Inst.setOpcode(ARM::t2DSB);
4525  break;
4526  case 0xf3bf8f5:
4527  Inst.setOpcode(ARM::t2DMB);
4528  break;
4529  case 0xf3bf8f6:
4530  Inst.setOpcode(ARM::t2ISB);
4531  break;
4532  }
4533 
4534  unsigned imm = fieldFromInstruction(Insn, 0, 4);
4535  return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4536  }
4537 
4538  unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4539  brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4540  brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4541  brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4542  brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4543 
4544  if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4545  return MCDisassembler::Fail;
4546  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4547  return MCDisassembler::Fail;
4548 
4549  return S;
4550 }
4551 
4552 // Decode a shifted immediate operand. These basically consist
4553 // of an 8-bit value, and a 4-bit directive that specifies either
4554 // a splat operation or a rotation.
4555 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4556  uint64_t Address, const void *Decoder) {
4557  unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4558  if (ctrl == 0) {
4559  unsigned byte = fieldFromInstruction(Val, 8, 2);
4560  unsigned imm = fieldFromInstruction(Val, 0, 8);
4561  switch (byte) {
4562  case 0:
4563  Inst.addOperand(MCOperand::createImm(imm));
4564  break;
4565  case 1:
4566  Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4567  break;
4568  case 2:
4569  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4570  break;
4571  case 3:
4572  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4573  (imm << 8) | imm));
4574  break;
4575  }
4576  } else {
4577  unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4578  unsigned rot = fieldFromInstruction(Val, 7, 5);
4579  unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4580  Inst.addOperand(MCOperand::createImm(imm));
4581  }
4582 
4583  return MCDisassembler::Success;
4584 }
4585 
4586 static DecodeStatus
4588  uint64_t Address, const void *Decoder) {
4589  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4590  true, 2, Inst, Decoder))
4591  Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4592  return MCDisassembler::Success;
4593 }
4594 
4596  uint64_t Address,
4597  const void *Decoder) {
4598  // Val is passed in as S:J1:J2:imm10:imm11
4599  // Note no trailing zero after imm11. Also the J1 and J2 values are from
4600  // the encoded instruction. So here change to I1 and I2 values via:
4601  // I1 = NOT(J1 EOR S);
4602  // I2 = NOT(J2 EOR S);
4603  // and build the imm32 with one trailing zero as documented:
4604  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4605  unsigned S = (Val >> 23) & 1;
4606  unsigned J1 = (Val >> 22) & 1;
4607  unsigned J2 = (Val >> 21) & 1;
4608  unsigned I1 = !(J1 ^ S);
4609  unsigned I2 = !(J2 ^ S);
4610  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4611  int imm32 = SignExtend32<25>(tmp << 1);
4612 
4613  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4614  true, 4, Inst, Decoder))
4615  Inst.addOperand(MCOperand::createImm(imm32));
4616  return MCDisassembler::Success;
4617 }
4618 
4619 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4620  uint64_t Address, const void *Decoder) {
4621  if (Val & ~0xf)
4622  return MCDisassembler::Fail;
4623 
4624  Inst.addOperand(MCOperand::createImm(Val));
4625  return MCDisassembler::Success;
4626 }
4627 
4629  uint64_t Address, const void *Decoder) {
4630  if (Val & ~0xf)
4631  return MCDisassembler::Fail;
4632 
4633  Inst.addOperand(MCOperand::createImm(Val));
4634  return MCDisassembler::Success;
4635 }
4636 
4637 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4638  uint64_t Address, const void *Decoder) {
4640  const FeatureBitset &FeatureBits =
4641  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4642 
4643  if (FeatureBits[ARM::FeatureMClass]) {
4644  unsigned ValLow = Val & 0xff;
4645 
4646  // Validate the SYSm value first.
4647  switch (ValLow) {
4648  case 0: // apsr
4649  case 1: // iapsr
4650  case 2: // eapsr
4651  case 3: // xpsr
4652  case 5: // ipsr
4653  case 6: // epsr
4654  case 7: // iepsr
4655  case 8: // msp
4656  case 9: // psp
4657  case 16: // primask
4658  case 20: // control
4659  break;
4660  case 17: // basepri
4661  case 18: // basepri_max
4662  case 19: // faultmask
4663  if (!(FeatureBits[ARM::HasV7Ops]))
4664  // Values basepri, basepri_max and faultmask are only valid for v7m.
4665  return MCDisassembler::Fail;
4666  break;
4667  case 0x8a: // msplim_ns
4668  case 0x8b: // psplim_ns
4669  case 0x91: // basepri_ns
4670  case 0x93: // faultmask_ns
4671  if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4672  return MCDisassembler::Fail;
4674  case 10: // msplim
4675  case 11: // psplim
4676  case 0x88: // msp_ns
4677  case 0x89: // psp_ns
4678  case 0x90: // primask_ns
4679  case 0x94: // control_ns
4680  case 0x98: // sp_ns
4681  if (!(FeatureBits[ARM::Feature8MSecExt]))
4682  return MCDisassembler::Fail;
4683  break;
4684  default:
4685  // Architecturally defined as unpredictable
4687  break;
4688  }
4689 
4690  if (Inst.getOpcode() == ARM::t2MSR_M) {
4691  unsigned Mask = fieldFromInstruction(Val, 10, 2);
4692  if (!(FeatureBits[ARM::HasV7Ops])) {
4693  // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4694  // unpredictable.
4695  if (Mask != 2)
4697  }
4698  else {
4699  // The ARMv7-M architecture stores an additional 2-bit mask value in
4700  // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4701  // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4702  // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4703  // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4704  // only if the processor includes the DSP extension.
4705  if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4706  (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4708  }
4709  }
4710  } else {
4711  // A/R class
4712  if (Val == 0)
4713  return MCDisassembler::Fail;
4714  }
4715  Inst.addOperand(MCOperand::createImm(Val));
4716  return S;
4717 }
4718 
4719 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4720  uint64_t Address, const void *Decoder) {
4721  unsigned R = fieldFromInstruction(Val, 5, 1);
4722  unsigned SysM = fieldFromInstruction(Val, 0, 5);
4723 
4724  // The table of encodings for these banked registers comes from B9.2.3 of the
4725  // ARM ARM. There are patterns, but nothing regular enough to make this logic
4726  // neater. So by fiat, these values are UNPREDICTABLE:
4727  if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4728  return MCDisassembler::Fail;
4729 
4730  Inst.addOperand(MCOperand::createImm(Val));
4731  return MCDisassembler::Success;
4732 }
4733 
4734 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4735  uint64_t Address, const void *Decoder) {
4737 
4738  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4739  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4740  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4741 
4742  if (Rn == 0xF)
4744 
4745  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4746  return MCDisassembler::Fail;
4747  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4748  return MCDisassembler::Fail;
4749  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4750  return MCDisassembler::Fail;
4751 
4752  return S;
4753 }
4754 
4755 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4756  uint64_t Address,
4757  const void *Decoder) {
4759 
4760  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4761  unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4762  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4763  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4764 
4765  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4766  return MCDisassembler::Fail;
4767 
4768  if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4770 
4771  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4772  return MCDisassembler::Fail;
4773  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4774  return MCDisassembler::Fail;
4775  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4776  return MCDisassembler::Fail;
4777 
4778  return S;
4779 }
4780 
4781 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4782  uint64_t Address, const void *Decoder) {
4784 
4785  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4786  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4787  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4788  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4789  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4790  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4791 
4792  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4793 
4794  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4795  return MCDisassembler::Fail;
4796  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4797  return MCDisassembler::Fail;
4798  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4799  return MCDisassembler::Fail;
4800  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4801  return MCDisassembler::Fail;
4802 
4803  return S;
4804 }
4805 
4806 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4807  uint64_t Address, const void *Decoder) {
4809 
4810  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4811  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4812  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4813  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4814  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4815  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4816  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4817 
4818  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4819  if (Rm == 0xF) S = MCDisassembler::SoftFail;
4820 
4821  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4822  return MCDisassembler::Fail;
4823  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4824  return MCDisassembler::Fail;
4825  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4826  return MCDisassembler::Fail;
4827  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4828  return MCDisassembler::Fail;
4829 
4830  return S;
4831 }
4832 
4833 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4834  uint64_t Address, const void *Decoder) {
4836 
4837  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4838  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4839  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4840  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4841  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4842  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4843 
4844  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4845 
4846  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4847  return MCDisassembler::Fail;
4848  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4849  return MCDisassembler::Fail;
4850  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4851  return MCDisassembler::Fail;
4852  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4853  return MCDisassembler::Fail;
4854 
4855  return S;
4856 }
4857 
4858 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4859  uint64_t Address, const void *Decoder) {
4861 
4862  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4863  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4864  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4865  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4866  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4867  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4868 
4869  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4870 
4871  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4872  return MCDisassembler::Fail;
4873  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4874  return MCDisassembler::Fail;
4875  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4876  return MCDisassembler::Fail;
4877  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4878  return MCDisassembler::Fail;
4879 
4880  return S;
4881 }
4882 
4883 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4884  uint64_t Address, const void *Decoder) {
4886 
4887  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4888  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4889  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4890  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4891  unsigned size = fieldFromInstruction(Insn, 10, 2);
4892 
4893  unsigned align = 0;
4894  unsigned index = 0;
4895  switch (size) {
4896  default:
4897  return MCDisassembler::Fail;
4898  case 0:
4899  if (fieldFromInstruction(Insn, 4, 1))
4900  return MCDisassembler::Fail; // UNDEFINED
4901  index = fieldFromInstruction(Insn, 5, 3);
4902  break;
4903  case 1:
4904  if (fieldFromInstruction(Insn, 5, 1))
4905  return MCDisassembler::Fail; // UNDEFINED
4906  index = fieldFromInstruction(Insn, 6, 2);
4907  if (fieldFromInstruction(Insn, 4, 1))
4908  align = 2;
4909  break;
4910  case 2:
4911  if (fieldFromInstruction(Insn, 6, 1))
4912  return MCDisassembler::Fail; // UNDEFINED
4913  index = fieldFromInstruction(Insn, 7, 1);
4914 
4915  switch (fieldFromInstruction(Insn, 4, 2)) {
4916  case 0 :
4917  align = 0; break;
4918  case 3:
4919  align = 4; break;
4920  default:
4921  return MCDisassembler::Fail;
4922  }
4923  break;
4924  }
4925 
4926  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4927  return MCDisassembler::Fail;
4928  if (Rm != 0xF) { // Writeback
4929  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4930  return MCDisassembler::Fail;
4931  }
4932  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4933  return MCDisassembler::Fail;
4934  Inst.addOperand(MCOperand::createImm(align));
4935  if (Rm != 0xF) {
4936  if (Rm != 0xD) {
4937  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4938  return MCDisassembler::Fail;
4939  } else
4941  }
4942 
4943  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4944  return MCDisassembler::Fail;
4945  Inst.addOperand(MCOperand::createImm(index));
4946 
4947  return S;
4948 }
4949 
4950 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4951  uint64_t Address, const void *Decoder) {
4953 
4954  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4955  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4956  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4957  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4958  unsigned size = fieldFromInstruction(Insn, 10, 2);
4959 
4960  unsigned align = 0;
4961  unsigned index = 0;
4962  switch (size) {
4963  default:
4964  return MCDisassembler::Fail;
4965  case 0:
4966  if (fieldFromInstruction(Insn, 4, 1))
4967  return MCDisassembler::Fail; // UNDEFINED
4968  index = fieldFromInstruction(Insn, 5, 3);
4969  break;
4970  case 1:
4971  if (fieldFromInstruction(Insn, 5, 1))
4972  return MCDisassembler::Fail; // UNDEFINED
4973  index = fieldFromInstruction(Insn, 6, 2);
4974  if (fieldFromInstruction(Insn, 4, 1))
4975  align = 2;
4976  break;
4977  case 2:
4978  if (fieldFromInstruction(Insn, 6, 1))
4979  return MCDisassembler::Fail; // UNDEFINED
4980  index = fieldFromInstruction(Insn, 7, 1);
4981 
4982  switch (fieldFromInstruction(Insn, 4, 2)) {
4983  case 0:
4984  align = 0; break;
4985  case 3:
4986  align = 4; break;
4987  default:
4988  return MCDisassembler::Fail;
4989  }
4990  break;
4991  }
4992 
4993  if (Rm != 0xF) { // Writeback
4994  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4995  return MCDisassembler::Fail;
4996  }
4997  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4998  return MCDisassembler::Fail;
4999  Inst.addOperand(MCOperand::createImm(align));
5000  if (Rm != 0xF) {
5001  if (Rm != 0xD) {
5002  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5003  return MCDisassembler::Fail;
5004  } else
5006  }
5007 
5008  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5009  return MCDisassembler::Fail;
5010  Inst.addOperand(MCOperand::createImm(index));
5011 
5012  return S;
5013 }
5014 
5015 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
5016  uint64_t Address, const void *Decoder) {
5018 
5019  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5020  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5021  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5022  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5023  unsigned size = fieldFromInstruction(Insn, 10, 2);
5024 
5025  unsigned align = 0;
5026  unsigned index = 0;
5027  unsigned inc = 1;
5028  switch (size) {
5029  default:
5030  return MCDisassembler::Fail;
5031  case 0:
5032  index = fieldFromInstruction(Insn, 5, 3);
5033  if (fieldFromInstruction(Insn, 4, 1))
5034  align = 2;
5035  break;
5036  case 1:
5037  index = fieldFromInstruction(Insn, 6, 2);
5038  if (fieldFromInstruction(Insn, 4, 1))
5039  align = 4;
5040  if (fieldFromInstruction(Insn, 5, 1))
5041  inc = 2;
5042  break;
5043  case 2:
5044  if (fieldFromInstruction(Insn, 5, 1))
5045  return MCDisassembler::Fail; // UNDEFINED
5046  index = fieldFromInstruction(Insn, 7, 1);
5047  if (fieldFromInstruction(Insn, 4, 1) != 0)
5048  align = 8;
5049  if (fieldFromInstruction(Insn, 6, 1))
5050  inc = 2;
5051  break;
5052  }
5053 
5054  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5055  return MCDisassembler::Fail;
5056  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5057  return MCDisassembler::Fail;
5058  if (Rm != 0xF) { // Writeback
5059  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5060  return MCDisassembler::Fail;
5061  }
5062  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5063  return MCDisassembler::Fail;
5064  Inst.addOperand(MCOperand::createImm(align));
5065  if (Rm != 0xF) {
5066  if (Rm != 0xD) {
5067  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5068  return MCDisassembler::Fail;
5069  } else
5071  }
5072 
5073  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5074  return MCDisassembler::Fail;
5075  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5076  return MCDisassembler::Fail;
5077  Inst.addOperand(MCOperand::createImm(index));
5078 
5079  return S;
5080 }
5081 
5082 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
5083  uint64_t Address, const void *Decoder) {
5085 
5086  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5087  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5088  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5089  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5090  unsigned size = fieldFromInstruction(Insn, 10, 2);
5091 
5092  unsigned align = 0;
5093  unsigned index = 0;
5094  unsigned inc = 1;
5095  switch (size) {
5096  default:
5097  return MCDisassembler::Fail;
5098  case 0:
5099  index = fieldFromInstruction(Insn, 5, 3);
5100  if (fieldFromInstruction(Insn, 4, 1))
5101  align = 2;
5102  break;
5103  case 1:
5104  index = fieldFromInstruction(Insn, 6, 2);
5105  if (fieldFromInstruction(Insn, 4, 1))
5106  align = 4;
5107  if (fieldFromInstruction(Insn, 5, 1))
5108  inc = 2;
5109  break;
5110  case 2:
5111  if (fieldFromInstruction(Insn, 5, 1))
5112  return MCDisassembler::Fail; // UNDEFINED
5113  index = fieldFromInstruction(Insn, 7, 1);
5114  if (fieldFromInstruction(Insn, 4, 1) != 0)
5115  align = 8;
5116  if (fieldFromInstruction(Insn, 6, 1))
5117  inc = 2;
5118  break;
5119  }
5120 
5121  if (Rm != 0xF) { // Writeback
5122  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5123  return MCDisassembler::Fail;
5124  }
5125  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5126  return MCDisassembler::Fail;
5127  Inst.addOperand(MCOperand::createImm(align));
5128  if (Rm != 0xF) {
5129  if (Rm != 0xD) {
5130  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5131