LLVM  16.0.0git
ARMDisassembler.cpp
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1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMBaseInstrInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDecoderOps.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/TargetRegistry.h"
23 #include "llvm/Support/Compiler.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arm-disassembler"
35 
37 
38 namespace {
39 
40  // Handles the condition code status of instructions in IT blocks
41  class ITStatus
42  {
43  public:
44  // Returns the condition code for instruction in IT block
45  unsigned getITCC() {
46  unsigned CC = ARMCC::AL;
47  if (instrInITBlock())
48  CC = ITStates.back();
49  return CC;
50  }
51 
52  // Advances the IT block state to the next T or E
53  void advanceITState() {
54  ITStates.pop_back();
55  }
56 
57  // Returns true if the current instruction is in an IT block
58  bool instrInITBlock() {
59  return !ITStates.empty();
60  }
61 
62  // Returns true if current instruction is the last instruction in an IT block
63  bool instrLastInITBlock() {
64  return ITStates.size() == 1;
65  }
66 
67  // Called when decoding an IT instruction. Sets the IT state for
68  // the following instructions that for the IT block. Firstcond
69  // corresponds to the field in the IT instruction encoding; Mask
70  // is in the MCOperand format in which 1 means 'else' and 0 'then'.
71  void setITState(char Firstcond, char Mask) {
72  // (3 - the number of trailing zeros) is the number of then / else.
73  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75  assert(NumTZ <= 3 && "Invalid IT mask!");
76  // push condition codes onto the stack the correct order for the pops
77  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78  unsigned Else = (Mask >> Pos) & 1;
79  ITStates.push_back(CCBits ^ Else);
80  }
81  ITStates.push_back(CCBits);
82  }
83 
84  private:
85  std::vector<unsigned char> ITStates;
86  };
87 
88  class VPTStatus
89  {
90  public:
91  unsigned getVPTPred() {
92  unsigned Pred = ARMVCC::None;
93  if (instrInVPTBlock())
94  Pred = VPTStates.back();
95  return Pred;
96  }
97 
98  void advanceVPTState() {
99  VPTStates.pop_back();
100  }
101 
102  bool instrInVPTBlock() {
103  return !VPTStates.empty();
104  }
105 
106  bool instrLastInVPTBlock() {
107  return VPTStates.size() == 1;
108  }
109 
110  void setVPTState(char Mask) {
111  // (3 - the number of trailing zeros) is the number of then / else.
112  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113  assert(NumTZ <= 3 && "Invalid VPT mask!");
114  // push predicates onto the stack the correct order for the pops
115  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116  bool T = ((Mask >> Pos) & 1) == 0;
117  if (T)
118  VPTStates.push_back(ARMVCC::Then);
119  else
120  VPTStates.push_back(ARMVCC::Else);
121  }
122  VPTStates.push_back(ARMVCC::Then);
123  }
124 
125  private:
127  };
128 
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
132  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133  MCDisassembler(STI, Ctx) {
134  InstructionEndianness = STI.getFeatureBits()[ARM::ModeBigEndianInstructions]
137  }
138 
139  ~ARMDisassembler() override = default;
140 
141  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
142  ArrayRef<uint8_t> Bytes, uint64_t Address,
143  raw_ostream &CStream) const override;
144 
145  uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
146  uint64_t Address) const override;
147 
148 private:
149  DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
150  ArrayRef<uint8_t> Bytes, uint64_t Address,
151  raw_ostream &CStream) const;
152 
153  DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
154  ArrayRef<uint8_t> Bytes, uint64_t Address,
155  raw_ostream &CStream) const;
156 
157  mutable ITStatus ITBlock;
158  mutable VPTStatus VPTBlock;
159 
160  DecodeStatus AddThumbPredicate(MCInst&) const;
161  void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
162 
163  llvm::support::endianness InstructionEndianness;
164 };
165 
166 } // end anonymous namespace
167 
168 static bool Check(DecodeStatus &Out, DecodeStatus In) {
169  switch (In) {
171  // Out stays the same.
172  return true;
174  Out = In;
175  return true;
177  Out = In;
178  return false;
179  }
180  llvm_unreachable("Invalid DecodeStatus!");
181 }
182 
183 // Forward declare these because the autogenerated code will reference them.
184 // Definitions are further down.
185 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
186  uint64_t Address,
187  const MCDisassembler *Decoder);
188 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
189  uint64_t Address,
190  const MCDisassembler *Decoder);
191 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
192  uint64_t Address,
193  const MCDisassembler *Decoder);
194 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
195  uint64_t Address,
196  const MCDisassembler *Decoder);
197 static DecodeStatus
198 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
199  uint64_t Address,
200  const MCDisassembler *Decoder);
201 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
202  uint64_t Address,
203  const MCDisassembler *Decoder);
204 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
205  uint64_t Address,
206  const MCDisassembler *Decoder);
207 static DecodeStatus
208 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
209  const MCDisassembler *Decoder);
210 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
211  uint64_t Address,
212  const MCDisassembler *Decoder);
213 static DecodeStatus
214 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
215  const MCDisassembler *Decoder);
216 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
217  uint64_t Address,
218  const MCDisassembler *Decoder);
219 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
220  uint64_t Address,
221  const MCDisassembler *Decoder);
222 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
223  uint64_t Address,
224  const MCDisassembler *Decoder);
225 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
226  uint64_t Address,
227  const MCDisassembler *Decoder);
228 static DecodeStatus
229 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
230  const MCDisassembler *Decoder);
231 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
232  uint64_t Address,
233  const MCDisassembler *Decoder);
234 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
235  uint64_t Address,
236  const MCDisassembler *Decoder);
237 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
238  uint64_t Address,
239  const MCDisassembler *Decoder);
240 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
241  uint64_t Address,
242  const MCDisassembler *Decoder);
243 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
244  uint64_t Address,
245  const MCDisassembler *Decoder);
246 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
247  uint64_t Address,
248  const MCDisassembler *Decoder);
249 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
250  uint64_t Address,
251  const MCDisassembler *Decoder);
252 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
253  uint64_t Address,
254  const MCDisassembler *Decoder);
255 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
256  uint64_t Address,
257  const MCDisassembler *Decoder);
258 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
259  uint64_t Address,
260  const MCDisassembler *Decoder);
261 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
262  uint64_t Address,
263  const MCDisassembler *Decoder);
264 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
265  uint64_t Address,
266  const MCDisassembler *Decoder);
267 static DecodeStatus
268 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
269  const MCDisassembler *Decoder);
270 
271 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
272  uint64_t Address,
273  const MCDisassembler *Decoder);
274 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
275  uint64_t Address,
276  const MCDisassembler *Decoder);
277 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
278  uint64_t Address,
279  const MCDisassembler *Decoder);
280 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
281  uint64_t Address,
282  const MCDisassembler *Decoder);
283 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
284  uint64_t Address,
285  const MCDisassembler *Decoder);
286 
287 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
288  uint64_t Address,
289  const MCDisassembler *Decoder);
290 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
291  uint64_t Address,
292  const MCDisassembler *Decoder);
293 static DecodeStatus
294 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
295  const MCDisassembler *Decoder);
296 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
297  uint64_t Address,
298  const MCDisassembler *Decoder);
299 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
300  uint64_t Address,
301  const MCDisassembler *Decoder);
302 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
303  uint64_t Address,
304  const MCDisassembler *Decoder);
305 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
306  uint64_t Address,
307  const MCDisassembler *Decoder);
308 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
309  uint64_t Address,
310  const MCDisassembler *Decoder);
311 
312 static DecodeStatus
314  uint64_t Adddress,
315  const MCDisassembler *Decoder);
316 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
317  uint64_t Address,
318  const MCDisassembler *Decoder);
319 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
320  uint64_t Address,
321  const MCDisassembler *Decoder);
322 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
323  uint64_t Address,
324  const MCDisassembler *Decoder);
325 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
326  uint64_t Address,
327  const MCDisassembler *Decoder);
328 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
329  uint64_t Address,
330  const MCDisassembler *Decoder);
331 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
332  uint64_t Address,
333  const MCDisassembler *Decoder);
334 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
335  uint64_t Address,
336  const MCDisassembler *Decoder);
337 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
338  uint64_t Address,
339  const MCDisassembler *Decoder);
341  uint64_t Address,
342  const MCDisassembler *Decoder);
343 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
344  uint64_t Address,
345  const MCDisassembler *Decoder);
346 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
347  uint64_t Address,
348  const MCDisassembler *Decoder);
349 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
350  uint64_t Address,
351  const MCDisassembler *Decoder);
352 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
353  uint64_t Address,
354  const MCDisassembler *Decoder);
355 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
356  uint64_t Address,
357  const MCDisassembler *Decoder);
358 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
359  uint64_t Address,
360  const MCDisassembler *Decoder);
361 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
362  uint64_t Address,
363  const MCDisassembler *Decoder);
364 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
365  uint64_t Address,
366  const MCDisassembler *Decoder);
367 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
368  uint64_t Address,
369  const MCDisassembler *Decoder);
370 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
371  uint64_t Address,
372  const MCDisassembler *Decoder);
373 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
374  uint64_t Address,
375  const MCDisassembler *Decoder);
376 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
377  uint64_t Address,
378  const MCDisassembler *Decoder);
379 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
380  uint64_t Address,
381  const MCDisassembler *Decoder);
382 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
383  uint64_t Address,
384  const MCDisassembler *Decoder);
385 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
386  uint64_t Address,
387  const MCDisassembler *Decoder);
388 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
389  uint64_t Address,
390  const MCDisassembler *Decoder);
391 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
392  uint64_t Address,
393  const MCDisassembler *Decoder);
394 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
395  uint64_t Address,
396  const MCDisassembler *Decoder);
397 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
398  uint64_t Address,
399  const MCDisassembler *Decoder);
400 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
401  uint64_t Address,
402  const MCDisassembler *Decoder);
403 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
404  uint64_t Address,
405  const MCDisassembler *Decoder);
406 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
407  uint64_t Address,
408  const MCDisassembler *Decoder);
409 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
410  uint64_t Address,
411  const MCDisassembler *Decoder);
412 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
413  uint64_t Address,
414  const MCDisassembler *Decoder);
415 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
416  uint64_t Address,
417  const MCDisassembler *Decoder);
418 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
419  uint64_t Address,
420  const MCDisassembler *Decoder);
421 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
422  uint64_t Address,
423  const MCDisassembler *Decoder);
424 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
425  uint64_t Address,
426  const MCDisassembler *Decoder);
427 template <int shift>
428 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
429  uint64_t Address,
430  const MCDisassembler *Decoder);
431 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
432  uint64_t Address,
433  const MCDisassembler *Decoder);
434 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
435  uint64_t Address,
436  const MCDisassembler *Decoder);
437 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
438  uint64_t Address,
439  const MCDisassembler *Decoder);
440 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
441  const MCDisassembler *Decoder);
442 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
443  uint64_t Address,
444  const MCDisassembler *Decoder);
445 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
446  uint64_t Address,
447  const MCDisassembler *Decoder);
448 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
449  uint64_t Address,
450  const MCDisassembler *Decoder);
451 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
452  uint64_t Address,
453  const MCDisassembler *Decoder);
454 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
455  uint64_t Address,
456  const MCDisassembler *Decoder);
457 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
458  uint64_t Address,
459  const MCDisassembler *Decoder);
460 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
461  uint64_t Address,
462  const MCDisassembler *Decoder);
463 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
464  const MCDisassembler *Decoder);
465 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
466  const MCDisassembler *Decoder);
467 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
468  const MCDisassembler *Decoder);
469 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
470  const MCDisassembler *Decoder);
471 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
472  const MCDisassembler *Decoder);
473 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
474  const MCDisassembler *Decoder);
475 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
476  const MCDisassembler *Decoder);
477 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
478  const MCDisassembler *Decoder);
479 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
480  const MCDisassembler *Decoder);
481 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
482  const MCDisassembler *Decoder);
483 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
484  const MCDisassembler *Decoder);
485 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
486  const MCDisassembler *Decoder);
487 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
488  const MCDisassembler *Decoder);
489 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
490  uint64_t Address,
491  const MCDisassembler *Decoder);
492 static DecodeStatus
493 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
494  const MCDisassembler *Decoder);
495 
497  uint64_t Address,
498  const MCDisassembler *Decoder);
499 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
500  uint64_t Address,
501  const MCDisassembler *Decoder);
502 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
503  uint64_t Address,
504  const MCDisassembler *Decoder);
505 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
506  uint64_t Address,
507  const MCDisassembler *Decoder);
508 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
509  uint64_t Address,
510  const MCDisassembler *Decoder);
511 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
512  uint64_t Address,
513  const MCDisassembler *Decoder);
514 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
515  uint64_t Address,
516  const MCDisassembler *Decoder);
517 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
518  uint64_t Address,
519  const MCDisassembler *Decoder);
520 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
521  uint64_t Address,
522  const MCDisassembler *Decoder);
523 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
524  uint64_t Address,
525  const MCDisassembler *Decoder);
526 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
527  uint64_t Address,
528  const MCDisassembler *Decoder);
529 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
530  uint64_t Address,
531  const MCDisassembler *Decoder);
532 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
533  const MCDisassembler *Decoder);
534 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
535  uint64_t Address,
536  const MCDisassembler *Decoder);
537 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
538  const MCDisassembler *Decoder);
539 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
540  const MCDisassembler *Decoder);
541 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
542  uint64_t Address,
543  const MCDisassembler *Decoder);
544 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
545  uint64_t Address,
546  const MCDisassembler *Decoder);
547 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
548  uint64_t Address,
549  const MCDisassembler *Decoder);
550 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
551  const MCDisassembler *Decoder);
552 template <int shift>
553 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
554  const MCDisassembler *Decoder);
555 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
556  uint64_t Address,
557  const MCDisassembler *Decoder);
558 template <int shift>
559 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
560  uint64_t Address,
561  const MCDisassembler *Decoder);
562 template <int shift, int WriteBack>
563 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
564  uint64_t Address,
565  const MCDisassembler *Decoder);
567  uint64_t Address,
568  const MCDisassembler *Decoder);
570  uint64_t Address,
571  const MCDisassembler *Decoder);
573  uint64_t Address,
574  const MCDisassembler *Decoder);
575 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
576  uint64_t Address,
577  const MCDisassembler *Decoder);
578 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
579  uint64_t Address,
580  const MCDisassembler *Decoder);
581 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
582  uint64_t Address,
583  const MCDisassembler *Decoder);
584 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
585  uint64_t Address,
586  const MCDisassembler *Decoder);
587 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
588  uint64_t Address,
589  const MCDisassembler *Decoder);
590 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
591  const MCDisassembler *Decoder);
592 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
593  uint64_t Address,
594  const MCDisassembler *Decoder);
595 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
596  uint64_t Address,
597  const MCDisassembler *Decoder);
598 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
599  const MCDisassembler *Decoder);
600 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
601  uint64_t Address,
602  const MCDisassembler *Decoder);
603 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
604  uint64_t Address,
605  const MCDisassembler *Decoder);
606 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
607  const MCDisassembler *Decoder);
608 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
609  uint64_t Address,
610  const MCDisassembler *Decoder);
611 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
612  uint64_t Address,
613  const MCDisassembler *Decoder);
614 
615 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
616  const MCDisassembler *Decoder);
617 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
618  uint64_t Address,
619  const MCDisassembler *Decoder);
620 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
621  uint64_t Address,
622  const MCDisassembler *Decoder);
623 
624 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
625 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
626  uint64_t Address,
627  const MCDisassembler *Decoder);
628 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
629  uint64_t Address,
630  const MCDisassembler *Decoder);
631 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
632  uint64_t Address,
633  const MCDisassembler *Decoder);
634 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
635  const MCDisassembler *Decoder);
636 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
637  uint64_t Address,
638  const MCDisassembler *Decoder);
639 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
640  const MCDisassembler *Decoder);
641 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
642  uint64_t Address,
643  const MCDisassembler *Decoder);
644 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
645  uint64_t Address,
646  const MCDisassembler *Decoder);
647 static DecodeStatus
648 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
649  const MCDisassembler *Decoder);
650 static DecodeStatus
651 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
652  const MCDisassembler *Decoder);
653 static DecodeStatus
654 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
655  const MCDisassembler *Decoder);
656 static DecodeStatus
657 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
658  const MCDisassembler *Decoder);
659 template <bool Writeback>
660 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
661  uint64_t Address,
662  const MCDisassembler *Decoder);
663 template <int shift>
664 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
665  uint64_t Address,
666  const MCDisassembler *Decoder);
667 template <int shift>
668 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
669  uint64_t Address,
670  const MCDisassembler *Decoder);
671 template <int shift>
672 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
673  uint64_t Address,
674  const MCDisassembler *Decoder);
675 template <unsigned MinLog, unsigned MaxLog>
676 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
677  uint64_t Address,
678  const MCDisassembler *Decoder);
679 template <unsigned start>
680 static DecodeStatus
681 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
682  const MCDisassembler *Decoder);
683 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
684  uint64_t Address,
685  const MCDisassembler *Decoder);
686 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
687  uint64_t Address,
688  const MCDisassembler *Decoder);
689 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
690  uint64_t Address,
691  const MCDisassembler *Decoder);
692 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
693  uint64_t Address,
694  const MCDisassembler *Decoder);
695 template <bool scalar, OperandDecoder predicate_decoder>
696 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
697  const MCDisassembler *Decoder);
698 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
699  const MCDisassembler *Decoder);
700 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
701  uint64_t Address,
702  const MCDisassembler *Decoder);
703 static DecodeStatus
704 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
705  const MCDisassembler *Decoder);
706 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
707  uint64_t Address,
708  const MCDisassembler *Decoder);
709 
710 #include "ARMGenDisassemblerTables.inc"
711 
713  const MCSubtargetInfo &STI,
714  MCContext &Ctx) {
715  return new ARMDisassembler(STI, Ctx);
716 }
717 
718 // Post-decoding checks
720  uint64_t Address, raw_ostream &CS,
721  uint32_t Insn,
722  DecodeStatus Result) {
723  switch (MI.getOpcode()) {
724  case ARM::HVC: {
725  // HVC is undefined if condition = 0xf otherwise upredictable
726  // if condition != 0xe
727  uint32_t Cond = (Insn >> 28) & 0xF;
728  if (Cond == 0xF)
729  return MCDisassembler::Fail;
730  if (Cond != 0xE)
732  return Result;
733  }
734  case ARM::t2ADDri:
735  case ARM::t2ADDri12:
736  case ARM::t2ADDrr:
737  case ARM::t2ADDrs:
738  case ARM::t2SUBri:
739  case ARM::t2SUBri12:
740  case ARM::t2SUBrr:
741  case ARM::t2SUBrs:
742  if (MI.getOperand(0).getReg() == ARM::SP &&
743  MI.getOperand(1).getReg() != ARM::SP)
745  return Result;
746  default: return Result;
747  }
748 }
749 
750 uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
751  uint64_t Address) const {
752  // In Arm state, instructions are always 4 bytes wide, so there's no
753  // point in skipping any smaller number of bytes if an instruction
754  // can't be decoded.
755  if (!STI.getFeatureBits()[ARM::ModeThumb])
756  return 4;
757 
758  // In a Thumb instruction stream, a halfword is a standalone 2-byte
759  // instruction if and only if its value is less than 0xE800.
760  // Otherwise, it's the first halfword of a 4-byte instruction.
761  //
762  // So, if we can see the upcoming halfword, we can judge on that
763  // basis, and maybe skip a whole 4-byte instruction that we don't
764  // know how to decode, without accidentally trying to interpret its
765  // second half as something else.
766  //
767  // If we don't have the instruction data available, we just have to
768  // recommend skipping the minimum sensible distance, which is 2
769  // bytes.
770  if (Bytes.size() < 2)
771  return 2;
772 
773  uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
774  Bytes.data(), InstructionEndianness);
775  return Insn16 < 0xE800 ? 2 : 4;
776 }
777 
778 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
779  ArrayRef<uint8_t> Bytes,
780  uint64_t Address,
781  raw_ostream &CS) const {
782  if (STI.getFeatureBits()[ARM::ModeThumb])
783  return getThumbInstruction(MI, Size, Bytes, Address, CS);
784  return getARMInstruction(MI, Size, Bytes, Address, CS);
785 }
786 
787 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
788  ArrayRef<uint8_t> Bytes,
789  uint64_t Address,
790  raw_ostream &CS) const {
791  CommentStream = &CS;
792 
793  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
794  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
795  "mode!");
796 
797  // We want to read exactly 4 bytes of data.
798  if (Bytes.size() < 4) {
799  Size = 0;
800  return MCDisassembler::Fail;
801  }
802 
803  // Encoded as a 32-bit word in the stream.
804  uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),
805  InstructionEndianness);
806 
807  // Calling the auto-generated decoder function.
809  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
810  if (Result != MCDisassembler::Fail) {
811  Size = 4;
812  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
813  }
814 
815  struct DecodeTable {
816  const uint8_t *P;
817  bool DecodePred;
818  };
819 
820  const DecodeTable Tables[] = {
821  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
822  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
823  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
824  {DecoderTablev8Crypto32, false},
825  };
826 
827  for (auto Table : Tables) {
828  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
829  if (Result != MCDisassembler::Fail) {
830  Size = 4;
831  // Add a fake predicate operand, because we share these instruction
832  // definitions with Thumb2 where these instructions are predicable.
833  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
834  return MCDisassembler::Fail;
835  return Result;
836  }
837  }
838 
839  Result =
840  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
841  if (Result != MCDisassembler::Fail) {
842  Size = 4;
843  return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
844  }
845 
846  Size = 4;
847  return MCDisassembler::Fail;
848 }
849 
850 namespace llvm {
851 
852 extern const MCInstrDesc ARMInsts[];
853 
854 } // end namespace llvm
855 
856 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
857 /// immediate Value in the MCInst. The immediate Value has had any PC
858 /// adjustment made by the caller. If the instruction is a branch instruction
859 /// then isBranch is true, else false. If the getOpInfo() function was set as
860 /// part of the setupForSymbolicDisassembly() call then that function is called
861 /// to get any symbolic information at the Address for this instruction. If
862 /// that returns non-zero then the symbolic information it returns is used to
863 /// create an MCExpr and that is added as an operand to the MCInst. If
864 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
865 /// Value is done and if a symbol is found an MCExpr is created with that, else
866 /// an MCExpr with Value is created. This function returns true if it adds an
867 /// operand to the MCInst and false otherwise.
868 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
869  bool isBranch, uint64_t InstSize,
870  MCInst &MI,
871  const MCDisassembler *Decoder) {
872  // FIXME: Does it make sense for value to be negative?
873  return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
874  isBranch, /*Offset=*/0, /*OpSize=*/0,
875  InstSize);
876 }
877 
878 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
879 /// referenced by a load instruction with the base register that is the Pc.
880 /// These can often be values in a literal pool near the Address of the
881 /// instruction. The Address of the instruction and its immediate Value are
882 /// used as a possible literal pool entry. The SymbolLookUp call back will
883 /// return the name of a symbol referenced by the literal pool's entry if
884 /// the referenced address is that of a symbol. Or it will return a pointer to
885 /// a literal 'C' string if the referenced address of the literal pool's entry
886 /// is an address into a section with 'C' string literals.
888  const MCDisassembler *Decoder) {
889  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
890  Dis->tryAddingPcLoadReferenceComment(Value, Address);
891 }
892 
893 // Thumb1 instructions don't have explicit S bits. Rather, they
894 // implicitly set CPSR. Since it's not represented in the encoding, the
895 // auto-generated decoder won't inject the CPSR operand. We need to fix
896 // that as a post-pass.
897 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
898  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
899  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
900  MCInst::iterator I = MI.begin();
901  for (unsigned i = 0; i < NumOps; ++i, ++I) {
902  if (I == MI.end()) break;
903  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
904  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
905  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
906  return;
907  }
908  }
909 
910  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
911 }
912 
913 static bool isVectorPredicable(unsigned Opcode) {
914  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
915  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
916  for (unsigned i = 0; i < NumOps; ++i) {
917  if (ARM::isVpred(OpInfo[i].OperandType))
918  return true;
919  }
920  return false;
921 }
922 
923 // Most Thumb instructions don't have explicit predicates in the
924 // encoding, but rather get their predicates from IT context. We need
925 // to fix up the predicate operands using this context information as a
926 // post-pass.
928 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
930 
931  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
932 
933  // A few instructions actually have predicates encoded in them. Don't
934  // try to overwrite it if we're seeing one of those.
935  switch (MI.getOpcode()) {
936  case ARM::tBcc:
937  case ARM::t2Bcc:
938  case ARM::tCBZ:
939  case ARM::tCBNZ:
940  case ARM::tCPS:
941  case ARM::t2CPS3p:
942  case ARM::t2CPS2p:
943  case ARM::t2CPS1p:
944  case ARM::t2CSEL:
945  case ARM::t2CSINC:
946  case ARM::t2CSINV:
947  case ARM::t2CSNEG:
948  case ARM::tMOVSr:
949  case ARM::tSETEND:
950  // Some instructions (mostly conditional branches) are not
951  // allowed in IT blocks.
952  if (ITBlock.instrInITBlock())
953  S = SoftFail;
954  else
955  return Success;
956  break;
957  case ARM::t2HINT:
958  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
959  S = SoftFail;
960  break;
961  case ARM::tB:
962  case ARM::t2B:
963  case ARM::t2TBB:
964  case ARM::t2TBH:
965  // Some instructions (mostly unconditional branches) can
966  // only appears at the end of, or outside of, an IT.
967  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
968  S = SoftFail;
969  break;
970  default:
971  break;
972  }
973 
974  // Warn on non-VPT predicable instruction in a VPT block and a VPT
975  // predicable instruction in an IT block
976  if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
977  (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
978  S = SoftFail;
979 
980  // If we're in an IT/VPT block, base the predicate on that. Otherwise,
981  // assume a predicate of AL.
982  unsigned CC = ARMCC::AL;
983  unsigned VCC = ARMVCC::None;
984  if (ITBlock.instrInITBlock()) {
985  CC = ITBlock.getITCC();
986  ITBlock.advanceITState();
987  } else if (VPTBlock.instrInVPTBlock()) {
988  VCC = VPTBlock.getVPTPred();
989  VPTBlock.advanceVPTState();
990  }
991 
992  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
993  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
994 
995  MCInst::iterator CCI = MI.begin();
996  for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
997  if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
998  }
999 
1000  if (ARMInsts[MI.getOpcode()].isPredicable()) {
1001  CCI = MI.insert(CCI, MCOperand::createImm(CC));
1002  ++CCI;
1003  if (CC == ARMCC::AL)
1004  MI.insert(CCI, MCOperand::createReg(0));
1005  else
1006  MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
1007  } else if (CC != ARMCC::AL) {
1008  Check(S, SoftFail);
1009  }
1010 
1011  MCInst::iterator VCCI = MI.begin();
1012  unsigned VCCPos;
1013  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
1014  if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
1015  }
1016 
1017  if (isVectorPredicable(MI.getOpcode())) {
1018  VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
1019  ++VCCI;
1020  if (VCC == ARMVCC::None)
1021  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
1022  else
1023  VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
1024  ++VCCI;
1025  VCCI = MI.insert(VCCI, MCOperand::createReg(0));
1026  ++VCCI;
1027  if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
1028  int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
1029  VCCPos + 3, MCOI::TIED_TO);
1030  assert(TiedOp >= 0 &&
1031  "Inactive register in vpred_r is not tied to an output!");
1032  // Copy the operand to ensure it's not invalidated when MI grows.
1033  MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
1034  }
1035  } else if (VCC != ARMVCC::None) {
1036  Check(S, SoftFail);
1037  }
1038 
1039  return S;
1040 }
1041 
1042 // Thumb VFP instructions are a special case. Because we share their
1043 // encodings between ARM and Thumb modes, and they are predicable in ARM
1044 // mode, the auto-generated decoder will give them an (incorrect)
1045 // predicate operand. We need to rewrite these operands based on the IT
1046 // context as a post-pass.
1047 void ARMDisassembler::UpdateThumbVFPPredicate(
1048  DecodeStatus &S, MCInst &MI) const {
1049  unsigned CC;
1050  CC = ITBlock.getITCC();
1051  if (CC == 0xF)
1052  CC = ARMCC::AL;
1053  if (ITBlock.instrInITBlock())
1054  ITBlock.advanceITState();
1055  else if (VPTBlock.instrInVPTBlock()) {
1056  CC = VPTBlock.getVPTPred();
1057  VPTBlock.advanceVPTState();
1058  }
1059 
1060  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
1061  MCInst::iterator I = MI.begin();
1062  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
1063  for (unsigned i = 0; i < NumOps; ++i, ++I) {
1064  if (OpInfo[i].isPredicate() ) {
1065  if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
1066  Check(S, SoftFail);
1067  I->setImm(CC);
1068  ++I;
1069  if (CC == ARMCC::AL)
1070  I->setReg(0);
1071  else
1072  I->setReg(ARM::CPSR);
1073  return;
1074  }
1075  }
1076 }
1077 
1078 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
1079  ArrayRef<uint8_t> Bytes,
1080  uint64_t Address,
1081  raw_ostream &CS) const {
1082  CommentStream = &CS;
1083 
1084  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
1085  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
1086 
1087  // We want to read exactly 2 bytes of data.
1088  if (Bytes.size() < 2) {
1089  Size = 0;
1090  return MCDisassembler::Fail;
1091  }
1092 
1093  uint16_t Insn16 = llvm::support::endian::read<uint16_t>(
1094  Bytes.data(), InstructionEndianness);
1096  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
1097  if (Result != MCDisassembler::Fail) {
1098  Size = 2;
1099  Check(Result, AddThumbPredicate(MI));
1100  return Result;
1101  }
1102 
1103  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
1104  STI);
1105  if (Result) {
1106  Size = 2;
1107  bool InITBlock = ITBlock.instrInITBlock();
1108  Check(Result, AddThumbPredicate(MI));
1109  AddThumb1SBit(MI, InITBlock);
1110  return Result;
1111  }
1112 
1113  Result =
1114  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
1115  if (Result != MCDisassembler::Fail) {
1116  Size = 2;
1117 
1118  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
1119  // the Thumb predicate.
1120  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
1122 
1123  Check(Result, AddThumbPredicate(MI));
1124 
1125  // If we find an IT instruction, we need to parse its condition
1126  // code and mask operands so that we can apply them correctly
1127  // to the subsequent instructions.
1128  if (MI.getOpcode() == ARM::t2IT) {
1129  unsigned Firstcond = MI.getOperand(0).getImm();
1130  unsigned Mask = MI.getOperand(1).getImm();
1131  ITBlock.setITState(Firstcond, Mask);
1132 
1133  // An IT instruction that would give a 'NV' predicate is unpredictable.
1134  if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
1135  CS << "unpredictable IT predicate sequence";
1136  }
1137 
1138  return Result;
1139  }
1140 
1141  // We want to read exactly 4 bytes of data.
1142  if (Bytes.size() < 4) {
1143  Size = 0;
1144  return MCDisassembler::Fail;
1145  }
1146 
1147  uint32_t Insn32 =
1148  (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(
1149  Bytes.data() + 2, InstructionEndianness);
1150 
1151  Result =
1152  decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
1153  if (Result != MCDisassembler::Fail) {
1154  Size = 4;
1155 
1156  // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
1157  // the VPT predicate.
1158  if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
1160 
1161  Check(Result, AddThumbPredicate(MI));
1162 
1163  if (isVPTOpcode(MI.getOpcode())) {
1164  unsigned Mask = MI.getOperand(0).getImm();
1165  VPTBlock.setVPTState(Mask);
1166  }
1167 
1168  return Result;
1169  }
1170 
1171  Result =
1172  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1173  if (Result != MCDisassembler::Fail) {
1174  Size = 4;
1175  bool InITBlock = ITBlock.instrInITBlock();
1176  Check(Result, AddThumbPredicate(MI));
1177  AddThumb1SBit(MI, InITBlock);
1178  return Result;
1179  }
1180 
1181  Result =
1182  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1183  if (Result != MCDisassembler::Fail) {
1184  Size = 4;
1185  Check(Result, AddThumbPredicate(MI));
1186  return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
1187  }
1188 
1189  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1190  Result =
1191  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1192  if (Result != MCDisassembler::Fail) {
1193  Size = 4;
1194  UpdateThumbVFPPredicate(Result, MI);
1195  return Result;
1196  }
1197  }
1198 
1199  Result =
1200  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1201  if (Result != MCDisassembler::Fail) {
1202  Size = 4;
1203  return Result;
1204  }
1205 
1206  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1207  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1208  STI);
1209  if (Result != MCDisassembler::Fail) {
1210  Size = 4;
1211  Check(Result, AddThumbPredicate(MI));
1212  return Result;
1213  }
1214  }
1215 
1216  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1217  uint32_t NEONLdStInsn = Insn32;
1218  NEONLdStInsn &= 0xF0FFFFFF;
1219  NEONLdStInsn |= 0x04000000;
1220  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1221  Address, this, STI);
1222  if (Result != MCDisassembler::Fail) {
1223  Size = 4;
1224  Check(Result, AddThumbPredicate(MI));
1225  return Result;
1226  }
1227  }
1228 
1229  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1230  uint32_t NEONDataInsn = Insn32;
1231  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1232  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1233  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1234  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1235  Address, this, STI);
1236  if (Result != MCDisassembler::Fail) {
1237  Size = 4;
1238  Check(Result, AddThumbPredicate(MI));
1239  return Result;
1240  }
1241 
1242  uint32_t NEONCryptoInsn = Insn32;
1243  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1244  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1245  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1246  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1247  Address, this, STI);
1248  if (Result != MCDisassembler::Fail) {
1249  Size = 4;
1250  return Result;
1251  }
1252 
1253  uint32_t NEONv8Insn = Insn32;
1254  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1255  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1256  this, STI);
1257  if (Result != MCDisassembler::Fail) {
1258  Size = 4;
1259  return Result;
1260  }
1261  }
1262 
1263  uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1264  const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1265  ? DecoderTableThumb2CDE32
1266  : DecoderTableThumb2CoProc32;
1267  Result =
1268  decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
1269  if (Result != MCDisassembler::Fail) {
1270  Size = 4;
1271  Check(Result, AddThumbPredicate(MI));
1272  return Result;
1273  }
1274 
1275  Size = 0;
1276  return MCDisassembler::Fail;
1277 }
1278 
1288 }
1289 
1290 static const uint16_t GPRDecoderTable[] = {
1291  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1292  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1293  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1294  ARM::R12, ARM::SP, ARM::LR, ARM::PC
1295 };
1296 
1297 static const uint16_t CLRMGPRDecoderTable[] = {
1298  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1299  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1300  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1301  ARM::R12, 0, ARM::LR, ARM::APSR
1302 };
1303 
1304 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1305  uint64_t Address,
1306  const MCDisassembler *Decoder) {
1307  if (RegNo > 15)
1308  return MCDisassembler::Fail;
1309 
1310  unsigned Register = GPRDecoderTable[RegNo];
1312  return MCDisassembler::Success;
1313 }
1314 
1315 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1316  uint64_t Address,
1317  const MCDisassembler *Decoder) {
1318  if (RegNo > 15)
1319  return MCDisassembler::Fail;
1320 
1321  unsigned Register = CLRMGPRDecoderTable[RegNo];
1322  if (Register == 0)
1323  return MCDisassembler::Fail;
1324 
1326  return MCDisassembler::Success;
1327 }
1328 
1329 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1330  uint64_t Address,
1331  const MCDisassembler *Decoder) {
1333 
1334  if (RegNo == 15)
1336 
1337  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1338 
1339  return S;
1340 }
1341 
1342 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1343  uint64_t Address,
1344  const MCDisassembler *Decoder) {
1346 
1347  if (RegNo == 13)
1349 
1350  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1351 
1352  return S;
1353 }
1354 
1355 static DecodeStatus
1356 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1357  const MCDisassembler *Decoder) {
1359 
1360  if (RegNo == 15)
1361  {
1362  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1363  return MCDisassembler::Success;
1364  }
1365 
1366  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1367  return S;
1368 }
1369 
1370 static DecodeStatus
1371 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1372  const MCDisassembler *Decoder) {
1374 
1375  if (RegNo == 15)
1376  {
1377  Inst.addOperand(MCOperand::createReg(ARM::ZR));
1378  return MCDisassembler::Success;
1379  }
1380 
1381  if (RegNo == 13)
1383 
1384  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1385  return S;
1386 }
1387 
1388 static DecodeStatus
1389 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1390  const MCDisassembler *Decoder) {
1392  if (RegNo == 13)
1393  return MCDisassembler::Fail;
1394  Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1395  return S;
1396 }
1397 
1398 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1399  uint64_t Address,
1400  const MCDisassembler *Decoder) {
1401  if (RegNo > 7)
1402  return MCDisassembler::Fail;
1403  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1404 }
1405 
1406 static const uint16_t GPRPairDecoderTable[] = {
1407  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1408  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1409 };
1410 
1411 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1412  uint64_t Address,
1413  const MCDisassembler *Decoder) {
1415 
1416  // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1417  // rather than SoftFail as there is no GPRPair table entry for index 7.
1418  if (RegNo > 13)
1419  return MCDisassembler::Fail;
1420 
1421  if (RegNo & 1)
1423 
1424  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1425  Inst.addOperand(MCOperand::createReg(RegisterPair));
1426  return S;
1427 }
1428 
1429 static DecodeStatus
1430 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1431  const MCDisassembler *Decoder) {
1432  if (RegNo > 13)
1433  return MCDisassembler::Fail;
1434 
1435  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1436  Inst.addOperand(MCOperand::createReg(RegisterPair));
1437 
1438  if ((RegNo & 1) || RegNo > 10)
1439  return MCDisassembler::SoftFail;
1440  return MCDisassembler::Success;
1441 }
1442 
1443 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1444  uint64_t Address,
1445  const MCDisassembler *Decoder) {
1446  if (RegNo != 13)
1447  return MCDisassembler::Fail;
1448 
1449  unsigned Register = GPRDecoderTable[RegNo];
1451  return MCDisassembler::Success;
1452 }
1453 
1454 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1455  uint64_t Address,
1456  const MCDisassembler *Decoder) {
1457  unsigned Register = 0;
1458  switch (RegNo) {
1459  case 0:
1460  Register = ARM::R0;
1461  break;
1462  case 1:
1463  Register = ARM::R1;
1464  break;
1465  case 2:
1466  Register = ARM::R2;
1467  break;
1468  case 3:
1469  Register = ARM::R3;
1470  break;
1471  case 9:
1472  Register = ARM::R9;
1473  break;
1474  case 12:
1475  Register = ARM::R12;
1476  break;
1477  default:
1478  return MCDisassembler::Fail;
1479  }
1480 
1482  return MCDisassembler::Success;
1483 }
1484 
1485 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1486  uint64_t Address,
1487  const MCDisassembler *Decoder) {
1489 
1490  const FeatureBitset &featureBits =
1491  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1492 
1493  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1495 
1496  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1497  return S;
1498 }
1499 
1500 static const uint16_t SPRDecoderTable[] = {
1501  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1502  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1503  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1504  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1505  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1506  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1507  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1508  ARM::S28, ARM::S29, ARM::S30, ARM::S31
1509 };
1510 
1511 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1512  uint64_t Address,
1513  const MCDisassembler *Decoder) {
1514  if (RegNo > 31)
1515  return MCDisassembler::Fail;
1516 
1517  unsigned Register = SPRDecoderTable[RegNo];
1519  return MCDisassembler::Success;
1520 }
1521 
1522 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1523  uint64_t Address,
1524  const MCDisassembler *Decoder) {
1525  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1526 }
1527 
1528 static const uint16_t DPRDecoderTable[] = {
1529  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1530  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1531  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1532  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1533  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1534  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1535  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1536  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1537 };
1538 
1539 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1540  uint64_t Address,
1541  const MCDisassembler *Decoder) {
1542  const FeatureBitset &featureBits =
1543  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1544 
1545  bool hasD32 = featureBits[ARM::FeatureD32];
1546 
1547  if (RegNo > 31 || (!hasD32 && RegNo > 15))
1548  return MCDisassembler::Fail;
1549 
1550  unsigned Register = DPRDecoderTable[RegNo];
1552  return MCDisassembler::Success;
1553 }
1554 
1555 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1556  uint64_t Address,
1557  const MCDisassembler *Decoder) {
1558  if (RegNo > 7)
1559  return MCDisassembler::Fail;
1560  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1561 }
1562 
1563 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1564  uint64_t Address,
1565  const MCDisassembler *Decoder) {
1566  if (RegNo > 15)
1567  return MCDisassembler::Fail;
1568  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1569 }
1570 
1571 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1572  uint64_t Address,
1573  const MCDisassembler *Decoder) {
1574  if (RegNo > 15)
1575  return MCDisassembler::Fail;
1576  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1577 }
1578 
1579 static const uint16_t QPRDecoderTable[] = {
1580  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1581  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1582  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1583  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1584 };
1585 
1586 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1587  uint64_t Address,
1588  const MCDisassembler *Decoder) {
1589  if (RegNo > 31 || (RegNo & 1) != 0)
1590  return MCDisassembler::Fail;
1591  RegNo >>= 1;
1592 
1593  unsigned Register = QPRDecoderTable[RegNo];
1595  return MCDisassembler::Success;
1596 }
1597 
1598 static const uint16_t DPairDecoderTable[] = {
1599  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1600  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1601  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1602  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1603  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1604  ARM::Q15
1605 };
1606 
1607 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1608  uint64_t Address,
1609  const MCDisassembler *Decoder) {
1610  if (RegNo > 30)
1611  return MCDisassembler::Fail;
1612 
1613  unsigned Register = DPairDecoderTable[RegNo];
1615  return MCDisassembler::Success;
1616 }
1617 
1619  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1620  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1621  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1622  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1623  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1624  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1625  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1626  ARM::D28_D30, ARM::D29_D31
1627 };
1628 
1629 static DecodeStatus
1630 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1631  const MCDisassembler *Decoder) {
1632  if (RegNo > 29)
1633  return MCDisassembler::Fail;
1634 
1635  unsigned Register = DPairSpacedDecoderTable[RegNo];
1637  return MCDisassembler::Success;
1638 }
1639 
1640 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1641  uint64_t Address,
1642  const MCDisassembler *Decoder) {
1644  if (Val == 0xF) return MCDisassembler::Fail;
1645  // AL predicate is not allowed on Thumb1 branches.
1646  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1647  return MCDisassembler::Fail;
1648  if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1650  Inst.addOperand(MCOperand::createImm(Val));
1651  if (Val == ARMCC::AL) {
1653  } else
1654  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1655  return S;
1656 }
1657 
1658 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1659  uint64_t Address,
1660  const MCDisassembler *Decoder) {
1661  if (Val)
1662  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1663  else
1665  return MCDisassembler::Success;
1666 }
1667 
1668 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1669  uint64_t Address,
1670  const MCDisassembler *Decoder) {
1672 
1673  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1674  unsigned type = fieldFromInstruction(Val, 5, 2);
1675  unsigned imm = fieldFromInstruction(Val, 7, 5);
1676 
1677  // Register-immediate
1678  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1679  return MCDisassembler::Fail;
1680 
1682  switch (type) {
1683  case 0:
1684  Shift = ARM_AM::lsl;
1685  break;
1686  case 1:
1687  Shift = ARM_AM::lsr;
1688  break;
1689  case 2:
1690  Shift = ARM_AM::asr;
1691  break;
1692  case 3:
1693  Shift = ARM_AM::ror;
1694  break;
1695  }
1696 
1697  if (Shift == ARM_AM::ror && imm == 0)
1698  Shift = ARM_AM::rrx;
1699 
1700  unsigned Op = Shift | (imm << 3);
1702 
1703  return S;
1704 }
1705 
1706 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1707  uint64_t Address,
1708  const MCDisassembler *Decoder) {
1710 
1711  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1712  unsigned type = fieldFromInstruction(Val, 5, 2);
1713  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1714 
1715  // Register-register
1716  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1717  return MCDisassembler::Fail;
1718  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1719  return MCDisassembler::Fail;
1720 
1722  switch (type) {
1723  case 0:
1724  Shift = ARM_AM::lsl;
1725  break;
1726  case 1:
1727  Shift = ARM_AM::lsr;
1728  break;
1729  case 2:
1730  Shift = ARM_AM::asr;
1731  break;
1732  case 3:
1733  Shift = ARM_AM::ror;
1734  break;
1735  }
1736 
1738 
1739  return S;
1740 }
1741 
1742 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1743  uint64_t Address,
1744  const MCDisassembler *Decoder) {
1746 
1747  bool NeedDisjointWriteback = false;
1748  unsigned WritebackReg = 0;
1749  bool CLRM = false;
1750  switch (Inst.getOpcode()) {
1751  default:
1752  break;
1753  case ARM::LDMIA_UPD:
1754  case ARM::LDMDB_UPD:
1755  case ARM::LDMIB_UPD:
1756  case ARM::LDMDA_UPD:
1757  case ARM::t2LDMIA_UPD:
1758  case ARM::t2LDMDB_UPD:
1759  case ARM::t2STMIA_UPD:
1760  case ARM::t2STMDB_UPD:
1761  NeedDisjointWriteback = true;
1762  WritebackReg = Inst.getOperand(0).getReg();
1763  break;
1764  case ARM::t2CLRM:
1765  CLRM = true;
1766  break;
1767  }
1768 
1769  // Empty register lists are not allowed.
1770  if (Val == 0) return MCDisassembler::Fail;
1771  for (unsigned i = 0; i < 16; ++i) {
1772  if (Val & (1 << i)) {
1773  if (CLRM) {
1774  if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1775  return MCDisassembler::Fail;
1776  }
1777  } else {
1778  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1779  return MCDisassembler::Fail;
1780  // Writeback not allowed if Rn is in the target list.
1781  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1783  }
1784  }
1785  }
1786 
1787  return S;
1788 }
1789 
1790 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1791  uint64_t Address,
1792  const MCDisassembler *Decoder) {
1794 
1795  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1796  unsigned regs = fieldFromInstruction(Val, 0, 8);
1797 
1798  // In case of unpredictable encoding, tweak the operands.
1799  if (regs == 0 || (Vd + regs) > 32) {
1800  regs = Vd + regs > 32 ? 32 - Vd : regs;
1801  regs = std::max( 1u, regs);
1803  }
1804 
1805  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1806  return MCDisassembler::Fail;
1807  for (unsigned i = 0; i < (regs - 1); ++i) {
1808  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1809  return MCDisassembler::Fail;
1810  }
1811 
1812  return S;
1813 }
1814 
1815 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1816  uint64_t Address,
1817  const MCDisassembler *Decoder) {
1819 
1820  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1821  unsigned regs = fieldFromInstruction(Val, 1, 7);
1822 
1823  // In case of unpredictable encoding, tweak the operands.
1824  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1825  regs = Vd + regs > 32 ? 32 - Vd : regs;
1826  regs = std::max( 1u, regs);
1827  regs = std::min(16u, regs);
1829  }
1830 
1831  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1832  return MCDisassembler::Fail;
1833  for (unsigned i = 0; i < (regs - 1); ++i) {
1834  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1835  return MCDisassembler::Fail;
1836  }
1837 
1838  return S;
1839 }
1840 
1841 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1842  uint64_t Address,
1843  const MCDisassembler *Decoder) {
1844  // This operand encodes a mask of contiguous zeros between a specified MSB
1845  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1846  // the mask of all bits LSB-and-lower, and then xor them to create
1847  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1848  // create the final mask.
1849  unsigned msb = fieldFromInstruction(Val, 5, 5);
1850  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1851 
1853  if (lsb > msb) {
1855  // The check above will cause the warning for the "potentially undefined
1856  // instruction encoding" but we can't build a bad MCOperand value here
1857  // with a lsb > msb or else printing the MCInst will cause a crash.
1858  lsb = msb;
1859  }
1860 
1861  uint32_t msb_mask = 0xFFFFFFFF;
1862  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1863  uint32_t lsb_mask = (1U << lsb) - 1;
1864 
1865  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1866  return S;
1867 }
1868 
1870  uint64_t Address,
1871  const MCDisassembler *Decoder) {
1873 
1874  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1875  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1876  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1877  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1878  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1879  unsigned U = fieldFromInstruction(Insn, 23, 1);
1880  const FeatureBitset &featureBits =
1881  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1882 
1883  switch (Inst.getOpcode()) {
1884  case ARM::LDC_OFFSET:
1885  case ARM::LDC_PRE:
1886  case ARM::LDC_POST:
1887  case ARM::LDC_OPTION:
1888  case ARM::LDCL_OFFSET:
1889  case ARM::LDCL_PRE:
1890  case ARM::LDCL_POST:
1891  case ARM::LDCL_OPTION:
1892  case ARM::STC_OFFSET:
1893  case ARM::STC_PRE:
1894  case ARM::STC_POST:
1895  case ARM::STC_OPTION:
1896  case ARM::STCL_OFFSET:
1897  case ARM::STCL_PRE:
1898  case ARM::STCL_POST:
1899  case ARM::STCL_OPTION:
1900  case ARM::t2LDC_OFFSET:
1901  case ARM::t2LDC_PRE:
1902  case ARM::t2LDC_POST:
1903  case ARM::t2LDC_OPTION:
1904  case ARM::t2LDCL_OFFSET:
1905  case ARM::t2LDCL_PRE:
1906  case ARM::t2LDCL_POST:
1907  case ARM::t2LDCL_OPTION:
1908  case ARM::t2STC_OFFSET:
1909  case ARM::t2STC_PRE:
1910  case ARM::t2STC_POST:
1911  case ARM::t2STC_OPTION:
1912  case ARM::t2STCL_OFFSET:
1913  case ARM::t2STCL_PRE:
1914  case ARM::t2STCL_POST:
1915  case ARM::t2STCL_OPTION:
1916  case ARM::t2LDC2_OFFSET:
1917  case ARM::t2LDC2L_OFFSET:
1918  case ARM::t2LDC2_PRE:
1919  case ARM::t2LDC2L_PRE:
1920  case ARM::t2STC2_OFFSET:
1921  case ARM::t2STC2L_OFFSET:
1922  case ARM::t2STC2_PRE:
1923  case ARM::t2STC2L_PRE:
1924  case ARM::LDC2_OFFSET:
1925  case ARM::LDC2L_OFFSET:
1926  case ARM::LDC2_PRE:
1927  case ARM::LDC2L_PRE:
1928  case ARM::STC2_OFFSET:
1929  case ARM::STC2L_OFFSET:
1930  case ARM::STC2_PRE:
1931  case ARM::STC2L_PRE:
1932  case ARM::t2LDC2_OPTION:
1933  case ARM::t2STC2_OPTION:
1934  case ARM::t2LDC2_POST:
1935  case ARM::t2LDC2L_POST:
1936  case ARM::t2STC2_POST:
1937  case ARM::t2STC2L_POST:
1938  case ARM::LDC2_POST:
1939  case ARM::LDC2L_POST:
1940  case ARM::STC2_POST:
1941  case ARM::STC2L_POST:
1942  if (coproc == 0xA || coproc == 0xB ||
1943  (featureBits[ARM::HasV8_1MMainlineOps] &&
1944  (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1945  coproc == 0xE || coproc == 0xF)))
1946  return MCDisassembler::Fail;
1947  break;
1948  default:
1949  break;
1950  }
1951 
1952  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1953  return MCDisassembler::Fail;
1954 
1955  Inst.addOperand(MCOperand::createImm(coproc));
1956  Inst.addOperand(MCOperand::createImm(CRd));
1957  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1958  return MCDisassembler::Fail;
1959 
1960  switch (Inst.getOpcode()) {
1961  case ARM::t2LDC2_OFFSET:
1962  case ARM::t2LDC2L_OFFSET:
1963  case ARM::t2LDC2_PRE:
1964  case ARM::t2LDC2L_PRE:
1965  case ARM::t2STC2_OFFSET:
1966  case ARM::t2STC2L_OFFSET:
1967  case ARM::t2STC2_PRE:
1968  case ARM::t2STC2L_PRE:
1969  case ARM::LDC2_OFFSET:
1970  case ARM::LDC2L_OFFSET:
1971  case ARM::LDC2_PRE:
1972  case ARM::LDC2L_PRE:
1973  case ARM::STC2_OFFSET:
1974  case ARM::STC2L_OFFSET:
1975  case ARM::STC2_PRE:
1976  case ARM::STC2L_PRE:
1977  case ARM::t2LDC_OFFSET:
1978  case ARM::t2LDCL_OFFSET:
1979  case ARM::t2LDC_PRE:
1980  case ARM::t2LDCL_PRE:
1981  case ARM::t2STC_OFFSET:
1982  case ARM::t2STCL_OFFSET:
1983  case ARM::t2STC_PRE:
1984  case ARM::t2STCL_PRE:
1985  case ARM::LDC_OFFSET:
1986  case ARM::LDCL_OFFSET:
1987  case ARM::LDC_PRE:
1988  case ARM::LDCL_PRE:
1989  case ARM::STC_OFFSET:
1990  case ARM::STCL_OFFSET:
1991  case ARM::STC_PRE:
1992  case ARM::STCL_PRE:
1993  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1994  Inst.addOperand(MCOperand::createImm(imm));
1995  break;
1996  case ARM::t2LDC2_POST:
1997  case ARM::t2LDC2L_POST:
1998  case ARM::t2STC2_POST:
1999  case ARM::t2STC2L_POST:
2000  case ARM::LDC2_POST:
2001  case ARM::LDC2L_POST:
2002  case ARM::STC2_POST:
2003  case ARM::STC2L_POST:
2004  case ARM::t2LDC_POST:
2005  case ARM::t2LDCL_POST:
2006  case ARM::t2STC_POST:
2007  case ARM::t2STCL_POST:
2008  case ARM::LDC_POST:
2009  case ARM::LDCL_POST:
2010  case ARM::STC_POST:
2011  case ARM::STCL_POST:
2012  imm |= U << 8;
2013  [[fallthrough]];
2014  default:
2015  // The 'option' variant doesn't encode 'U' in the immediate since
2016  // the immediate is unsigned [0,255].
2017  Inst.addOperand(MCOperand::createImm(imm));
2018  break;
2019  }
2020 
2021  switch (Inst.getOpcode()) {
2022  case ARM::LDC_OFFSET:
2023  case ARM::LDC_PRE:
2024  case ARM::LDC_POST:
2025  case ARM::LDC_OPTION:
2026  case ARM::LDCL_OFFSET:
2027  case ARM::LDCL_PRE:
2028  case ARM::LDCL_POST:
2029  case ARM::LDCL_OPTION:
2030  case ARM::STC_OFFSET:
2031  case ARM::STC_PRE:
2032  case ARM::STC_POST:
2033  case ARM::STC_OPTION:
2034  case ARM::STCL_OFFSET:
2035  case ARM::STCL_PRE:
2036  case ARM::STCL_POST:
2037  case ARM::STCL_OPTION:
2038  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2039  return MCDisassembler::Fail;
2040  break;
2041  default:
2042  break;
2043  }
2044 
2045  return S;
2046 }
2047 
2048 static DecodeStatus
2050  const MCDisassembler *Decoder) {
2052 
2053  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2054  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2055  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2056  unsigned imm = fieldFromInstruction(Insn, 0, 12);
2057  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2058  unsigned reg = fieldFromInstruction(Insn, 25, 1);
2059  unsigned P = fieldFromInstruction(Insn, 24, 1);
2060  unsigned W = fieldFromInstruction(Insn, 21, 1);
2061 
2062  // On stores, the writeback operand precedes Rt.
2063  switch (Inst.getOpcode()) {
2064  case ARM::STR_POST_IMM:
2065  case ARM::STR_POST_REG:
2066  case ARM::STRB_POST_IMM:
2067  case ARM::STRB_POST_REG:
2068  case ARM::STRT_POST_REG:
2069  case ARM::STRT_POST_IMM:
2070  case ARM::STRBT_POST_REG:
2071  case ARM::STRBT_POST_IMM:
2072  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2073  return MCDisassembler::Fail;
2074  break;
2075  default:
2076  break;
2077  }
2078 
2079  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2080  return MCDisassembler::Fail;
2081 
2082  // On loads, the writeback operand comes after Rt.
2083  switch (Inst.getOpcode()) {
2084  case ARM::LDR_POST_IMM:
2085  case ARM::LDR_POST_REG:
2086  case ARM::LDRB_POST_IMM:
2087  case ARM::LDRB_POST_REG:
2088  case ARM::LDRBT_POST_REG:
2089  case ARM::LDRBT_POST_IMM:
2090  case ARM::LDRT_POST_REG:
2091  case ARM::LDRT_POST_IMM:
2092  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2093  return MCDisassembler::Fail;
2094  break;
2095  default:
2096  break;
2097  }
2098 
2099  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2100  return MCDisassembler::Fail;
2101 
2103  if (!fieldFromInstruction(Insn, 23, 1))
2104  Op = ARM_AM::sub;
2105 
2106  bool writeback = (P == 0) || (W == 1);
2107  unsigned idx_mode = 0;
2108  if (P && writeback)
2109  idx_mode = ARMII::IndexModePre;
2110  else if (!P && writeback)
2111  idx_mode = ARMII::IndexModePost;
2112 
2113  if (writeback && (Rn == 15 || Rn == Rt))
2114  S = MCDisassembler::SoftFail; // UNPREDICTABLE
2115 
2116  if (reg) {
2117  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2118  return MCDisassembler::Fail;
2120  switch( fieldFromInstruction(Insn, 5, 2)) {
2121  case 0:
2122  Opc = ARM_AM::lsl;
2123  break;
2124  case 1:
2125  Opc = ARM_AM::lsr;
2126  break;
2127  case 2:
2128  Opc = ARM_AM::asr;
2129  break;
2130  case 3:
2131  Opc = ARM_AM::ror;
2132  break;
2133  default:
2134  return MCDisassembler::Fail;
2135  }
2136  unsigned amt = fieldFromInstruction(Insn, 7, 5);
2137  if (Opc == ARM_AM::ror && amt == 0)
2138  Opc = ARM_AM::rrx;
2139  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
2140 
2141  Inst.addOperand(MCOperand::createImm(imm));
2142  } else {
2144  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
2146  }
2147 
2148  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2149  return MCDisassembler::Fail;
2150 
2151  return S;
2152 }
2153 
2154 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
2155  uint64_t Address,
2156  const MCDisassembler *Decoder) {
2158 
2159  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2160  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2161  unsigned type = fieldFromInstruction(Val, 5, 2);
2162  unsigned imm = fieldFromInstruction(Val, 7, 5);
2163  unsigned U = fieldFromInstruction(Val, 12, 1);
2164 
2166  switch (type) {
2167  case 0:
2168  ShOp = ARM_AM::lsl;
2169  break;
2170  case 1:
2171  ShOp = ARM_AM::lsr;
2172  break;
2173  case 2:
2174  ShOp = ARM_AM::asr;
2175  break;
2176  case 3:
2177  ShOp = ARM_AM::ror;
2178  break;
2179  }
2180 
2181  if (ShOp == ARM_AM::ror && imm == 0)
2182  ShOp = ARM_AM::rrx;
2183 
2184  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2185  return MCDisassembler::Fail;
2186  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2187  return MCDisassembler::Fail;
2188  unsigned shift;
2189  if (U)
2190  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
2191  else
2192  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
2194 
2195  return S;
2196 }
2197 
2199  uint64_t Address,
2200  const MCDisassembler *Decoder) {
2201  if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
2202  return MCDisassembler::Fail;
2203 
2204  // The "csync" operand is not encoded into the "tsb" instruction (as this is
2205  // the only available operand), but LLVM expects the instruction to have one
2206  // operand, so we need to add the csync when decoding.
2208  return MCDisassembler::Success;
2209 }
2210 
2212  uint64_t Address,
2213  const MCDisassembler *Decoder) {
2215 
2216  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2217  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2218  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2219  unsigned type = fieldFromInstruction(Insn, 22, 1);
2220  unsigned imm = fieldFromInstruction(Insn, 8, 4);
2221  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2222  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2223  unsigned W = fieldFromInstruction(Insn, 21, 1);
2224  unsigned P = fieldFromInstruction(Insn, 24, 1);
2225  unsigned Rt2 = Rt + 1;
2226 
2227  bool writeback = (W == 1) | (P == 0);
2228 
2229  // For {LD,ST}RD, Rt must be even, else undefined.
2230  switch (Inst.getOpcode()) {
2231  case ARM::STRD:
2232  case ARM::STRD_PRE:
2233  case ARM::STRD_POST:
2234  case ARM::LDRD:
2235  case ARM::LDRD_PRE:
2236  case ARM::LDRD_POST:
2237  if (Rt & 0x1) S = MCDisassembler::SoftFail;
2238  break;
2239  default:
2240  break;
2241  }
2242  switch (Inst.getOpcode()) {
2243  case ARM::STRD:
2244  case ARM::STRD_PRE:
2245  case ARM::STRD_POST:
2246  if (P == 0 && W == 1)
2248 
2249  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2251  if (type && Rm == 15)
2253  if (Rt2 == 15)
2255  if (!type && fieldFromInstruction(Insn, 8, 4))
2257  break;
2258  case ARM::STRH:
2259  case ARM::STRH_PRE:
2260  case ARM::STRH_POST:
2261  if (Rt == 15)
2263  if (writeback && (Rn == 15 || Rn == Rt))
2265  if (!type && Rm == 15)
2267  break;
2268  case ARM::LDRD:
2269  case ARM::LDRD_PRE:
2270  case ARM::LDRD_POST:
2271  if (type && Rn == 15) {
2272  if (Rt2 == 15)
2274  break;
2275  }
2276  if (P == 0 && W == 1)
2278  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2280  if (!type && writeback && Rn == 15)
2282  if (writeback && (Rn == Rt || Rn == Rt2))
2284  break;
2285  case ARM::LDRH:
2286  case ARM::LDRH_PRE:
2287  case ARM::LDRH_POST:
2288  if (type && Rn == 15) {
2289  if (Rt == 15)
2291  break;
2292  }
2293  if (Rt == 15)
2295  if (!type && Rm == 15)
2297  if (!type && writeback && (Rn == 15 || Rn == Rt))
2299  break;
2300  case ARM::LDRSH:
2301  case ARM::LDRSH_PRE:
2302  case ARM::LDRSH_POST:
2303  case ARM::LDRSB:
2304  case ARM::LDRSB_PRE:
2305  case ARM::LDRSB_POST:
2306  if (type && Rn == 15) {
2307  if (Rt == 15)
2309  break;
2310  }
2311  if (type && (Rt == 15 || (writeback && Rn == Rt)))
2313  if (!type && (Rt == 15 || Rm == 15))
2315  if (!type && writeback && (Rn == 15 || Rn == Rt))
2317  break;
2318  default:
2319  break;
2320  }
2321 
2322  if (writeback) { // Writeback
2323  if (P)
2324  U |= ARMII::IndexModePre << 9;
2325  else
2326  U |= ARMII::IndexModePost << 9;
2327 
2328  // On stores, the writeback operand precedes Rt.
2329  switch (Inst.getOpcode()) {
2330  case ARM::STRD:
2331  case ARM::STRD_PRE:
2332  case ARM::STRD_POST:
2333  case ARM::STRH:
2334  case ARM::STRH_PRE:
2335  case ARM::STRH_POST:
2336  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2337  return MCDisassembler::Fail;
2338  break;
2339  default:
2340  break;
2341  }
2342  }
2343 
2344  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2345  return MCDisassembler::Fail;
2346  switch (Inst.getOpcode()) {
2347  case ARM::STRD:
2348  case ARM::STRD_PRE:
2349  case ARM::STRD_POST:
2350  case ARM::LDRD:
2351  case ARM::LDRD_PRE:
2352  case ARM::LDRD_POST:
2353  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2354  return MCDisassembler::Fail;
2355  break;
2356  default:
2357  break;
2358  }
2359 
2360  if (writeback) {
2361  // On loads, the writeback operand comes after Rt.
2362  switch (Inst.getOpcode()) {
2363  case ARM::LDRD:
2364  case ARM::LDRD_PRE:
2365  case ARM::LDRD_POST:
2366  case ARM::LDRH:
2367  case ARM::LDRH_PRE:
2368  case ARM::LDRH_POST:
2369  case ARM::LDRSH:
2370  case ARM::LDRSH_PRE:
2371  case ARM::LDRSH_POST:
2372  case ARM::LDRSB:
2373  case ARM::LDRSB_PRE:
2374  case ARM::LDRSB_POST:
2375  case ARM::LDRHTr:
2376  case ARM::LDRSBTr:
2377  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2378  return MCDisassembler::Fail;
2379  break;
2380  default:
2381  break;
2382  }
2383  }
2384 
2385  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2386  return MCDisassembler::Fail;
2387 
2388  if (type) {
2390  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2391  } else {
2392  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2393  return MCDisassembler::Fail;
2395  }
2396 
2397  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2398  return MCDisassembler::Fail;
2399 
2400  return S;
2401 }
2402 
2404  uint64_t Address,
2405  const MCDisassembler *Decoder) {
2407 
2408  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2409  unsigned mode = fieldFromInstruction(Insn, 23, 2);
2410 
2411  switch (mode) {
2412  case 0:
2413  mode = ARM_AM::da;
2414  break;
2415  case 1:
2416  mode = ARM_AM::ia;
2417  break;
2418  case 2:
2419  mode = ARM_AM::db;
2420  break;
2421  case 3:
2422  mode = ARM_AM::ib;
2423  break;
2424  }
2425 
2427  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2428  return MCDisassembler::Fail;
2429 
2430  return S;
2431 }
2432 
2434  uint64_t Address,
2435  const MCDisassembler *Decoder) {
2437 
2438  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2439  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2440  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2441  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2442 
2443  if (pred == 0xF)
2444  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2445 
2446  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2447  return MCDisassembler::Fail;
2448  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2449  return MCDisassembler::Fail;
2450  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2451  return MCDisassembler::Fail;
2452  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2453  return MCDisassembler::Fail;
2454  return S;
2455 }
2456 
2457 static DecodeStatus
2459  uint64_t Address,
2460  const MCDisassembler *Decoder) {
2462 
2463  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2464  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2465  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2466 
2467  if (pred == 0xF) {
2468  // Ambiguous with RFE and SRS
2469  switch (Inst.getOpcode()) {
2470  case ARM::LDMDA:
2471  Inst.setOpcode(ARM::RFEDA);
2472  break;
2473  case ARM::LDMDA_UPD:
2474  Inst.setOpcode(ARM::RFEDA_UPD);
2475  break;
2476  case ARM::LDMDB:
2477  Inst.setOpcode(ARM::RFEDB);
2478  break;
2479  case ARM::LDMDB_UPD:
2480  Inst.setOpcode(ARM::RFEDB_UPD);
2481  break;
2482  case ARM::LDMIA:
2483  Inst.setOpcode(ARM::RFEIA);
2484  break;
2485  case ARM::LDMIA_UPD:
2486  Inst.setOpcode(ARM::RFEIA_UPD);
2487  break;
2488  case ARM::LDMIB:
2489  Inst.setOpcode(ARM::RFEIB);
2490  break;
2491  case ARM::LDMIB_UPD:
2492  Inst.setOpcode(ARM::RFEIB_UPD);
2493  break;
2494  case ARM::STMDA:
2495  Inst.setOpcode(ARM::SRSDA);
2496  break;
2497  case ARM::STMDA_UPD:
2498  Inst.setOpcode(ARM::SRSDA_UPD);
2499  break;
2500  case ARM::STMDB:
2501  Inst.setOpcode(ARM::SRSDB);
2502  break;
2503  case ARM::STMDB_UPD:
2504  Inst.setOpcode(ARM::SRSDB_UPD);
2505  break;
2506  case ARM::STMIA:
2507  Inst.setOpcode(ARM::SRSIA);
2508  break;
2509  case ARM::STMIA_UPD:
2510  Inst.setOpcode(ARM::SRSIA_UPD);
2511  break;
2512  case ARM::STMIB:
2513  Inst.setOpcode(ARM::SRSIB);
2514  break;
2515  case ARM::STMIB_UPD:
2516  Inst.setOpcode(ARM::SRSIB_UPD);
2517  break;
2518  default:
2519  return MCDisassembler::Fail;
2520  }
2521 
2522  // For stores (which become SRS's, the only operand is the mode.
2523  if (fieldFromInstruction(Insn, 20, 1) == 0) {
2524  // Check SRS encoding constraints
2525  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2526  fieldFromInstruction(Insn, 20, 1) == 0))
2527  return MCDisassembler::Fail;
2528 
2529  Inst.addOperand(
2530  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2531  return S;
2532  }
2533 
2534  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2535  }
2536 
2537  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2538  return MCDisassembler::Fail;
2539  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2540  return MCDisassembler::Fail; // Tied
2541  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2542  return MCDisassembler::Fail;
2543  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2544  return MCDisassembler::Fail;
2545 
2546  return S;
2547 }
2548 
2549 // Check for UNPREDICTABLE predicated ESB instruction
2551  uint64_t Address,
2552  const MCDisassembler *Decoder) {
2553  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2554  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2555  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2556  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2557 
2559 
2560  Inst.addOperand(MCOperand::createImm(imm8));
2561 
2562  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2563  return MCDisassembler::Fail;
2564 
2565  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2566  // so all predicates should be allowed.
2567  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2569 
2570  return S;
2571 }
2572 
2574  uint64_t Address,
2575  const MCDisassembler *Decoder) {
2576  unsigned imod = fieldFromInstruction(Insn, 18, 2);
2577  unsigned M = fieldFromInstruction(Insn, 17, 1);
2578  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2579  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2580 
2582 
2583  // This decoder is called from multiple location that do not check
2584  // the full encoding is valid before they do.
2585  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2586  fieldFromInstruction(Insn, 16, 1) != 0 ||
2587  fieldFromInstruction(Insn, 20, 8) != 0x10)
2588  return MCDisassembler::Fail;
2589 
2590  // imod == '01' --> UNPREDICTABLE
2591  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2592  // return failure here. The '01' imod value is unprintable, so there's
2593  // nothing useful we could do even if we returned UNPREDICTABLE.
2594 
2595  if (imod == 1) return MCDisassembler::Fail;
2596 
2597  if (imod && M) {
2598  Inst.setOpcode(ARM::CPS3p);
2599  Inst.addOperand(MCOperand::createImm(imod));
2600  Inst.addOperand(MCOperand::createImm(iflags));
2602  } else if (imod && !M) {
2603  Inst.setOpcode(ARM::CPS2p);
2604  Inst.addOperand(MCOperand::createImm(imod));
2605  Inst.addOperand(MCOperand::createImm(iflags));
2607  } else if (!imod && M) {
2608  Inst.setOpcode(ARM::CPS1p);
2610  if (iflags) S = MCDisassembler::SoftFail;
2611  } else {
2612  // imod == '00' && M == '0' --> UNPREDICTABLE
2613  Inst.setOpcode(ARM::CPS1p);
2616  }
2617 
2618  return S;
2619 }
2620 
2622  uint64_t Address,
2623  const MCDisassembler *Decoder) {
2624  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2625  unsigned M = fieldFromInstruction(Insn, 8, 1);
2626  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2627  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2628 
2630 
2631  // imod == '01' --> UNPREDICTABLE
2632  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2633  // return failure here. The '01' imod value is unprintable, so there's
2634  // nothing useful we could do even if we returned UNPREDICTABLE.
2635 
2636  if (imod == 1) return MCDisassembler::Fail;
2637 
2638  if (imod && M) {
2639  Inst.setOpcode(ARM::t2CPS3p);
2640  Inst.addOperand(MCOperand::createImm(imod));
2641  Inst.addOperand(MCOperand::createImm(iflags));
2643  } else if (imod && !M) {
2644  Inst.setOpcode(ARM::t2CPS2p);
2645  Inst.addOperand(MCOperand::createImm(imod));
2646  Inst.addOperand(MCOperand::createImm(iflags));
2648  } else if (!imod && M) {
2649  Inst.setOpcode(ARM::t2CPS1p);
2651  if (iflags) S = MCDisassembler::SoftFail;
2652  } else {
2653  // imod == '00' && M == '0' --> this is a HINT instruction
2654  int imm = fieldFromInstruction(Insn, 0, 8);
2655  // HINT are defined only for immediate in [0..4]
2656  if(imm > 4) return MCDisassembler::Fail;
2657  Inst.setOpcode(ARM::t2HINT);
2658  Inst.addOperand(MCOperand::createImm(imm));
2659  }
2660 
2661  return S;
2662 }
2663 
2664 static DecodeStatus
2666  const MCDisassembler *Decoder) {
2667  unsigned imm = fieldFromInstruction(Insn, 0, 8);
2668 
2669  unsigned Opcode = ARM::t2HINT;
2670 
2671  if (imm == 0x0D) {
2672  Opcode = ARM::t2PACBTI;
2673  } else if (imm == 0x1D) {
2674  Opcode = ARM::t2PAC;
2675  } else if (imm == 0x2D) {
2676  Opcode = ARM::t2AUT;
2677  } else if (imm == 0x0F) {
2678  Opcode = ARM::t2BTI;
2679  }
2680 
2681  Inst.setOpcode(Opcode);
2682  if (Opcode == ARM::t2HINT) {
2683  Inst.addOperand(MCOperand::createImm(imm));
2684  }
2685 
2686  return MCDisassembler::Success;
2687 }
2688 
2690  uint64_t Address,
2691  const MCDisassembler *Decoder) {
2693 
2694  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2695  unsigned imm = 0;
2696 
2697  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2698  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2699  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2700  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2701 
2702  if (Inst.getOpcode() == ARM::t2MOVTi16)
2703  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2704  return MCDisassembler::Fail;
2705  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2706  return MCDisassembler::Fail;
2707 
2708  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2709  Inst.addOperand(MCOperand::createImm(imm));
2710 
2711  return S;
2712 }
2713 
2715  uint64_t Address,
2716  const MCDisassembler *Decoder) {
2718 
2719  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2720  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2721  unsigned imm = 0;
2722 
2723  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2724  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2725 
2726  if (Inst.getOpcode() == ARM::MOVTi16)
2727  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2728  return MCDisassembler::Fail;
2729 
2730  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2731  return MCDisassembler::Fail;
2732 
2733  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2734  Inst.addOperand(MCOperand::createImm(imm));
2735 
2736  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2737  return MCDisassembler::Fail;
2738 
2739  return S;
2740 }
2741 
2743  uint64_t Address,
2744  const MCDisassembler *Decoder) {
2746 
2747  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2748  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2749  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2750  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2751  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2752 
2753  if (pred == 0xF)
2754  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2755 
2756  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2757  return MCDisassembler::Fail;
2758  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2759  return MCDisassembler::Fail;
2760  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2761  return MCDisassembler::Fail;
2762  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2763  return MCDisassembler::Fail;
2764 
2765  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2766  return MCDisassembler::Fail;
2767 
2768  return S;
2769 }
2770 
2772  uint64_t Address,
2773  const MCDisassembler *Decoder) {
2775 
2776  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2777  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2778  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2779 
2780  if (Pred == 0xF)
2781  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2782 
2783  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2784  return MCDisassembler::Fail;
2785  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2786  return MCDisassembler::Fail;
2787  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2788  return MCDisassembler::Fail;
2789 
2790  return S;
2791 }
2792 
2794  uint64_t Address,
2795  const MCDisassembler *Decoder) {
2797 
2798  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2799 
2800  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2801  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2802 
2803  if (!FeatureBits[ARM::HasV8_1aOps] ||
2804  !FeatureBits[ARM::HasV8Ops])
2805  return MCDisassembler::Fail;
2806 
2807  // Decoder can be called from DecodeTST, which does not check the full
2808  // encoding is valid.
2809  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2810  fieldFromInstruction(Insn, 4,4) != 0)
2811  return MCDisassembler::Fail;
2812  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2813  fieldFromInstruction(Insn, 0,4) != 0)
2815 
2816  Inst.setOpcode(ARM::SETPAN);
2818 
2819  return S;
2820 }
2821 
2823  uint64_t Address,
2824  const MCDisassembler *Decoder) {
2826 
2827  unsigned add = fieldFromInstruction(Val, 12, 1);
2828  unsigned imm = fieldFromInstruction(Val, 0, 12);
2829  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2830 
2831  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2832  return MCDisassembler::Fail;
2833 
2834  if (!add) imm *= -1;
2835  if (imm == 0 && !add) imm = INT32_MIN;
2836  Inst.addOperand(MCOperand::createImm(imm));
2837  if (Rn == 15)
2838  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2839 
2840  return S;
2841 }
2842 
2843 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2844  uint64_t Address,
2845  const MCDisassembler *Decoder) {
2847 
2848  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2849  // U == 1 to add imm, 0 to subtract it.
2850  unsigned U = fieldFromInstruction(Val, 8, 1);
2851  unsigned imm = fieldFromInstruction(Val, 0, 8);
2852 
2853  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2854  return MCDisassembler::Fail;
2855 
2856  if (U)
2858  else
2860 
2861  return S;
2862 }
2863 
2865  uint64_t Address,
2866  const MCDisassembler *Decoder) {
2868 
2869  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2870  // U == 1 to add imm, 0 to subtract it.
2871  unsigned U = fieldFromInstruction(Val, 8, 1);
2872  unsigned imm = fieldFromInstruction(Val, 0, 8);
2873 
2874  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2875  return MCDisassembler::Fail;
2876 
2877  if (U)
2879  else
2881 
2882  return S;
2883 }
2884 
2885 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2886  uint64_t Address,
2887  const MCDisassembler *Decoder) {
2888  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2889 }
2890 
2892  uint64_t Address,
2893  const MCDisassembler *Decoder) {
2895 
2896  // Note the J1 and J2 values are from the encoded instruction. So here
2897  // change them to I1 and I2 values via as documented:
2898  // I1 = NOT(J1 EOR S);
2899  // I2 = NOT(J2 EOR S);
2900  // and build the imm32 with one trailing zero as documented:
2901  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2902  unsigned S = fieldFromInstruction(Insn, 26, 1);
2903  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2904  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2905  unsigned I1 = !(J1 ^ S);
2906  unsigned I2 = !(J2 ^ S);
2907  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2908  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2909  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2910  int imm32 = SignExtend32<25>(tmp << 1);
2911  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2912  true, 4, Inst, Decoder))
2913  Inst.addOperand(MCOperand::createImm(imm32));
2914 
2915  return Status;
2916 }
2917 
2919  uint64_t Address,
2920  const MCDisassembler *Decoder) {
2922 
2923  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2924  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2925 
2926  if (pred == 0xF) {
2927  Inst.setOpcode(ARM::BLXi);
2928  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2929  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2930  true, 4, Inst, Decoder))
2931  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2932  return S;
2933  }
2934 
2935  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2936  true, 4, Inst, Decoder))
2937  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2938 
2939  // We already have BL_pred for BL w/ predicate, no need to add addition
2940  // predicate opreands for BL
2941  if (Inst.getOpcode() != ARM::BL)
2942  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2943  return MCDisassembler::Fail;
2944 
2945  return S;
2946 }
2947 
2948 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2949  uint64_t Address,
2950  const MCDisassembler *Decoder) {
2952 
2953  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2954  unsigned align = fieldFromInstruction(Val, 4, 2);
2955 
2956  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2957  return MCDisassembler::Fail;
2958  if (!align)
2960  else
2962 
2963  return S;
2964 }
2965 
2967  uint64_t Address,
2968  const MCDisassembler *Decoder) {
2970 
2971  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2972  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2973  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2974  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2975  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2976  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2977 
2978  // First output register
2979  switch (Inst.getOpcode()) {
2980  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2981  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2982  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2983  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2984  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2985  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2986  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2987  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2988  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2989  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2990  return MCDisassembler::Fail;
2991  break;
2992  case ARM::VLD2b16:
2993  case ARM::VLD2b32:
2994  case ARM::VLD2b8:
2995  case ARM::VLD2b16wb_fixed:
2996  case ARM::VLD2b16wb_register:
2997  case ARM::VLD2b32wb_fixed:
2998  case ARM::VLD2b32wb_register:
2999  case ARM::VLD2b8wb_fixed:
3000  case ARM::VLD2b8wb_register:
3001  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3002  return MCDisassembler::Fail;
3003  break;
3004  default:
3005  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3006  return MCDisassembler::Fail;
3007  }
3008 
3009  // Second output register
3010  switch (Inst.getOpcode()) {
3011  case ARM::VLD3d8:
3012  case ARM::VLD3d16:
3013  case ARM::VLD3d32:
3014  case ARM::VLD3d8_UPD:
3015  case ARM::VLD3d16_UPD:
3016  case ARM::VLD3d32_UPD:
3017  case ARM::VLD4d8:
3018  case ARM::VLD4d16:
3019  case ARM::VLD4d32:
3020  case ARM::VLD4d8_UPD:
3021  case ARM::VLD4d16_UPD:
3022  case ARM::VLD4d32_UPD:
3023  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3024  return MCDisassembler::Fail;
3025  break;
3026  case ARM::VLD3q8:
3027  case ARM::VLD3q16:
3028  case ARM::VLD3q32:
3029  case ARM::VLD3q8_UPD:
3030  case ARM::VLD3q16_UPD:
3031  case ARM::VLD3q32_UPD:
3032  case ARM::VLD4q8:
3033  case ARM::VLD4q16:
3034  case ARM::VLD4q32:
3035  case ARM::VLD4q8_UPD:
3036  case ARM::VLD4q16_UPD:
3037  case ARM::VLD4q32_UPD:
3038  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3039  return MCDisassembler::Fail;
3040  break;
3041  default:
3042  break;
3043  }
3044 
3045  // Third output register
3046  switch(Inst.getOpcode()) {
3047  case ARM::VLD3d8:
3048  case ARM::VLD3d16:
3049  case ARM::VLD3d32:
3050  case ARM::VLD3d8_UPD:
3051  case ARM::VLD3d16_UPD:
3052  case ARM::VLD3d32_UPD:
3053  case ARM::VLD4d8:
3054  case ARM::VLD4d16:
3055  case ARM::VLD4d32:
3056  case ARM::VLD4d8_UPD:
3057  case ARM::VLD4d16_UPD:
3058  case ARM::VLD4d32_UPD:
3059  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3060  return MCDisassembler::Fail;
3061  break;
3062  case ARM::VLD3q8:
3063  case ARM::VLD3q16:
3064  case ARM::VLD3q32:
3065  case ARM::VLD3q8_UPD:
3066  case ARM::VLD3q16_UPD:
3067  case ARM::VLD3q32_UPD:
3068  case ARM::VLD4q8:
3069  case ARM::VLD4q16:
3070  case ARM::VLD4q32:
3071  case ARM::VLD4q8_UPD:
3072  case ARM::VLD4q16_UPD:
3073  case ARM::VLD4q32_UPD:
3074  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3075  return MCDisassembler::Fail;
3076  break;
3077  default:
3078  break;
3079  }
3080 
3081  // Fourth output register
3082  switch (Inst.getOpcode()) {
3083  case ARM::VLD4d8:
3084  case ARM::VLD4d16:
3085  case ARM::VLD4d32:
3086  case ARM::VLD4d8_UPD:
3087  case ARM::VLD4d16_UPD:
3088  case ARM::VLD4d32_UPD:
3089  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3090  return MCDisassembler::Fail;
3091  break;
3092  case ARM::VLD4q8:
3093  case ARM::VLD4q16:
3094  case ARM::VLD4q32:
3095  case ARM::VLD4q8_UPD:
3096  case ARM::VLD4q16_UPD:
3097  case ARM::VLD4q32_UPD:
3098  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3099  return MCDisassembler::Fail;
3100  break;
3101  default:
3102  break;
3103  }
3104 
3105  // Writeback operand
3106  switch (Inst.getOpcode()) {
3107  case ARM::VLD1d8wb_fixed:
3108  case ARM::VLD1d16wb_fixed:
3109  case ARM::VLD1d32wb_fixed:
3110  case ARM::VLD1d64wb_fixed:
3111  case ARM::VLD1d8wb_register:
3112  case ARM::VLD1d16wb_register:
3113  case ARM::VLD1d32wb_register:
3114  case ARM::VLD1d64wb_register:
3115  case ARM::VLD1q8wb_fixed:
3116  case ARM::VLD1q16wb_fixed:
3117  case ARM::VLD1q32wb_fixed:
3118  case ARM::VLD1q64wb_fixed:
3119  case ARM::VLD1q8wb_register:
3120  case ARM::VLD1q16wb_register:
3121  case ARM::VLD1q32wb_register:
3122  case ARM::VLD1q64wb_register:
3123  case ARM::VLD1d8Twb_fixed:
3124  case ARM::VLD1d8Twb_register:
3125  case ARM::VLD1d16Twb_fixed:
3126  case ARM::VLD1d16Twb_register:
3127  case ARM::VLD1d32Twb_fixed:
3128  case ARM::VLD1d32Twb_register:
3129  case ARM::VLD1d64Twb_fixed:
3130  case ARM::VLD1d64Twb_register:
3131  case ARM::VLD1d8Qwb_fixed:
3132  case ARM::VLD1d8Qwb_register:
3133  case ARM::VLD1d16Qwb_fixed:
3134  case ARM::VLD1d16Qwb_register:
3135  case ARM::VLD1d32Qwb_fixed:
3136  case ARM::VLD1d32Qwb_register:
3137  case ARM::VLD1d64Qwb_fixed:
3138  case ARM::VLD1d64Qwb_register:
3139  case ARM::VLD2d8wb_fixed:
3140  case ARM::VLD2d16wb_fixed:
3141  case ARM::VLD2d32wb_fixed:
3142  case ARM::VLD2q8wb_fixed:
3143  case ARM::VLD2q16wb_fixed:
3144  case ARM::VLD2q32wb_fixed:
3145  case ARM::VLD2d8wb_register:
3146  case ARM::VLD2d16wb_register:
3147  case ARM::VLD2d32wb_register:
3148  case ARM::VLD2q8wb_register:
3149  case ARM::VLD2q16wb_register:
3150  case ARM::VLD2q32wb_register:
3151  case ARM::VLD2b8wb_fixed:
3152  case ARM::VLD2b16wb_fixed:
3153  case ARM::VLD2b32wb_fixed:
3154  case ARM::VLD2b8wb_register:
3155  case ARM::VLD2b16wb_register:
3156  case ARM::VLD2b32wb_register:
3158  break;
3159  case ARM::VLD3d8_UPD:
3160  case ARM::VLD3d16_UPD:
3161  case ARM::VLD3d32_UPD:
3162  case ARM::VLD3q8_UPD:
3163  case ARM::VLD3q16_UPD:
3164  case ARM::VLD3q32_UPD:
3165  case ARM::VLD4d8_UPD:
3166  case ARM::VLD4d16_UPD:
3167  case ARM::VLD4d32_UPD:
3168  case ARM::VLD4q8_UPD:
3169  case ARM::VLD4q16_UPD:
3170  case ARM::VLD4q32_UPD:
3171  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3172  return MCDisassembler::Fail;
3173  break;
3174  default:
3175  break;
3176  }
3177 
3178  // AddrMode6 Base (register+alignment)
3179  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3180  return MCDisassembler::Fail;
3181 
3182  // AddrMode6 Offset (register)
3183  switch (Inst.getOpcode()) {
3184  default:
3185  // The below have been updated to have explicit am6offset split
3186  // between fixed and register offset. For those instructions not
3187  // yet updated, we need to add an additional reg0 operand for the
3188  // fixed variant.
3189  //
3190  // The fixed offset encodes as Rm == 0xd, so we check for that.
3191  if (Rm == 0xd) {
3193  break;
3194  }
3195  // Fall through to handle the register offset variant.
3196  [[fallthrough]];
3197  case ARM::VLD1d8wb_fixed:
3198  case ARM::VLD1d16wb_fixed:
3199  case ARM::VLD1d32wb_fixed:
3200  case ARM::VLD1d64wb_fixed:
3201  case ARM::VLD1d8Twb_fixed:
3202  case ARM::VLD1d16Twb_fixed:
3203  case ARM::VLD1d32Twb_fixed:
3204  case ARM::VLD1d64Twb_fixed:
3205  case ARM::VLD1d8Qwb_fixed:
3206  case ARM::VLD1d16Qwb_fixed:
3207  case ARM::VLD1d32Qwb_fixed:
3208  case ARM::VLD1d64Qwb_fixed:
3209  case ARM::VLD1d8wb_register:
3210  case ARM::VLD1d16wb_register:
3211  case ARM::VLD1d32wb_register:
3212  case ARM::VLD1d64wb_register:
3213  case ARM::VLD1q8wb_fixed:
3214  case ARM::VLD1q16wb_fixed:
3215  case ARM::VLD1q32wb_fixed:
3216  case ARM::VLD1q64wb_fixed:
3217  case ARM::VLD1q8wb_register:
3218  case ARM::VLD1q16wb_register:
3219  case ARM::VLD1q32wb_register:
3220  case ARM::VLD1q64wb_register:
3221  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3222  // variant encodes Rm == 0xf. Anything else is a register offset post-
3223  // increment and we need to add the register operand to the instruction.
3224  if (Rm != 0xD && Rm != 0xF &&
3225  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3226  return MCDisassembler::Fail;
3227  break;
3228  case ARM::VLD2d8wb_fixed:
3229  case ARM::VLD2d16wb_fixed:
3230  case ARM::VLD2d32wb_fixed:
3231  case ARM::VLD2b8wb_fixed:
3232  case ARM::VLD2b16wb_fixed:
3233  case ARM::VLD2b32wb_fixed:
3234  case ARM::VLD2q8wb_fixed:
3235  case ARM::VLD2q16wb_fixed:
3236  case ARM::VLD2q32wb_fixed:
3237  break;
3238  }
3239 
3240  return S;
3241 }
3242 
3244  uint64_t Address,
3245  const MCDisassembler *Decoder) {
3246  unsigned type = fieldFromInstruction(Insn, 8, 4);
3247  unsigned align = fieldFromInstruction(Insn, 4, 2);
3248  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
3249  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
3250  if (type == 10 && align == 3) return MCDisassembler::Fail;
3251 
3252  unsigned load = fieldFromInstruction(Insn, 21, 1);
3253  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3254  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3255 }
3256 
3258  uint64_t Address,
3259  const MCDisassembler *Decoder) {
3260  unsigned size = fieldFromInstruction(Insn, 6, 2);
3261  if (size == 3) return MCDisassembler::Fail;
3262 
3263  unsigned type = fieldFromInstruction(Insn, 8, 4);
3264  unsigned align = fieldFromInstruction(Insn, 4, 2);
3265  if (type == 8 && align == 3) return MCDisassembler::Fail;
3266  if (type == 9 && align == 3) return MCDisassembler::Fail;
3267 
3268  unsigned load = fieldFromInstruction(Insn, 21, 1);
3269  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3270  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3271 }
3272 
3274  uint64_t Address,
3275  const MCDisassembler *Decoder) {
3276  unsigned size = fieldFromInstruction(Insn, 6, 2);
3277  if (size == 3) return MCDisassembler::Fail;
3278 
3279  unsigned align = fieldFromInstruction(Insn, 4, 2);
3280  if (align & 2) return MCDisassembler::Fail;
3281 
3282  unsigned load = fieldFromInstruction(Insn, 21, 1);
3283  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3284  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3285 }
3286 
3288  uint64_t Address,
3289  const MCDisassembler *Decoder) {
3290  unsigned size = fieldFromInstruction(Insn, 6, 2);
3291  if (size == 3) return MCDisassembler::Fail;
3292 
3293  unsigned load = fieldFromInstruction(Insn, 21, 1);
3294  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3295  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3296 }
3297 
3299  uint64_t Address,
3300  const MCDisassembler *Decoder) {
3302 
3303  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3304  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3305  unsigned wb = fieldFromInstruction(Insn, 16, 4);
3306  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3307  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3308  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3309 
3310  // Writeback Operand
3311  switch (Inst.getOpcode()) {
3312  case ARM::VST1d8wb_fixed:
3313  case ARM::VST1d16wb_fixed:
3314  case ARM::VST1d32wb_fixed:
3315  case ARM::VST1d64wb_fixed:
3316  case ARM::VST1d8wb_register:
3317  case ARM::VST1d16wb_register:
3318  case ARM::VST1d32wb_register:
3319  case ARM::VST1d64wb_register:
3320  case ARM::VST1q8wb_fixed:
3321  case ARM::VST1q16wb_fixed:
3322  case ARM::VST1q32wb_fixed:
3323  case ARM::VST1q64wb_fixed:
3324  case ARM::VST1q8wb_register:
3325  case ARM::VST1q16wb_register:
3326  case ARM::VST1q32wb_register:
3327  case ARM::VST1q64wb_register:
3328  case ARM::VST1d8Twb_fixed:
3329  case ARM::VST1d16Twb_fixed:
3330  case ARM::VST1d32Twb_fixed:
3331  case ARM::VST1d64Twb_fixed:
3332  case ARM::VST1d8Twb_register:
3333  case ARM::VST1d16Twb_register:
3334  case ARM::VST1d32Twb_register:
3335  case ARM::VST1d64Twb_register:
3336  case ARM::VST1d8Qwb_fixed:
3337  case ARM::VST1d16Qwb_fixed:
3338  case ARM::VST1d32Qwb_fixed:
3339  case ARM::VST1d64Qwb_fixed:
3340  case ARM::VST1d8Qwb_register:
3341  case ARM::VST1d16Qwb_register:
3342  case ARM::VST1d32Qwb_register:
3343  case ARM::VST1d64Qwb_register:
3344  case ARM::VST2d8wb_fixed:
3345  case ARM::VST2d16wb_fixed:
3346  case ARM::VST2d32wb_fixed:
3347  case ARM::VST2d8wb_register:
3348  case ARM::VST2d16wb_register:
3349  case ARM::VST2d32wb_register:
3350  case ARM::VST2q8wb_fixed:
3351  case ARM::VST2q16wb_fixed:
3352  case ARM::VST2q32wb_fixed:
3353  case ARM::VST2q8wb_register:
3354  case ARM::VST2q16wb_register:
3355  case ARM::VST2q32wb_register:
3356  case ARM::VST2b8wb_fixed:
3357  case ARM::VST2b16wb_fixed:
3358  case ARM::VST2b32wb_fixed:
3359  case ARM::VST2b8wb_register:
3360  case ARM::VST2b16wb_register:
3361  case ARM::VST2b32wb_register:
3362  if (Rm == 0xF)
3363  return MCDisassembler::Fail;
3365  break;
3366  case ARM::VST3d8_UPD:
3367  case ARM::VST3d16_UPD:
3368  case ARM::VST3d32_UPD:
3369  case ARM::VST3q8_UPD:
3370  case ARM::VST3q16_UPD:
3371  case ARM::VST3q32_UPD:
3372  case ARM::VST4d8_UPD:
3373  case ARM::VST4d16_UPD:
3374  case ARM::VST4d32_UPD:
3375  case ARM::VST4q8_UPD:
3376  case ARM::VST4q16_UPD:
3377  case ARM::VST4q32_UPD:
3378  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3379  return MCDisassembler::Fail;
3380  break;
3381  default:
3382  break;
3383  }
3384 
3385  // AddrMode6 Base (register+alignment)
3386  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3387  return MCDisassembler::Fail;
3388 
3389  // AddrMode6 Offset (register)
3390  switch (Inst.getOpcode()) {
3391  default:
3392  if (Rm == 0xD)
3394  else if (Rm != 0xF) {
3395  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3396  return MCDisassembler::Fail;
3397  }
3398  break;
3399  case ARM::VST1d8wb_fixed:
3400  case ARM::VST1d16wb_fixed:
3401  case ARM::VST1d32wb_fixed:
3402  case ARM::VST1d64wb_fixed:
3403  case ARM::VST1q8wb_fixed:
3404  case ARM::VST1q16wb_fixed:
3405  case ARM::VST1q32wb_fixed:
3406  case ARM::VST1q64wb_fixed:
3407  case ARM::VST1d8Twb_fixed:
3408  case ARM::VST1d16Twb_fixed:
3409  case ARM::VST1d32Twb_fixed:
3410  case ARM::VST1d64Twb_fixed:
3411  case ARM::VST1d8Qwb_fixed:
3412  case ARM::VST1d16Qwb_fixed:
3413  case ARM::VST1d32Qwb_fixed:
3414  case ARM::VST1d64Qwb_fixed:
3415  case ARM::VST2d8wb_fixed:
3416  case ARM::VST2d16wb_fixed:
3417  case ARM::VST2d32wb_fixed:
3418  case ARM::VST2q8wb_fixed:
3419  case ARM::VST2q16wb_fixed:
3420  case ARM::VST2q32wb_fixed:
3421  case ARM::VST2b8wb_fixed:
3422  case ARM::VST2b16wb_fixed:
3423  case ARM::VST2b32wb_fixed:
3424  break;
3425  }
3426 
3427  // First input register
3428  switch (Inst.getOpcode()) {
3429  case ARM::VST1q16:
3430  case ARM::VST1q32:
3431  case ARM::VST1q64:
3432  case ARM::VST1q8:
3433  case ARM::VST1q16wb_fixed:
3434  case ARM::VST1q16wb_register:
3435  case ARM::VST1q32wb_fixed:
3436  case ARM::VST1q32wb_register:
3437  case ARM::VST1q64wb_fixed:
3438  case ARM::VST1q64wb_register:
3439  case ARM::VST1q8wb_fixed:
3440  case ARM::VST1q8wb_register:
3441  case ARM::VST2d16:
3442  case ARM::VST2d32:
3443  case ARM::VST2d8:
3444  case ARM::VST2d16wb_fixed:
3445  case ARM::VST2d16wb_register:
3446  case ARM::VST2d32wb_fixed:
3447  case ARM::VST2d32wb_register:
3448  case ARM::VST2d8wb_fixed:
3449  case ARM::VST2d8wb_register:
3450  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3451  return MCDisassembler::Fail;
3452  break;
3453  case ARM::VST2b16:
3454  case ARM::VST2b32:
3455  case ARM::VST2b8:
3456  case ARM::VST2b16wb_fixed:
3457  case ARM::VST2b16wb_register:
3458  case ARM::VST2b32wb_fixed:
3459  case ARM::VST2b32wb_register:
3460  case ARM::VST2b8wb_fixed:
3461  case ARM::VST2b8wb_register:
3462  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3463  return MCDisassembler::Fail;
3464  break;
3465  default:
3466  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3467  return MCDisassembler::Fail;
3468  }
3469 
3470  // Second input register
3471  switch (Inst.getOpcode()) {
3472  case ARM::VST3d8:
3473  case ARM::VST3d16:
3474  case ARM::VST3d32:
3475  case ARM::VST3d8_UPD:
3476  case ARM::VST3d16_UPD:
3477  case ARM::VST3d32_UPD:
3478  case ARM::VST4d8:
3479  case ARM::VST4d16:
3480  case ARM::VST4d32:
3481  case ARM::VST4d8_UPD:
3482  case ARM::VST4d16_UPD:
3483  case ARM::VST4d32_UPD:
3484  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3485  return MCDisassembler::Fail;
3486  break;
3487  case ARM::VST3q8:
3488  case ARM::VST3q16:
3489  case ARM::VST3q32:
3490  case ARM::VST3q8_UPD:
3491  case ARM::VST3q16_UPD:
3492  case ARM::VST3q32_UPD:
3493  case ARM::VST4q8:
3494  case ARM::VST4q16:
3495  case ARM::VST4q32:
3496  case ARM::VST4q8_UPD:
3497  case ARM::VST4q16_UPD:
3498  case ARM::VST4q32_UPD:
3499  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3500  return MCDisassembler::Fail;
3501  break;
3502  default:
3503  break;
3504  }
3505 
3506  // Third input register
3507  switch (Inst.getOpcode()) {
3508  case ARM::VST3d8:
3509  case ARM::VST3d16:
3510  case ARM::VST3d32:
3511  case ARM::VST3d8_UPD:
3512  case ARM::VST3d16_UPD:
3513  case ARM::VST3d32_UPD:
3514  case ARM::VST4d8:
3515  case ARM::VST4d16:
3516  case ARM::VST4d32:
3517  case ARM::VST4d8_UPD:
3518  case ARM::VST4d16_UPD:
3519  case ARM::VST4d32_UPD:
3520  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3521  return MCDisassembler::Fail;
3522  break;
3523  case ARM::VST3q8:
3524  case ARM::VST3q16:
3525  case ARM::VST3q32:
3526  case ARM::VST3q8_UPD:
3527  case ARM::VST3q16_UPD:
3528  case ARM::VST3q32_UPD:
3529  case ARM::VST4q8:
3530  case ARM::VST4q16:
3531  case ARM::VST4q32:
3532  case ARM::VST4q8_UPD:
3533  case ARM::VST4q16_UPD:
3534  case ARM::VST4q32_UPD:
3535  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3536  return MCDisassembler::Fail;
3537  break;
3538  default:
3539  break;
3540  }
3541 
3542  // Fourth input register
3543  switch (Inst.getOpcode()) {
3544  case ARM::VST4d8:
3545  case ARM::VST4d16:
3546  case ARM::VST4d32:
3547  case ARM::VST4d8_UPD:
3548  case ARM::VST4d16_UPD:
3549  case ARM::VST4d32_UPD:
3550  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3551  return MCDisassembler::Fail;
3552  break;
3553  case ARM::VST4q8:
3554  case ARM::VST4q16:
3555  case ARM::VST4q32:
3556  case ARM::VST4q8_UPD:
3557  case ARM::VST4q16_UPD:
3558  case ARM::VST4q32_UPD:
3559  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3560  return MCDisassembler::Fail;
3561  break;
3562  default:
3563  break;
3564  }
3565 
3566  return S;
3567 }
3568 
3570  uint64_t Address,
3571  const MCDisassembler *Decoder) {
3573 
3574  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3575  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3576  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3577  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3578  unsigned align = fieldFromInstruction(Insn, 4, 1);
3579  unsigned size = fieldFromInstruction(Insn, 6, 2);
3580 
3581  if (size == 0 && align == 1)
3582  return MCDisassembler::Fail;
3583  align *= (1 << size);
3584 
3585  switch (Inst.getOpcode()) {
3586  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3587  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3588  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3589  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3590  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3591  return MCDisassembler::Fail;
3592  break;
3593  default:
3594  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3595  return MCDisassembler::Fail;
3596  break;
3597  }
3598  if (Rm != 0xF) {
3599  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3600  return MCDisassembler::Fail;
3601  }
3602 
3603  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3604  return MCDisassembler::Fail;
3606 
3607  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3608  // variant encodes Rm == 0xf. Anything else is a register offset post-
3609  // increment and we need to add the register operand to the instruction.
3610  if (Rm != 0xD && Rm != 0xF &&
3611  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3612  return MCDisassembler::Fail;
3613 
3614  return S;
3615 }
3616 
3618  uint64_t Address,
3619  const MCDisassembler *Decoder) {
3621 
3622  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3623  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3624  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3625  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3626  unsigned align = fieldFromInstruction(Insn, 4, 1);
3627  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3628  align *= 2*size;
3629 
3630  switch (Inst.getOpcode()) {
3631  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3632  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3633  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3634  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3635  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3636  return MCDisassembler::Fail;
3637  break;
3638  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3639  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3640  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3641  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3642  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3643  return MCDisassembler::Fail;
3644  break;
3645  default:
3646  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3647  return MCDisassembler::Fail;
3648  break;
3649  }
3650 
3651  if (Rm != 0xF)
3653 
3654  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3655  return MCDisassembler::Fail;
3657 
3658  if (Rm != 0xD && Rm != 0xF) {
3659  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3660  return MCDisassembler::Fail;
3661  }
3662 
3663  return S;
3664 }
3665 
3667  uint64_t Address,
3668  const MCDisassembler *Decoder) {
3670 
3671  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3672  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3673  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3674  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3675  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3676 
3677  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3678  return MCDisassembler::Fail;
3679  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3680  return MCDisassembler::Fail;
3681  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3682  return MCDisassembler::Fail;
3683  if (Rm != 0xF) {
3684  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3685  return MCDisassembler::Fail;
3686  }
3687 
3688  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3689  return MCDisassembler::Fail;
3691 
3692  if (Rm == 0xD)
3694  else if (Rm != 0xF) {
3695  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3696  return MCDisassembler::Fail;
3697  }
3698 
3699  return S;
3700 }
3701 
3703  uint64_t Address,
3704  const MCDisassembler *Decoder) {
3706 
3707  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3708  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3709  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3710  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3711  unsigned size = fieldFromInstruction(Insn, 6, 2);
3712  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3713  unsigned align = fieldFromInstruction(Insn, 4, 1);
3714 
3715  if (size == 0x3) {
3716  if (align == 0)
3717  return MCDisassembler::Fail;
3718  align = 16;
3719  } else {
3720  if (size == 2) {
3721  align *= 8;
3722  } else {
3723  size = 1 << size;
3724  align *= 4*size;
3725  }
3726  }
3727 
3728  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3729  return MCDisassembler::Fail;
3730  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3731  return MCDisassembler::Fail;
3732  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3733  return MCDisassembler::Fail;
3734  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3735  return MCDisassembler::Fail;
3736  if (Rm != 0xF) {
3737  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3738  return MCDisassembler::Fail;
3739  }
3740 
3741  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742  return MCDisassembler::Fail;
3744 
3745  if (Rm == 0xD)
3747  else if (Rm != 0xF) {
3748  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3749  return MCDisassembler::Fail;
3750  }
3751 
3752  return S;
3753 }
3754 
3756  uint64_t Address,
3757  const MCDisassembler *Decoder) {
3759 
3760  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3761  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3762  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3763  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3764  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3765  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3766  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3767  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3768 
3769  if (Q) {
3770  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3771  return MCDisassembler::Fail;
3772  } else {
3773  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3774  return MCDisassembler::Fail;
3775  }
3776 
3777  Inst.addOperand(MCOperand::createImm(imm));
3778 
3779  switch (Inst.getOpcode()) {
3780  case ARM::VORRiv4i16:
3781  case ARM::VORRiv2i32:
3782  case ARM::VBICiv4i16:
3783  case ARM::VBICiv2i32:
3784  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3785  return MCDisassembler::Fail;
3786  break;
3787  case ARM::VORRiv8i16:
3788  case ARM::VORRiv4i32:
3789  case ARM::VBICiv8i16:
3790  case ARM::VBICiv4i32:
3791  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3792  return MCDisassembler::Fail;
3793  break;
3794  default:
3795  break;
3796  }
3797 
3798  return S;
3799 }
3800 
3802  uint64_t Address,
3803  const MCDisassembler *Decoder) {
3805 
3806  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3807  fieldFromInstruction(Insn, 13, 3));
3808  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3809  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3810  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3811  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3812  imm |= cmode << 8;
3813  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3814 
3815  if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3816  return MCDisassembler::Fail;
3817 
3818  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3819  return MCDisassembler::Fail;
3820 
3821  Inst.addOperand(MCOperand::createImm(imm));
3822 
3826 
3827  return S;
3828 }
3829 
3831  uint64_t Address,
3832  const MCDisassembler *Decoder) {
3834 
3835  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3836  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3837  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3838  return MCDisassembler::Fail;
3839  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3840 
3841  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3842  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3843  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3844  return MCDisassembler::Fail;
3845  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3846  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3847  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3848  return MCDisassembler::Fail;
3849  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3850  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3851  Inst.addOperand(MCOperand::createImm(Qd));
3852 
3853  return S;
3854 }
3855 
3857  uint64_t Address,
3858  const MCDisassembler *Decoder) {
3860 
3861  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3862  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3863  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3864  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3865  unsigned size = fieldFromInstruction(Insn, 18, 2);
3866 
3867  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3868  return MCDisassembler::Fail;
3869  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3870  return MCDisassembler::Fail;
3871  Inst.addOperand(MCOperand::createImm(8 << size));
3872 
3873  return S;
3874 }
3875 
3876 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3877  uint64_t Address,
3878  const MCDisassembler *Decoder) {
3879  Inst.addOperand(MCOperand::createImm(8 - Val));
3880  return MCDisassembler::Success;
3881 }
3882 
3883 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3884  uint64_t Address,
3885  const MCDisassembler *Decoder) {
3886  Inst.addOperand(MCOperand::createImm(16 - Val));
3887  return MCDisassembler::Success;
3888 }
3889 
3890 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3891  uint64_t Address,
3892  const MCDisassembler *Decoder) {
3893  Inst.addOperand(MCOperand::createImm(32 - Val));
3894  return MCDisassembler::Success;
3895 }
3896 
3897 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3898  uint64_t Address,
3899  const MCDisassembler *Decoder) {
3900  Inst.addOperand(MCOperand::createImm(64 - Val));
3901  return MCDisassembler::Success;
3902 }
3903 
3905  uint64_t Address,
3906  const MCDisassembler *Decoder) {
3908 
3909  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3910  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3911  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3912  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3913  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3914  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3915  unsigned op = fieldFromInstruction(Insn, 6, 1);
3916 
3917  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3918  return MCDisassembler::Fail;
3919  if (op) {
3920  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3921  return MCDisassembler::Fail; // Writeback
3922  }
3923 
3924  switch (Inst.getOpcode()) {
3925  case ARM::VTBL2:
3926  case ARM::VTBX2:
3927  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3928  return MCDisassembler::Fail;
3929  break;
3930  default:
3931  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3932  return MCDisassembler::Fail;
3933  }
3934 
3935  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3936  return MCDisassembler::Fail;
3937 
3938  return S;
3939 }
3940 
3942  uint64_t Address,
3943  const MCDisassembler *Decoder) {
3945 
3946  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3947  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3948 
3949  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3950  return MCDisassembler::Fail;
3951 
3952  switch(Inst.getOpcode()) {
3953  default:
3954  return MCDisassembler::Fail;
3955  case ARM::tADR:
3956  break; // tADR does not explicitly represent the PC as an operand.
3957  case ARM::tADDrSPi:
3958  Inst.addOperand(MCOperand::createReg(ARM::SP));
3959  break;
3960  }
3961 
3962  Inst.addOperand(MCOperand::createImm(imm));
3963  return S;
3964 }
3965 
3966 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3967  uint64_t Address,
3968  const MCDisassembler *Decoder) {
3969  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3970  true, 2, Inst, Decoder))
3971  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3972  return MCDisassembler::Success;
3973 }
3974 
3975 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3976  uint64_t Address,
3977  const MCDisassembler *Decoder) {
3978  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3979  true, 4, Inst, Decoder))
3980  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3981  return MCDisassembler::Success;
3982 }
3983 
3984 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3985  uint64_t Address,
3986  const MCDisassembler *Decoder) {
3987  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3988  true, 2, Inst, Decoder))
3989  Inst.addOperand(MCOperand::createImm(Val << 1));
3990  return MCDisassembler::Success;
3991 }
3992 
3993 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3994  uint64_t Address,
3995  const MCDisassembler *Decoder) {
3997 
3998  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3999  unsigned Rm = fieldFromInstruction(Val, 3, 3);
4000 
4001  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4002  return MCDisassembler::Fail;
4003  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
4004  return MCDisassembler::Fail;
4005 
4006  return S;
4007 }
4008 
4009 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
4010  uint64_t Address,
4011  const MCDisassembler *Decoder) {
4013 
4014  unsigned Rn = fieldFromInstruction(Val, 0, 3);
4015  unsigned imm = fieldFromInstruction(Val, 3, 5);
4016 
4017  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4018  return MCDisassembler::Fail;
4019  Inst.addOperand(MCOperand::createImm(imm));
4020 
4021  return S;
4022 }
4023 
4024 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
4025  uint64_t Address,
4026  const MCDisassembler *Decoder) {
4027  unsigned imm = Val << 2;
4028 
4029  Inst.addOperand(MCOperand::createImm(imm));
4030  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
4031 
4032  return MCDisassembler::Success;
4033 }
4034 
4035 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
4036  uint64_t Address,
4037  const MCDisassembler *Decoder) {
4038  Inst.addOperand(MCOperand::createReg(ARM::SP));
4039  Inst.addOperand(MCOperand::createImm(Val));
4040 
4041  return MCDisassembler::Success;
4042 }
4043 
4044 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
4045  uint64_t Address,
4046  const MCDisassembler *Decoder) {
4048 
4049  unsigned Rn = fieldFromInstruction(Val, 6, 4);
4050  unsigned Rm = fieldFromInstruction(Val, 2, 4);
4051  unsigned imm = fieldFromInstruction(Val, 0, 2);
4052 
4053  // Thumb stores cannot use PC as dest register.
4054  switch (Inst.getOpcode()) {
4055  case ARM::t2STRHs:
4056  case ARM::t2STRBs:
4057  case ARM::t2STRs:
4058  if (Rn == 15)
4059  return MCDisassembler::Fail;
4060  break;
4061  default:
4062  break;
4063  }
4064 
4065  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4066  return MCDisassembler::Fail;
4067  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4068  return MCDisassembler::Fail;
4069  Inst.addOperand(MCOperand::createImm(imm));
4070 
4071  return S;
4072 }
4073 
4075  uint64_t Address,
4076  const MCDisassembler *Decoder) {
4078 
4079  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4080  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4081 
4082  const FeatureBitset &featureBits =
4083  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4084 
4085  bool hasMP = featureBits[ARM::FeatureMP];
4086  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4087 
4088  if (Rn == 15) {
4089  switch (Inst.getOpcode()) {
4090  case ARM::t2LDRBs:
4091  Inst.setOpcode(ARM::t2LDRBpci);
4092  break;
4093  case ARM::t2LDRHs:
4094  Inst.setOpcode(ARM::t2LDRHpci);
4095  break;
4096  case ARM::t2LDRSHs:
4097  Inst.setOpcode(ARM::t2LDRSHpci);
4098  break;
4099  case ARM::t2LDRSBs:
4100  Inst.setOpcode(ARM::t2LDRSBpci);
4101  break;
4102  case ARM::t2LDRs:
4103  Inst.setOpcode(ARM::t2LDRpci);
4104  break;
4105  case ARM::t2PLDs:
4106  Inst.setOpcode(ARM::t2PLDpci);
4107  break;
4108  case ARM::t2PLIs:
4109  Inst.setOpcode(ARM::t2PLIpci);
4110  break;
4111  default:
4112  return MCDisassembler::Fail;
4113  }
4114 
4115  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4116  }
4117 
4118  if (Rt == 15) {
4119  switch (Inst.getOpcode()) {
4120  case ARM::t2LDRSHs:
4121  return MCDisassembler::Fail;
4122  case ARM::t2LDRHs:
4123  Inst.setOpcode(ARM::t2PLDWs);
4124  break;
4125  case ARM::t2LDRSBs:
4126  Inst.setOpcode(ARM::t2PLIs);
4127  break;
4128  default:
4129  break;
4130  }
4131  }
4132 
4133  switch (Inst.getOpcode()) {
4134  case ARM::t2PLDs:
4135  break;
4136  case ARM::t2PLIs:
4137  if (!hasV7Ops)
4138  return MCDisassembler::Fail;
4139  break;
4140  case ARM::t2PLDWs:
4141  if (!hasV7Ops || !hasMP)
4142  return MCDisassembler::Fail;
4143  break;
4144  default:
4145  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4146  return MCDisassembler::Fail;
4147  }
4148 
4149  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
4150  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
4151  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
4152  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
4153  return MCDisassembler::Fail;
4154 
4155  return S;
4156 }
4157 
4158 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
4159  uint64_t Address,
4160  const MCDisassembler *Decoder) {
4162 
4163  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4164  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4165  unsigned U = fieldFromInstruction(Insn, 9, 1);
4166  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4167  imm |= (U << 8);
4168  imm |= (Rn << 9);
4169  unsigned add = fieldFromInstruction(Insn, 9, 1);
4170 
4171  const FeatureBitset &featureBits =
4172  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4173 
4174  bool hasMP = featureBits[ARM::FeatureMP];
4175  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4176 
4177  if (Rn == 15) {
4178  switch (Inst.getOpcode()) {
4179  case ARM::t2LDRi8:
4180  Inst.setOpcode(ARM::t2LDRpci);
4181  break;
4182  case ARM::t2LDRBi8:
4183  Inst.setOpcode(ARM::t2LDRBpci);
4184  break;
4185  case ARM::t2LDRSBi8:
4186  Inst.setOpcode(ARM::t2LDRSBpci);
4187  break;
4188  case ARM::t2LDRHi8:
4189  Inst.setOpcode(ARM::t2LDRHpci);
4190  break;
4191  case ARM::t2LDRSHi8:
4192  Inst.setOpcode(ARM::t2LDRSHpci);
4193  break;
4194  case ARM::t2PLDi8:
4195  Inst.setOpcode(ARM::t2PLDpci);
4196  break;
4197  case ARM::t2PLIi8:
4198  Inst.setOpcode(ARM::t2PLIpci);
4199  break;
4200  default:
4201  return MCDisassembler::Fail;
4202  }
4203  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4204  }
4205 
4206  if (Rt == 15) {
4207  switch (Inst.getOpcode()) {
4208  case ARM::t2LDRSHi8:
4209  return MCDisassembler::Fail;
4210  case ARM::t2LDRHi8:
4211  if (!add)
4212  Inst.setOpcode(ARM::t2PLDWi8);
4213  break;
4214  case ARM::t2LDRSBi8:
4215  Inst.setOpcode(ARM::t2PLIi8);
4216  break;
4217  default:
4218  break;
4219  }
4220  }
4221 
4222  switch (Inst.getOpcode()) {
4223  case ARM::t2PLDi8:
4224  break;
4225  case ARM::t2PLIi8:
4226  if (!hasV7Ops)
4227  return MCDisassembler::Fail;
4228  break;
4229  case ARM::t2PLDWi8:
4230  if (!hasV7Ops || !hasMP)
4231  return MCDisassembler::Fail;
4232  break;
4233  default:
4234  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4235  return MCDisassembler::Fail;
4236  }
4237 
4238  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4239  return MCDisassembler::Fail;
4240  return S;
4241 }
4242 
4244  uint64_t Address,
4245  const MCDisassembler *Decoder) {
4247 
4248  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4249  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4250  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4251  imm |= (Rn << 13);
4252 
4253  const FeatureBitset &featureBits =
4254  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4255 
4256  bool hasMP = featureBits[ARM::FeatureMP];
4257  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4258 
4259  if (Rn == 15) {
4260  switch (Inst.getOpcode()) {
4261  case ARM::t2LDRi12:
4262  Inst.setOpcode(ARM::t2LDRpci);
4263  break;
4264  case ARM::t2LDRHi12:
4265  Inst.setOpcode(ARM::t2LDRHpci);
4266  break;
4267  case ARM::t2LDRSHi12:
4268  Inst.setOpcode(ARM::t2LDRSHpci);
4269  break;
4270  case ARM::t2LDRBi12:
4271  Inst.setOpcode(ARM::t2LDRBpci);
4272  break;
4273  case ARM::t2LDRSBi12:
4274  Inst.setOpcode(ARM::t2LDRSBpci);
4275  break;
4276  case ARM::t2PLDi12:
4277  Inst.setOpcode(ARM::t2PLDpci);
4278  break;
4279  case ARM::t2PLIi12:
4280  Inst.setOpcode(ARM::t2PLIpci);
4281  break;
4282  default:
4283  return MCDisassembler::Fail;
4284  }
4285  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4286  }
4287 
4288  if (Rt == 15) {
4289  switch (Inst.getOpcode()) {
4290  case ARM::t2LDRSHi12:
4291  return MCDisassembler::Fail;
4292  case ARM::t2LDRHi12:
4293  Inst.setOpcode(ARM::t2PLDWi12);
4294  break;
4295  case ARM::t2LDRSBi12:
4296  Inst.setOpcode(ARM::t2PLIi12);
4297  break;
4298  default:
4299  break;
4300  }
4301  }
4302 
4303  switch (Inst.getOpcode()) {
4304  case ARM::t2PLDi12:
4305  break;
4306  case ARM::t2PLIi12:
4307  if (!hasV7Ops)
4308  return MCDisassembler::Fail;
4309  break;
4310  case ARM::t2PLDWi12:
4311  if (!hasV7Ops || !hasMP)
4312  return MCDisassembler::Fail;
4313  break;
4314  default:
4315  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4316  return MCDisassembler::Fail;
4317  }
4318 
4319  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4320  return MCDisassembler::Fail;
4321  return S;
4322 }
4323 
4324 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
4325  const MCDisassembler *Decoder) {
4327 
4328  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4329  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4330  unsigned imm = fieldFromInstruction(Insn, 0, 8);
4331  imm |= (Rn << 9);
4332 
4333  if (Rn == 15) {
4334  switch (Inst.getOpcode()) {
4335  case ARM::t2LDRT:
4336  Inst.setOpcode(ARM::t2LDRpci);
4337  break;
4338  case ARM::t2LDRBT:
4339  Inst.setOpcode(ARM::t2LDRBpci);
4340  break;
4341  case ARM::t2LDRHT:
4342  Inst.setOpcode(ARM::t2LDRHpci);
4343  break;
4344  case ARM::t2LDRSBT:
4345  Inst.setOpcode(ARM::t2LDRSBpci);
4346  break;
4347  case ARM::t2LDRSHT:
4348  Inst.setOpcode(ARM::t2LDRSHpci);
4349  break;
4350  default:
4351  return MCDisassembler::Fail;
4352  }
4353  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4354  }
4355 
4356  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4357  return MCDisassembler::Fail;
4358  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4359  return MCDisassembler::Fail;
4360  return S;
4361 }
4362 
4364  uint64_t Address,
4365  const MCDisassembler *Decoder) {
4367 
4368  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4369  unsigned U = fieldFromInstruction(Insn, 23, 1);
4370  int imm = fieldFromInstruction(Insn, 0, 12);
4371 
4372  const FeatureBitset &featureBits =
4373  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4374 
4375  bool hasV7Ops = featureBits[ARM::HasV7Ops];
4376 
4377  if (Rt == 15) {
4378  switch (Inst.getOpcode()) {
4379  case ARM::t2LDRBpci:
4380  case ARM::t2LDRHpci:
4381  Inst.setOpcode(ARM::t2PLDpci);
4382  break;
4383  case ARM::t2LDRSBpci:
4384  Inst.setOpcode(ARM::t2PLIpci);
4385  break;
4386  case ARM::t2LDRSHpci:
4387  return MCDisassembler::Fail;
4388  default:
4389  break;
4390  }
4391  }
4392 
4393  switch(Inst.getOpcode()) {
4394  case ARM::t2PLDpci:
4395  break;
4396  case ARM::t2PLIpci:
4397  if (!hasV7Ops)
4398  return MCDisassembler::Fail;
4399  break;
4400  default:
4401  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4402  return MCDisassembler::Fail;
4403  }
4404 
4405  if (!U) {
4406  // Special case for #-0.
4407  if (imm == 0)
4408  imm = INT32_MIN;
4409  else
4410  imm = -imm;
4411  }
4412  Inst.addOperand(MCOperand::createImm(imm));
4413 
4414  return S;
4415 }
4416 
4417 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
4418  const MCDisassembler *Decoder) {
4419  if (Val == 0)
4420  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4421  else {
4422  int imm = Val & 0xFF;
4423 
4424  if (!(Val & 0x100)) imm *= -1;
4425  Inst.addOperand(MCOperand::createImm(imm * 4));
4426  }
4427 
4428  return MCDisassembler::Success;
4429 }
4430 
4431 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4432  const MCDisassembler *Decoder) {
4433  if (Val == 0)
4434  Inst.addOperand(MCOperand::createImm(INT32_MIN));
4435  else {
4436  int imm = Val & 0x7F;
4437 
4438  if (!(Val & 0x80))
4439  imm *= -1;
4440  Inst.addOperand(MCOperand::createImm(imm * 4));
4441  }
4442 
4443  return MCDisassembler::Success;
4444 }
4445 
4446 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4447  uint64_t Address,
4448  const MCDisassembler *Decoder) {
4450 
4451  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4452  unsigned imm = fieldFromInstruction(Val, 0, 9);
4453 
4454  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4455  return MCDisassembler::Fail;
4456  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4457  return MCDisassembler::Fail;
4458 
4459  return S;
4460 }
4461 
4462 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4463  uint64_t Address,
4464  const MCDisassembler *Decoder) {
4466 
4467  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4468  unsigned imm = fieldFromInstruction(Val, 0, 8);
4469 
4470  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4471  return MCDisassembler::Fail;
4472  if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4473  return MCDisassembler::Fail;
4474 
4475  return S;
4476 }
4477 
4479  uint64_t Address,
4480  const MCDisassembler *Decoder) {
4482 
4483  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4484  unsigned imm = fieldFromInstruction(Val, 0, 8);
4485 
4486  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4487  return MCDisassembler::Fail;
4488 
4489  Inst.addOperand(MCOperand::createImm(imm));
4490 
4491  return S;
4492 }
4493 
4494 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
4495  const MCDisassembler *Decoder) {
4496  int imm = Val & 0xFF;
4497  if (Val == 0)
4498  imm = INT32_MIN;
4499  else if (!(Val & 0x100))
4500  imm *= -1;
4501  Inst.addOperand(MCOperand::createImm(imm));
4502 
4503  return MCDisassembler::Success;
4504 }
4505 
4506 template <int shift>
4507 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
4508  const MCDisassembler *Decoder) {
4509  int imm = Val & 0x7F;
4510  if (Val == 0)
4511  imm = INT32_MIN;
4512  else if (!(Val & 0x80))
4513  imm *= -1;
4514  if (imm != INT32_MIN)
4515  imm *= (1U << shift);
4516  Inst.addOperand(MCOperand::createImm(imm));
4517 
4518  return MCDisassembler::Success;
4519 }
4520 
4521 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4522  uint64_t Address,
4523  const MCDisassembler *Decoder) {
4525 
4526  unsigned Rn = fieldFromInstruction(Val, 9, 4);
4527  unsigned imm = fieldFromInstruction(Val, 0, 9);
4528 
4529  // Thumb stores cannot use PC as dest register.
4530  switch (Inst.getOpcode()) {
4531  case ARM::t2STRT:
4532  case ARM::t2STRBT:
4533  case ARM::t2STRHT:
4534  case ARM::t2STRi8:
4535  case ARM::t2STRHi8:
4536  case ARM::t2STRBi8:
4537  if (Rn == 15)
4538  return MCDisassembler::Fail;
4539  break;
4540  default:
4541  break;
4542  }
4543 
4544  // Some instructions always use an additive offset.
4545  switch (Inst.getOpcode()) {
4546  case ARM::t2LDRT:
4547  case ARM::t2LDRBT:
4548  case ARM::t2LDRHT:
4549  case ARM::t2LDRSBT:
4550  case ARM::t2LDRSHT:
4551  case ARM::t2STRT:
4552  case ARM::t2STRBT:
4553  case ARM::t2STRHT:
4554  imm |= 0x100;
4555  break;
4556  default:
4557  break;
4558  }
4559 
4560  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4561  return MCDisassembler::Fail;
4562  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4563  return MCDisassembler::Fail;
4564 
4565  return S;
4566 }
4567 
4568 template <int shift>
4569 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4570  uint64_t Address,
4571  const MCDisassembler *Decoder) {
4573 
4574  unsigned Rn = fieldFromInstruction(Val, 8, 3);
4575  unsigned imm = fieldFromInstruction(Val, 0, 8);
4576 
4577  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4578  return MCDisassembler::Fail;
4579  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4580  return MCDisassembler::Fail;
4581 
4582  return S;
4583 }
4584 
4585 template <int shift, int WriteBack>
4586 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4587  uint64_t Address,
4588  const MCDisassembler *Decoder) {
4590 
4591  unsigned Rn = fieldFromInstruction(Val, 8, 4);
4592  unsigned imm = fieldFromInstruction(Val, 0, 8);
4593  if (WriteBack) {
4594  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4595  return MCDisassembler::Fail;
4596  } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4597  return MCDisassembler::Fail;
4598  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4599  return MCDisassembler::Fail;
4600 
4601  return S;
4602 }
4603 
4604 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4605  uint64_t Address,
4606  const MCDisassembler *Decoder) {
4608 
4609  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4610  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4611  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4612  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4613  addr |= Rn << 9;
4614  unsigned load = fieldFromInstruction(Insn, 20, 1);
4615 
4616  if (Rn == 15) {
4617  switch (Inst.getOpcode()) {
4618  case ARM::t2LDR_PRE:
4619  case ARM::t2LDR_POST:
4620  Inst.setOpcode(ARM::t2LDRpci);
4621  break;
4622  case ARM::t2LDRB_PRE:
4623  case ARM::t2LDRB_POST:
4624  Inst.setOpcode(ARM::t2LDRBpci);
4625  break;
4626  case ARM::t2LDRH_PRE:
4627  case ARM::t2LDRH_POST:
4628  Inst.setOpcode(ARM::t2LDRHpci);
4629  break;
4630  case ARM::t2LDRSB_PRE:
4631  case ARM::t2LDRSB_POST:
4632  if (Rt == 15)
4633  Inst.setOpcode(ARM::t2PLIpci);
4634  else
4635  Inst.setOpcode(ARM::t2LDRSBpci);
4636  break;
4637  case ARM::t2LDRSH_PRE:
4638  case ARM::t2LDRSH_POST:
4639  Inst.setOpcode(ARM::t2LDRSHpci);
4640  break;
4641  default:
4642  return MCDisassembler::Fail;
4643  }
4644  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4645  }
4646 
4647  if (!load) {
4648  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4649  return MCDisassembler::Fail;
4650  }
4651 
4652  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4653  return MCDisassembler::Fail;
4654 
4655  if (load) {
4656  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4657  return MCDisassembler::Fail;
4658  }
4659 
4660  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4661  return MCDisassembler::Fail;
4662 
4663  return S;
4664 }
4665 
4666 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4667  uint64_t Address,
4668  const MCDisassembler *Decoder) {
4670 
4671  unsigned Rn = fieldFromInstruction(Val, 13, 4);
4672  unsigned imm = fieldFromInstruction(Val, 0, 12);
4673 
4674  // Thumb stores cannot use PC as dest register.
4675  switch (Inst.getOpcode()) {
4676  case ARM::t2STRi12:
4677  case ARM::t2STRBi12:
4678  case ARM::t2STRHi12:
4679  if (Rn == 15)
4680  return MCDisassembler::Fail;
4681  break;
4682  default:
4683  break;
4684  }
4685 
4686  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4687  return MCDisassembler::Fail;
4688  Inst.addOperand(MCOperand::createImm(imm));
4689 
4690  return S;
4691 }
4692 
4694  uint64_t Address,
4695  const MCDisassembler *Decoder) {
4696  unsigned imm = fieldFromInstruction(Insn, 0, 7);
4697 
4698  Inst.addOperand(MCOperand::createReg(ARM::SP));
4699  Inst.addOperand(MCOperand::createReg(ARM::SP));
4700  Inst.addOperand(MCOperand::createImm(imm));
4701 
4702  return MCDisassembler::Success;
4703 }
4704 
4706  uint64_t Address,
4707  const MCDisassembler *Decoder) {
4709 
4710  if (Inst.getOpcode() == ARM::tADDrSP) {
4711  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4712  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4713 
4714  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4715  return MCDisassembler::Fail;
4716  Inst.addOperand(MCOperand::createReg(ARM::SP));
4717  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4718  return MCDisassembler::Fail;
4719  } else if (Inst.getOpcode() == ARM::tADDspr) {
4720  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4721 
4722  Inst.addOperand(MCOperand::createReg(ARM::SP));
4723  Inst.addOperand(MCOperand::createReg(ARM::SP));
4724  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4725  return MCDisassembler::Fail;
4726  }
4727 
4728  return S;
4729 }
4730 
4732  uint64_t Address,
4733  const MCDisassembler *Decoder) {
4734  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4735  unsigned flags = fieldFromInstruction(Insn, 0, 3);
4736 
4737  Inst.addOperand(MCOperand::createImm(imod));
4738  Inst.addOperand(MCOperand::createImm(flags));
4739 
4740  return MCDisassembler::Success;
4741 }
4742 
4743 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4744  uint64_t Address,
4745  const MCDisassembler *Decoder) {
4747  unsigned Rm = fieldFromInstruction(