LLVM  9.0.0svn
ARMAsmParser.cpp
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1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMFeatures.h"
10 #include "ARMBaseInstrInfo.h"
11 #include "Utils/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringMap.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/MC/MCInstrDesc.h"
33 #include "llvm/MC/MCInstrInfo.h"
41 #include "llvm/MC/MCRegisterInfo.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/ARMEHABI.h"
49 #include "llvm/Support/Casting.h"
51 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/SMLoc.h"
58 #include <algorithm>
59 #include <cassert>
60 #include <cstddef>
61 #include <cstdint>
62 #include <iterator>
63 #include <limits>
64 #include <memory>
65 #include <string>
66 #include <utility>
67 #include <vector>
68 
69 #define DEBUG_TYPE "asm-parser"
70 
71 using namespace llvm;
72 
73 namespace llvm {
74 extern const MCInstrDesc ARMInsts[];
75 } // end namespace llvm
76 
77 namespace {
78 
79 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
80 
81 static cl::opt<ImplicitItModeTy> ImplicitItMode(
82  "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
83  cl::desc("Allow conditional instructions outdside of an IT block"),
84  cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
85  "Accept in both ISAs, emit implicit ITs in Thumb"),
86  clEnumValN(ImplicitItModeTy::Never, "never",
87  "Warn in ARM, reject in Thumb"),
88  clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
89  "Accept in ARM, reject in Thumb"),
90  clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
91  "Warn in ARM, emit implicit ITs in Thumb")));
92 
93 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
94  cl::init(false));
95 
96 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
97 
98 static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) {
99  // Position==0 means we're not in an IT block at all. Position==1
100  // means we want the first state bit, which is always 0 (Then).
101  // Position==2 means we want the second state bit, stored at bit 3
102  // of Mask, and so on downwards. So (5 - Position) will shift the
103  // right bit down to bit 0, including the always-0 bit at bit 4 for
104  // the mandatory initial Then.
105  return (Mask >> (5 - Position) & 1);
106 }
107 
108 class UnwindContext {
109  using Locs = SmallVector<SMLoc, 4>;
110 
111  MCAsmParser &Parser;
112  Locs FnStartLocs;
113  Locs CantUnwindLocs;
114  Locs PersonalityLocs;
115  Locs PersonalityIndexLocs;
116  Locs HandlerDataLocs;
117  int FPReg;
118 
119 public:
120  UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
121 
122  bool hasFnStart() const { return !FnStartLocs.empty(); }
123  bool cantUnwind() const { return !CantUnwindLocs.empty(); }
124  bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
125 
126  bool hasPersonality() const {
127  return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
128  }
129 
130  void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
131  void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
132  void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
133  void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
134  void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
135 
136  void saveFPReg(int Reg) { FPReg = Reg; }
137  int getFPReg() const { return FPReg; }
138 
139  void emitFnStartLocNotes() const {
140  for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
141  FI != FE; ++FI)
142  Parser.Note(*FI, ".fnstart was specified here");
143  }
144 
145  void emitCantUnwindLocNotes() const {
146  for (Locs::const_iterator UI = CantUnwindLocs.begin(),
147  UE = CantUnwindLocs.end(); UI != UE; ++UI)
148  Parser.Note(*UI, ".cantunwind was specified here");
149  }
150 
151  void emitHandlerDataLocNotes() const {
152  for (Locs::const_iterator HI = HandlerDataLocs.begin(),
153  HE = HandlerDataLocs.end(); HI != HE; ++HI)
154  Parser.Note(*HI, ".handlerdata was specified here");
155  }
156 
157  void emitPersonalityLocNotes() const {
158  for (Locs::const_iterator PI = PersonalityLocs.begin(),
159  PE = PersonalityLocs.end(),
160  PII = PersonalityIndexLocs.begin(),
161  PIE = PersonalityIndexLocs.end();
162  PI != PE || PII != PIE;) {
163  if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
164  Parser.Note(*PI++, ".personality was specified here");
165  else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
166  Parser.Note(*PII++, ".personalityindex was specified here");
167  else
168  llvm_unreachable(".personality and .personalityindex cannot be "
169  "at the same location");
170  }
171  }
172 
173  void reset() {
174  FnStartLocs = Locs();
175  CantUnwindLocs = Locs();
176  PersonalityLocs = Locs();
177  HandlerDataLocs = Locs();
178  PersonalityIndexLocs = Locs();
179  FPReg = ARM::SP;
180  }
181 };
182 
183 
184 class ARMAsmParser : public MCTargetAsmParser {
185  const MCRegisterInfo *MRI;
186  UnwindContext UC;
187 
188  ARMTargetStreamer &getTargetStreamer() {
189  assert(getParser().getStreamer().getTargetStreamer() &&
190  "do not have a target streamer");
191  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
192  return static_cast<ARMTargetStreamer &>(TS);
193  }
194 
195  // Map of register aliases registers via the .req directive.
196  StringMap<unsigned> RegisterReqs;
197 
198  bool NextSymbolIsThumb;
199 
200  bool useImplicitITThumb() const {
201  return ImplicitItMode == ImplicitItModeTy::Always ||
202  ImplicitItMode == ImplicitItModeTy::ThumbOnly;
203  }
204 
205  bool useImplicitITARM() const {
206  return ImplicitItMode == ImplicitItModeTy::Always ||
207  ImplicitItMode == ImplicitItModeTy::ARMOnly;
208  }
209 
210  struct {
211  ARMCC::CondCodes Cond; // Condition for IT block.
212  unsigned Mask:4; // Condition mask for instructions.
213  // Starting at first 1 (from lsb).
214  // '1' condition as indicated in IT.
215  // '0' inverse of condition (else).
216  // Count of instructions in IT block is
217  // 4 - trailingzeroes(mask)
218  // Note that this does not have the same encoding
219  // as in the IT instruction, which also depends
220  // on the low bit of the condition code.
221 
222  unsigned CurPosition; // Current position in parsing of IT
223  // block. In range [0,4], with 0 being the IT
224  // instruction itself. Initialized according to
225  // count of instructions in block. ~0U if no
226  // active IT block.
227 
228  bool IsExplicit; // true - The IT instruction was present in the
229  // input, we should not modify it.
230  // false - The IT instruction was added
231  // implicitly, we can extend it if that
232  // would be legal.
233  } ITState;
234 
235  SmallVector<MCInst, 4> PendingConditionalInsts;
236 
237  void flushPendingInstructions(MCStreamer &Out) override {
238  if (!inImplicitITBlock()) {
239  assert(PendingConditionalInsts.size() == 0);
240  return;
241  }
242 
243  // Emit the IT instruction
244  MCInst ITInst;
245  ITInst.setOpcode(ARM::t2IT);
246  ITInst.addOperand(MCOperand::createImm(ITState.Cond));
247  ITInst.addOperand(MCOperand::createImm(ITState.Mask));
248  Out.EmitInstruction(ITInst, getSTI());
249 
250  // Emit the conditonal instructions
251  assert(PendingConditionalInsts.size() <= 4);
252  for (const MCInst &Inst : PendingConditionalInsts) {
253  Out.EmitInstruction(Inst, getSTI());
254  }
255  PendingConditionalInsts.clear();
256 
257  // Clear the IT state
258  ITState.Mask = 0;
259  ITState.CurPosition = ~0U;
260  }
261 
262  bool inITBlock() { return ITState.CurPosition != ~0U; }
263  bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
264  bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
265 
266  bool lastInITBlock() {
267  return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
268  }
269 
270  void forwardITPosition() {
271  if (!inITBlock()) return;
272  // Move to the next instruction in the IT block, if there is one. If not,
273  // mark the block as done, except for implicit IT blocks, which we leave
274  // open until we find an instruction that can't be added to it.
275  unsigned TZ = countTrailingZeros(ITState.Mask);
276  if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
277  ITState.CurPosition = ~0U; // Done with the IT block after this.
278  }
279 
280  // Rewind the state of the current IT block, removing the last slot from it.
281  void rewindImplicitITPosition() {
282  assert(inImplicitITBlock());
283  assert(ITState.CurPosition > 1);
284  ITState.CurPosition--;
285  unsigned TZ = countTrailingZeros(ITState.Mask);
286  unsigned NewMask = 0;
287  NewMask |= ITState.Mask & (0xC << TZ);
288  NewMask |= 0x2 << TZ;
289  ITState.Mask = NewMask;
290  }
291 
292  // Rewind the state of the current IT block, removing the last slot from it.
293  // If we were at the first slot, this closes the IT block.
294  void discardImplicitITBlock() {
295  assert(inImplicitITBlock());
296  assert(ITState.CurPosition == 1);
297  ITState.CurPosition = ~0U;
298  }
299 
300  // Return the low-subreg of a given Q register.
301  unsigned getDRegFromQReg(unsigned QReg) const {
302  return MRI->getSubReg(QReg, ARM::dsub_0);
303  }
304 
305  // Get the condition code corresponding to the current IT block slot.
306  ARMCC::CondCodes currentITCond() {
307  unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
308  return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
309  }
310 
311  // Invert the condition of the current IT block slot without changing any
312  // other slots in the same block.
313  void invertCurrentITCondition() {
314  if (ITState.CurPosition == 1) {
315  ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
316  } else {
317  ITState.Mask ^= 1 << (5 - ITState.CurPosition);
318  }
319  }
320 
321  // Returns true if the current IT block is full (all 4 slots used).
322  bool isITBlockFull() {
323  return inITBlock() && (ITState.Mask & 1);
324  }
325 
326  // Extend the current implicit IT block to have one more slot with the given
327  // condition code.
328  void extendImplicitITBlock(ARMCC::CondCodes Cond) {
329  assert(inImplicitITBlock());
330  assert(!isITBlockFull());
331  assert(Cond == ITState.Cond ||
332  Cond == ARMCC::getOppositeCondition(ITState.Cond));
333  unsigned TZ = countTrailingZeros(ITState.Mask);
334  unsigned NewMask = 0;
335  // Keep any existing condition bits.
336  NewMask |= ITState.Mask & (0xE << TZ);
337  // Insert the new condition bit.
338  NewMask |= (Cond != ITState.Cond) << TZ;
339  // Move the trailing 1 down one bit.
340  NewMask |= 1 << (TZ - 1);
341  ITState.Mask = NewMask;
342  }
343 
344  // Create a new implicit IT block with a dummy condition code.
345  void startImplicitITBlock() {
346  assert(!inITBlock());
347  ITState.Cond = ARMCC::AL;
348  ITState.Mask = 8;
349  ITState.CurPosition = 1;
350  ITState.IsExplicit = false;
351  }
352 
353  // Create a new explicit IT block with the given condition and mask.
354  // The mask should be in the format used in ARMOperand and
355  // MCOperand, with a 1 implying 'e', regardless of the low bit of
356  // the condition.
357  void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
358  assert(!inITBlock());
359  ITState.Cond = Cond;
360  ITState.Mask = Mask;
361  ITState.CurPosition = 0;
362  ITState.IsExplicit = true;
363  }
364 
365  struct {
366  unsigned Mask : 4;
367  unsigned CurPosition;
368  } VPTState;
369  bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
370  void forwardVPTPosition() {
371  if (!inVPTBlock()) return;
372  unsigned TZ = countTrailingZeros(VPTState.Mask);
373  if (++VPTState.CurPosition == 5 - TZ)
374  VPTState.CurPosition = ~0U;
375  }
376 
377  void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
378  return getParser().Note(L, Msg, Range);
379  }
380 
381  bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
382  return getParser().Warning(L, Msg, Range);
383  }
384 
385  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
386  return getParser().Error(L, Msg, Range);
387  }
388 
389  bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
390  unsigned ListNo, bool IsARPop = false);
391  bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
392  unsigned ListNo);
393 
394  int tryParseRegister();
395  bool tryParseRegisterWithWriteBack(OperandVector &);
396  int tryParseShiftRegister(OperandVector &);
397  bool parseRegisterList(OperandVector &, bool EnforceOrder = true);
398  bool parseMemory(OperandVector &);
399  bool parseOperand(OperandVector &, StringRef Mnemonic);
400  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
401  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
402  unsigned &ShiftAmount);
403  bool parseLiteralValues(unsigned Size, SMLoc L);
404  bool parseDirectiveThumb(SMLoc L);
405  bool parseDirectiveARM(SMLoc L);
406  bool parseDirectiveThumbFunc(SMLoc L);
407  bool parseDirectiveCode(SMLoc L);
408  bool parseDirectiveSyntax(SMLoc L);
409  bool parseDirectiveReq(StringRef Name, SMLoc L);
410  bool parseDirectiveUnreq(SMLoc L);
411  bool parseDirectiveArch(SMLoc L);
412  bool parseDirectiveEabiAttr(SMLoc L);
413  bool parseDirectiveCPU(SMLoc L);
414  bool parseDirectiveFPU(SMLoc L);
415  bool parseDirectiveFnStart(SMLoc L);
416  bool parseDirectiveFnEnd(SMLoc L);
417  bool parseDirectiveCantUnwind(SMLoc L);
418  bool parseDirectivePersonality(SMLoc L);
419  bool parseDirectiveHandlerData(SMLoc L);
420  bool parseDirectiveSetFP(SMLoc L);
421  bool parseDirectivePad(SMLoc L);
422  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
423  bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
424  bool parseDirectiveLtorg(SMLoc L);
425  bool parseDirectiveEven(SMLoc L);
426  bool parseDirectivePersonalityIndex(SMLoc L);
427  bool parseDirectiveUnwindRaw(SMLoc L);
428  bool parseDirectiveTLSDescSeq(SMLoc L);
429  bool parseDirectiveMovSP(SMLoc L);
430  bool parseDirectiveObjectArch(SMLoc L);
431  bool parseDirectiveArchExtension(SMLoc L);
432  bool parseDirectiveAlign(SMLoc L);
433  bool parseDirectiveThumbSet(SMLoc L);
434 
435  bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
436  StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
437  unsigned &PredicationCode,
438  unsigned &VPTPredicationCode, bool &CarrySetting,
439  unsigned &ProcessorIMod, StringRef &ITMask);
440  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
441  StringRef FullInst, bool &CanAcceptCarrySet,
442  bool &CanAcceptPredicationCode,
443  bool &CanAcceptVPTPredicationCode);
444 
445  void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
446  OperandVector &Operands);
447  bool isThumb() const {
448  // FIXME: Can tablegen auto-generate this?
449  return getSTI().getFeatureBits()[ARM::ModeThumb];
450  }
451 
452  bool isThumbOne() const {
453  return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
454  }
455 
456  bool isThumbTwo() const {
457  return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
458  }
459 
460  bool hasThumb() const {
461  return getSTI().getFeatureBits()[ARM::HasV4TOps];
462  }
463 
464  bool hasThumb2() const {
465  return getSTI().getFeatureBits()[ARM::FeatureThumb2];
466  }
467 
468  bool hasV6Ops() const {
469  return getSTI().getFeatureBits()[ARM::HasV6Ops];
470  }
471 
472  bool hasV6T2Ops() const {
473  return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
474  }
475 
476  bool hasV6MOps() const {
477  return getSTI().getFeatureBits()[ARM::HasV6MOps];
478  }
479 
480  bool hasV7Ops() const {
481  return getSTI().getFeatureBits()[ARM::HasV7Ops];
482  }
483 
484  bool hasV8Ops() const {
485  return getSTI().getFeatureBits()[ARM::HasV8Ops];
486  }
487 
488  bool hasV8MBaseline() const {
489  return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
490  }
491 
492  bool hasV8MMainline() const {
493  return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
494  }
495  bool hasV8_1MMainline() const {
496  return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
497  }
498  bool hasMVE() const {
499  return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
500  }
501  bool hasMVEFloat() const {
502  return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
503  }
504  bool has8MSecExt() const {
505  return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
506  }
507 
508  bool hasARM() const {
509  return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
510  }
511 
512  bool hasDSP() const {
513  return getSTI().getFeatureBits()[ARM::FeatureDSP];
514  }
515 
516  bool hasD32() const {
517  return getSTI().getFeatureBits()[ARM::FeatureD32];
518  }
519 
520  bool hasV8_1aOps() const {
521  return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
522  }
523 
524  bool hasRAS() const {
525  return getSTI().getFeatureBits()[ARM::FeatureRAS];
526  }
527 
528  void SwitchMode() {
529  MCSubtargetInfo &STI = copySTI();
530  auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
531  setAvailableFeatures(FB);
532  }
533 
534  void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
535 
536  bool isMClass() const {
537  return getSTI().getFeatureBits()[ARM::FeatureMClass];
538  }
539 
540  /// @name Auto-generated Match Functions
541  /// {
542 
543 #define GET_ASSEMBLER_HEADER
544 #include "ARMGenAsmMatcher.inc"
545 
546  /// }
547 
548  OperandMatchResultTy parseITCondCode(OperandVector &);
549  OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
550  OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
551  OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
552  OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
553  OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
554  OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
555  OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
556  OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
557  OperandMatchResultTy parseBankedRegOperand(OperandVector &);
558  OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
559  int High);
560  OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
561  return parsePKHImm(O, "lsl", 0, 31);
562  }
563  OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
564  return parsePKHImm(O, "asr", 1, 32);
565  }
566  OperandMatchResultTy parseSetEndImm(OperandVector &);
567  OperandMatchResultTy parseShifterImm(OperandVector &);
568  OperandMatchResultTy parseRotImm(OperandVector &);
569  OperandMatchResultTy parseModImm(OperandVector &);
570  OperandMatchResultTy parseBitfield(OperandVector &);
571  OperandMatchResultTy parsePostIdxReg(OperandVector &);
572  OperandMatchResultTy parseAM3Offset(OperandVector &);
573  OperandMatchResultTy parseFPImm(OperandVector &);
574  OperandMatchResultTy parseVectorList(OperandVector &);
575  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
576  SMLoc &EndLoc);
577 
578  // Asm Match Converter Methods
579  void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
580  void cvtThumbBranches(MCInst &Inst, const OperandVector &);
581  void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
582 
583  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
584  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
585  bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
586  bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
587  bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
588  bool isITBlockTerminator(MCInst &Inst) const;
589  void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
590  bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
591  bool Load, bool ARMMode, bool Writeback);
592 
593 public:
594  enum ARMMatchResultTy {
595  Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
596  Match_RequiresNotITBlock,
597  Match_RequiresV6,
598  Match_RequiresThumb2,
599  Match_RequiresV8,
600  Match_RequiresFlagSetting,
601 #define GET_OPERAND_DIAGNOSTIC_TYPES
602 #include "ARMGenAsmMatcher.inc"
603 
604  };
605 
606  ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
607  const MCInstrInfo &MII, const MCTargetOptions &Options)
608  : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
610 
611  // Cache the MCRegisterInfo.
612  MRI = getContext().getRegisterInfo();
613 
614  // Initialize the set of available features.
615  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
616 
617  // Add build attributes based on the selected target.
618  if (AddBuildAttributes)
619  getTargetStreamer().emitTargetAttributes(STI);
620 
621  // Not in an ITBlock to start with.
622  ITState.CurPosition = ~0U;
623 
624  VPTState.CurPosition = ~0U;
625 
626  NextSymbolIsThumb = false;
627  }
628 
629  // Implementation of the MCTargetAsmParser interface:
630  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
631  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
632  SMLoc NameLoc, OperandVector &Operands) override;
633  bool ParseDirective(AsmToken DirectiveID) override;
634 
635  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
636  unsigned Kind) override;
637  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
638 
639  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
640  OperandVector &Operands, MCStreamer &Out,
641  uint64_t &ErrorInfo,
642  bool MatchingInlineAsm) override;
643  unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
644  SmallVectorImpl<NearMissInfo> &NearMisses,
645  bool MatchingInlineAsm, bool &EmitInITBlock,
646  MCStreamer &Out);
647 
648  struct NearMissMessage {
649  SMLoc Loc;
650  SmallString<128> Message;
651  };
652 
653  const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
654 
655  void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
656  SmallVectorImpl<NearMissMessage> &NearMissesOut,
657  SMLoc IDLoc, OperandVector &Operands);
658  void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
659  OperandVector &Operands);
660 
661  void doBeforeLabelEmit(MCSymbol *Symbol) override;
662 
663  void onLabelParsed(MCSymbol *Symbol) override;
664 };
665 
666 /// ARMOperand - Instances of this class represent a parsed ARM machine
667 /// operand.
668 class ARMOperand : public MCParsedAsmOperand {
669  enum KindTy {
670  k_CondCode,
671  k_VPTPred,
672  k_CCOut,
673  k_ITCondMask,
674  k_CoprocNum,
675  k_CoprocReg,
676  k_CoprocOption,
677  k_Immediate,
678  k_MemBarrierOpt,
679  k_InstSyncBarrierOpt,
680  k_TraceSyncBarrierOpt,
681  k_Memory,
682  k_PostIndexRegister,
683  k_MSRMask,
684  k_BankedReg,
685  k_ProcIFlags,
686  k_VectorIndex,
687  k_Register,
688  k_RegisterList,
689  k_RegisterListWithAPSR,
690  k_DPRRegisterList,
691  k_SPRRegisterList,
692  k_FPSRegisterListWithVPR,
693  k_FPDRegisterListWithVPR,
694  k_VectorList,
695  k_VectorListAllLanes,
696  k_VectorListIndexed,
697  k_ShiftedRegister,
698  k_ShiftedImmediate,
699  k_ShifterImmediate,
700  k_RotateImmediate,
701  k_ModifiedImmediate,
702  k_ConstantPoolImmediate,
703  k_BitfieldDescriptor,
704  k_Token,
705  } Kind;
706 
707  SMLoc StartLoc, EndLoc, AlignmentLoc;
709 
710  struct CCOp {
711  ARMCC::CondCodes Val;
712  };
713 
714  struct VCCOp {
715  ARMVCC::VPTCodes Val;
716  };
717 
718  struct CopOp {
719  unsigned Val;
720  };
721 
722  struct CoprocOptionOp {
723  unsigned Val;
724  };
725 
726  struct ITMaskOp {
727  unsigned Mask:4;
728  };
729 
730  struct MBOptOp {
731  ARM_MB::MemBOpt Val;
732  };
733 
734  struct ISBOptOp {
736  };
737 
738  struct TSBOptOp {
740  };
741 
742  struct IFlagsOp {
743  ARM_PROC::IFlags Val;
744  };
745 
746  struct MMaskOp {
747  unsigned Val;
748  };
749 
750  struct BankedRegOp {
751  unsigned Val;
752  };
753 
754  struct TokOp {
755  const char *Data;
756  unsigned Length;
757  };
758 
759  struct RegOp {
760  unsigned RegNum;
761  };
762 
763  // A vector register list is a sequential list of 1 to 4 registers.
764  struct VectorListOp {
765  unsigned RegNum;
766  unsigned Count;
767  unsigned LaneIndex;
768  bool isDoubleSpaced;
769  };
770 
771  struct VectorIndexOp {
772  unsigned Val;
773  };
774 
775  struct ImmOp {
776  const MCExpr *Val;
777  };
778 
779  /// Combined record for all forms of ARM address expressions.
780  struct MemoryOp {
781  unsigned BaseRegNum;
782  // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
783  // was specified.
784  const MCConstantExpr *OffsetImm; // Offset immediate value
785  unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
786  ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
787  unsigned ShiftImm; // shift for OffsetReg.
788  unsigned Alignment; // 0 = no alignment specified
789  // n = alignment in bytes (2, 4, 8, 16, or 32)
790  unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
791  };
792 
793  struct PostIdxRegOp {
794  unsigned RegNum;
795  bool isAdd;
796  ARM_AM::ShiftOpc ShiftTy;
797  unsigned ShiftImm;
798  };
799 
800  struct ShifterImmOp {
801  bool isASR;
802  unsigned Imm;
803  };
804 
805  struct RegShiftedRegOp {
806  ARM_AM::ShiftOpc ShiftTy;
807  unsigned SrcReg;
808  unsigned ShiftReg;
809  unsigned ShiftImm;
810  };
811 
812  struct RegShiftedImmOp {
813  ARM_AM::ShiftOpc ShiftTy;
814  unsigned SrcReg;
815  unsigned ShiftImm;
816  };
817 
818  struct RotImmOp {
819  unsigned Imm;
820  };
821 
822  struct ModImmOp {
823  unsigned Bits;
824  unsigned Rot;
825  };
826 
827  struct BitfieldOp {
828  unsigned LSB;
829  unsigned Width;
830  };
831 
832  union {
833  struct CCOp CC;
834  struct VCCOp VCC;
835  struct CopOp Cop;
836  struct CoprocOptionOp CoprocOption;
837  struct MBOptOp MBOpt;
838  struct ISBOptOp ISBOpt;
839  struct TSBOptOp TSBOpt;
840  struct ITMaskOp ITMask;
841  struct IFlagsOp IFlags;
842  struct MMaskOp MMask;
843  struct BankedRegOp BankedReg;
844  struct TokOp Tok;
845  struct RegOp Reg;
846  struct VectorListOp VectorList;
847  struct VectorIndexOp VectorIndex;
848  struct ImmOp Imm;
849  struct MemoryOp Memory;
850  struct PostIdxRegOp PostIdxReg;
851  struct ShifterImmOp ShifterImm;
852  struct RegShiftedRegOp RegShiftedReg;
853  struct RegShiftedImmOp RegShiftedImm;
854  struct RotImmOp RotImm;
855  struct ModImmOp ModImm;
856  struct BitfieldOp Bitfield;
857  };
858 
859 public:
860  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
861 
862  /// getStartLoc - Get the location of the first token of this operand.
863  SMLoc getStartLoc() const override { return StartLoc; }
864 
865  /// getEndLoc - Get the location of the last token of this operand.
866  SMLoc getEndLoc() const override { return EndLoc; }
867 
868  /// getLocRange - Get the range between the first and last token of this
869  /// operand.
870  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
871 
872  /// getAlignmentLoc - Get the location of the Alignment token of this operand.
873  SMLoc getAlignmentLoc() const {
874  assert(Kind == k_Memory && "Invalid access!");
875  return AlignmentLoc;
876  }
877 
878  ARMCC::CondCodes getCondCode() const {
879  assert(Kind == k_CondCode && "Invalid access!");
880  return CC.Val;
881  }
882 
883  ARMVCC::VPTCodes getVPTPred() const {
884  assert(isVPTPred() && "Invalid access!");
885  return VCC.Val;
886  }
887 
888  unsigned getCoproc() const {
889  assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
890  return Cop.Val;
891  }
892 
893  StringRef getToken() const {
894  assert(Kind == k_Token && "Invalid access!");
895  return StringRef(Tok.Data, Tok.Length);
896  }
897 
898  unsigned getReg() const override {
899  assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
900  return Reg.RegNum;
901  }
902 
903  const SmallVectorImpl<unsigned> &getRegList() const {
904  assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
905  Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
906  Kind == k_FPSRegisterListWithVPR ||
907  Kind == k_FPDRegisterListWithVPR) &&
908  "Invalid access!");
909  return Registers;
910  }
911 
912  const MCExpr *getImm() const {
913  assert(isImm() && "Invalid access!");
914  return Imm.Val;
915  }
916 
917  const MCExpr *getConstantPoolImm() const {
918  assert(isConstantPoolImm() && "Invalid access!");
919  return Imm.Val;
920  }
921 
922  unsigned getVectorIndex() const {
923  assert(Kind == k_VectorIndex && "Invalid access!");
924  return VectorIndex.Val;
925  }
926 
927  ARM_MB::MemBOpt getMemBarrierOpt() const {
928  assert(Kind == k_MemBarrierOpt && "Invalid access!");
929  return MBOpt.Val;
930  }
931 
932  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
933  assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
934  return ISBOpt.Val;
935  }
936 
937  ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
938  assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
939  return TSBOpt.Val;
940  }
941 
942  ARM_PROC::IFlags getProcIFlags() const {
943  assert(Kind == k_ProcIFlags && "Invalid access!");
944  return IFlags.Val;
945  }
946 
947  unsigned getMSRMask() const {
948  assert(Kind == k_MSRMask && "Invalid access!");
949  return MMask.Val;
950  }
951 
952  unsigned getBankedReg() const {
953  assert(Kind == k_BankedReg && "Invalid access!");
954  return BankedReg.Val;
955  }
956 
957  bool isCoprocNum() const { return Kind == k_CoprocNum; }
958  bool isCoprocReg() const { return Kind == k_CoprocReg; }
959  bool isCoprocOption() const { return Kind == k_CoprocOption; }
960  bool isCondCode() const { return Kind == k_CondCode; }
961  bool isVPTPred() const { return Kind == k_VPTPred; }
962  bool isCCOut() const { return Kind == k_CCOut; }
963  bool isITMask() const { return Kind == k_ITCondMask; }
964  bool isITCondCode() const { return Kind == k_CondCode; }
965  bool isImm() const override {
966  return Kind == k_Immediate;
967  }
968 
969  bool isARMBranchTarget() const {
970  if (!isImm()) return false;
971 
972  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
973  return CE->getValue() % 4 == 0;
974  return true;
975  }
976 
977 
978  bool isThumbBranchTarget() const {
979  if (!isImm()) return false;
980 
981  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
982  return CE->getValue() % 2 == 0;
983  return true;
984  }
985 
986  // checks whether this operand is an unsigned offset which fits is a field
987  // of specified width and scaled by a specific number of bits
988  template<unsigned width, unsigned scale>
989  bool isUnsignedOffset() const {
990  if (!isImm()) return false;
991  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
992  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
993  int64_t Val = CE->getValue();
994  int64_t Align = 1LL << scale;
995  int64_t Max = Align * ((1LL << width) - 1);
996  return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
997  }
998  return false;
999  }
1000 
1001  // checks whether this operand is an signed offset which fits is a field
1002  // of specified width and scaled by a specific number of bits
1003  template<unsigned width, unsigned scale>
1004  bool isSignedOffset() const {
1005  if (!isImm()) return false;
1006  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1007  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1008  int64_t Val = CE->getValue();
1009  int64_t Align = 1LL << scale;
1010  int64_t Max = Align * ((1LL << (width-1)) - 1);
1011  int64_t Min = -Align * (1LL << (width-1));
1012  return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1013  }
1014  return false;
1015  }
1016 
1017  // checks whether this operand is an offset suitable for the LE /
1018  // LETP instructions in Arm v8.1M
1019  bool isLEOffset() const {
1020  if (!isImm()) return false;
1021  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1022  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1023  int64_t Val = CE->getValue();
1024  return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1025  }
1026  return false;
1027  }
1028 
1029  // checks whether this operand is a memory operand computed as an offset
1030  // applied to PC. the offset may have 8 bits of magnitude and is represented
1031  // with two bits of shift. textually it may be either [pc, #imm], #imm or
1032  // relocable expression...
1033  bool isThumbMemPC() const {
1034  int64_t Val = 0;
1035  if (isImm()) {
1036  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1037  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1038  if (!CE) return false;
1039  Val = CE->getValue();
1040  }
1041  else if (isGPRMem()) {
1042  if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
1043  if(Memory.BaseRegNum != ARM::PC) return false;
1044  Val = Memory.OffsetImm->getValue();
1045  }
1046  else return false;
1047  return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1048  }
1049 
1050  bool isFPImm() const {
1051  if (!isImm()) return false;
1052  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1053  if (!CE) return false;
1054  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1055  return Val != -1;
1056  }
1057 
1058  template<int64_t N, int64_t M>
1059  bool isImmediate() const {
1060  if (!isImm()) return false;
1061  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062  if (!CE) return false;
1063  int64_t Value = CE->getValue();
1064  return Value >= N && Value <= M;
1065  }
1066 
1067  template<int64_t N, int64_t M>
1068  bool isImmediateS4() const {
1069  if (!isImm()) return false;
1070  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1071  if (!CE) return false;
1072  int64_t Value = CE->getValue();
1073  return ((Value & 3) == 0) && Value >= N && Value <= M;
1074  }
1075  template<int64_t N, int64_t M>
1076  bool isImmediateS2() const {
1077  if (!isImm()) return false;
1078  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1079  if (!CE) return false;
1080  int64_t Value = CE->getValue();
1081  return ((Value & 1) == 0) && Value >= N && Value <= M;
1082  }
1083  bool isFBits16() const {
1084  return isImmediate<0, 17>();
1085  }
1086  bool isFBits32() const {
1087  return isImmediate<1, 33>();
1088  }
1089  bool isImm8s4() const {
1090  return isImmediateS4<-1020, 1020>();
1091  }
1092  bool isImm7s4() const {
1093  return isImmediateS4<-508, 508>();
1094  }
1095  bool isImm7Shift0() const {
1096  return isImmediate<-127, 127>();
1097  }
1098  bool isImm7Shift1() const {
1099  return isImmediateS2<-255, 255>();
1100  }
1101  bool isImm7Shift2() const {
1102  return isImmediateS4<-511, 511>();
1103  }
1104  bool isImm7() const {
1105  return isImmediate<-127, 127>();
1106  }
1107  bool isImm0_1020s4() const {
1108  return isImmediateS4<0, 1020>();
1109  }
1110  bool isImm0_508s4() const {
1111  return isImmediateS4<0, 508>();
1112  }
1113  bool isImm0_508s4Neg() const {
1114  if (!isImm()) return false;
1115  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1116  if (!CE) return false;
1117  int64_t Value = -CE->getValue();
1118  // explicitly exclude zero. we want that to use the normal 0_508 version.
1119  return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1120  }
1121 
1122  bool isImm0_4095Neg() const {
1123  if (!isImm()) return false;
1124  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1125  if (!CE) return false;
1126  // isImm0_4095Neg is used with 32-bit immediates only.
1127  // 32-bit immediates are zero extended to 64-bit when parsed,
1128  // thus simple -CE->getValue() results in a big negative number,
1129  // not a small positive number as intended
1130  if ((CE->getValue() >> 32) > 0) return false;
1131  uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1132  return Value > 0 && Value < 4096;
1133  }
1134 
1135  bool isImm0_7() const {
1136  return isImmediate<0, 7>();
1137  }
1138 
1139  bool isImm1_16() const {
1140  return isImmediate<1, 16>();
1141  }
1142 
1143  bool isImm1_32() const {
1144  return isImmediate<1, 32>();
1145  }
1146 
1147  bool isImm8_255() const {
1148  return isImmediate<8, 255>();
1149  }
1150 
1151  bool isImm256_65535Expr() const {
1152  if (!isImm()) return false;
1153  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1154  // If it's not a constant expression, it'll generate a fixup and be
1155  // handled later.
1156  if (!CE) return true;
1157  int64_t Value = CE->getValue();
1158  return Value >= 256 && Value < 65536;
1159  }
1160 
1161  bool isImm0_65535Expr() const {
1162  if (!isImm()) return false;
1163  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1164  // If it's not a constant expression, it'll generate a fixup and be
1165  // handled later.
1166  if (!CE) return true;
1167  int64_t Value = CE->getValue();
1168  return Value >= 0 && Value < 65536;
1169  }
1170 
1171  bool isImm24bit() const {
1172  return isImmediate<0, 0xffffff + 1>();
1173  }
1174 
1175  bool isImmThumbSR() const {
1176  return isImmediate<1, 33>();
1177  }
1178 
1179  template<int shift>
1180  bool isExpImmValue(uint64_t Value) const {
1181  uint64_t mask = (1 << shift) - 1;
1182  if ((Value & mask) != 0 || (Value >> shift) > 0xff)
1183  return false;
1184  return true;
1185  }
1186 
1187  template<int shift>
1188  bool isExpImm() const {
1189  if (!isImm()) return false;
1190  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191  if (!CE) return false;
1192 
1193  return isExpImmValue<shift>(CE->getValue());
1194  }
1195 
1196  template<int shift, int size>
1197  bool isInvertedExpImm() const {
1198  if (!isImm()) return false;
1199  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1200  if (!CE) return false;
1201 
1202  uint64_t OriginalValue = CE->getValue();
1203  uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
1204  return isExpImmValue<shift>(InvertedValue);
1205  }
1206 
1207  bool isPKHLSLImm() const {
1208  return isImmediate<0, 32>();
1209  }
1210 
1211  bool isPKHASRImm() const {
1212  return isImmediate<0, 33>();
1213  }
1214 
1215  bool isAdrLabel() const {
1216  // If we have an immediate that's not a constant, treat it as a label
1217  // reference needing a fixup.
1218  if (isImm() && !isa<MCConstantExpr>(getImm()))
1219  return true;
1220 
1221  // If it is a constant, it must fit into a modified immediate encoding.
1222  if (!isImm()) return false;
1223  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224  if (!CE) return false;
1225  int64_t Value = CE->getValue();
1226  return (ARM_AM::getSOImmVal(Value) != -1 ||
1227  ARM_AM::getSOImmVal(-Value) != -1);
1228  }
1229 
1230  bool isT2SOImm() const {
1231  // If we have an immediate that's not a constant, treat it as an expression
1232  // needing a fixup.
1233  if (isImm() && !isa<MCConstantExpr>(getImm())) {
1234  // We want to avoid matching :upper16: and :lower16: as we want these
1235  // expressions to match in isImm0_65535Expr()
1236  const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1237  return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1238  ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1239  }
1240  if (!isImm()) return false;
1241  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1242  if (!CE) return false;
1243  int64_t Value = CE->getValue();
1244  return ARM_AM::getT2SOImmVal(Value) != -1;
1245  }
1246 
1247  bool isT2SOImmNot() const {
1248  if (!isImm()) return false;
1249  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1250  if (!CE) return false;
1251  int64_t Value = CE->getValue();
1252  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1253  ARM_AM::getT2SOImmVal(~Value) != -1;
1254  }
1255 
1256  bool isT2SOImmNeg() const {
1257  if (!isImm()) return false;
1258  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1259  if (!CE) return false;
1260  int64_t Value = CE->getValue();
1261  // Only use this when not representable as a plain so_imm.
1262  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1263  ARM_AM::getT2SOImmVal(-Value) != -1;
1264  }
1265 
1266  bool isSetEndImm() const {
1267  if (!isImm()) return false;
1268  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1269  if (!CE) return false;
1270  int64_t Value = CE->getValue();
1271  return Value == 1 || Value == 0;
1272  }
1273 
1274  bool isReg() const override { return Kind == k_Register; }
1275  bool isRegList() const { return Kind == k_RegisterList; }
1276  bool isRegListWithAPSR() const {
1277  return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1278  }
1279  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1280  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1281  bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1282  bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
1283  bool isToken() const override { return Kind == k_Token; }
1284  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1285  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1286  bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1287  bool isMem() const override {
1288  return isGPRMem() || isMVEMem();
1289  }
1290  bool isMVEMem() const {
1291  if (Kind != k_Memory)
1292  return false;
1293  if (Memory.BaseRegNum &&
1294  !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1295  !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1296  return false;
1297  if (Memory.OffsetRegNum &&
1298  !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1299  Memory.OffsetRegNum))
1300  return false;
1301  return true;
1302  }
1303  bool isGPRMem() const {
1304  if (Kind != k_Memory)
1305  return false;
1306  if (Memory.BaseRegNum &&
1307  !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1308  return false;
1309  if (Memory.OffsetRegNum &&
1310  !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1311  return false;
1312  return true;
1313  }
1314  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1315  bool isRegShiftedReg() const {
1316  return Kind == k_ShiftedRegister &&
1317  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1318  RegShiftedReg.SrcReg) &&
1319  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1320  RegShiftedReg.ShiftReg);
1321  }
1322  bool isRegShiftedImm() const {
1323  return Kind == k_ShiftedImmediate &&
1324  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1325  RegShiftedImm.SrcReg);
1326  }
1327  bool isRotImm() const { return Kind == k_RotateImmediate; }
1328 
1329  template<unsigned Min, unsigned Max>
1330  bool isPowerTwoInRange() const {
1331  if (!isImm()) return false;
1332  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1333  if (!CE) return false;
1334  int64_t Value = CE->getValue();
1335  return Value > 0 && countPopulation((uint64_t)Value) == 1 &&
1336  Value >= Min && Value <= Max;
1337  }
1338  bool isModImm() const { return Kind == k_ModifiedImmediate; }
1339 
1340  bool isModImmNot() const {
1341  if (!isImm()) return false;
1342  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1343  if (!CE) return false;
1344  int64_t Value = CE->getValue();
1345  return ARM_AM::getSOImmVal(~Value) != -1;
1346  }
1347 
1348  bool isModImmNeg() const {
1349  if (!isImm()) return false;
1350  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1351  if (!CE) return false;
1352  int64_t Value = CE->getValue();
1353  return ARM_AM::getSOImmVal(Value) == -1 &&
1354  ARM_AM::getSOImmVal(-Value) != -1;
1355  }
1356 
1357  bool isThumbModImmNeg1_7() const {
1358  if (!isImm()) return false;
1359  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1360  if (!CE) return false;
1361  int32_t Value = -(int32_t)CE->getValue();
1362  return 0 < Value && Value < 8;
1363  }
1364 
1365  bool isThumbModImmNeg8_255() const {
1366  if (!isImm()) return false;
1367  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1368  if (!CE) return false;
1369  int32_t Value = -(int32_t)CE->getValue();
1370  return 7 < Value && Value < 256;
1371  }
1372 
1373  bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1374  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1375  bool isPostIdxRegShifted() const {
1376  return Kind == k_PostIndexRegister &&
1377  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1378  }
1379  bool isPostIdxReg() const {
1380  return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1381  }
1382  bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1383  if (!isGPRMem())
1384  return false;
1385  // No offset of any kind.
1386  return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1387  (alignOK || Memory.Alignment == Alignment);
1388  }
1389  bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1390  if (!isGPRMem())
1391  return false;
1392 
1393  if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1394  Memory.BaseRegNum))
1395  return false;
1396 
1397  // No offset of any kind.
1398  return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1399  (alignOK || Memory.Alignment == Alignment);
1400  }
1401  bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1402  if (!isGPRMem())
1403  return false;
1404 
1405  if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1406  Memory.BaseRegNum))
1407  return false;
1408 
1409  // No offset of any kind.
1410  return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1411  (alignOK || Memory.Alignment == Alignment);
1412  }
1413  bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1414  if (!isGPRMem())
1415  return false;
1416 
1417  if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1418  Memory.BaseRegNum))
1419  return false;
1420 
1421  // No offset of any kind.
1422  return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1423  (alignOK || Memory.Alignment == Alignment);
1424  }
1425  bool isMemPCRelImm12() const {
1426  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1427  return false;
1428  // Base register must be PC.
1429  if (Memory.BaseRegNum != ARM::PC)
1430  return false;
1431  // Immediate offset in range [-4095, 4095].
1432  if (!Memory.OffsetImm) return true;
1433  int64_t Val = Memory.OffsetImm->getValue();
1434  return (Val > -4096 && Val < 4096) ||
1435  (Val == std::numeric_limits<int32_t>::min());
1436  }
1437 
1438  bool isAlignedMemory() const {
1439  return isMemNoOffset(true);
1440  }
1441 
1442  bool isAlignedMemoryNone() const {
1443  return isMemNoOffset(false, 0);
1444  }
1445 
1446  bool isDupAlignedMemoryNone() const {
1447  return isMemNoOffset(false, 0);
1448  }
1449 
1450  bool isAlignedMemory16() const {
1451  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1452  return true;
1453  return isMemNoOffset(false, 0);
1454  }
1455 
1456  bool isDupAlignedMemory16() const {
1457  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1458  return true;
1459  return isMemNoOffset(false, 0);
1460  }
1461 
1462  bool isAlignedMemory32() const {
1463  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1464  return true;
1465  return isMemNoOffset(false, 0);
1466  }
1467 
1468  bool isDupAlignedMemory32() const {
1469  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1470  return true;
1471  return isMemNoOffset(false, 0);
1472  }
1473 
1474  bool isAlignedMemory64() const {
1475  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1476  return true;
1477  return isMemNoOffset(false, 0);
1478  }
1479 
1480  bool isDupAlignedMemory64() const {
1481  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1482  return true;
1483  return isMemNoOffset(false, 0);
1484  }
1485 
1486  bool isAlignedMemory64or128() const {
1487  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1488  return true;
1489  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1490  return true;
1491  return isMemNoOffset(false, 0);
1492  }
1493 
1494  bool isDupAlignedMemory64or128() const {
1495  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1496  return true;
1497  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1498  return true;
1499  return isMemNoOffset(false, 0);
1500  }
1501 
1502  bool isAlignedMemory64or128or256() const {
1503  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1504  return true;
1505  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1506  return true;
1507  if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1508  return true;
1509  return isMemNoOffset(false, 0);
1510  }
1511 
1512  bool isAddrMode2() const {
1513  if (!isGPRMem() || Memory.Alignment != 0) return false;
1514  // Check for register offset.
1515  if (Memory.OffsetRegNum) return true;
1516  // Immediate offset in range [-4095, 4095].
1517  if (!Memory.OffsetImm) return true;
1518  int64_t Val = Memory.OffsetImm->getValue();
1519  return Val > -4096 && Val < 4096;
1520  }
1521 
1522  bool isAM2OffsetImm() const {
1523  if (!isImm()) return false;
1524  // Immediate offset in range [-4095, 4095].
1525  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1526  if (!CE) return false;
1527  int64_t Val = CE->getValue();
1528  return (Val == std::numeric_limits<int32_t>::min()) ||
1529  (Val > -4096 && Val < 4096);
1530  }
1531 
1532  bool isAddrMode3() const {
1533  // If we have an immediate that's not a constant, treat it as a label
1534  // reference needing a fixup. If it is a constant, it's something else
1535  // and we reject it.
1536  if (isImm() && !isa<MCConstantExpr>(getImm()))
1537  return true;
1538  if (!isGPRMem() || Memory.Alignment != 0) return false;
1539  // No shifts are legal for AM3.
1540  if (Memory.ShiftType != ARM_AM::no_shift) return false;
1541  // Check for register offset.
1542  if (Memory.OffsetRegNum) return true;
1543  // Immediate offset in range [-255, 255].
1544  if (!Memory.OffsetImm) return true;
1545  int64_t Val = Memory.OffsetImm->getValue();
1546  // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1547  // have to check for this too.
1548  return (Val > -256 && Val < 256) ||
1549  Val == std::numeric_limits<int32_t>::min();
1550  }
1551 
1552  bool isAM3Offset() const {
1553  if (isPostIdxReg())
1554  return true;
1555  if (!isImm())
1556  return false;
1557  // Immediate offset in range [-255, 255].
1558  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1559  if (!CE) return false;
1560  int64_t Val = CE->getValue();
1561  // Special case, #-0 is std::numeric_limits<int32_t>::min().
1562  return (Val > -256 && Val < 256) ||
1563  Val == std::numeric_limits<int32_t>::min();
1564  }
1565 
1566  bool isAddrMode5() const {
1567  // If we have an immediate that's not a constant, treat it as a label
1568  // reference needing a fixup. If it is a constant, it's something else
1569  // and we reject it.
1570  if (isImm() && !isa<MCConstantExpr>(getImm()))
1571  return true;
1572  if (!isGPRMem() || Memory.Alignment != 0) return false;
1573  // Check for register offset.
1574  if (Memory.OffsetRegNum) return false;
1575  // Immediate offset in range [-1020, 1020] and a multiple of 4.
1576  if (!Memory.OffsetImm) return true;
1577  int64_t Val = Memory.OffsetImm->getValue();
1578  return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1579  Val == std::numeric_limits<int32_t>::min();
1580  }
1581 
1582  bool isAddrMode5FP16() const {
1583  // If we have an immediate that's not a constant, treat it as a label
1584  // reference needing a fixup. If it is a constant, it's something else
1585  // and we reject it.
1586  if (isImm() && !isa<MCConstantExpr>(getImm()))
1587  return true;
1588  if (!isGPRMem() || Memory.Alignment != 0) return false;
1589  // Check for register offset.
1590  if (Memory.OffsetRegNum) return false;
1591  // Immediate offset in range [-510, 510] and a multiple of 2.
1592  if (!Memory.OffsetImm) return true;
1593  int64_t Val = Memory.OffsetImm->getValue();
1594  return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1595  Val == std::numeric_limits<int32_t>::min();
1596  }
1597 
1598  bool isMemTBB() const {
1599  if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1600  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1601  return false;
1602  return true;
1603  }
1604 
1605  bool isMemTBH() const {
1606  if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1607  Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1608  Memory.Alignment != 0 )
1609  return false;
1610  return true;
1611  }
1612 
1613  bool isMemRegOffset() const {
1614  if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1615  return false;
1616  return true;
1617  }
1618 
1619  bool isT2MemRegOffset() const {
1620  if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1621  Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1622  return false;
1623  // Only lsl #{0, 1, 2, 3} allowed.
1624  if (Memory.ShiftType == ARM_AM::no_shift)
1625  return true;
1626  if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1627  return false;
1628  return true;
1629  }
1630 
1631  bool isMemThumbRR() const {
1632  // Thumb reg+reg addressing is simple. Just two registers, a base and
1633  // an offset. No shifts, negations or any other complicating factors.
1634  if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1635  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1636  return false;
1637  return isARMLowRegister(Memory.BaseRegNum) &&
1638  (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1639  }
1640 
1641  bool isMemThumbRIs4() const {
1642  if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1643  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1644  return false;
1645  // Immediate offset, multiple of 4 in range [0, 124].
1646  if (!Memory.OffsetImm) return true;
1647  int64_t Val = Memory.OffsetImm->getValue();
1648  return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1649  }
1650 
1651  bool isMemThumbRIs2() const {
1652  if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1653  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1654  return false;
1655  // Immediate offset, multiple of 4 in range [0, 62].
1656  if (!Memory.OffsetImm) return true;
1657  int64_t Val = Memory.OffsetImm->getValue();
1658  return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1659  }
1660 
1661  bool isMemThumbRIs1() const {
1662  if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1663  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1664  return false;
1665  // Immediate offset in range [0, 31].
1666  if (!Memory.OffsetImm) return true;
1667  int64_t Val = Memory.OffsetImm->getValue();
1668  return Val >= 0 && Val <= 31;
1669  }
1670 
1671  bool isMemThumbSPI() const {
1672  if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1673  Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1674  return false;
1675  // Immediate offset, multiple of 4 in range [0, 1020].
1676  if (!Memory.OffsetImm) return true;
1677  int64_t Val = Memory.OffsetImm->getValue();
1678  return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1679  }
1680 
1681  bool isMemImm8s4Offset() const {
1682  // If we have an immediate that's not a constant, treat it as a label
1683  // reference needing a fixup. If it is a constant, it's something else
1684  // and we reject it.
1685  if (isImm() && !isa<MCConstantExpr>(getImm()))
1686  return true;
1687  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1688  return false;
1689  // Immediate offset a multiple of 4 in range [-1020, 1020].
1690  if (!Memory.OffsetImm) return true;
1691  int64_t Val = Memory.OffsetImm->getValue();
1692  // Special case, #-0 is std::numeric_limits<int32_t>::min().
1693  return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1694  Val == std::numeric_limits<int32_t>::min();
1695  }
1696  bool isMemImm7s4Offset() const {
1697  // If we have an immediate that's not a constant, treat it as a label
1698  // reference needing a fixup. If it is a constant, it's something else
1699  // and we reject it.
1700  if (isImm() && !isa<MCConstantExpr>(getImm()))
1701  return true;
1702  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1703  !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1704  Memory.BaseRegNum))
1705  return false;
1706  // Immediate offset a multiple of 4 in range [-508, 508].
1707  if (!Memory.OffsetImm) return true;
1708  int64_t Val = Memory.OffsetImm->getValue();
1709  // Special case, #-0 is INT32_MIN.
1710  return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
1711  }
1712  bool isMemImm0_1020s4Offset() const {
1713  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1714  return false;
1715  // Immediate offset a multiple of 4 in range [0, 1020].
1716  if (!Memory.OffsetImm) return true;
1717  int64_t Val = Memory.OffsetImm->getValue();
1718  return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1719  }
1720 
1721  bool isMemImm8Offset() const {
1722  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1723  return false;
1724  // Base reg of PC isn't allowed for these encodings.
1725  if (Memory.BaseRegNum == ARM::PC) return false;
1726  // Immediate offset in range [-255, 255].
1727  if (!Memory.OffsetImm) return true;
1728  int64_t Val = Memory.OffsetImm->getValue();
1729  return (Val == std::numeric_limits<int32_t>::min()) ||
1730  (Val > -256 && Val < 256);
1731  }
1732 
1733  template<unsigned Bits, unsigned RegClassID>
1734  bool isMemImm7ShiftedOffset() const {
1735  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1736  !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1737  return false;
1738 
1739  // Expect an immediate offset equal to an element of the range
1740  // [-127, 127], shifted left by Bits.
1741 
1742  if (!Memory.OffsetImm) return true;
1743  int64_t Val = Memory.OffsetImm->getValue();
1744 
1745  // INT32_MIN is a special-case value (indicating the encoding with
1746  // zero offset and the subtract bit set)
1747  if (Val == INT32_MIN)
1748  return true;
1749 
1750  unsigned Divisor = 1U << Bits;
1751 
1752  // Check that the low bits are zero
1753  if (Val % Divisor != 0)
1754  return false;
1755 
1756  // Check that the remaining offset is within range.
1757  Val /= Divisor;
1758  return (Val >= -127 && Val <= 127);
1759  }
1760 
1761  template <int shift> bool isMemRegRQOffset() const {
1762  if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)
1763  return false;
1764 
1765  if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1766  Memory.BaseRegNum))
1767  return false;
1768  if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1769  Memory.OffsetRegNum))
1770  return false;
1771 
1772  if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1773  return false;
1774 
1775  if (shift > 0 &&
1776  (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1777  return false;
1778 
1779  return true;
1780  }
1781 
1782  template <int shift> bool isMemRegQOffset() const {
1783  if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1784  return false;
1785 
1786  if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1787  Memory.BaseRegNum))
1788  return false;
1789 
1790  if(!Memory.OffsetImm) return true;
1791  static_assert(shift < 56,
1792  "Such that we dont shift by a value higher than 62");
1793  int64_t Val = Memory.OffsetImm->getValue();
1794 
1795  // The value must be a multiple of (1 << shift)
1796  if ((Val & ((1U << shift) - 1)) != 0)
1797  return false;
1798 
1799  // And be in the right range, depending on the amount that it is shifted
1800  // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
1801  // separately.
1802  int64_t Range = (1U << (7+shift)) - 1;
1803  return (Val == INT32_MIN) || (Val > -Range && Val < Range);
1804  }
1805 
1806  bool isMemPosImm8Offset() const {
1807  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1808  return false;
1809  // Immediate offset in range [0, 255].
1810  if (!Memory.OffsetImm) return true;
1811  int64_t Val = Memory.OffsetImm->getValue();
1812  return Val >= 0 && Val < 256;
1813  }
1814 
1815  bool isMemNegImm8Offset() const {
1816  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1817  return false;
1818  // Base reg of PC isn't allowed for these encodings.
1819  if (Memory.BaseRegNum == ARM::PC) return false;
1820  // Immediate offset in range [-255, -1].
1821  if (!Memory.OffsetImm) return false;
1822  int64_t Val = Memory.OffsetImm->getValue();
1823  return (Val == std::numeric_limits<int32_t>::min()) ||
1824  (Val > -256 && Val < 0);
1825  }
1826 
1827  bool isMemUImm12Offset() const {
1828  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1829  return false;
1830  // Immediate offset in range [0, 4095].
1831  if (!Memory.OffsetImm) return true;
1832  int64_t Val = Memory.OffsetImm->getValue();
1833  return (Val >= 0 && Val < 4096);
1834  }
1835 
1836  bool isMemImm12Offset() const {
1837  // If we have an immediate that's not a constant, treat it as a label
1838  // reference needing a fixup. If it is a constant, it's something else
1839  // and we reject it.
1840 
1841  if (isImm() && !isa<MCConstantExpr>(getImm()))
1842  return true;
1843 
1844  if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1845  return false;
1846  // Immediate offset in range [-4095, 4095].
1847  if (!Memory.OffsetImm) return true;
1848  int64_t Val = Memory.OffsetImm->getValue();
1849  return (Val > -4096 && Val < 4096) ||
1850  (Val == std::numeric_limits<int32_t>::min());
1851  }
1852 
1853  bool isConstPoolAsmImm() const {
1854  // Delay processing of Constant Pool Immediate, this will turn into
1855  // a constant. Match no other operand
1856  return (isConstantPoolImm());
1857  }
1858 
1859  bool isPostIdxImm8() const {
1860  if (!isImm()) return false;
1861  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1862  if (!CE) return false;
1863  int64_t Val = CE->getValue();
1864  return (Val > -256 && Val < 256) ||
1865  (Val == std::numeric_limits<int32_t>::min());
1866  }
1867 
1868  bool isPostIdxImm8s4() const {
1869  if (!isImm()) return false;
1870  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1871  if (!CE) return false;
1872  int64_t Val = CE->getValue();
1873  return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1874  (Val == std::numeric_limits<int32_t>::min());
1875  }
1876 
1877  bool isMSRMask() const { return Kind == k_MSRMask; }
1878  bool isBankedReg() const { return Kind == k_BankedReg; }
1879  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1880 
1881  // NEON operands.
1882  bool isSingleSpacedVectorList() const {
1883  return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1884  }
1885 
1886  bool isDoubleSpacedVectorList() const {
1887  return Kind == k_VectorList && VectorList.isDoubleSpaced;
1888  }
1889 
1890  bool isVecListOneD() const {
1891  if (!isSingleSpacedVectorList()) return false;
1892  return VectorList.Count == 1;
1893  }
1894 
1895  bool isVecListTwoMQ() const {
1896  return isSingleSpacedVectorList() && VectorList.Count == 2 &&
1897  ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1898  VectorList.RegNum);
1899  }
1900 
1901  bool isVecListDPair() const {
1902  if (!isSingleSpacedVectorList()) return false;
1903  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1904  .contains(VectorList.RegNum));
1905  }
1906 
1907  bool isVecListThreeD() const {
1908  if (!isSingleSpacedVectorList()) return false;
1909  return VectorList.Count == 3;
1910  }
1911 
1912  bool isVecListFourD() const {
1913  if (!isSingleSpacedVectorList()) return false;
1914  return VectorList.Count == 4;
1915  }
1916 
1917  bool isVecListDPairSpaced() const {
1918  if (Kind != k_VectorList) return false;
1919  if (isSingleSpacedVectorList()) return false;
1920  return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1921  .contains(VectorList.RegNum));
1922  }
1923 
1924  bool isVecListThreeQ() const {
1925  if (!isDoubleSpacedVectorList()) return false;
1926  return VectorList.Count == 3;
1927  }
1928 
1929  bool isVecListFourQ() const {
1930  if (!isDoubleSpacedVectorList()) return false;
1931  return VectorList.Count == 4;
1932  }
1933 
1934  bool isVecListFourMQ() const {
1935  return isSingleSpacedVectorList() && VectorList.Count == 4 &&
1936  ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1937  VectorList.RegNum);
1938  }
1939 
1940  bool isSingleSpacedVectorAllLanes() const {
1941  return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1942  }
1943 
1944  bool isDoubleSpacedVectorAllLanes() const {
1945  return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1946  }
1947 
1948  bool isVecListOneDAllLanes() const {
1949  if (!isSingleSpacedVectorAllLanes()) return false;
1950  return VectorList.Count == 1;
1951  }
1952 
1953  bool isVecListDPairAllLanes() const {
1954  if (!isSingleSpacedVectorAllLanes()) return false;
1955  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1956  .contains(VectorList.RegNum));
1957  }
1958 
1959  bool isVecListDPairSpacedAllLanes() const {
1960  if (!isDoubleSpacedVectorAllLanes()) return false;
1961  return VectorList.Count == 2;
1962  }
1963 
1964  bool isVecListThreeDAllLanes() const {
1965  if (!isSingleSpacedVectorAllLanes()) return false;
1966  return VectorList.Count == 3;
1967  }
1968 
1969  bool isVecListThreeQAllLanes() const {
1970  if (!isDoubleSpacedVectorAllLanes()) return false;
1971  return VectorList.Count == 3;
1972  }
1973 
1974  bool isVecListFourDAllLanes() const {
1975  if (!isSingleSpacedVectorAllLanes()) return false;
1976  return VectorList.Count == 4;
1977  }
1978 
1979  bool isVecListFourQAllLanes() const {
1980  if (!isDoubleSpacedVectorAllLanes()) return false;
1981  return VectorList.Count == 4;
1982  }
1983 
1984  bool isSingleSpacedVectorIndexed() const {
1985  return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1986  }
1987 
1988  bool isDoubleSpacedVectorIndexed() const {
1989  return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1990  }
1991 
1992  bool isVecListOneDByteIndexed() const {
1993  if (!isSingleSpacedVectorIndexed()) return false;
1994  return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1995  }
1996 
1997  bool isVecListOneDHWordIndexed() const {
1998  if (!isSingleSpacedVectorIndexed()) return false;
1999  return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
2000  }
2001 
2002  bool isVecListOneDWordIndexed() const {
2003  if (!isSingleSpacedVectorIndexed()) return false;
2004  return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
2005  }
2006 
2007  bool isVecListTwoDByteIndexed() const {
2008  if (!isSingleSpacedVectorIndexed()) return false;
2009  return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
2010  }
2011 
2012  bool isVecListTwoDHWordIndexed() const {
2013  if (!isSingleSpacedVectorIndexed()) return false;
2014  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2015  }
2016 
2017  bool isVecListTwoQWordIndexed() const {
2018  if (!isDoubleSpacedVectorIndexed()) return false;
2019  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2020  }
2021 
2022  bool isVecListTwoQHWordIndexed() const {
2023  if (!isDoubleSpacedVectorIndexed()) return false;
2024  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2025  }
2026 
2027  bool isVecListTwoDWordIndexed() const {
2028  if (!isSingleSpacedVectorIndexed()) return false;
2029  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2030  }
2031 
2032  bool isVecListThreeDByteIndexed() const {
2033  if (!isSingleSpacedVectorIndexed()) return false;
2034  return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
2035  }
2036 
2037  bool isVecListThreeDHWordIndexed() const {
2038  if (!isSingleSpacedVectorIndexed()) return false;
2039  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2040  }
2041 
2042  bool isVecListThreeQWordIndexed() const {
2043  if (!isDoubleSpacedVectorIndexed()) return false;
2044  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2045  }
2046 
2047  bool isVecListThreeQHWordIndexed() const {
2048  if (!isDoubleSpacedVectorIndexed()) return false;
2049  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2050  }
2051 
2052  bool isVecListThreeDWordIndexed() const {
2053  if (!isSingleSpacedVectorIndexed()) return false;
2054  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2055  }
2056 
2057  bool isVecListFourDByteIndexed() const {
2058  if (!isSingleSpacedVectorIndexed()) return false;
2059  return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
2060  }
2061 
2062  bool isVecListFourDHWordIndexed() const {
2063  if (!isSingleSpacedVectorIndexed()) return false;
2064  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2065  }
2066 
2067  bool isVecListFourQWordIndexed() const {
2068  if (!isDoubleSpacedVectorIndexed()) return false;
2069  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2070  }
2071 
2072  bool isVecListFourQHWordIndexed() const {
2073  if (!isDoubleSpacedVectorIndexed()) return false;
2074  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2075  }
2076 
2077  bool isVecListFourDWordIndexed() const {
2078  if (!isSingleSpacedVectorIndexed()) return false;
2079  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2080  }
2081 
2082  bool isVectorIndex() const { return Kind == k_VectorIndex; }
2083 
2084  template <unsigned NumLanes>
2085  bool isVectorIndexInRange() const {
2086  if (Kind != k_VectorIndex) return false;
2087  return VectorIndex.Val < NumLanes;
2088  }
2089 
2090  bool isVectorIndex8() const { return isVectorIndexInRange<8>(); }
2091  bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
2092  bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
2093  bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
2094 
2095  template<int PermittedValue, int OtherPermittedValue>
2096  bool isMVEPairVectorIndex() const {
2097  if (Kind != k_VectorIndex) return false;
2098  return VectorIndex.Val == PermittedValue ||
2099  VectorIndex.Val == OtherPermittedValue;
2100  }
2101 
2102  bool isNEONi8splat() const {
2103  if (!isImm()) return false;
2104  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2105  // Must be a constant.
2106  if (!CE) return false;
2107  int64_t Value = CE->getValue();
2108  // i8 value splatted across 8 bytes. The immediate is just the 8 byte
2109  // value.
2110  return Value >= 0 && Value < 256;
2111  }
2112 
2113  bool isNEONi16splat() const {
2114  if (isNEONByteReplicate(2))
2115  return false; // Leave that for bytes replication and forbid by default.
2116  if (!isImm())
2117  return false;
2118  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2119  // Must be a constant.
2120  if (!CE) return false;
2121  unsigned Value = CE->getValue();
2122  return ARM_AM::isNEONi16splat(Value);
2123  }
2124 
2125  bool isNEONi16splatNot() const {
2126  if (!isImm())
2127  return false;
2128  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2129  // Must be a constant.
2130  if (!CE) return false;
2131  unsigned Value = CE->getValue();
2132  return ARM_AM::isNEONi16splat(~Value & 0xffff);
2133  }
2134 
2135  bool isNEONi32splat() const {
2136  if (isNEONByteReplicate(4))
2137  return false; // Leave that for bytes replication and forbid by default.
2138  if (!isImm())
2139  return false;
2140  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2141  // Must be a constant.
2142  if (!CE) return false;
2143  unsigned Value = CE->getValue();
2144  return ARM_AM::isNEONi32splat(Value);
2145  }
2146 
2147  bool isNEONi32splatNot() const {
2148  if (!isImm())
2149  return false;
2150  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2151  // Must be a constant.
2152  if (!CE) return false;
2153  unsigned Value = CE->getValue();
2154  return ARM_AM::isNEONi32splat(~Value);
2155  }
2156 
2157  static bool isValidNEONi32vmovImm(int64_t Value) {
2158  // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2159  // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2160  return ((Value & 0xffffffffffffff00) == 0) ||
2161  ((Value & 0xffffffffffff00ff) == 0) ||
2162  ((Value & 0xffffffffff00ffff) == 0) ||
2163  ((Value & 0xffffffff00ffffff) == 0) ||
2164  ((Value & 0xffffffffffff00ff) == 0xff) ||
2165  ((Value & 0xffffffffff00ffff) == 0xffff);
2166  }
2167 
2168  bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
2169  assert((Width == 8 || Width == 16 || Width == 32) &&
2170  "Invalid element width");
2171  assert(NumElems * Width <= 64 && "Invalid result width");
2172 
2173  if (!isImm())
2174  return false;
2175  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2176  // Must be a constant.
2177  if (!CE)
2178  return false;
2179  int64_t Value = CE->getValue();
2180  if (!Value)
2181  return false; // Don't bother with zero.
2182  if (Inv)
2183  Value = ~Value;
2184 
2185  uint64_t Mask = (1ull << Width) - 1;
2186  uint64_t Elem = Value & Mask;
2187  if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2188  return false;
2189  if (Width == 32 && !isValidNEONi32vmovImm(Elem))
2190  return false;
2191 
2192  for (unsigned i = 1; i < NumElems; ++i) {
2193  Value >>= Width;
2194  if ((Value & Mask) != Elem)
2195  return false;
2196  }
2197  return true;
2198  }
2199 
2200  bool isNEONByteReplicate(unsigned NumBytes) const {
2201  return isNEONReplicate(8, NumBytes, false);
2202  }
2203 
2204  static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
2205  assert((FromW == 8 || FromW == 16 || FromW == 32) &&
2206  "Invalid source width");
2207  assert((ToW == 16 || ToW == 32 || ToW == 64) &&
2208  "Invalid destination width");
2209  assert(FromW < ToW && "ToW is not less than FromW");
2210  }
2211 
2212  template<unsigned FromW, unsigned ToW>
2213  bool isNEONmovReplicate() const {
2214  checkNeonReplicateArgs(FromW, ToW);
2215  if (ToW == 64 && isNEONi64splat())
2216  return false;
2217  return isNEONReplicate(FromW, ToW / FromW, false);
2218  }
2219 
2220  template<unsigned FromW, unsigned ToW>
2221  bool isNEONinvReplicate() const {
2222  checkNeonReplicateArgs(FromW, ToW);
2223  return isNEONReplicate(FromW, ToW / FromW, true);
2224  }
2225 
2226  bool isNEONi32vmov() const {
2227  if (isNEONByteReplicate(4))
2228  return false; // Let it to be classified as byte-replicate case.
2229  if (!isImm())
2230  return false;
2231  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2232  // Must be a constant.
2233  if (!CE)
2234  return false;
2235  return isValidNEONi32vmovImm(CE->getValue());
2236  }
2237 
2238  bool isNEONi32vmovNeg() const {
2239  if (!isImm()) return false;
2240  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2241  // Must be a constant.
2242  if (!CE) return false;
2243  return isValidNEONi32vmovImm(~CE->getValue());
2244  }
2245 
2246  bool isNEONi64splat() const {
2247  if (!isImm()) return false;
2248  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2249  // Must be a constant.
2250  if (!CE) return false;
2251  uint64_t Value = CE->getValue();
2252  // i64 value with each byte being either 0 or 0xff.
2253  for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2254  if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2255  return true;
2256  }
2257 
2258  template<int64_t Angle, int64_t Remainder>
2259  bool isComplexRotation() const {
2260  if (!isImm()) return false;
2261 
2262  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2263  if (!CE) return false;
2264  uint64_t Value = CE->getValue();
2265 
2266  return (Value % Angle == Remainder && Value <= 270);
2267  }
2268 
2269  bool isMVELongShift() const {
2270  if (!isImm()) return false;
2271  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2272  // Must be a constant.
2273  if (!CE) return false;
2274  uint64_t Value = CE->getValue();
2275  return Value >= 1 && Value <= 32;
2276  }
2277 
2278  bool isITCondCodeNoAL() const {
2279  if (!isITCondCode()) return false;
2281  return CC != ARMCC::AL;
2282  }
2283 
2284  bool isITCondCodeRestrictedI() const {
2285  if (!isITCondCode())
2286  return false;
2288  return CC == ARMCC::EQ || CC == ARMCC::NE;
2289  }
2290 
2291  bool isITCondCodeRestrictedS() const {
2292  if (!isITCondCode())
2293  return false;
2295  return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
2296  CC == ARMCC::GE;
2297  }
2298 
2299  bool isITCondCodeRestrictedU() const {
2300  if (!isITCondCode())
2301  return false;
2303  return CC == ARMCC::HS || CC == ARMCC::HI;
2304  }
2305 
2306  bool isITCondCodeRestrictedFP() const {
2307  if (!isITCondCode())
2308  return false;
2310  return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
2311  CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
2312  }
2313 
2314  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2315  // Add as immediates when possible. Null MCExpr = 0.
2316  if (!Expr)
2318  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2319  Inst.addOperand(MCOperand::createImm(CE->getValue()));
2320  else
2321  Inst.addOperand(MCOperand::createExpr(Expr));
2322  }
2323 
2324  void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2325  assert(N == 1 && "Invalid number of operands!");
2326  addExpr(Inst, getImm());
2327  }
2328 
2329  void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2330  assert(N == 1 && "Invalid number of operands!");
2331  addExpr(Inst, getImm());
2332  }
2333 
2334  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2335  assert(N == 2 && "Invalid number of operands!");
2336  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2337  unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2338  Inst.addOperand(MCOperand::createReg(RegNum));
2339  }
2340 
2341  void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2342  assert(N == 2 && "Invalid number of operands!");
2343  Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2344  unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2345  Inst.addOperand(MCOperand::createReg(RegNum));
2346  }
2347 
2348  void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2349  assert(N == 3 && "Invalid number of operands!");
2350  addVPTPredNOperands(Inst, N-1);
2351  unsigned RegNum;
2352  if (getVPTPred() == ARMVCC::None) {
2353  RegNum = 0;
2354  } else {
2355  unsigned NextOpIndex = Inst.getNumOperands();
2356  const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
2357  int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
2358  assert(TiedOp >= 0 &&
2359  "Inactive register in vpred_r is not tied to an output!");
2360  RegNum = Inst.getOperand(TiedOp).getReg();
2361  }
2362  Inst.addOperand(MCOperand::createReg(RegNum));
2363  }
2364 
2365  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2366  assert(N == 1 && "Invalid number of operands!");
2367  Inst.addOperand(MCOperand::createImm(getCoproc()));
2368  }
2369 
2370  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2371  assert(N == 1 && "Invalid number of operands!");
2372  Inst.addOperand(MCOperand::createImm(getCoproc()));
2373  }
2374 
2375  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2376  assert(N == 1 && "Invalid number of operands!");
2377  Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2378  }
2379 
2380  void addITMaskOperands(MCInst &Inst, unsigned N) const {
2381  assert(N == 1 && "Invalid number of operands!");
2382  Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2383  }
2384 
2385  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2386  assert(N == 1 && "Invalid number of operands!");
2387  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2388  }
2389 
2390  void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2391  assert(N == 1 && "Invalid number of operands!");
2393  }
2394 
2395  void addCCOutOperands(MCInst &Inst, unsigned N) const {
2396  assert(N == 1 && "Invalid number of operands!");
2398  }
2399 
2400  void addRegOperands(MCInst &Inst, unsigned N) const {
2401  assert(N == 1 && "Invalid number of operands!");
2403  }
2404 
2405  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2406  assert(N == 3 && "Invalid number of operands!");
2407  assert(isRegShiftedReg() &&
2408  "addRegShiftedRegOperands() on non-RegShiftedReg!");
2409  Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2410  Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2412  ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2413  }
2414 
2415  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2416  assert(N == 2 && "Invalid number of operands!");
2417  assert(isRegShiftedImm() &&
2418  "addRegShiftedImmOperands() on non-RegShiftedImm!");
2419  Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2420  // Shift of #32 is encoded as 0 where permitted
2421  unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2423  ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2424  }
2425 
2426  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2427  assert(N == 1 && "Invalid number of operands!");
2428  Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2429  ShifterImm.Imm));
2430  }
2431 
2432  void addRegListOperands(MCInst &Inst, unsigned N) const {
2433  assert(N == 1 && "Invalid number of operands!");
2434  const SmallVectorImpl<unsigned> &RegList = getRegList();
2436  I = RegList.begin(), E = RegList.end(); I != E; ++I)
2438  }
2439 
2440  void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2441  assert(N == 1 && "Invalid number of operands!");
2442  const SmallVectorImpl<unsigned> &RegList = getRegList();
2444  I = RegList.begin(), E = RegList.end(); I != E; ++I)
2446  }
2447 
2448  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2449  addRegListOperands(Inst, N);
2450  }
2451 
2452  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2453  addRegListOperands(Inst, N);
2454  }
2455 
2456  void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2457  addRegListOperands(Inst, N);
2458  }
2459 
2460  void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2461  addRegListOperands(Inst, N);
2462  }
2463 
2464  void addRotImmOperands(MCInst &Inst, unsigned N) const {
2465  assert(N == 1 && "Invalid number of operands!");
2466  // Encoded as val>>3. The printer handles display as 8, 16, 24.
2467  Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2468  }
2469 
2470  void addModImmOperands(MCInst &Inst, unsigned N) const {
2471  assert(N == 1 && "Invalid number of operands!");
2472 
2473  // Support for fixups (MCFixup)
2474  if (isImm())
2475  return addImmOperands(Inst, N);
2476 
2477  Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2478  }
2479 
2480  void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2481  assert(N == 1 && "Invalid number of operands!");
2482  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2483  uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2484  Inst.addOperand(MCOperand::createImm(Enc));
2485  }
2486 
2487  void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2488  assert(N == 1 && "Invalid number of operands!");
2489  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2490  uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2491  Inst.addOperand(MCOperand::createImm(Enc));
2492  }
2493 
2494  void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2495  assert(N == 1 && "Invalid number of operands!");
2496  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2497  uint32_t Val = -CE->getValue();
2498  Inst.addOperand(MCOperand::createImm(Val));
2499  }
2500 
2501  void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2502  assert(N == 1 && "Invalid number of operands!");
2503  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2504  uint32_t Val = -CE->getValue();
2505  Inst.addOperand(MCOperand::createImm(Val));
2506  }
2507 
2508  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2509  assert(N == 1 && "Invalid number of operands!");
2510  // Munge the lsb/width into a bitfield mask.
2511  unsigned lsb = Bitfield.LSB;
2512  unsigned width = Bitfield.Width;
2513  // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2514  uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2515  (32 - (lsb + width)));
2516  Inst.addOperand(MCOperand::createImm(Mask));
2517  }
2518 
2519  void addImmOperands(MCInst &Inst, unsigned N) const {
2520  assert(N == 1 && "Invalid number of operands!");
2521  addExpr(Inst, getImm());
2522  }
2523 
2524  void addFBits16Operands(MCInst &Inst, unsigned N) const {
2525  assert(N == 1 && "Invalid number of operands!");
2526  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2527  Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2528  }
2529 
2530  void addFBits32Operands(MCInst &Inst, unsigned N) const {
2531  assert(N == 1 && "Invalid number of operands!");
2532  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2533  Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2534  }
2535 
2536  void addFPImmOperands(MCInst &Inst, unsigned N) const {
2537  assert(N == 1 && "Invalid number of operands!");
2538  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2539  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2540  Inst.addOperand(MCOperand::createImm(Val));
2541  }
2542 
2543  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2544  assert(N == 1 && "Invalid number of operands!");
2545  // FIXME: We really want to scale the value here, but the LDRD/STRD
2546  // instruction don't encode operands that way yet.
2547  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2549  }
2550 
2551  void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2552  assert(N == 1 && "Invalid number of operands!");
2553  // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2554  // instruction don't encode operands that way yet.
2555  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2557  }
2558 
2559  void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2560  assert(N == 1 && "Invalid number of operands!");
2561  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2562  assert(CE != nullptr && "Invalid operand type!");
2564  }
2565 
2566  void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2567  assert(N == 1 && "Invalid number of operands!");
2568  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2569  assert(CE != nullptr && "Invalid operand type!");
2571  }
2572 
2573  void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2574  assert(N == 1 && "Invalid number of operands!");
2575  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2576  assert(CE != nullptr && "Invalid operand type!");
2578  }
2579 
2580  void addImm7Operands(MCInst &Inst, unsigned N) const {
2581  assert(N == 1 && "Invalid number of operands!");
2582  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2583  assert(CE != nullptr && "Invalid operand type!");
2585  }
2586 
2587  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2588  assert(N == 1 && "Invalid number of operands!");
2589  // The immediate is scaled by four in the encoding and is stored
2590  // in the MCInst as such. Lop off the low two bits here.
2591  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2592  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2593  }
2594 
2595  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2596  assert(N == 1 && "Invalid number of operands!");
2597  // The immediate is scaled by four in the encoding and is stored
2598  // in the MCInst as such. Lop off the low two bits here.
2599  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2600  Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2601  }
2602 
2603  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2604  assert(N == 1 && "Invalid number of operands!");
2605  // The immediate is scaled by four in the encoding and is stored
2606  // in the MCInst as such. Lop off the low two bits here.
2607  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2608  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2609  }
2610 
2611  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2612  assert(N == 1 && "Invalid number of operands!");
2613  // The constant encodes as the immediate-1, and we store in the instruction
2614  // the bits as encoded, so subtract off one here.
2615  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2616  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2617  }
2618 
2619  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2620  assert(N == 1 && "Invalid number of operands!");
2621  // The constant encodes as the immediate-1, and we store in the instruction
2622  // the bits as encoded, so subtract off one here.
2623  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2624  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2625  }
2626 
2627  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2628  assert(N == 1 && "Invalid number of operands!");
2629  // The constant encodes as the immediate, except for 32, which encodes as
2630  // zero.
2631  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2632  unsigned Imm = CE->getValue();
2633  Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2634  }
2635 
2636  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2637  assert(N == 1 && "Invalid number of operands!");
2638  // An ASR value of 32 encodes as 0, so that's how we want to add it to
2639  // the instruction as well.
2640  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2641  int Val = CE->getValue();
2642  Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2643  }
2644 
2645  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2646  assert(N == 1 && "Invalid number of operands!");
2647  // The operand is actually a t2_so_imm, but we have its bitwise
2648  // negation in the assembly source, so twiddle it here.
2649  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2651  }
2652 
2653  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2654  assert(N == 1 && "Invalid number of operands!");
2655  // The operand is actually a t2_so_imm, but we have its
2656  // negation in the assembly source, so twiddle it here.
2657  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2659  }
2660 
2661  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2662  assert(N == 1 && "Invalid number of operands!");
2663  // The operand is actually an imm0_4095, but we have its
2664  // negation in the assembly source, so twiddle it here.
2665  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2667  }
2668 
2669  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2670  if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2671  Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2672  return;
2673  }
2674 
2675  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2676  assert(SR && "Unknown value type!");
2678  }
2679 
2680  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2681  assert(N == 1 && "Invalid number of operands!");
2682  if (isImm()) {
2683  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2684  if (CE) {
2686  return;
2687  }
2688 
2689  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2690 
2691  assert(SR && "Unknown value type!");
2693  return;
2694  }
2695 
2696  assert(isGPRMem() && "Unknown value type!");
2697  assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2698  Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2699  }
2700 
2701  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2702  assert(N == 1 && "Invalid number of operands!");
2703  Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2704  }
2705 
2706  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2707  assert(N == 1 && "Invalid number of operands!");
2708  Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2709  }
2710 
2711  void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2712  assert(N == 1 && "Invalid number of operands!");
2713  Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2714  }
2715 
2716  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2717  assert(N == 1 && "Invalid number of operands!");
2718  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2719  }
2720 
2721  void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2722  assert(N == 1 && "Invalid number of operands!");
2723  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2724  }
2725 
2726  void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2727  assert(N == 1 && "Invalid number of operands!");
2728  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2729  }
2730 
2731  void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2732  assert(N == 1 && "Invalid number of operands!");
2733  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2734  }
2735 
2736  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2737  assert(N == 1 && "Invalid number of operands!");
2738  int32_t Imm = Memory.OffsetImm->getValue();
2739  Inst.addOperand(MCOperand::createImm(Imm));
2740  }
2741 
2742  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2743  assert(N == 1 && "Invalid number of operands!");
2744  assert(isImm() && "Not an immediate!");
2745 
2746  // If we have an immediate that's not a constant, treat it as a label
2747  // reference needing a fixup.
2748  if (!isa<MCConstantExpr>(getImm())) {
2749  Inst.addOperand(MCOperand::createExpr(getImm()));
2750  return;
2751  }
2752 
2753  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2754  int Val = CE->getValue();
2755  Inst.addOperand(MCOperand::createImm(Val));
2756  }
2757 
2758  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2759  assert(N == 2 && "Invalid number of operands!");
2760  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2761  Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2762  }
2763 
2764  void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2765  addAlignedMemoryOperands(Inst, N);
2766  }
2767 
2768  void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2769  addAlignedMemoryOperands(Inst, N);
2770  }
2771 
2772  void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2773  addAlignedMemoryOperands(Inst, N);
2774  }
2775 
2776  void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2777  addAlignedMemoryOperands(Inst, N);
2778  }
2779 
2780  void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2781  addAlignedMemoryOperands(Inst, N);
2782  }
2783 
2784  void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2785  addAlignedMemoryOperands(Inst, N);
2786  }
2787 
2788  void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2789  addAlignedMemoryOperands(Inst, N);
2790  }
2791 
2792  void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2793  addAlignedMemoryOperands(Inst, N);
2794  }
2795 
2796  void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2797  addAlignedMemoryOperands(Inst, N);
2798  }
2799 
2800  void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2801  addAlignedMemoryOperands(Inst, N);
2802  }
2803 
2804  void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2805  addAlignedMemoryOperands(Inst, N);
2806  }
2807 
2808  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2809  assert(N == 3 && "Invalid number of operands!");
2810  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2811  if (!Memory.OffsetRegNum) {
2812  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2813  // Special case for #-0
2814  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2815  if (Val < 0) Val = -Val;
2816  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2817  } else {
2818  // For register offset, we encode the shift type and negation flag
2819  // here.
2820  Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2821  Memory.ShiftImm, Memory.ShiftType);
2822  }
2823  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2824  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2825  Inst.addOperand(MCOperand::createImm(Val));
2826  }
2827 
2828  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2829  assert(N == 2 && "Invalid number of operands!");
2830  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2831  assert(CE && "non-constant AM2OffsetImm operand!");
2832  int32_t Val = CE->getValue();
2833  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2834  // Special case for #-0
2835  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2836  if (Val < 0) Val = -Val;
2837  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2839  Inst.addOperand(MCOperand::createImm(Val));
2840  }
2841 
2842  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2843  assert(N == 3 && "Invalid number of operands!");
2844  // If we have an immediate that's not a constant, treat it as a label
2845  // reference needing a fixup. If it is a constant, it's something else
2846  // and we reject it.
2847  if (isImm()) {
2848  Inst.addOperand(MCOperand::createExpr(getImm()));
2851  return;
2852  }
2853 
2854  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2855  if (!Memory.OffsetRegNum) {
2856  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2857  // Special case for #-0
2858  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2859  if (Val < 0) Val = -Val;
2860  Val = ARM_AM::getAM3Opc(AddSub, Val);
2861  } else {
2862  // For register offset, we encode the shift type and negation flag
2863  // here.
2864  Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2865  }
2866  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2867  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2868  Inst.addOperand(MCOperand::createImm(Val));
2869  }
2870 
2871  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2872  assert(N == 2 && "Invalid number of operands!");
2873  if (Kind == k_PostIndexRegister) {
2874  int32_t Val =
2875  ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2876  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2877  Inst.addOperand(MCOperand::createImm(Val));
2878  return;
2879  }
2880 
2881  // Constant offset.
2882  const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2883  int32_t Val = CE->getValue();
2884  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2885  // Special case for #-0
2886  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2887  if (Val < 0) Val = -Val;
2888  Val = ARM_AM::getAM3Opc(AddSub, Val);
2890  Inst.addOperand(MCOperand::createImm(Val));
2891  }
2892 
2893  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2894  assert(N == 2 && "Invalid number of operands!");
2895  // If we have an immediate that's not a constant, treat it as a label
2896  // reference needing a fixup. If it is a constant, it's something else
2897  // and we reject it.
2898  if (isImm()) {
2899  Inst.addOperand(MCOperand::createExpr(getImm()));
2901  return;
2902  }
2903 
2904  // The lower two bits are always zero and as such are not encoded.
2905  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2906  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2907  // Special case for #-0
2908  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2909  if (Val < 0) Val = -Val;
2910  Val = ARM_AM::getAM5Opc(AddSub, Val);
2911  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2912  Inst.addOperand(MCOperand::createImm(Val));
2913  }
2914 
2915  void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2916  assert(N == 2 && "Invalid number of operands!");
2917  // If we have an immediate that's not a constant, treat it as a label
2918  // reference needing a fixup. If it is a constant, it's something else
2919  // and we reject it.
2920  if (isImm()) {
2921  Inst.addOperand(MCOperand::createExpr(getImm()));
2923  return;
2924  }
2925 
2926  // The lower bit is always zero and as such is not encoded.
2927  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2928  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2929  // Special case for #-0
2930  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2931  if (Val < 0) Val = -Val;
2932  Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2933  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2934  Inst.addOperand(MCOperand::createImm(Val));
2935  }
2936 
2937  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2938  assert(N == 2 && "Invalid number of operands!");
2939  // If we have an immediate that's not a constant, treat it as a label
2940  // reference needing a fixup. If it is a constant, it's something else
2941  // and we reject it.
2942  if (isImm()) {
2943  Inst.addOperand(MCOperand::createExpr(getImm()));
2945  return;
2946  }
2947 
2948  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2949  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2950  Inst.addOperand(MCOperand::createImm(Val));
2951  }
2952 
2953  void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
2954  assert(N == 2 && "Invalid number of operands!");
2955  // If we have an immediate that's not a constant, treat it as a label
2956  // reference needing a fixup. If it is a constant, it's something else
2957  // and we reject it.
2958  if (isImm()) {
2959  Inst.addOperand(MCOperand::createExpr(getImm()));
2961  return;
2962  }
2963 
2964  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2965  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2966  Inst.addOperand(MCOperand::createImm(Val));
2967  }
2968 
2969  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2970  assert(N == 2 && "Invalid number of operands!");
2971  // The lower two bits are always zero and as such are not encoded.
2972  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2973  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2974  Inst.addOperand(MCOperand::createImm(Val));
2975  }
2976 
2977  void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
2978  assert(N == 2 && "Invalid number of operands!");
2979  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2980  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2981  Inst.addOperand(MCOperand::createImm(Val));
2982  }
2983 
2984  void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
2985  assert(N == 2 && "Invalid number of operands!");
2986  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2987  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2988  }
2989 
2990  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2991  assert(N == 2 && "Invalid number of operands!");
2992  // If this is an immediate, it's a label reference.
2993  if (isImm()) {
2994  addExpr(Inst, getImm());
2996  return;
2997  }
2998 
2999  // Otherwise, it's a normal memory reg+offset.
3000  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3001  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3002  Inst.addOperand(MCOperand::createImm(Val));
3003  }
3004 
3005  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3006  assert(N == 2 && "Invalid number of operands!");
3007  // If this is an immediate, it's a label reference.
3008  if (isImm()) {
3009  addExpr(Inst, getImm());
3011  return;
3012  }
3013 
3014  // Otherwise, it's a normal memory reg+offset.
3015  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3016  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3017  Inst.addOperand(MCOperand::createImm(Val));
3018  }
3019 
3020  void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3021  assert(N == 1 && "Invalid number of operands!");
3022  // This is container for the immediate that we will create the constant
3023  // pool from
3024  addExpr(Inst, getConstantPoolImm());
3025  return;
3026  }
3027 
3028  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3029  assert(N == 2 && "Invalid number of operands!");
3030  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3031  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3032  }
3033 
3034  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3035  assert(N == 2 && "Invalid number of operands!");
3036  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3037  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3038  }
3039 
3040  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3041  assert(N == 3 && "Invalid number of operands!");
3042  unsigned Val =
3044  Memory.ShiftImm, Memory.ShiftType);
3045  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3046  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3047  Inst.addOperand(MCOperand::createImm(Val));
3048  }
3049 
3050  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3051  assert(N == 3 && "Invalid number of operands!");
3052  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3053  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3054  Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3055  }
3056 
3057  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3058  assert(N == 2 && "Invalid number of operands!");
3059  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3060  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3061  }
3062 
3063  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3064  assert(N == 2 && "Invalid number of operands!");
3065  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3066  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3067  Inst.addOperand(MCOperand::createImm(Val));
3068  }
3069 
3070  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3071  assert(N == 2 && "Invalid number of operands!");
3072  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
3073  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3074  Inst.addOperand(MCOperand::createImm(Val));
3075  }
3076 
3077  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3078  assert(N == 2 && "Invalid number of operands!");
3079  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
3080  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3081  Inst.addOperand(MCOperand::createImm(Val));
3082  }
3083 
3084  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3085  assert(N == 2 && "Invalid number of operands!");
3086  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3087  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3088  Inst.addOperand(MCOperand::createImm(Val));
3089  }
3090 
3091  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3092  assert(N == 1 && "Invalid number of operands!");
3093  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3094  assert(CE && "non-constant post-idx-imm8 operand!");
3095  int Imm = CE->getValue();
3096  bool isAdd = Imm >= 0;
3097  if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3098  Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3099  Inst.addOperand(MCOperand::createImm(Imm));
3100  }
3101 
3102  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3103  assert(N == 1 && "Invalid number of operands!");
3104  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3105  assert(CE && "non-constant post-idx-imm8s4 operand!");
3106  int Imm = CE->getValue();
3107  bool isAdd = Imm >= 0;
3108  if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3109  // Immediate is scaled by 4.
3110  Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3111  Inst.addOperand(MCOperand::createImm(Imm));
3112  }
3113 
3114  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3115  assert(N == 2 && "Invalid number of operands!");
3116  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3117  Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
3118  }
3119 
3120  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3121  assert(N == 2 && "Invalid number of operands!");
3122  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3123  // The sign, shift type, and shift amount are encoded in a single operand
3124  // using the AM2 encoding helpers.
3125  ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3126  unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3127  PostIdxReg.ShiftTy);
3128  Inst.addOperand(MCOperand::createImm(Imm));
3129  }
3130 
3131  void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3132  assert(N == 1 && "Invalid number of operands!");
3133  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3135  }
3136 
3137  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3138  assert(N == 1 && "Invalid number of operands!");
3139  Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
3140  }
3141 
3142  void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3143  assert(N == 1 && "Invalid number of operands!");
3144  Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
3145  }
3146 
3147  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3148  assert(N == 1 && "Invalid number of operands!");
3149  Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
3150  }
3151 
3152  void addVecListOperands(MCInst &Inst, unsigned N) const {
3153  assert(N == 1 && "Invalid number of operands!");
3154  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3155  }
3156 
3157  void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3158  assert(N == 1 && "Invalid number of operands!");
3159 
3160  // When we come here, the VectorList field will identify a range
3161  // of q-registers by its base register and length, and it will
3162  // have already been error-checked to be the expected length of
3163  // range and contain only q-regs in the range q0-q7. So we can
3164  // count on the base register being in the range q0-q6 (for 2
3165  // regs) or q0-q4 (for 4)
3166  //
3167  // The MVE instructions taking a register range of this kind will
3168  // need an operand in the QQPR or QQQQPR class, representing the
3169  // entire range as a unit. So we must translate into that class,
3170  // by finding the index of the base register in the MQPR reg
3171  // class, and returning the super-register at the corresponding
3172  // index in the target class.
3173 
3174  const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3175  const MCRegisterClass *RC_out = (VectorList.Count == 2) ?
3176  &ARMMCRegisterClasses[ARM::QQPRRegClassID] :
3177  &ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
3178 
3179  unsigned I, E = RC_out->getNumRegs();
3180  for (I = 0; I < E; I++)
3181  if (RC_in->getRegister(I) == VectorList.RegNum)
3182  break;
3183  assert(I < E && "Invalid vector list start register!");
3184 
3185  Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
3186  }
3187 
3188  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3189  assert(N == 2 && "Invalid number of operands!");
3190  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3191  Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
3192  }
3193 
3194  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3195  assert(N == 1 && "Invalid number of operands!");
3196  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3197  }
3198 
3199  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3200  assert(N == 1 && "Invalid number of operands!");
3201  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3202  }
3203 
3204  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3205  assert(N == 1 && "Invalid number of operands!");
3206  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3207  }
3208 
3209  void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3210  assert(N == 1 && "Invalid number of operands!");
3211  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3212  }
3213 
3214  void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3215  assert(N == 1 && "Invalid number of operands!");
3216  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3217  }
3218 
3219  void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3220  assert(N == 1 && "Invalid number of operands!");
3221  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3222  }
3223 
3224  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3225  assert(N == 1 && "Invalid number of operands!");
3226  // The immediate encodes the type of constant as well as the value.
3227  // Mask in that this is an i8 splat.
3228  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3229  Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3230  }
3231 
3232  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3233  assert(N == 1 && "Invalid number of operands!");
3234  // The immediate encodes the type of constant as well as the value.
3235  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3236  unsigned Value = CE->getValue();
3237  Value = ARM_AM::encodeNEONi16splat(Value);
3238  Inst.addOperand(MCOperand::createImm(Value));
3239  }
3240 
3241  void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3242  assert(N == 1 && "Invalid number of operands!");
3243  // The immediate encodes the type of constant as well as the value.
3244  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3245  unsigned Value = CE->getValue();
3246  Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3247  Inst.addOperand(MCOperand::createImm(Value));
3248  }
3249 
3250  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3251  assert(N == 1 && "Invalid number of operands!");
3252  // The immediate encodes the type of constant as well as the value.
3253  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3254  unsigned Value = CE->getValue();
3255  Value = ARM_AM::encodeNEONi32splat(Value);
3256  Inst.addOperand(MCOperand::createImm(Value));
3257  }
3258 
3259  void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3260  assert(N == 1 && "Invalid number of operands!");
3261  // The immediate encodes the type of constant as well as the value.
3262  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3263  unsigned Value = CE->getValue();
3264  Value = ARM_AM::encodeNEONi32splat(~Value);
3265  Inst.addOperand(MCOperand::createImm(Value));
3266  }
3267 
3268  void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3269  // The immediate encodes the type of constant as well as the value.
3270  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3271  assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
3272  Inst.getOpcode() == ARM::VMOVv16i8) &&
3273  "All instructions that wants to replicate non-zero byte "
3274  "always must be replaced with VMOVv8i8 or VMOVv16i8.");
3275  unsigned Value = CE->getValue();
3276  if (Inv)
3277  Value = ~Value;
3278  unsigned B = Value & 0xff;
3279  B |= 0xe00; // cmode = 0b1110
3281  }
3282 
3283  void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3284  assert(N == 1 && "Invalid number of operands!");
3285  addNEONi8ReplicateOperands(Inst, true);
3286  }
3287 
3288  static unsigned encodeNeonVMOVImmediate(unsigned Value) {
3289  if (Value >= 256 && Value <= 0xffff)
3290  Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3291  else if (Value > 0xffff && Value <= 0xffffff)
3292  Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3293  else if (Value > 0xffffff)
3294  Value = (Value >> 24) | 0x600;
3295  return Value;
3296  }
3297 
3298  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3299  assert(N == 1 && "Invalid number of operands!");
3300  // The immediate encodes the type of constant as well as the value.
3301  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3302  unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
3303  Inst.addOperand(MCOperand::createImm(Value));
3304  }
3305 
3306  void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3307  assert(N == 1 && "Invalid number of operands!");
3308  addNEONi8ReplicateOperands(Inst, false);
3309  }
3310 
3311  void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3312  assert(N == 1 && "Invalid number of operands!");
3313  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3314  assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
3315  Inst.getOpcode() == ARM::VMOVv8i16 ||
3316  Inst.getOpcode() == ARM::VMVNv4i16 ||
3317  Inst.getOpcode() == ARM::VMVNv8i16) &&
3318  "All instructions that want to replicate non-zero half-word "
3319  "always must be replaced with V{MOV,MVN}v{4,8}i16.");
3320  uint64_t Value = CE->getValue();
3321  unsigned Elem = Value & 0xffff;
3322  if (Elem >= 256)
3323  Elem = (Elem >> 8) | 0x200;
3324  Inst.addOperand(MCOperand::createImm(Elem));
3325  }
3326 
3327  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3328  assert(N == 1 && "Invalid number of operands!");
3329  // The immediate encodes the type of constant as well as the value.
3330  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3331  unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
3332  Inst.addOperand(MCOperand::createImm(Value));
3333  }
3334 
3335  void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3336  assert(N == 1 && "Invalid number of operands!");
3337  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3338  assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
3339  Inst.getOpcode() == ARM::VMOVv4i32 ||
3340  Inst.getOpcode() == ARM::VMVNv2i32 ||
3341  Inst.getOpcode() == ARM::VMVNv4i32) &&
3342  "All instructions that want to replicate non-zero word "
3343  "always must be replaced with V{MOV,MVN}v{2,4}i32.");
3344  uint64_t Value = CE->getValue();
3345  unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3346  Inst.addOperand(MCOperand::createImm(Elem));
3347  }
3348 
3349  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3350  assert(N == 1 && "Invalid number of operands!");
3351  // The immediate encodes the type of constant as well as the value.
3352  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3353  uint64_t Value = CE->getValue();
3354  unsigned Imm = 0;
3355  for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3356  Imm |= (Value & 1) << i;
3357  }
3358  Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3359  }
3360 
3361  void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3362  assert(N == 1 && "Invalid number of operands!");
3363  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3364  Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
3365  }
3366 
3367  void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3368  assert(N == 1 && "Invalid number of operands!");
3369  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3370  Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
3371  }
3372 
3373  void print(raw_ostream &OS) const override;
3374 
3375  static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
3376  auto Op = make_unique<ARMOperand>(k_ITCondMask);
3377  Op->ITMask.Mask = Mask;
3378  Op->StartLoc = S;
3379  Op->EndLoc = S;
3380  return Op;
3381  }
3382 
3383  static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
3384  SMLoc S) {
3385  auto Op = make_unique<ARMOperand>(k_CondCode);
3386  Op->CC.Val = CC;
3387  Op->StartLoc = S;
3388  Op->EndLoc = S;
3389  return Op;
3390  }
3391 
3392  static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC,
3393  SMLoc S) {
3394  auto Op = make_unique<ARMOperand>(k_VPTPred);
3395  Op->VCC.Val = CC;
3396  Op->StartLoc = S;
3397  Op->EndLoc = S;
3398  return Op;
3399  }
3400 
3401  static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
3402  auto Op = make_unique<ARMOperand>(k_CoprocNum);
3403  Op->Cop.Val = CopVal;
3404  Op->StartLoc = S;
3405  Op->EndLoc = S;
3406  return Op;
3407  }
3408 
3409  static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
3410  auto Op = make_unique<ARMOperand>(k_CoprocReg);
3411  Op->Cop.Val = CopVal;
3412  Op->StartLoc = S;
3413  Op->EndLoc = S;
3414  return Op;
3415  }
3416 
3417  static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
3418  SMLoc E) {
3419  auto Op = make_unique<ARMOperand>(k_CoprocOption);
3420  Op->Cop.Val = Val;
3421  Op->StartLoc = S;
3422  Op->EndLoc = E;
3423  return Op;
3424  }
3425 
3426  static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
3427  auto Op = make_unique<ARMOperand>(k_CCOut);
3428  Op->Reg.RegNum = RegNum;
3429  Op->StartLoc = S;
3430  Op->EndLoc = S;
3431  return Op;
3432  }
3433 
3434  static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
3435  auto Op = make_unique<ARMOperand>(k_Token);
3436  Op->Tok.Data = Str.data();
3437  Op->Tok.Length = Str.size();
3438  Op->StartLoc = S;
3439  Op->EndLoc = S;
3440  return Op;
3441  }
3442 
3443  static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3444  SMLoc E) {
3445  auto Op = make_unique<ARMOperand>(k_Register);
3446  Op->Reg.RegNum = RegNum;
3447  Op->StartLoc = S;
3448  Op->EndLoc = E;
3449  return Op;
3450  }
3451 
3452  static std::unique_ptr<ARMOperand>
3453  CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3454  unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3455  SMLoc E) {
3456  auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
3457  Op->RegShiftedReg.ShiftTy = ShTy;
3458  Op->RegShiftedReg.SrcReg = SrcReg;
3459  Op->RegShiftedReg.ShiftReg = ShiftReg;
3460  Op->RegShiftedReg.ShiftImm = ShiftImm;
3461  Op->StartLoc = S;
3462  Op->EndLoc = E;
3463  return Op;
3464  }
3465 
3466  static std::unique_ptr<ARMOperand>
3467  CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3468  unsigned ShiftImm, SMLoc S, SMLoc E) {
3469  auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
3470  Op->RegShiftedImm.ShiftTy = ShTy;
3471  Op->RegShiftedImm.SrcReg = SrcReg;
3472  Op->RegShiftedImm.ShiftImm = ShiftImm;
3473  Op->StartLoc = S;
3474  Op->EndLoc = E;
3475  return Op;
3476  }
3477 
3478  static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
3479  SMLoc S, SMLoc E) {
3480  auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
3481  Op->ShifterImm.isASR = isASR;
3482  Op->ShifterImm.Imm = Imm;
3483  Op->StartLoc = S;
3484  Op->EndLoc = E;
3485  return Op;
3486  }
3487 
3488  static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3489  SMLoc E) {
3490  auto Op = make_unique<ARMOperand>(k_RotateImmediate);
3491  Op->RotImm.Imm = Imm;
3492  Op->StartLoc = S;
3493  Op->EndLoc = E;
3494  return Op;
3495  }
3496 
3497  static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3498  SMLoc S, SMLoc E) {
3499  auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
3500  Op->ModImm.Bits = Bits;
3501  Op->ModImm.Rot = Rot;
3502  Op->StartLoc = S;
3503  Op->EndLoc = E;
3504  return Op;
3505  }
3506 
3507  static std::unique_ptr<ARMOperand>
3508  CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3509  auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
3510  Op->Imm.Val = Val;
3511  Op->StartLoc = S;
3512  Op->EndLoc = E;
3513  return Op;
3514  }
3515 
3516  static std::unique_ptr<ARMOperand>
3517  CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3518  auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
3519  Op->Bitfield.LSB = LSB;
3520  Op->Bitfield.Width = Width;
3521  Op->StartLoc = S;
3522  Op->EndLoc = E;
3523  return Op;
3524  }
3525 
3526  static std::unique_ptr<ARMOperand>
3527  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3528  SMLoc StartLoc, SMLoc EndLoc) {
3529  assert(Regs.size() > 0 && "RegList contains no registers?");
3530  KindTy Kind = k_RegisterList;
3531 
3532  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3533  Regs.front().second)) {
3534  if (Regs.back().second == ARM::VPR)
3535  Kind = k_FPDRegisterListWithVPR;
3536  else
3537  Kind = k_DPRRegisterList;
3538  } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3539  Regs.front().second)) {
3540  if (Regs.back().second == ARM::VPR)
3541  Kind = k_FPSRegisterListWithVPR;
3542  else
3543  Kind = k_SPRRegisterList;
3544  }
3545 
3546  // Sort based on the register encoding values.
3547  array_pod_sort(Regs.begin(), Regs.end());
3548 
3549  if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3550  Kind = k_RegisterListWithAPSR;
3551 
3552  auto Op = make_unique<ARMOperand>(Kind);
3553  for (SmallVectorImpl<std::pair<unsigned, unsigned>>::const_iterator
3554  I = Regs.begin(), E = Regs.end(); I != E; ++I)
3555  Op->Registers.push_back(I->second);
3556 
3557  Op->StartLoc = StartLoc;
3558  Op->EndLoc = EndLoc;
3559  return Op;
3560  }
3561 
3562  static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3563  unsigned Count,
3564  bool isDoubleSpaced,
3565  SMLoc S, SMLoc E) {
3566  auto Op = make_unique<ARMOperand>(k_VectorList);
3567  Op->VectorList.RegNum = RegNum;
3568  Op->VectorList.Count = Count;
3569  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3570  Op->StartLoc = S;
3571  Op->EndLoc = E;
3572  return Op;
3573  }
3574 
3575  static std::unique_ptr<ARMOperand>
3576  CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3577  SMLoc S, SMLoc E) {
3578  auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
3579  Op->VectorList.RegNum = RegNum;
3580  Op->VectorList.Count = Count;
3581  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3582  Op->StartLoc = S;
3583  Op->EndLoc = E;
3584  return Op;
3585  }
3586 
3587  static std::unique_ptr<ARMOperand>
3588  CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3589  bool isDoubleSpaced, SMLoc S, SMLoc E) {
3590  auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
3591  Op->VectorList.RegNum = RegNum;
3592  Op->VectorList.Count = Count;
3593  Op->VectorList.LaneIndex = Index;
3594  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3595  Op->StartLoc = S;
3596  Op->EndLoc = E;
3597  return Op;
3598  }
3599 
3600  static std::unique_ptr<ARMOperand>
3601  CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3602  auto Op = make_unique<ARMOperand>(k_VectorIndex);
3603  Op->VectorIndex.Val = Idx;
3604  Op->StartLoc = S;
3605  Op->EndLoc = E;
3606  return Op;
3607  }
3608 
3609  static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3610  SMLoc E) {
3611  auto Op = make_unique<ARMOperand>(k_Immediate);
3612  Op->Imm.Val = Val;
3613  Op->StartLoc = S;
3614  Op->EndLoc = E;
3615  return Op;
3616  }
3617 
3618  static std::unique_ptr<ARMOperand>
3619  CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3620  unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3621  unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3622  SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3623  auto Op = make_unique<ARMOperand>(k_Memory);
3624  Op->Memory.BaseRegNum = BaseRegNum;
3625  Op->Memory.OffsetImm = OffsetImm;
3626  Op->Memory.OffsetRegNum = OffsetRegNum;
3627  Op->Memory.ShiftType = ShiftType;
3628  Op->Memory.ShiftImm = ShiftImm;
3629  Op->Memory.Alignment = Alignment;
3630  Op->Memory.isNegative = isNegative;
3631  Op->StartLoc = S;
3632  Op->EndLoc = E;
3633  Op->AlignmentLoc = AlignmentLoc;
3634  return Op;
3635  }
3636 
3637  static std::unique_ptr<ARMOperand>
3638  CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3639  unsigned ShiftImm, SMLoc S, SMLoc E) {
3640  auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
3641  Op->PostIdxReg.RegNum = RegNum;
3642  Op->PostIdxReg.isAdd = isAdd;
3643  Op->PostIdxReg.ShiftTy = ShiftTy;
3644  Op->PostIdxReg.ShiftImm = ShiftImm;
3645  Op->StartLoc = S;
3646  Op->EndLoc = E;
3647  return Op;
3648  }
3649 
3650  static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3651  SMLoc S) {
3652  auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
3653  Op->MBOpt.Val = Opt;
3654  Op->StartLoc = S;
3655  Op->EndLoc = S;
3656  return Op;
3657  }
3658 
3659  static std::unique_ptr<ARMOperand>
3660  CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3661  auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3662  Op->ISBOpt.Val = Opt;
3663  Op->StartLoc = S;
3664  Op->EndLoc = S;
3665  return Op;
3666  }
3667 
3668  static std::unique_ptr<ARMOperand>
3669  CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3670  auto Op = make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3671  Op->TSBOpt.Val = Opt;
3672  Op->StartLoc = S;
3673  Op->EndLoc = S;
3674  return Op;
3675  }
3676 
3677  static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3678  SMLoc S) {
3679  auto Op = make_unique<ARMOperand>(k_ProcIFlags);
3680  Op->IFlags.Val = IFlags;
3681  Op->StartLoc = S;
3682  Op->EndLoc = S;
3683  return Op;
3684  }
3685 
3686  static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3687  auto Op = make_unique<ARMOperand>(k_MSRMask);
3688  Op->MMask.Val = MMask;
3689  Op->StartLoc = S;
3690  Op->EndLoc = S;
3691  return Op;
3692  }
3693 
3694  static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3695  auto Op = make_unique<ARMOperand>(k_BankedReg);
3696  Op->BankedReg.Val = Reg;
3697  Op->StartLoc = S;
3698  Op->EndLoc = S;
3699  return Op;
3700  }
3701 };
3702 
3703 } // end anonymous namespace.
3704 
3705 void ARMOperand::print(raw_ostream &OS) const {
3706  auto RegName = [](unsigned Reg) {
3707  if (Reg)
3709  else
3710  return "noreg";
3711  };
3712 
3713  switch (Kind) {
3714  case k_CondCode:
3715  OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3716  break;
3717  case k_VPTPred:
3718  OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
3719  break;
3720  case k_CCOut:
3721  OS << "<ccout " << RegName(getReg()) << ">";
3722  break;
3723  case k_ITCondMask: {
3724  static const char *const MaskStr[] = {
3725  "(invalid)", "(tttt)", "(ttt)", "(ttte)",
3726  "(tt)", "(ttet)", "(tte)", "(ttee)",
3727  "(t)", "(tett)", "(tet)", "(tete)",
3728  "(te)", "(teet)", "(tee)", "(teee)",
3729  };
3730  assert((ITMask.Mask & 0xf) == ITMask.Mask);
3731  OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3732  break;
3733  }
3734  case k_CoprocNum:
3735  OS << "<coprocessor number: " << getCoproc() << ">";
3736  break;
3737  case k_CoprocReg:
3738  OS << "<coprocessor register: " << getCoproc() << ">";
3739  break;
3740  case k_CoprocOption:
3741  OS << "<coprocessor option: " << CoprocOption.Val << ">";
3742  break;
3743  case k_MSRMask:
3744  OS << "<mask: " << getMSRMask() << ">";
3745  break;
3746  case k_BankedReg:
3747  OS << "<banked reg: " << getBankedReg() << ">";
3748  break;
3749  case k_Immediate:
3750  OS << *getImm();
3751  break;
3752  case k_MemBarrierOpt:
3753  OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3754  break;
3755  case k_InstSyncBarrierOpt:
3756  OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3757  break;
3758  case k_TraceSyncBarrierOpt:
3759  OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3760  break;
3761  case k_Memory:
3762  OS << "<memory";
3763  if (Memory.BaseRegNum)
3764  OS << " base:" << RegName(Memory.BaseRegNum);
3765  if (Memory.OffsetImm)
3766  OS << " offset-imm:" << *Memory.OffsetImm;
3767  if (Memory.OffsetRegNum)
3768  OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3769  << RegName(Memory.OffsetRegNum);
3770  if (Memory.ShiftType != ARM_AM::no_shift) {
3771  OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3772  OS << " shift-imm:" << Memory.ShiftImm;
3773  }
3774  if (Memory.Alignment)
3775  OS << " alignment:" << Memory.Alignment;
3776  OS << ">";
3777  break;
3778  case k_PostIndexRegister:
3779  OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3780  << RegName(PostIdxReg.RegNum);
3781  if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3782  OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3783  << PostIdxReg.ShiftImm;
3784  OS << ">";
3785  break;
3786  case k_ProcIFlags: {
3787  OS << "<ARM_PROC::";
3788  unsigned IFlags = getProcIFlags();
3789  for (int i=2; i >= 0; --i)
3790  if (IFlags & (1 << i))
3791  OS << ARM_PROC::IFlagsToString(1 << i);
3792  OS << ">";
3793  break;
3794  }
3795  case k_Register:
3796  OS << "<register " << RegName(getReg()) << ">";
3797  break;
3798  case k_ShifterImmediate:
3799  OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3800  << " #" << ShifterImm.Imm << ">";
3801  break;
3802  case k_ShiftedRegister:
3803  OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3804  << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3805  << RegName(RegShiftedReg.ShiftReg) << ">";
3806  break;
3807  case k_ShiftedImmediate:
3808  OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
3809  << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3810  << RegShiftedImm.ShiftImm << ">";
3811  break;
3812  case k_RotateImmediate:
3813  OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3814  break;
3815  case k_ModifiedImmediate:
3816  OS << "<mod_imm #" << ModImm.Bits << ", #"
3817  << ModImm.Rot << ")>";
3818  break;
3819  case k_ConstantPoolImmediate:
3820  OS << "<constant_pool_imm #" << *getConstantPoolImm();
3821  break;
3822  case k_BitfieldDescriptor:
3823  OS << "<bitfield " << "lsb: " << Bitfield.LSB
3824  << ", width: " << Bitfield.Width << ">";
3825  break;
3826  case k_RegisterList:
3827  case k_RegisterListWithAPSR:
3828  case k_DPRRegisterList:
3829  case k_SPRRegisterList:
3830  case k_FPSRegisterListWithVPR:
3831  case k_FPDRegisterListWithVPR: {
3832  OS << "<register_list ";
3833 
3834  const SmallVectorImpl<unsigned> &RegList = getRegList();
3836  I = RegList.begin(), E = RegList.end(); I != E; ) {
3837  OS << RegName(*I);
3838  if (++I < E) OS << ", ";
3839  }
3840 
3841  OS << ">";
3842  break;
3843  }
3844  case k_VectorList:
3845  OS << "<vector_list " << VectorList.Count << " * "
3846  << RegName(VectorList.RegNum) << ">";
3847  break;
3848  case k_VectorListAllLanes:
3849  OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3850  << RegName(VectorList.RegNum) << ">";
3851  break;
3852  case k_VectorListIndexed:
3853  OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3854  << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
3855  break;
3856  case k_Token:
3857  OS << "'" << getToken() << "'";
3858  break;
3859  case k_VectorIndex:
3860  OS << "<vectorindex " << getVectorIndex() << ">";
3861  break;
3862  }
3863 }
3864 
3865 /// @name Auto-generated Match Functions
3866 /// {
3867 
3868 static unsigned MatchRegisterName(StringRef Name);
3869 
3870 /// }
3871 
3872 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3873  SMLoc &StartLoc, SMLoc &EndLoc) {
3874  const AsmToken &Tok = getParser().getTok();
3875  StartLoc = Tok.getLoc();
3876  EndLoc = Tok.getEndLoc();
3877  RegNo = tryParseRegister();
3878 
3879  return (RegNo == (unsigned)-1);
3880 }
3881 
3882 /// Try to parse a register name. The token must be an Identifier when called,
3883 /// and if it is a register name the token is eaten and the register number is
3884 /// returned. Otherwise return -1.
3885 int ARMAsmParser::tryParseRegister() {
3886  MCAsmParser &Parser = getParser();
3887  const AsmToken &Tok = Parser.getTok();
3888  if (Tok.isNot(AsmToken::Identifier)) return -1;
3889 
3890  std::string lowerCase = Tok.getString().lower();
3891  unsigned RegNum = MatchRegisterName(lowerCase);
3892  if (!RegNum) {
3893  RegNum = StringSwitch<unsigned>(lowerCase)
3894  .Case("r13", ARM::SP)
3895  .Case("r14", ARM::LR)
3896  .Case("r15", ARM::PC)
3897  .Case("ip", ARM::R12)
3898  // Additional register name aliases for 'gas' compatibility.
3899  .Case("a1", ARM::R0)
3900  .Case("a2", ARM::R1)
3901  .Case("a3", ARM::R2)
3902  .Case("a4", ARM::R3)
3903  .Case("v1", ARM::R4)
3904  .Case("v2", ARM::R5)
3905  .Case("v3", ARM::R6)
3906  .Case("v4", ARM::R7)
3907  .Case("v5", ARM::R8)
3908  .Case("v6", ARM::R9)
3909  .Case("v7", ARM::R10)
3910  .Case("v8", ARM::R11)
3911  .Case("sb", ARM::R9)
3912  .Case("sl", ARM::R10)
3913  .Case("fp", ARM::R11)
3914  .Default(0);
3915  }
3916  if (!RegNum) {
3917  // Check for aliases registered via .req. Canonicalize to lower case.
3918  // That's more consistent since register names are case insensitive, and
3919  // it's how the original entry was passed in from MC/MCParser/AsmParser.
3920  StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3921  // If no match, return failure.
3922  if (Entry == RegisterReqs.end())
3923  return -1;
3924  Parser.Lex(); // Eat identifier token.
3925  return Entry->getValue();
3926  }
3927 
3928  // Some FPUs only have 16 D registers, so D16-D31 are invalid
3929  if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3930  return -1;
3931 
3932  Parser.Lex(); // Eat identifier token.
3933 
3934  return RegNum;
3935 }
3936 
3937 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3938 // If a recoverable error occurs, return 1. If an irrecoverable error
3939 // occurs, return -1. An irrecoverable error is one where tokens have been
3940 // consumed in the process of trying to parse the shifter (i.e., when it is
3941 // indeed a shifter operand, but malformed).
3942 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3943  MCAsmParser &Parser = getParser();
3944  SMLoc S = Parser.getTok().getLoc();
3945  const AsmToken &Tok = Parser.getTok();
3946  if (Tok.isNot(AsmToken::Identifier))
3947  return -1;
3948 
3949  std::string lowerCase = Tok.getString().lower();
3951  .Case("asl", ARM_AM::lsl)
3952  .Case("lsl", ARM_AM::lsl)
3953  .Case("lsr", ARM_AM::lsr)
3954  .Case("asr", ARM_AM::asr)
3955  .Case("ror", ARM_AM::ror)
3956  .Case("rrx", ARM_AM::rrx)
3958 
3959  if (ShiftTy == ARM_AM::no_shift)
3960  return 1;
3961 
3962  Parser.Lex(); // Eat the operator.
3963 
3964  // The source register for the shift has already been added to the
3965  // operand list, so we need to pop it off and combine it into the shifted
3966  // register operand instead.
3967  std::unique_ptr<ARMOperand> PrevOp(
3968  (ARMOperand *)Operands.pop_back_val().release());
3969  if (!PrevOp->isReg())
3970  return Error(PrevOp->getStartLoc(), "shift must be of a register");
3971  int SrcReg = PrevOp->getReg();
3972 
3973  SMLoc EndLoc;
3974  int64_t Imm = 0;
3975  int ShiftReg = 0;
3976  if (ShiftTy == ARM_AM::rrx) {
3977  // RRX Doesn't have an explicit shift amount. The encoder expects
3978  // the shift register to be the same as the source register. Seems odd,
3979  // but OK.
3980  ShiftReg = SrcReg;
3981  } else {
3982  // Figure out if this is shifted by a constant or a register (for non-RRX).
3983  if (Parser.getTok().is(AsmToken::Hash) ||
3984  Parser.getTok().is(AsmToken::Dollar)) {
3985  Parser.Lex(); // Eat hash.
3986  SMLoc ImmLoc = Parser.getTok().getLoc();
3987  const MCExpr *ShiftExpr = nullptr;
3988  if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3989  Error(ImmLoc, "invalid immediate shift value");
3990  return -1;
3991  }
3992  // The expression must be evaluatable as an immediate.
3993  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3994  if (!CE) {
3995  Error(ImmLoc, "invalid immediate shift value");
3996  return -1;
3997  }
3998  // Range check the immediate.
3999  // lsl, ror: 0 <= imm <= 31
4000  // lsr, asr: 0 <= imm <= 32
4001  Imm = CE->getValue();
4002  if (Imm < 0 ||
4003  ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4004  ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4005  Error(ImmLoc, "immediate shift value out of range");
4006  return -1;
4007  }
4008  // shift by zero is a nop. Always send it through as lsl.
4009  // ('as' compatibility)
4010  if (Imm == 0)
4011  ShiftTy = ARM_AM::lsl;
4012  } else if (Parser.getTok().is(AsmToken::Identifier)) {
4013  SMLoc L = Parser.getTok().getLoc();
4014  EndLoc = Parser.getTok().getEndLoc();
4015  ShiftReg = tryParseRegister();
4016  if (ShiftReg == -1) {
4017  Error(L, "expected immediate or register in shift operand");
4018  return -1;
4019  }
4020  } else {
4021  Error(Parser.getTok().getLoc(),
4022  "expected immediate or register in shift operand");
4023  return -1;
4024  }
4025  }
4026 
4027  if (ShiftReg && ShiftTy != ARM_AM::rrx)
4028  Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
4029  ShiftReg, Imm,
4030  S, EndLoc));
4031  else
4032  Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4033  S, EndLoc));
4034 
4035  return 0;
4036 }
4037 
4038 /// Try to parse a register name. The token must be an Identifier when called.
4039 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
4040 /// if there is a "writeback". 'true' if it's not a register.
4041 ///
4042 /// TODO this is likely to change to allow different register types and or to
4043 /// parse for a specific register type.
4044 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4045  MCAsmParser &Parser = getParser();
4046  SMLoc RegStartLoc = Parser.getTok().getLoc();
4047  SMLoc RegEndLoc = Parser.getTok().getEndLoc();
4048  int RegNo = tryParseRegister();
4049  if (RegNo == -1)
4050  return true;
4051 
4052  Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
4053 
4054  const AsmToken &ExclaimTok = Parser.getTok();
4055  if (ExclaimTok.is(AsmToken::Exclaim)) {
4056  Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4057  ExclaimTok.getLoc()));
4058  Parser.Lex(); // Eat exclaim token
4059  return false;
4060  }
4061 
4062  // Also check for an index operand. This is only legal for vector registers,
4063  // but that'll get caught OK in operand matching, so we don't need to
4064  // explicitly filter everything else out here.
4065  if (Parser.getTok().is(AsmToken::LBrac)) {
4066  SMLoc SIdx = Parser.getTok().getLoc();
4067  Parser.Lex(); // Eat left bracket token.
4068 
4069  const MCExpr *ImmVal;
4070  if (getParser().parseExpression(ImmVal))
4071  return true;
4072  const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
4073  if (!MCE)
4074  return TokError("immediate value expected for vector index");
4075 
4076  if (Parser.getTok().isNot(AsmToken::RBrac))
4077  return Error(Parser.getTok().getLoc(), "']' expected");
4078 
4079  SMLoc E = Parser.getTok().getEndLoc();
4080  Parser.Lex(); // Eat right bracket token.
4081 
4082  Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
4083  SIdx, E,
4084  getContext()));
4085  }
4086 
4087  return false;
4088 }
4089 
4090 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
4091 /// instruction with a symbolic operand name.
4092 /// We accept "crN" syntax for GAS compatibility.
4093 /// <operand-name> ::= <prefix><number>
4094 /// If CoprocOp is 'c', then:
4095 /// <prefix> ::= c | cr
4096 /// If CoprocOp is 'p', then :
4097 /// <prefix> ::= p
4098 /// <number> ::= integer in range [0, 15]
4099 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
4100  // Use the same layout as the tablegen'erated register name matcher. Ugly,
4101  // but efficient.
4102  if (Name.size() < 2 || Name[0] != CoprocOp)
4103  return -1;
4104  Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
4105 
4106  switch (Name.size()) {
4107  default: return -1;
4108  case 1:
4109  switch (Name[0]) {
4110  default: return -1;
4111  case '0': return 0;
4112  case '1': return 1;
4113  case '2': return 2;
4114  case '3': return 3;
4115  case '4': return 4;
4116  case '5': return 5;
4117  case '6': return 6;
4118  case '7': return 7;
4119  case '8': return 8;
4120  case '9': return 9;
4121  }
4122  case 2:
4123  if (Name[0] != '1')
4124  return -1;
4125  switch (Name[1]) {
4126  default: return -1;
4127  // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
4128  // However, old cores (v5/v6) did use them in that way.
4129  case '0': return 10;
4130  case '1': return 11;
4131  case '2': return 12;
4132  case '3': return 13;
4133  case '4': return 14;
4134  case '5': return 15;
4135  }
4136  }
4137 }
4138 
4139 /// parseITCondCode - Try to parse a condition code for an IT instruction.
4141 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4142  MCAsmParser &Parser = getParser();
4143  SMLoc S = Parser.getTok().getLoc();
4144  const AsmToken &Tok = Parser.getTok();
4145  if (!Tok.is(AsmToken::Identifier))
4146  return MatchOperand_NoMatch;
4147  unsigned CC = ARMCondCodeFromString(Tok.getString());
4148  if (CC == ~0U)
4149  return MatchOperand_NoMatch;
4150  Parser.Lex(); // Eat the token.
4151 
4152  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
4153 
4154  return MatchOperand_Success;
4155 }
4156 
4157 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
4158 /// token must be an Identifier when called, and if it is a coprocessor
4159 /// number, the token is eaten and the operand is added to the operand list.
4161 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4162  MCAsmParser &Parser = getParser();
4163  SMLoc S = Parser.getTok().getLoc();
4164  const AsmToken &Tok = Parser.getTok();
4165  if (Tok.isNot(AsmToken::Identifier))
4166  return MatchOperand_NoMatch;
4167 
4168  int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
4169  if (Num == -1)
4170  return MatchOperand_NoMatch;
4171  if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4172  return MatchOperand_NoMatch;
4173 
4174  Parser.Lex(); // Eat identifier token.
4175  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
4176  return MatchOperand_Success;
4177 }
4178 
4179 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
4180 /// token must be an Identifier when called, and if it is a coprocessor
4181 /// number, the token is eaten and the operand is added to the operand list.
4183 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4184  MCAsmParser &Parser = getParser();
4185  SMLoc S = Parser.getTok().getLoc();
4186  const AsmToken &Tok = Parser.getTok();
4187  if (Tok.isNot(AsmToken::Identifier))
4188  return MatchOperand_NoMatch;
4189 
4190  int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
4191  if (Reg == -1)
4192  return MatchOperand_NoMatch;
4193 
4194  Parser.Lex(); // Eat identifier token.
4195  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
4196  return MatchOperand_Success;
4197 }
4198 
4199 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
4200 /// coproc_option : '{' imm0_255 '}'
4202 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4203  MCAsmParser &Parser = getParser();
4204  SMLoc S = Parser.getTok().getLoc();
4205 
4206  // If this isn't a '{', this isn't a coprocessor immediate operand.
4207  if (Parser.getTok().isNot(AsmToken::LCurly))
4208  return MatchOperand_NoMatch;
4209  Parser.Lex(); // Eat the '{'
4210 
4211  const MCExpr *Expr;
4212  SMLoc Loc = Parser.getTok().getLoc();
4213  if (getParser().parseExpression(Expr)) {
4214  Error(Loc, "illegal expression");
4215  return MatchOperand_ParseFail;
4216  }
4217  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4218  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
4219  Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
4220  return MatchOperand_ParseFail;
4221  }
4222  int Val = CE->getValue();
4223 
4224  // Check for and consume the closing '}'
4225  if (Parser.getTok().isNot(AsmToken::RCurly))
4226  return MatchOperand_ParseFail;
4227  SMLoc E = Parser.getTok().getEndLoc();
4228  Parser.Lex(); // Eat the '}'
4229 
4230  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
4231  return MatchOperand_Success;
4232 }
4233 
4234 // For register list parsing, we need to map from raw GPR register numbering
4235 // to the enumeration values. The enumeration values aren't sorted by
4236 // register number due to our using "sp", "lr" and "pc" as canonical names.
4237 static unsigned getNextRegister(unsigned Reg) {
4238  // If this is a GPR, we need to do it manually, otherwise we can rely
4239  // on the sort ordering of the enumeration since the other reg-classes
4240  // are sane.
4241  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4242  return Reg + 1;
4243  switch(Reg) {
4244  default: llvm_unreachable("Invalid GPR number!");
4245  case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
4246  case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
4247  case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
4248  case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
4249  case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
4250  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
4251  case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
4252  case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
4253  }
4254 }
4255 
4256 /// Parse a register list.
4257 bool ARMAsmParser::parseRegisterList(OperandVector &Operands,
4258  bool EnforceOrder) {
4259  MCAsmParser &Parser = getParser();
4260  if (Parser.getTok().isNot(AsmToken::LCurly))
4261  return TokError("Token is not a Left Curly Brace");
4262  SMLoc S = Parser.getTok().getLoc();
4263  Parser.Lex(); // Eat '{' token.
4264  SMLoc RegLoc = Parser.getTok().getLoc();
4265 
4266  // Check the first register in the list to see what register class
4267  // this is a list of.
4268  int Reg = tryParseRegister();
4269  if (Reg == -1)
4270  return Error(RegLoc, "register expected");
4271 
4272  // The reglist instructions have at most 16 registers, so reserve
4273  // space for that many.
4274  int EReg = 0;
4276 
4277  // Allow Q regs and just interpret them as the two D sub-registers.
4278  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4279  Reg = getDRegFromQReg(Reg);
4280  EReg = MRI->getEncodingValue(Reg);
4281  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
4282  ++Reg;
4283  }
4284  const MCRegisterClass *RC;
4285  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4286  RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
4287  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
4288  RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
4289  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
4290  RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
4291  else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4292  RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4293  else
4294  return Error(RegLoc, "invalid register in register list");
4295 
4296  // Store the register.
4297  EReg = MRI->getEncodingValue(Reg);
4298  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
4299 
4300  // This starts immediately after the first register token in the list,
4301  // so we can see either a comma or a minus (range separator) as a legal
4302  // next token.
4303  while (Parser.getTok().is(AsmToken::Comma) ||
4304  Parser.getTok().is(AsmToken::Minus)) {
4305  if (Parser.getTok().is(AsmToken::Minus)) {
4306  Parser.Lex(); // Eat the minus.
4307  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4308  int EndReg = tryParseRegister();
4309  if (EndReg == -1)
4310  return Error(AfterMinusLoc, "register expected");
4311  // Allow Q regs and just interpret them as the two D sub-registers.
4312  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4313  EndReg = getDRegFromQReg(EndReg) + 1;
4314  // If the register is the same as the start reg, there's nothing
4315  // more to do.
4316  if (Reg == EndReg)
4317  continue;
4318  // The register must be in the same register class as the first.
4319  if (!RC->contains(EndReg))
4320  return Error(AfterMinusLoc, "invalid register in register list");
4321  // Ranges must go from low to high.
4322  if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
4323  return Error(AfterMinusLoc, "bad range in register list");
4324 
4325  // Add all the registers in the range to the register list.
4326  while (Reg != EndReg) {
4327  Reg = getNextRegister(Reg);
4328  EReg = MRI->getEncodingValue(Reg);
4329  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
4330  }
4331  continue;
4332  }
4333  Parser.Lex(); // Eat the comma.
4334  RegLoc = Parser.getTok().getLoc();
4335  int OldReg = Reg;
4336  const AsmToken RegTok = Parser.getTok();
4337  Reg = tryParseRegister();
4338  if (Reg == -1)
4339  return Error(RegLoc, "register expected");
4340  // Allow Q regs and just interpret them as the two D sub-registers.
4341  bool isQReg = false;
4342  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4343  Reg = getDRegFromQReg(Reg);
4344  isQReg = true;
4345  }
4346  if (!RC->contains(Reg) &&
4347  RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
4348  ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
4349  // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
4350  // subset of GPRRegClassId except it contains APSR as well.
4351  RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4352  }
4353  if (Reg == ARM::VPR && (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
4354  RC == &ARMMCRegisterClasses[ARM::DPRRegClassID])) {
4355  RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
4356  EReg = MRI->getEncodingValue(Reg);
4357  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
4358  continue;
4359  }
4360  // The register must be in the same register class as the first.
4361  if (!RC->contains(Reg))
4362  return Error(RegLoc, "invalid register in register list");
4363  // In most cases, the list must be monotonically increasing. An
4364  // exception is CLRM, which is order-independent anyway, so
4365  // there's no potential for confusion if you write clrm {r2,r1}
4366  // instead of clrm {r1,r2}.
4367  if (EnforceOrder &&
4368  MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
4369  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4370  Warning(RegLoc, "register list not in ascending order");
4371  else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4372  return Error(RegLoc, "register list not in ascending order");
4373  }
4374  if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
4375  Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4376  ") in register list");
4377  continue;
4378  }
4379  // VFP register lists must also be contiguous.
4380  if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
4381  RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
4382  Reg != OldReg + 1)
4383  return Error(RegLoc, "non-contiguous register range");
4384  EReg = MRI->getEncodingValue(Reg);
4385  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
4386  if (isQReg) {
4387  EReg = MRI->getEncodingValue(++Reg);
4388  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
4389  }
4390  }
4391 
4392  if (Parser.getTok().isNot(AsmToken::RCurly))
4393  return Error(Parser.getTok().getLoc(), "'}' expected");
4394  SMLoc E = Parser.getTok().getEndLoc();
4395  Parser.Lex(); // Eat '}' token.
4396 
4397  // Push the register list operand.
4398  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
4399 
4400  // The ARM system instruction variants for LDM/STM have a '^' token here.
4401  if (Parser.getTok().is(AsmToken::Caret)) {
4402  Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
4403  Parser.Lex(); // Eat '^' token.
4404  }
4405 
4406  return false;
4407 }
4408 
4409 // Helper function to parse the lane index for vector lists.
4410 OperandMatchResultTy ARMAsmParser::
4411 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
4412  MCAsmParser &Parser = getParser();
4413  Index = 0; // Always return a defined index value.
4414  if (Parser.getTok().is(AsmToken::LBrac)) {
4415  Parser.Lex(); // Eat the '['.
4416  if (Parser.getTok().is(AsmToken::RBrac)) {
4417  // "Dn[]" is the 'all lanes' syntax.
4418  LaneKind = AllLanes;
4419  EndLoc = Parser.getTok().getEndLoc();
4420  Parser.Lex(); // Eat the ']'.
4421  return MatchOperand_Success;
4422  }
4423 
4424  // There's an optional '#' token here. Normally there wouldn't be, but
4425  // inline assemble puts one in, and it's friendly to accept that.
4426  if (Parser.getTok().is(AsmToken::Hash))
4427  Parser.Lex(); // Eat '#' or '$'.
4428 
4429  const MCExpr *LaneIndex;
4430  SMLoc Loc = Parser.getTok().getLoc();
4431  if (getParser().parseExpression(LaneIndex)) {
4432  Error(Loc, "illegal expression");
4433  return MatchOperand_ParseFail;
4434  }
4435  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
4436  if (!CE) {
4437  Error(Loc, "lane index must be empty or an integer");
4438  return MatchOperand_ParseFail;
4439  }
4440  if (Parser.getTok().isNot(AsmToken::RBrac)) {
4441  Error(Parser.getTok().getLoc(), "']' expected");
4442  return MatchOperand_ParseFail;
4443  }
4444  EndLoc = Parser.getTok().getEndLoc();
4445  Parser.Lex(); // Eat the ']'.
4446  int64_t Val = CE->getValue();
4447 
4448  // FIXME: Make this range check context sensitive for .8, .16, .32.
4449  if (Val < 0 || Val > 7) {
4450  Error(Parser.getTok().getLoc(), "lane index out of range");
4451  return MatchOperand_ParseFail;
4452  }
4453  Index = Val;
4454  LaneKind = IndexedLane;
4455  return MatchOperand_Success;
4456  }
4457  LaneKind = NoLanes;
4458  return MatchOperand_Success;
4459 }
4460 
4461 // parse a vector register list
4463 ARMAsmParser::parseVectorList(OperandVector &Operands) {
4464  MCAsmParser &Parser = getParser();
4465  VectorLaneTy LaneKind;
4466  unsigned LaneIndex;
4467  SMLoc S = Parser.getTok().getLoc();
4468  // As an extension (to match gas), support a plain D register or Q register
4469  // (without encosing curly braces) as a single or double entry list,
4470  // respectively.
4471  if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
4472  SMLoc E = Parser.getTok().getEndLoc();
4473  int Reg = tryParseRegister();
4474  if (Reg == -1)
4475  return MatchOperand_NoMatch;
4476  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
4477  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4478  if (Res != MatchOperand_Success)
4479  return Res;
4480  switch (LaneKind) {
4481  case NoLanes:
4482  Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
4483  break;
4484  case AllLanes:
4485  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
4486  S, E));
4487  break;
4488  case IndexedLane:
4489  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
4490  LaneIndex,
4491  false, S, E));
4492  break;
4493  }
4494  return MatchOperand_Success;
4495  }
4496  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4497  Reg = getDRegFromQReg(Reg);
4498  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4499  if (Res != MatchOperand_Success)
4500  return Res;
4501  switch (LaneKind) {
4502  case NoLanes:
4503  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4504  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4505  Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
4506  break;
4507  case AllLanes:
4508  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4509  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4510  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
4511  S, E));
4512  break;
4513  case IndexedLane:
4514  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
4515  LaneIndex,
4516  false, S, E));
4517  break;
4518  }
4519  return MatchOperand_Success;
4520  }
4521  Error(S, "vector register expected");
4522  return MatchOperand_ParseFail;
4523  }
4524 
4525  if (Parser.getTok().isNot(AsmToken::LCurly))
4526  return MatchOperand_NoMatch;
4527 
4528  Parser.Lex(); // Eat '{' token.
4529  SMLoc RegLoc = Parser.getTok().getLoc();
4530 
4531  int Reg = tryParseRegister();
4532  if (Reg == -1) {
4533  Error(RegLoc, "register expected");
4534  return MatchOperand_ParseFail;
4535  }
4536  unsigned Count = 1;
4537  int Spacing = 0;
4538  unsigned FirstReg = Reg;
4539 
4540  if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4541  Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
4542  return MatchOperand_ParseFail;
4543  }
4544  // The list is of D registers, but we also allow Q regs and just interpret
4545  // them as the two D sub-registers.
4546  else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4547  FirstReg = Reg = getDRegFromQReg(Reg);
4548  Spacing = 1; // double-spacing requires explicit D registers, otherwise
4549  // it's ambiguous with four-register single spaced.
4550  ++Reg;
4551  ++Count;
4552  }
4553 
4554  SMLoc E;
4555  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4556  return MatchOperand_ParseFail;
4557 
4558  while (Parser.getTok().is(AsmToken::Comma) ||
4559  Parser.getTok().is(AsmToken::Minus)) {
4560  if (Parser.getTok().is(AsmToken::Minus)) {
4561  if (!Spacing)
4562  Spacing = 1; // Register range implies a single spaced list.
4563  else if (Spacing == 2) {
4564  Error(Parser.getTok().getLoc(),
4565  "sequential registers in double spaced list");
4566  return MatchOperand_ParseFail;
4567  }
4568  Parser.Lex(); // Eat the minus.
4569  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4570  int EndReg = tryParseRegister();
4571  if (EndReg == -1) {
4572  Error(AfterMinusLoc, "register expected");
4573  return MatchOperand_ParseFail;
4574  }
4575  // Allow Q regs and just interpret them as the two D sub-registers.
4576  if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4577  EndReg = getDRegFromQReg(EndReg) + 1;
4578  // If the register is the same as the start reg, there's nothing
4579  // more to do.
4580  if (Reg == EndReg)
4581  continue;
4582  // The register must be in the same register class as the first.
4583  if ((hasMVE() &&
4584  !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4585  (!hasMVE() &&
4586  !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
4587  Error(AfterMinusLoc, "invalid register in register list");
4588  return MatchOperand_ParseFail;
4589  }
4590  // Ranges must go from low to high.
4591  if (Reg > EndReg) {
4592  Error(AfterMinusLoc, "bad range in register list");
4593  return MatchOperand_ParseFail;
4594  }
4595  // Parse the lane specifier if present.
4596  VectorLaneTy NextLaneKind;
4597  unsigned NextLaneIndex;
4598  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4600  return MatchOperand_ParseFail;
4601  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4602  Error(AfterMinusLoc, "mismatched lane index in register list");
4603  return MatchOperand_ParseFail;
4604  }
4605 
4606  // Add all the registers in the range to the register list.
4607  Count += EndReg - Reg;
4608  Reg = EndReg;
4609  continue;
4610  }
4611  Parser.Lex(); // Eat the comma.
4612  RegLoc = Parser.getTok().getLoc();
4613  int OldReg = Reg;
4614  Reg = tryParseRegister();
4615  if (Reg == -1) {
4616  Error(RegLoc, "register expected");
4617  return MatchOperand_ParseFail;
4618  }
4619 
4620  if (hasMVE()) {
4621  if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4622  Error(RegLoc, "vector register in range Q0-Q7 expected");
4623  return MatchOperand_ParseFail;
4624  }
4625  Spacing = 1;
4626  }
4627  // vector register lists must be contiguous.
4628  // It's OK to use the enumeration values directly here rather, as the
4629  // VFP register classes have the enum sorted properly.
4630  //
4631  // The list is of D registers, but we also allow Q regs and just interpret
4632  // them as the two D sub-registers.
4633  else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4634  if (!Spacing)
4635  Spacing = 1; // Register range implies a single spaced list.
4636  else if (Spacing == 2) {
4637  Error(RegLoc,
4638  "invalid register in double-spaced list (must be 'D' register')");
4639  return MatchOperand_ParseFail;
4640  }
4641  Reg = getDRegFromQReg(Reg);
4642  if (Reg != OldReg + 1) {
4643  Error(RegLoc, "non-contiguous register range");
4644  return MatchOperand_ParseFail;
4645  }
4646  ++Reg;
4647  Count += 2;
4648  // Parse the lane specifier if present.
4649  VectorLaneTy NextLaneKind;
4650  unsigned NextLaneIndex;
4651  SMLoc LaneLoc = Parser.getTok().getLoc();
4652  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4654  return MatchOperand_ParseFail;
4655  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4656  Error(LaneLoc, "mismatched lane index in register list");
4657  return MatchOperand_ParseFail;
4658  }
4659  continue;
4660  }
4661  // Normal D register.
4662  // Figure out the register spacing (single or double) of the list if
4663  // we don't know it already.
4664  if (!Spacing)
4665  Spacing = 1 + (Reg == OldReg + 2);
4666 
4667  // Just check that it's contiguous and keep going.
4668  if (Reg != OldReg + Spacing) {
4669  Error(RegLoc, "non-contiguous register range");
4670  return MatchOperand_ParseFail;
4671  }
4672  ++Count;
4673  // Parse the lane specifier if present.
4674  VectorLaneTy NextLaneKind;
4675  unsigned NextLaneIndex;
4676  SMLoc EndLoc = Parser.getTok().getLoc();
4677  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4678  return MatchOperand_ParseFail;
4679  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4680  Error(EndLoc, "mismatched lane index in register list");
4681  return MatchOperand_ParseFail;
4682  }
4683  }
4684 
4685  if (Parser.getTok().isNot(AsmToken::RCurly)) {
4686  Error(Parser.getTok().getLoc(), "'}' expected");
4687  return MatchOperand_ParseFail;
4688  }
4689  E = Parser.getTok().getEndLoc();
4690  Parser.Lex(); // Eat '}' token.
4691 
4692  switch (LaneKind) {
4693  case NoLanes:
4694  case AllLanes: {
4695  // Two-register operands have been converted to the
4696  // composite register classes.
4697  if (Count == 2 && !hasMVE()) {
4698  const MCRegisterClass *RC = (Spacing == 1) ?
4699  &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4700  &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4701  FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4702  }
4703  auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
4704  ARMOperand::CreateVectorListAllLanes);
4705  Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
4706  break;
4707  }
4708  case IndexedLane:
4709  Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4710  LaneIndex,
4711  (Spacing == 2),
4712  S, E));
4713  break;
4714  }
4715  return MatchOperand_Success;
4716 }
4717 
4718 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4720 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4721  MCAsmParser &Parser = getParser();
4722  SMLoc S = Parser.getTok().getLoc();
4723  const AsmToken &Tok = Parser.getTok();
4724  unsigned Opt;
4725 
4726  if (Tok.is(AsmToken::Identifier)) {
4727  StringRef OptStr = Tok.getString();
4728 
4729  Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4730  .Case("sy", ARM_MB::SY)
4731  .Case("st", ARM_MB::ST)
4732  .Case("ld", ARM_MB::LD)
4733  .Case("sh", ARM_MB::ISH)
4734  .Case("ish", ARM_MB::ISH)
4735  .Case("shst", ARM_MB::ISHST)
4736  .Case("ishst", ARM_MB::ISHST)
4737  .Case("ishld", ARM_MB::ISHLD)
4738  .Case("nsh", ARM_MB::NSH)
4739  .Case("un", ARM_MB::NSH)
4740  .Case("nshst", ARM_MB::NSHST)
4741  .Case("nshld", ARM_MB::NSHLD)
4742  .Case("unst", ARM_MB::NSHST)
4743  .Case("osh", ARM_MB::OSH)
4744  .Case("oshst", ARM_MB::OSHST)
4745  .Case("oshld", ARM_MB::OSHLD)
4746  .Default(~0U);
4747 
4748  // ishld, oshld, nshld and ld are only available from ARMv8.
4749  if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4750  Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4751  Opt = ~0U;
4752 
4753  if (Opt == ~0U)
4754  return MatchOperand_NoMatch;
4755 
4756  Parser.Lex(); // Eat identifier token.
4757  } else if (Tok.is(AsmToken::Hash) ||
4758  Tok.is(AsmToken::Dollar) ||
4759  Tok.is(AsmToken::Integer)) {
4760  if (Parser.getTok().isNot(AsmToken::Integer))
4761  Parser.Lex(); // Eat '#' or '$'.
4762  SMLoc Loc = Parser.getTok().getLoc();
4763 
4764  const MCExpr *MemBarrierID;
4765  if (getParser().parseExpression(MemBarrierID)) {
4766  Error(Loc, "illegal expression");
4767  return MatchOperand_ParseFail;
4768  }
4769 
4770  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4771  if (!CE) {
4772  Error(Loc, "constant expression expected");
4773  return MatchOperand_ParseFail;
4774  }
4775 
4776  int Val = CE->getValue();
4777  if (Val & ~0xf) {
4778  Error(Loc, "immediate value out of range");
4779  return MatchOperand_ParseFail;
4780  }
4781 
4782  Opt = ARM_MB::RESERVED_0 + Val;
4783  } else
4784  return MatchOperand_ParseFail;
4785 
4786  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4787  return MatchOperand_Success;
4788 }
4789 
4791 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
4792  MCAsmParser &Parser = getParser();
4793  SMLoc S = Parser.getTok().getLoc();
4794  const AsmToken &Tok = Parser.getTok();
4795 
4796  if (Tok.isNot(AsmToken::Identifier))
4797  return MatchOperand_NoMatch;
4798 
4799  if (!Tok.getString().equals_lower("csync"))
4800  return MatchOperand_NoMatch;
4801 
4802  Parser.Lex(); // Eat identifier token.
4803 
4804  Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
4805  return MatchOperand_Success;
4806 }
4807 
4808 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4810 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4811  MCAsmParser &Parser = getParser();
4812  SMLoc S = Parser.getTok().getLoc();
4813  const AsmToken &Tok = Parser.getTok();
4814  unsigned Opt;
4815 
4816  if (Tok.is(AsmToken::Identifier)) {
4817  StringRef OptStr = Tok.getString();
4818 
4819  if (OptStr.equals_lower("sy"))
4820  Opt = ARM_ISB::SY;
4821  else
4822  return MatchOperand_NoMatch;
4823 
4824  Parser.Lex(); // Eat identifier token.
4825  } else if (Tok.is(AsmToken::Hash) ||
4826  Tok.is(AsmToken::Dollar) ||
4827  Tok.is(AsmToken::Integer)) {
4828  if (Parser.getTok().isNot(AsmToken::Integer))
4829  Parser.Lex(); // Eat '#' or '$'.
4830  SMLoc Loc = Parser.getTok().getLoc();
4831 
4832  const MCExpr *ISBarrierID;
4833  if (getParser().parseExpression(ISBarrierID)) {
4834  Error(Loc, "illegal expression");
4835  return MatchOperand_ParseFail;
4836  }
4837 
4838  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4839  if (!CE) {
4840  Error(Loc, "constant expression expected");
4841  return MatchOperand_ParseFail;
4842  }
4843 
4844  int Val = CE->getValue();
4845  if (Val & ~0xf) {
4846  Error(Loc, "immediate value out of range");
4847  return MatchOperand_ParseFail;
4848  }
4849 
4850  Opt = ARM_ISB::RESERVED_0 + Val;
4851  } else
4852  return MatchOperand_ParseFail;
4853 
4854  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4855  (ARM_ISB::InstSyncBOpt)Opt, S));
4856  return MatchOperand_Success;
4857 }
4858 
4859 
4860 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4862 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4863  MCAsmParser &Parser = getParser();
4864  SMLoc S = Parser.getTok().getLoc();
4865  const AsmToken &Tok = Parser.getTok();
4866  if (!Tok.is(AsmToken::Identifier))
4867  return MatchOperand_NoMatch;
4868  StringRef IFlagsStr = Tok.getString();
4869 
4870  // An iflags string of "none" is interpreted to mean that none of the AIF
4871  // bits are set. Not a terribly useful instruction, but a valid encoding.
4872  unsigned IFlags = 0;
4873  if (IFlagsStr != "none") {
4874  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4875  unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4876  .Case("a", ARM_PROC::A)
4877  .Case("i", ARM_PROC::I)
4878  .Case("f", ARM_PROC::F)
4879  .Default(~0U);
4880 
4881  // If some specific iflag is already set, it means that some letter is
4882  // present more than once, this is not acceptable.
4883  if (Flag == ~0U || (IFlags & Flag))
4884  return MatchOperand_NoMatch;
4885 
4886  IFlags |= Flag;
4887  }
4888  }
4889 
4890  Parser.Lex(); // Eat identifier token.
4891  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4892  return MatchOperand_Success;
4893 }
4894 
4895 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4897 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4898  MCAsmParser &Parser = getParser();
4899  SMLoc S = Parser.getTok().getLoc();
4900  const AsmToken &Tok = Parser.getTok();
4901 
4902  if (Tok.is(AsmToken::Integer)) {
4903  int64_t Val = Tok.getIntVal();
4904  if (Val > 255 || Val < 0) {
4905  return MatchOperand_NoMatch;
4906  }
4907  unsigned SYSmvalue = Val & 0xFF;
4908  Parser.Lex();
4909  Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4910  return MatchOperand_Success;
4911  }
4912 
4913  if (!Tok.is(AsmToken::Identifier))
4914  return MatchOperand_NoMatch;
4915  StringRef Mask = Tok.getString();
4916 
4917  if (isMClass()) {
4918  auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4919  if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4920  return MatchOperand_NoMatch;
4921 
4922  unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4923 
4924  Parser.Lex(); // Eat identifier token.
4925  Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4926  return MatchOperand_Success;
4927  }
4928 
4929  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4930  size_t Start = 0, Next = Mask.find('_');
4931  StringRef Flags = "";
4932  std::string SpecReg = Mask.slice(Start, Next).lower();
4933  if (Next != StringRef::npos)
4934  Flags = Mask.slice(Next+1, Mask.size());
4935 
4936  // FlagsVal contains the complete mask:
4937  // 3-0: Mask
4938  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4939  unsigned FlagsVal = 0;
4940 
4941  if (SpecReg == "apsr") {
4942  FlagsVal = StringSwitch<unsigned>(Flags)
4943  .Case("nzcvq", 0x8) // same as CPSR_f
4944  .Case("g", 0x4) // same as CPSR_s
4945  .Case("nzcvqg", 0xc) // same as CPSR_fs
4946  .Default(~0U);
4947 
4948  if (FlagsVal == ~0U) {
4949  if (!Flags.empty())
4950  return MatchOperand_NoMatch;
4951  else
4952  FlagsVal = 8; // No flag
4953  }
4954  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4955  // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4956  if (Flags == "all" || Flags == "")
4957  Flags = "fc";
4958  for (int i = 0, e = Flags.size(); i != e; ++i) {
4959  unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4960  .Case("c", 1)
4961  .Case("x", 2)
4962  .Case("s", 4)
4963  .Case("f", 8)
4964  .Default(~0U);
4965 
4966  // If some specific flag is already set, it means that some letter is
4967  // present more than once, this is not acceptable.
4968  if (Flag == ~0U || (FlagsVal & Flag))
4969  return MatchOperand_NoMatch;
4970  FlagsVal |= Flag;
4971  }
4972  } else // No match for special register.
4973  return MatchOperand_NoMatch;
4974 
4975  // Special register without flags is NOT equivalent to "fc" flags.
4976  // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4977  // two lines would enable gas compatibility at the expense of breaking
4978  // round-tripping.
4979  //
4980  // if (!FlagsVal)
4981  // FlagsVal = 0x9;
4982 
4983  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4984  if (SpecReg == "spsr")
4985  FlagsVal |= 16;
4986 
4987  Parser.Lex(); // Eat identifier token.
4988  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4989  return MatchOperand_Success;
4990 }
4991 
4992 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4993 /// use in the MRS/MSR instructions added to support virtualization.
4995 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4996  MCAsmParser &Parser = getParser();
4997  SMLoc S = Parser.getTok().getLoc();
4998  const AsmToken &Tok = Parser.getTok();
4999  if (!Tok.is(AsmToken::Identifier))
5000  return MatchOperand_NoMatch;
5001  StringRef RegName = Tok.getString();
5002 
5003  auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
5004  if (!TheReg)
5005  return MatchOperand_NoMatch;
5006  unsigned Encoding = TheReg->Encoding;
5007 
5008  Parser.Lex(); // Eat identifier token.
5009  Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
5010  return MatchOperand_Success;
5011 }
5012 
5014 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
5015  int High) {
5016  MCAsmParser &Parser = getParser();
5017  const AsmToken &Tok = Parser.getTok();
5018  if (Tok.isNot(AsmToken::Identifier)) {
5019  Error(Parser.getTok().getLoc(), Op + " operand expected.");
5020  return MatchOperand_ParseFail;
5021  }
5022  StringRef ShiftName = Tok.getString();
5023  std::string LowerOp = Op.lower();
5024  std::string UpperOp = Op.upper();
5025  if (ShiftName != LowerOp && ShiftName != UpperOp) {
5026  Error(Parser.getTok().getLoc(), Op + " operand expected.");
5027  return MatchOperand_ParseFail;
5028  }
5029  Parser.Lex(); // Eat shift type token.
5030 
5031  // There must be a '#' and a shift amount.
5032  if (Parser.getTok().isNot(AsmToken::Hash) &&
5033  Parser.getTok().isNot(AsmToken::Dollar)) {
5034  Error(Parser.getTok().getLoc(), "'#' expected");
5035  return MatchOperand_ParseFail;
5036  }
5037  Parser.Lex(); // Eat hash token.
5038 
5039  const MCExpr *ShiftAmount;
5040  SMLoc Loc = Parser.getTok().getLoc();
5041  SMLoc EndLoc;
5042  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5043  Error(Loc, "illegal expression");
5044  return MatchOperand_ParseFail;
5045  }
5046  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5047  if (!CE) {
5048  Error(Loc, "constant expression expected");
5049  return MatchOperand_ParseFail;
5050  }
5051  int Val = CE->getValue();
5052  if (Val < Low || Val > High) {
5053  Error(Loc, "immediate value out of range");
5054  return MatchOperand_ParseFail;
5055  }
5056 
5057  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
5058 
5059  return MatchOperand_Success;
5060 }
5061 
5063 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5064  MCAsmParser &Parser = getParser();
5065  const AsmToken &Tok = Parser.getTok();
5066  SMLoc S = Tok.getLoc();
5067  if (Tok.isNot(AsmToken::Identifier)) {
5068  Error(S, "'be' or 'le' operand expected");
5069  return MatchOperand_ParseFail;
5070  }
5071  int Val = StringSwitch<int>(Tok.getString().lower())
5072  .Case("be", 1)
5073  .Case("le", 0)
5074  .Default(-1);
5075  Parser.Lex(); // Eat the token.
5076 
5077  if (Val == -1) {
5078  Error(S, "'be' or 'le' operand expected");
5079  return MatchOperand_ParseFail;
5080  }
5081  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
5082  getContext()),
5083  S, Tok.getEndLoc()));
5084  return MatchOperand_Success;
5085 }
5086 
5087 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
5088 /// instructions. Legal values are:
5089 /// lsl #n 'n' in [0,31]
5090 /// asr #n 'n' in [1,32]
5091 /// n == 32 encoded as n == 0.
5093 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5094  MCAsmParser &Parser = getParser();
5095  const AsmToken &Tok = Parser.getTok();
5096  SMLoc S = Tok.getLoc();
5097  if (Tok.isNot(AsmToken::Identifier)) {
5098  Error(S, "shift operator 'asr' or 'lsl' expected");
5099  return MatchOperand_ParseFail;
5100  }
5101  StringRef ShiftName = Tok.getString();
5102  bool isASR;
5103  if (ShiftName == "lsl" || ShiftName == "LSL")
5104  isASR = false;
5105  else if (ShiftName == "asr" || ShiftName == "ASR")
5106  isASR = true;
5107  else {
5108  Error(S, "shift operator 'asr' or 'lsl' expected");
5109  return MatchOperand_ParseFail;
5110  }
5111  Parser.Lex(); // Eat the operator.
5112 
5113  // A '#' and a shift amount.
5114  if (Parser.getTok().isNot(AsmToken::Hash) &&
5115  Parser.getTok().isNot(AsmToken::Dollar)) {
5116  Error(Parser.getTok().getLoc(), "'#' expected");
5117  return MatchOperand_ParseFail;
5118  }
5119  Parser.Lex(); // Eat hash token.
5120  SMLoc ExLoc = Parser.getTok().getLoc();
5121 
5122  const MCExpr *ShiftAmount;
5123  SMLoc EndLoc;
5124  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5125  Error(ExLoc, "malformed shift expression");
5126  return MatchOperand_ParseFail;
5127  }
5128  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5129  if (!CE) {
5130  Error(ExLoc, "shift amount must be an immediate");
5131  return MatchOperand_ParseFail;
5132  }
5133 
5134  int64_t Val = CE->getValue();
5135  if (isASR) {
5136  // Shift amount must be in [1,32]
5137  if (Val < 1 || Val > 32) {
5138  Error(ExLoc, "'asr' shift amount must be in range [1,32]");
5139  return MatchOperand_ParseFail;
5140  }
5141  // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
5142  if (isThumb() && Val == 32) {
5143  Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
5144  return MatchOperand_ParseFail;
5145  }
5146  if (Val == 32) Val = 0;
5147  } else {
5148  // Shift amount must be in [1,32]
5149  if (Val < 0 || Val > 31) {
5150  Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
5151  return MatchOperand_ParseFail;
5152  }
5153  }
5154 
5155  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
5156 
5157  return MatchOperand_Success;
5158 }
5159 
5160 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
5161 /// of instructions. Legal values are:
5162 /// ror #n 'n' in {0, 8, 16, 24}
5164 ARMAsmParser::parseRotImm(OperandVector &Operands) {
5165  MCAsmParser &Parser = getParser();
5166  const AsmToken &Tok = Parser.getTok();
5167  SMLoc S = Tok.getLoc();
5168  if (Tok.isNot(AsmToken::Identifier))
5169  return MatchOperand_NoMatch;
5170  StringRef ShiftName = Tok.getString();
5171  if (ShiftName != "ror" && ShiftName != "ROR")
5172  return MatchOperand_NoMatch;
5173  Parser.Lex(); // Eat the operator.
5174 
5175  // A '#' and a rotate amount.
5176  if (Parser.getTok().isNot(AsmToken::Hash) &&
5177  Parser.getTok().isNot(AsmToken::Dollar)) {
5178  Error(Parser.getTok().getLoc(), "'#' expected");
5179  return MatchOperand_ParseFail;
5180  }
5181  Parser.Lex(); // Eat hash token.
5182  SMLoc ExLoc = Parser.getTok().getLoc();
5183 
5184  const MCExpr *ShiftAmount;
5185  SMLoc EndLoc;
5186  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5187  Error(ExLoc, "malformed rotate expression");
5188  return MatchOperand_ParseFail;
5189  }
5190  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5191  if (!CE) {
5192  Error(ExLoc, "rotate amount must be an immediate");
5193  return MatchOperand_ParseFail;
5194  }
5195 
5196  int64_t Val = CE->getValue();
5197  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
5198  // normally, zero is represented in asm by omitting the rotate operand
5199  // entirely.
5200  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
5201  Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
5202  return MatchOperand_ParseFail;
5203  }
5204 
5205  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
5206 
5207  return MatchOperand_Success;
5208 }
5209 
5211 ARMAsmParser::parseModImm(OperandVector &Operands) {
5212  MCAsmParser &Parser = getParser();
5213  MCAsmLexer &Lexer = getLexer();
5214  int64_t Imm1, Imm2;
5215 
5216  SMLoc S = Parser.getTok().getLoc();
5217 
5218  // 1) A mod_imm operand can appear in the place of a register name:
5219  // add r0, #mod_imm
5220  // add r0, r0, #mod_imm
5221  // to correctly handle the latter, we bail out as soon as we see an
5222  // identifier.
5223  //
5224  // 2) Similarly, we do not want to parse into complex operands:
5225  // mov r0, #mod_imm
5226  // mov r0, :lower16:(_foo)
5227  if (Parser.getTok().is(AsmToken::Identifier) ||
5228  Parser.getTok().is(AsmToken::Colon))
5229  return MatchOperand_NoMatch;
5230 
5231  // Hash (dollar) is optional as per the ARMARM
5232  if (Parser.getTok().is(AsmToken::Hash) ||
5233  Parser.getTok().is(AsmToken::Dollar)) {
5234  // Avoid parsing into complex operands (#:)
5235  if (Lexer.peekTok().is(AsmToken::Colon))
5236  return MatchOperand_NoMatch;
5237 
5238  // Eat the hash (dollar)
5239  Parser.Lex();
5240  }
5241 
5242  SMLoc Sx1, Ex1;
5243  Sx1 = Parser.getTok().getLoc();
5244  const MCExpr *Imm1Exp;
5245  if (getParser().parseExpression(Imm1Exp, Ex1)) {
5246  Error(Sx1, "malformed expression");
5247  return MatchOperand_ParseFail;
5248  }
5249 
5250  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
5251 
5252  if (CE) {
5253  // Immediate must fit within 32-bits
5254  Imm1 = CE->getValue();
5255  int Enc = ARM_AM::getSOImmVal(Imm1);
5256  if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
5257  // We have a match!
5258  Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
5259  (Enc & 0xF00) >> 7,
5260  Sx1, Ex1));
5261  return MatchOperand_Success;
5262  }
5263 
5264  // We have parsed an immediate which is not for us, fallback to a plain
5265  // immediate. This can happen for instruction aliases. For an example,
5266  // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
5267  // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
5268  // instruction with a mod_imm operand. The alias is defined such that the
5269  // parser method is shared, that's why we have to do this here.
5270  if (Parser.getTok().is(AsmToken::EndOfStatement)) {
5271  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5272  return MatchOperand_Success;
5273  }
5274  } else {
5275  // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5276  // MCFixup). Fallback to a plain immediate.
5277  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5278  return MatchOperand_Success;
5279  }
5280 
5281  // From this point onward, we expect the input to be a (#bits, #rot) pair
5282  if (Parser.getTok().isNot(AsmToken::Comma)) {
5283  Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
5284  return MatchOperand_ParseFail;
5285  }
5286 
5287  if (Imm1 & ~0xFF) {
5288  Error(Sx1, "immediate operand must a number in the range [0, 255]");
5289  return MatchOperand_ParseFail;
5290  }
5291 
5292  // Eat the comma
5293  Parser.Lex();
5294 
5295  // Repeat for #rot
5296  SMLoc Sx2, Ex2;
5297  Sx2 = Parser.getTok().getLoc();
5298 
5299  // Eat the optional hash (dollar)
5300  if (Parser.getTok().is(AsmToken::Hash) ||
5301  Parser.getTok().is(AsmToken::Dollar))
5302  Parser.Lex();
5303 
5304  const MCExpr *Imm2Exp;
5305  if (getParser().parseExpression(Imm2Exp, Ex2)) {
5306  Error(Sx2, "malformed expression");
5307  return MatchOperand_ParseFail;
5308  }
5309 
5310  CE = dyn_cast<MCConstantExpr>(Imm2Exp);
5311 
5312  if (CE) {
5313  Imm2 = CE->getValue();
5314  if (!(Imm2 & ~0x1E)) {
5315  // We have a match!
5316  Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
5317  return MatchOperand_Success;
5318  }
5319  Error(Sx2, "immediate operand must an even number in the range [0, 30]");
5320  return MatchOperand_ParseFail;
5321  } else {
5322  Error(Sx2, "constant expression expected");
5323  return MatchOperand_ParseFail;
5324  }
5325 }
5326 
5328 ARMAsmParser::parseBitfield(OperandVector &Operands) {
5329  MCAsmParser &Parser = getParser();
5330  SMLoc S = Parser.getTok().getLoc();
5331  // The bitfield descriptor is really two operands, the LSB and the width.
5332  if (Parser.getTok().isNot(AsmToken::Hash) &&
5333  Parser.getTok().isNot(AsmToken::Dollar)) {
5334  Error(Parser.getTok().getLoc(), "'#' expected");
5335  return MatchOperand_ParseFail;
5336  }
5337  Parser.Lex(); // Eat hash token.
5338 
5339  const MCExpr *LSBExpr;
5340  SMLoc E = Parser.getTok().getLoc();
5341  if (getParser().parseExpression(LSBExpr)) {
5342  Error(E, "malformed immediate expression");
5343  return MatchOperand_ParseFail;
5344  }
5345  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
5346  if (!CE) {
5347  Error(E, "'lsb' operand must be an immediate");
5348  return MatchOperand_ParseFail;
5349  }
5350 
5351  int64_t LSB = CE->getValue();
53