25#define DEBUG_TYPE "regalloc"
39 while (SegPos.valid()) {
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
41 if (++RegPos == RegEnd)
43 SegPos.advanceTo(RegPos->start);
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
68 assert(SegPos.value() == &VirtReg &&
"Inconsistent LiveInterval");
74 RegPos =
Range.advanceTo(RegPos, SegPos.start());
78 SegPos.advanceTo(RegPos->start);
89 OS <<
" [" << SI.start() <<
' ' << SI.stop()
99 VisitedVRegs.
set(SI.value()->reg());
115bool LiveIntervalUnion::Query::isSeenInterference(
130LiveIntervalUnion::Query::collectInterferingVRegs(
unsigned MaxInterferingRegs) {
132 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
133 return InterferingVRegs.size();
136 if (!CheckedFirstInterference) {
137 CheckedFirstInterference =
true;
140 if (LR->empty() || LiveUnion->empty()) {
141 SeenAllInterferences =
true;
147 LiveUnionI.setMap(LiveUnion->getMap());
148 LiveUnionI.find(LRI->start);
153 while (LiveUnionI.valid()) {
154 assert(LRI != LREnd &&
"Reached end of LR");
157 while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
160 if (VReg != RecentReg && !isSeenInterference(VReg)) {
162 InterferingVRegs.push_back(VReg);
163 if (InterferingVRegs.size() >= MaxInterferingRegs)
164 return InterferingVRegs.
size();
167 if (!(++LiveUnionI).valid()) {
168 SeenAllInterferences =
true;
169 return InterferingVRegs.size();
175 assert(LRI->end <= LiveUnionI.start() &&
"Expected non-overlap");
178 LRI = LR->advanceTo(LRI, LiveUnionI.start());
183 if (LRI->start < LiveUnionI.stop())
187 LiveUnionI.advanceTo(LRI->start);
189 SeenAllInterferences =
true;
190 return InterferingVRegs.size();
202 for (
unsigned i = 0; i !=
Size; ++i)
209 for (
unsigned i = 0; i !=
Size; ++i)
unsigned const TargetRegisterInfo * TRI
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const_iterator begin() const
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end().
friend class const_iterator
void init(LiveIntervalUnion::Allocator &, unsigned Size)
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
void unify(const LiveInterval &VirtReg, const LiveRange &Range)
const LiveInterval * getOneVReg() const
NDEBUG.
void extract(const LiveInterval &VirtReg, const LiveRange &Range)
LiveSegments::iterator SegmentIter
void verify(LiveVirtRegBitSet &VisitedVRegs)
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
LiveSegments::Allocator Allocator
LiveInterval - This class represents the liveness of a register, or stack slot.
This class represents the liveness of a register, stack slot, etc.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_malloc(size_t Sz)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.