LLVM 17.0.0git
LiveIntervalUnion.cpp
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1//===- LiveIntervalUnion.cpp - Live interval union data structure ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// LiveIntervalUnion represents a coalesced set of live intervals. This may be
10// used during coalescing to represent a congruence class, or during register
11// allocation to model liveness of a physical register.
12//
13//===----------------------------------------------------------------------===//
14
16#include "llvm/ADT/STLExtras.h"
21#include <cassert>
22#include <cstdlib>
23
24using namespace llvm;
25
26#define DEBUG_TYPE "regalloc"
27
28// Merge a LiveInterval's segments. Guarantee no overlaps.
30 const LiveRange &Range) {
31 if (Range.empty())
32 return;
33 ++Tag;
34
35 // Insert each of the virtual register's live segments into the map.
36 LiveRange::const_iterator RegPos = Range.begin();
37 LiveRange::const_iterator RegEnd = Range.end();
38 SegmentIter SegPos = Segments.find(RegPos->start);
39
40 while (SegPos.valid()) {
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
42 if (++RegPos == RegEnd)
43 return;
44 SegPos.advanceTo(RegPos->start);
45 }
46
47 // We have reached the end of Segments, so it is no longer necessary to search
48 // for the insertion position.
49 // It is faster to insert the end first.
50 --RegEnd;
51 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
52 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
54}
55
56// Remove a live virtual register's segments from this union.
58 const LiveRange &Range) {
59 if (Range.empty())
60 return;
61 ++Tag;
62
63 // Remove each of the virtual register's live segments from the map.
64 LiveRange::const_iterator RegPos = Range.begin();
65 LiveRange::const_iterator RegEnd = Range.end();
66 SegmentIter SegPos = Segments.find(RegPos->start);
67
68 while (true) {
69 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
70 SegPos.erase();
71 if (!SegPos.valid())
72 return;
73
74 // Skip all segments that may have been coalesced.
75 RegPos = Range.advanceTo(RegPos, SegPos.start());
76 if (RegPos == RegEnd)
77 return;
78
79 SegPos.advanceTo(RegPos->start);
80 }
81}
82
83void
85 if (empty()) {
86 OS << " empty\n";
87 return;
88 }
89 for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
90 OS << " [" << SI.start() << ' ' << SI.stop()
91 << "):" << printReg(SI.value()->reg(), TRI);
92 }
93 OS << '\n';
94}
95
96#ifndef NDEBUG
97// Verify the live intervals in this union and add them to the visited set.
99 for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
100 VisitedVRegs.set(SI.value()->reg());
101}
102#endif //!NDEBUG
103
105 if (empty())
106 return nullptr;
107 for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
108 // return the first valid live interval
109 return SI.value();
110 }
111 return nullptr;
112}
113
114// Scan the vector of interfering virtual registers in this union. Assume it's
115// quite small.
116bool LiveIntervalUnion::Query::isSeenInterference(
117 const LiveInterval *VirtReg) const {
118 return is_contained(InterferingVRegs, VirtReg);
119}
120
121// Collect virtual registers in this union that interfere with this
122// query's live virtual register.
123//
124// The query state is one of:
125//
126// 1. CheckedFirstInterference == false: Iterators are uninitialized.
127// 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
128// 3. Iterators left at the last seen intersection.
129//
130unsigned
131LiveIntervalUnion::Query::collectInterferingVRegs(unsigned MaxInterferingRegs) {
132 // Fast path return if we already have the desired information.
133 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
134 return InterferingVRegs.size();
135
136 // Set up iterators on the first call.
137 if (!CheckedFirstInterference) {
138 CheckedFirstInterference = true;
139
140 // Quickly skip interference check for empty sets.
141 if (LR->empty() || LiveUnion->empty()) {
142 SeenAllInterferences = true;
143 return 0;
144 }
145
146 // In most cases, the union will start before LR.
147 LRI = LR->begin();
148 LiveUnionI.setMap(LiveUnion->getMap());
149 LiveUnionI.find(LRI->start);
150 }
151
152 LiveRange::const_iterator LREnd = LR->end();
153 const LiveInterval *RecentReg = nullptr;
154 while (LiveUnionI.valid()) {
155 assert(LRI != LREnd && "Reached end of LR");
156
157 // Check for overlapping interference.
158 while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
159 // This is an overlap, record the interfering register.
160 const LiveInterval *VReg = LiveUnionI.value();
161 if (VReg != RecentReg && !isSeenInterference(VReg)) {
162 RecentReg = VReg;
163 InterferingVRegs.push_back(VReg);
164 if (InterferingVRegs.size() >= MaxInterferingRegs)
165 return InterferingVRegs.size();
166 }
167 // This LiveUnion segment is no longer interesting.
168 if (!(++LiveUnionI).valid()) {
169 SeenAllInterferences = true;
170 return InterferingVRegs.size();
171 }
172 }
173
174 // The iterators are now not overlapping, LiveUnionI has been advanced
175 // beyond LRI.
176 assert(LRI->end <= LiveUnionI.start() && "Expected non-overlap");
177
178 // Advance the iterator that ends first.
179 LRI = LR->advanceTo(LRI, LiveUnionI.start());
180 if (LRI == LREnd)
181 break;
182
183 // Detect overlap, handle above.
184 if (LRI->start < LiveUnionI.stop())
185 continue;
186
187 // Still not overlapping. Catch up LiveUnionI.
188 LiveUnionI.advanceTo(LRI->start);
189 }
190 SeenAllInterferences = true;
191 return InterferingVRegs.size();
192}
193
195 unsigned NSize) {
196 // Reuse existing allocation.
197 if (NSize == Size)
198 return;
199 clear();
200 Size = NSize;
201 LIUs = static_cast<LiveIntervalUnion*>(
202 safe_malloc(sizeof(LiveIntervalUnion)*NSize));
203 for (unsigned i = 0; i != Size; ++i)
204 new(LIUs + i) LiveIntervalUnion(Alloc);
205}
206
208 if (!LIUs)
209 return;
210 for (unsigned i = 0; i != Size; ++i)
211 LIUs[i].~LiveIntervalUnion();
212 free(LIUs);
213 Size = 0;
214 LIUs = nullptr;
215}
uint64_t Size
unsigned const TargetRegisterInfo * TRI
@ SI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SparseBitVector class.
const_iterator begin() const
Definition: IntervalMap.h:1146
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end().
Definition: IntervalMap.h:1172
void init(LiveIntervalUnion::Allocator &, unsigned Size)
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
void unify(const LiveInterval &VirtReg, const LiveRange &Range)
const LiveInterval * getOneVReg() const
NDEBUG.
void extract(const LiveInterval &VirtReg, const LiveRange &Range)
LiveSegments::iterator SegmentIter
void verify(LiveVirtRegBitSet &VisitedVRegs)
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
LiveSegments::Allocator Allocator
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
size_t size() const
Definition: LiveInterval.h:305
void set(unsigned Idx)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_malloc(size_t Sz)
Definition: MemAlloc.h:25
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1869
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.