94 if (
MI->memoperands_empty())
99 EE =
MI->memoperands_end(); MMOI != EE; ++MMOI)
100 if ((*MMOI)->getAlign() < Alignment)
101 Alignment = (*MMOI)->getAlign();
103 unsigned AlignmentHint = 0;
104 if (Alignment >=
Align(16))
106 else if (Alignment >=
Align(8))
108 if (AlignmentHint == 0)
122 .
addReg(
MI->getOperand(3).getReg());
141void SystemZAsmPrinter::emitCallInformation(CallType CT) {
150 auto Key = std::make_pair(
Sym, SlotKind);
151 auto It = Displacements.find(Key);
153 if (It != Displacements.end())
167 uint32_t Displacement = NextDisplacement;
168 Displacements[std::make_pair(
Sym, SlotKind)] = NextDisplacement;
169 NextDisplacement +=
Length;
175SystemZAsmPrinter::AssociatedDataAreaTable::insert(
const MachineOperand MO) {
189 return insert(
Sym, ADAslotType);
193 SystemZ_MC::verifyInstructionPredicates(
MI->getOpcode(),
198 switch (
MI->getOpcode()) {
199 case SystemZ::Return:
204 case SystemZ::Return_XPLINK:
211 case SystemZ::CondReturn:
218 case SystemZ::CondReturn_XPLINK:
227 case SystemZ::CRBReturn:
236 case SystemZ::CGRBReturn:
245 case SystemZ::CIBReturn:
254 case SystemZ::CGIBReturn:
263 case SystemZ::CLRBReturn:
272 case SystemZ::CLGRBReturn:
281 case SystemZ::CLIBReturn:
290 case SystemZ::CLGIBReturn:
299 case SystemZ::CallBRASL_XPLINK64:
302 .addReg(SystemZ::R7D)
303 .addExpr(
Lower.getExpr(
MI->getOperand(0),
305 emitCallInformation(CallType::BRASL7);
308 case SystemZ::CallBASR_XPLINK64:
310 .addReg(SystemZ::R7D)
311 .addReg(
MI->getOperand(0).getReg()));
312 emitCallInformation(CallType::BASR76);
315 case SystemZ::CallBASR_STACKEXT:
317 .addReg(SystemZ::R3D)
318 .addReg(
MI->getOperand(0).getReg()));
319 emitCallInformation(CallType::BASR33);
322 case SystemZ::ADA_ENTRY_VALUE:
323 case SystemZ::ADA_ENTRY: {
326 uint32_t Disp = ADATable.insert(
MI->getOperand(1));
327 Register TargetReg =
MI->getOperand(0).getReg();
330 Disp +=
MI->getOperand(3).getImm();
331 bool LoadAddr =
MI->getOpcode() == SystemZ::ADA_ENTRY;
333 unsigned Op0 = LoadAddr ? SystemZ::LA : SystemZ::LG;
334 unsigned Op =
TII->getOpcodeForOffset(Op0, Disp);
338 if (TargetReg != ADAReg) {
339 IndexReg = TargetReg;
343 MCInstBuilder(SystemZ::LLILF).addReg(TargetReg).addImm(Disp));
347 MCInstBuilder(SystemZ::ALGFI).addReg(TargetReg).addImm(Disp));
359 case SystemZ::CallBRASL:
365 case SystemZ::CallBASR:
368 .
addReg(
MI->getOperand(0).getReg());
371 case SystemZ::CallJG:
376 case SystemZ::CallBRCL:
383 case SystemZ::CallBR:
385 .
addReg(
MI->getOperand(0).getReg());
388 case SystemZ::CallBCR:
392 .
addReg(
MI->getOperand(2).getReg());
395 case SystemZ::CRBCall:
404 case SystemZ::CGRBCall:
413 case SystemZ::CIBCall:
422 case SystemZ::CGIBCall:
431 case SystemZ::CLRBCall:
440 case SystemZ::CLGRBCall:
449 case SystemZ::CLIBCall:
458 case SystemZ::CLGIBCall:
467 case SystemZ::TLS_GDCALL:
474 case SystemZ::TLS_LDCALL:
487 case SystemZ::IILF64:
490 .
addImm(
MI->getOperand(2).getImm());
493 case SystemZ::IIHF64:
496 .
addImm(
MI->getOperand(2).getImm());
499 case SystemZ::RISBHH:
500 case SystemZ::RISBHL:
504 case SystemZ::RISBLH:
505 case SystemZ::RISBLL:
509 case SystemZ::VLVGP32:
574#define LOWER_LOW(NAME) \
575 case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
591#define LOWER_HIGH(NAME) \
592 case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
608 case SystemZ::Serialize:
621 case SystemZ::Trap: {
634 case SystemZ::CondTrap: {
647 case TargetOpcode::FENTRY_CALL:
651 case TargetOpcode::STACKMAP:
655 case TargetOpcode::PATCHPOINT:
659 case SystemZ::EXRL_Pseudo: {
660 unsigned TargetInsOpc =
MI->getOperand(0).getImm();
661 Register LenMinus1Reg =
MI->getOperand(1).getReg();
662 Register DestReg =
MI->getOperand(2).getReg();
663 int64_t DestDisp =
MI->getOperand(3).getImm();
665 int64_t SrcDisp =
MI->getOperand(5).getImm();
672 SystemZTargetStreamer::EXRLT2SymMap::iterator
I =
681 MCInstBuilder(SystemZ::EXRL).addReg(LenMinus1Reg).addExpr(Dot));
700 else if (NumBytes < 4) {
702 MCInstBuilder(SystemZ::BCRAsm).addImm(0).addReg(SystemZ::R0D), STI);
705 else if (NumBytes < 6) {
707 MCInstBuilder(SystemZ::BCAsm).addImm(0).addReg(0).addImm(0).addReg(0),
716 MCInstBuilder(SystemZ::BRCLAsm).addImm(0).addExpr(Dot), STI);
750 unsigned NumNOPBytes =
MI.getOperand(1).getImm();
757 assert(NumNOPBytes % 2 == 0 &&
"Invalid number of NOP bytes requested!");
760 unsigned ShadowBytes = 0;
764 while (ShadowBytes < NumNOPBytes) {
766 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
767 MII->getOpcode() == TargetOpcode::STACKMAP)
769 ShadowBytes +=
TII->getInstSizeInBytes(*MII);
776 while (ShadowBytes < NumNOPBytes)
792 unsigned EncodedBytes = 0;
795 if (CalleeMO.
isImm()) {
798 unsigned ScratchIdx = -1;
799 unsigned ScratchReg = 0;
801 ScratchIdx = Opers.getNextScratchIdx(ScratchIdx + 1);
802 ScratchReg =
MI.getOperand(ScratchIdx).getReg();
803 }
while (ScratchReg == SystemZ::R0D);
808 .addImm(CallTarget & 0xFFFFFFFF));
810 if (CallTarget >> 32) {
813 .addImm(CallTarget >> 32));
818 .addReg(SystemZ::R14D)
819 .addReg(ScratchReg));
825 .addReg(SystemZ::R14D)
831 unsigned NumBytes = Opers.getNumPatchBytes();
832 assert(NumBytes >= EncodedBytes &&
833 "Patchpoint can't request size less than the length of a call.");
834 assert((NumBytes - EncodedBytes) % 2 == 0 &&
835 "Invalid number of NOP bytes requested!");
836 while (EncodedBytes < NumBytes)
844void SystemZAsmPrinter::emitAttributes(
Module &M) {
845 if (
M.getModuleFlag(
"s390x-visible-vector-ABI")) {
846 bool HasVectorFeature =
848 OutStreamer->emitGNUAttribute(8, HasVectorFeature ? 2 : 1);
896 }
else if (MCOp.
isImm())
922 const char *ExtraCode,
928 if (ExtraCode[0] ==
'N' && !ExtraCode[1] && MO.
isReg() &&
929 SystemZ::GR128BitRegClass.contains(MO.
getReg()))
936 MCOp =
Lower.lowerOperand(MO);
944 const char *ExtraCode,
948 MI->getOperand(OpNo + 2).getReg(),
OS);
960void SystemZAsmPrinter::emitADASection() {
966 unsigned EmittedBytes = 0;
967 for (
auto &Entry : ADATable.getTable()) {
970 std::tie(
Sym, SlotKind) = Entry.first;
971 unsigned Offset = Entry.second;
972 assert(
Offset == EmittedBytes &&
"Offset not as expected");
974#define EMIT_COMMENT(Str) \
975 OutStreamer->AddComment(Twine("Offset ") \
976 .concat(utostr(Offset)) \
977 .concat(" " Str " ") \
978 .concat(Sym->getName()));
994 EmittedBytes += PointerSize * 2;
1003 EmittedBytes += PointerSize;
1018 EmittedBytes += PointerSize;
1041 CurrentFnPPA1Sym =
nullptr;
1042 CurrentFnEPMarkerSym =
nullptr;
1049 enum class PPA1Flag1 : uint8_t {
1050 DSA64Bit = (0x80 >> 0),
1051 VarArg = (0x80 >> 7),
1054 enum class PPA1Flag2 : uint8_t {
1055 ExternalProcedure = (0x80 >> 0),
1056 STACKPROTECTOR = (0x80 >> 3),
1059 enum class PPA1Flag3 : uint8_t {
1060 FPRMask = (0x80 >> 2),
1063 enum class PPA1Flag4 : uint8_t {
1064 EPMOffsetPresent = (0x80 >> 0),
1065 VRMask = (0x80 >> 2),
1066 ProcedureNamePresent = (0x80 >> 7),
1071 auto Flags1 = PPA1Flag1(0);
1072 auto Flags2 = PPA1Flag2::ExternalProcedure;
1073 auto Flags3 = PPA1Flag3(0);
1074 auto Flags4 = PPA1Flag4::EPMOffsetPresent;
1076 Flags1 |= PPA1Flag1::DSA64Bit;
1079 Flags1 |= PPA1Flag1::VarArg;
1082 Flags2 |= PPA1Flag2::STACKPROTECTOR;
1086 Flags3 |= PPA1Flag3::FPRMask;
1089 Flags4 |= PPA1Flag4::VRMask;
1092 Flags4 |= PPA1Flag4::ProcedureNamePresent;
1094 OutStreamer->AddComment(
"PPA1 Flags 1");
1095 if ((Flags1 & PPA1Flag1::DSA64Bit) == PPA1Flag1::DSA64Bit)
1096 OutStreamer->AddComment(
" Bit 0: 1 = 64-bit DSA");
1098 OutStreamer->AddComment(
" Bit 0: 0 = 32-bit DSA");
1099 if ((Flags1 & PPA1Flag1::VarArg) == PPA1Flag1::VarArg)
1100 OutStreamer->AddComment(
" Bit 7: 1 = Vararg function");
1101 OutStreamer->emitInt8(
static_cast<uint8_t
>(Flags1));
1103 OutStreamer->AddComment(
"PPA1 Flags 2");
1104 if ((Flags2 & PPA1Flag2::ExternalProcedure) == PPA1Flag2::ExternalProcedure)
1105 OutStreamer->AddComment(
" Bit 0: 1 = External procedure");
1106 if ((Flags2 & PPA1Flag2::STACKPROTECTOR) == PPA1Flag2::STACKPROTECTOR)
1107 OutStreamer->AddComment(
" Bit 3: 1 = STACKPROTECT is enabled");
1109 OutStreamer->AddComment(
" Bit 3: 0 = STACKPROTECT is not enabled");
1110 OutStreamer->emitInt8(
static_cast<uint8_t
>(Flags2));
1112 OutStreamer->AddComment(
"PPA1 Flags 3");
1113 if ((Flags3 & PPA1Flag3::FPRMask) == PPA1Flag3::FPRMask)
1114 OutStreamer->AddComment(
" Bit 2: 1 = FP Reg Mask is in optional area");
1115 OutStreamer->emitInt8(
1116 static_cast<uint8_t
>(Flags3));
1118 OutStreamer->AddComment(
"PPA1 Flags 4");
1119 if ((Flags4 & PPA1Flag4::VRMask) == PPA1Flag4::VRMask)
1120 OutStreamer->AddComment(
" Bit 2: 1 = Vector Reg Mask is in optional area");
1121 if ((Flags4 & PPA1Flag4::ProcedureNamePresent) ==
1122 PPA1Flag4::ProcedureNamePresent)
1123 OutStreamer->AddComment(
" Bit 7: 1 = Name Length and Name");
1124 OutStreamer->emitInt8(
static_cast<uint8_t
>(
1135 OutName = OutName.
substr(0, UINT16_MAX);
1136 OutSize = UINT16_MAX;
1139 uint8_t ExtraZeros = 4 - ((2 + OutSize) % 4);
1143 OutName = OutnameConv.
str();
1145 OutStreamer->AddComment(
"Length of Name");
1146 OutStreamer->emitInt16(OutSize);
1147 OutStreamer->AddComment(
"Name of Function");
1148 OutStreamer->emitBytes(OutName);
1149 OutStreamer->emitZeros(ExtraZeros);
1152void SystemZAsmPrinter::emitPPA1(
MCSymbol *FnEndSym) {
1155 const auto TargetHasVector = Subtarget.hasVector();
1167 uint8_t SavedVRMask = 0;
1168 int64_t OffsetFPR = 0;
1169 int64_t OffsetVR = 0;
1170 const int64_t TopOfStack =
1177 I &&
E &&
I <=
E; ++
I) {
1179 assert(V < 16 &&
"GPR index out of range");
1180 SavedGPRMask |= 1 << (15 -
V);
1183 for (
auto &CS : CSI) {
1184 unsigned Reg = CS.getReg();
1185 unsigned I =
TRI->getEncodingValue(Reg);
1187 if (SystemZ::FP64BitRegClass.
contains(Reg)) {
1188 assert(
I < 16 &&
"FPR index out of range");
1189 SavedFPRMask |= 1 << (15 -
I);
1191 if (Temp < OffsetFPR)
1193 }
else if (SystemZ::VR128BitRegClass.
contains(Reg)) {
1194 assert(
I >= 16 &&
I <= 23 &&
"VPR index out of range");
1195 unsigned BitNum =
I - 16;
1196 SavedVRMask |= 1 << (7 - BitNum);
1198 if (Temp < OffsetVR)
1204 OffsetFPR += (OffsetFPR < 0) ? TopOfStack : 0;
1205 OffsetVR += (OffsetVR < 0) ? TopOfStack : 0;
1208 uint8_t FrameReg =
TRI->getEncodingValue(
TRI->getFrameRegister(*
MF));
1209 uint8_t AllocaReg = ZFL->hasFP(*
MF) ? FrameReg : 0;
1210 assert(AllocaReg < 16 &&
"Can't have alloca register larger than 15");
1216 uint64_t FPRSaveAreaOffset = OffsetFPR;
1217 assert(FPRSaveAreaOffset < 0x10000000 &&
"Offset out of range");
1219 FrameAndFPROffset = FPRSaveAreaOffset & 0x0FFFFFFF;
1220 FrameAndFPROffset |= FrameReg << 28;
1225 if (TargetHasVector && SavedVRMask) {
1226 uint64_t VRSaveAreaOffset = OffsetVR;
1227 assert(VRSaveAreaOffset < 0x10000000 &&
"Offset out of range");
1229 FrameAndVROffset = VRSaveAreaOffset & 0x0FFFFFFF;
1230 FrameAndVROffset |= FrameReg << 28;
1248 TargetHasVector && SavedVRMask != 0, HasName);
1254 OutStreamer->emitAbsoluteSymbolDiff(FnEndSym, CurrentFnEPMarkerSym, 4);
1264 .
concat(utostr(FrameAndFPROffset >> 28))
1267 .
concat(utostr(FrameAndFPROffset & 0x0FFFFFFF))
1275 if (TargetHasVector && SavedVRMask) {
1282 .
concat(utostr(FrameAndVROffset >> 28))
1285 .
concat(utostr(FrameAndVROffset & 0x0FFFFFFF))
1295 OutStreamer->emitAbsoluteSymbolDiff(CurrentFnEPMarkerSym, CurrentFnPPA1Sym,
1302 if (Subtarget.getTargetTriple().isOSzOS()) {
1310 CurrentFnEPMarkerSym =
1329 uint32_t DSAAndFlags = DSASize & 0xFFFFFFE0;
1330 DSAAndFlags |= Flags;
1333 OutStreamer->AddComment(
"XPLINK Routine Layout Entry");
1335 OutStreamer->AddComment(
"Eyecatcher 0x00C300C500C500");
1336 OutStreamer->emitIntValueInHex(0x00C300C500C500, 7);
1340 OutStreamer->emitAbsoluteSymbolDiff(CurrentFnPPA1Sym, CurrentFnEPMarkerSym,
1346 OutStreamer->AddComment(
" Bit 1: 1 = Leaf function");
1348 OutStreamer->AddComment(
" Bit 1: 0 = Non-leaf function");
1350 OutStreamer->AddComment(
" Bit 2: 1 = Uses alloca");
1352 OutStreamer->AddComment(
" Bit 2: 0 = Does not use alloca");
unsigned const MachineRegisterInfo * MRI
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
This file provides utility functions for converting between EBCDIC-1047 and UTF-8.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
static void emitPPA1Name(std::unique_ptr< MCStreamer > &OutStreamer, StringRef OutName)
static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI, unsigned Opcode)
#define EMIT_COMMENT(Str)
static const MCSymbolRefExpr * getGlobalOffsetTable(MCContext &Context)
static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo, raw_ostream &OS)
static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode)
static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmPrinter()
static void emitPPA1Flags(std::unique_ptr< MCStreamer > &OutStreamer, bool VarArg, bool StackProtector, bool FPRMask, bool VRMask, bool HasName)
static void printAddress(const MCAsmInfo *MAI, unsigned Base, const MCOperand &DispMO, unsigned Index, raw_ostream &OS)
static const MCSymbolRefExpr * getTLSGetOffset(MCContext &Context)
static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode)
static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer, unsigned NumBytes, const MCSubtargetInfo &STI)
static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode)
static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
MCSymbol * getSymbol(const GlobalValue *GV) const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
TargetMachine & TM
Target machine description.
const MCAsmInfo * MAI
Target Asm Printer information.
MachineFunction * MF
The current machine function.
MCContext & OutContext
This is the context for the output file that we are streaming.
MCSymbol * createTempSymbol(const Twine &Name) const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
const DataLayout & getDataLayout() const
Return information about data layout.
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
This class represents an Operation in the Expression.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
This class is intended to be used as a base class for asm properties and features specific to the tar...
unsigned getAssemblerDialect() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
const Triple & getTargetTriple() const
Base class for the full range of assembler expressions which are needed for parsing.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Abstract base class for all machine specific constantpool value subclasses.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int getOffsetAdjustment() const
Return the correction for frame offsets.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool hasStackProtectorIndex() const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
@ MO_GlobalAddress
Address of a global value.
@ MO_ExternalSymbol
Name of external global symbol.
const TargetRegisterInfo * getTargetRegisterInfo() const
A Module instance is used to store all the information related to an LLVM module.
MI-level patchpoint operands.
Wrapper class representing virtual and physical registers.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef str() const
Explicit conversion to StringRef.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
StringRef - Represent a constant reference to a string, i.e.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
constexpr size_t size() const
size - Get the string size.
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
A SystemZ-specific constant pool value.
static const char * getRegisterName(MCRegister Reg)
static const SystemZMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
SystemZ::GPRRegs getSpillGPRRegs() const
unsigned getSizeOfFnParams() const
const SystemZInstrInfo * getInstrInfo() const override
const TargetFrameLowering * getFrameLowering() const override
std::pair< MCInst, const MCSubtargetInfo * > MCInstSTIPair
EXRLT2SymMap EXRLTargets2Sym
const Triple & getTargetTriple() const
const MCSubtargetInfo * getMCSubtargetInfo() const
MCSymbol * getSymbol(const GlobalValue *GV) const
const MCRegisterInfo * getMCRegisterInfo() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
std::string str() const
Return the twine contents as a std::string.
Twine concat(const Twine &Suffix) const
static Twine utohexstr(const uint64_t &Val)
StringRef getName() const
Return a constant reference to the value's name.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::error_code convertToEBCDIC(StringRef Source, SmallVectorImpl< char > &Result)
@ MO_ADA_DATA_SYMBOL_ADDR
@ MO_ADA_DIRECT_FUNC_DESC
@ MO_ADA_INDIRECT_FUNC_DESC
unsigned getRegAsGR32(unsigned Reg)
const unsigned GR64Regs[16]
unsigned getRegAsGRH32(unsigned Reg)
unsigned getRegAsVR128(unsigned Reg)
unsigned getRegAsGR64(unsigned Reg)
Reg
All possible values of the reg field in the ModR/M byte.
constexpr size_t NameSize
constexpr uint64_t PointerSize
aarch64 pointer size.
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheSystemZTarget()
detail::concat_range< ValueT, RangeTs... > concat(RangeTs &&... Ranges)
Concatenated range across two or more ranges.
@ LLVM_MARK_AS_BITMASK_ENUM
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
This struct is a compact representation of a valid (non-zero power of two) alignment.
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...