LLVM  16.0.0git
SystemZAsmPrinter.cpp
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1 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Streams SystemZ assembly language and associated data, in the form of
10 // MCInsts and MCExprs respectively.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZAsmPrinter.h"
17 #include "SystemZMCInstLower.h"
19 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/IR/Mangler.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInstBuilder.h"
25 #include "llvm/MC/MCSectionELF.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/TargetRegistry.h"
28 
29 using namespace llvm;
30 
31 // Return an RI instruction like MI with opcode Opcode, but with the
32 // GR64 register operands turned into GR32s.
33 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
34  if (MI->isCompare())
35  return MCInstBuilder(Opcode)
36  .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
37  .addImm(MI->getOperand(1).getImm());
38  else
39  return MCInstBuilder(Opcode)
40  .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
41  .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
42  .addImm(MI->getOperand(2).getImm());
43 }
44 
45 // Return an RI instruction like MI with opcode Opcode, but with the
46 // GR64 register operands turned into GRH32s.
47 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
48  if (MI->isCompare())
49  return MCInstBuilder(Opcode)
50  .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
51  .addImm(MI->getOperand(1).getImm());
52  else
53  return MCInstBuilder(Opcode)
54  .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
55  .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
56  .addImm(MI->getOperand(2).getImm());
57 }
58 
59 // Return an RI instruction like MI with opcode Opcode, but with the
60 // R2 register turned into a GR64.
61 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
62  return MCInstBuilder(Opcode)
63  .addReg(MI->getOperand(0).getReg())
64  .addReg(MI->getOperand(1).getReg())
65  .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
66  .addImm(MI->getOperand(3).getImm())
67  .addImm(MI->getOperand(4).getImm())
68  .addImm(MI->getOperand(5).getImm());
69 }
70 
72  StringRef Name = "__tls_get_offset";
73  return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
75  Context);
76 }
77 
79  StringRef Name = "_GLOBAL_OFFSET_TABLE_";
80  return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
82  Context);
83 }
84 
85 // MI is an instruction that accepts an optional alignment hint,
86 // and which was already lowered to LoweredMI. If the alignment
87 // of the original memory operand is known, update LoweredMI to
88 // an instruction with the corresponding hint set.
89 static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
90  unsigned Opcode) {
91  if (MI->memoperands_empty())
92  return;
93 
94  Align Alignment = Align(16);
95  for (MachineInstr::mmo_iterator MMOI = MI->memoperands_begin(),
96  EE = MI->memoperands_end(); MMOI != EE; ++MMOI)
97  if ((*MMOI)->getAlign() < Alignment)
98  Alignment = (*MMOI)->getAlign();
99 
100  unsigned AlignmentHint = 0;
101  if (Alignment >= Align(16))
102  AlignmentHint = 4;
103  else if (Alignment >= Align(8))
104  AlignmentHint = 3;
105  if (AlignmentHint == 0)
106  return;
107 
108  LoweredMI.setOpcode(Opcode);
109  LoweredMI.addOperand(MCOperand::createImm(AlignmentHint));
110 }
111 
112 // MI loads the high part of a vector from memory. Return an instruction
113 // that uses replicating vector load Opcode to do the same thing.
114 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
115  return MCInstBuilder(Opcode)
116  .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
117  .addReg(MI->getOperand(1).getReg())
118  .addImm(MI->getOperand(2).getImm())
119  .addReg(MI->getOperand(3).getReg());
120 }
121 
122 // MI stores the high part of a vector to memory. Return an instruction
123 // that uses elemental vector store Opcode to do the same thing.
124 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
125  return MCInstBuilder(Opcode)
126  .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
127  .addReg(MI->getOperand(1).getReg())
128  .addImm(MI->getOperand(2).getImm())
129  .addReg(MI->getOperand(3).getReg())
130  .addImm(0);
131 }
132 
133 // The XPLINK ABI requires that a no-op encoding the call type is emitted after
134 // each call to a subroutine. This information can be used by the called
135 // function to determine its entry point, e.g. for generating a backtrace. The
136 // call type is encoded as a register number in the bcr instruction. See
137 // enumeration CallType for the possible values.
138 void SystemZAsmPrinter::emitCallInformation(CallType CT) {
140  MCInstBuilder(SystemZ::BCRAsm)
141  .addImm(0)
142  .addReg(SystemZMC::GR64Regs[static_cast<unsigned>(CT)]));
143 }
144 
146  SystemZ_MC::verifyInstructionPredicates(MI->getOpcode(),
147  getSubtargetInfo().getFeatureBits());
148 
149  SystemZMCInstLower Lower(MF->getContext(), *this);
150  MCInst LoweredMI;
151  switch (MI->getOpcode()) {
152  case SystemZ::Return:
153  LoweredMI = MCInstBuilder(SystemZ::BR)
154  .addReg(SystemZ::R14D);
155  break;
156 
157  case SystemZ::Return_XPLINK:
158  LoweredMI = MCInstBuilder(SystemZ::B)
159  .addReg(SystemZ::R7D)
160  .addImm(2)
161  .addReg(0);
162  break;
163 
164  case SystemZ::CondReturn:
165  LoweredMI = MCInstBuilder(SystemZ::BCR)
166  .addImm(MI->getOperand(0).getImm())
167  .addImm(MI->getOperand(1).getImm())
168  .addReg(SystemZ::R14D);
169  break;
170 
171  case SystemZ::CondReturn_XPLINK:
172  LoweredMI = MCInstBuilder(SystemZ::BC)
173  .addImm(MI->getOperand(0).getImm())
174  .addImm(MI->getOperand(1).getImm())
175  .addReg(SystemZ::R7D)
176  .addImm(2)
177  .addReg(0);
178  break;
179 
180  case SystemZ::CRBReturn:
181  LoweredMI = MCInstBuilder(SystemZ::CRB)
182  .addReg(MI->getOperand(0).getReg())
183  .addReg(MI->getOperand(1).getReg())
184  .addImm(MI->getOperand(2).getImm())
185  .addReg(SystemZ::R14D)
186  .addImm(0);
187  break;
188 
189  case SystemZ::CGRBReturn:
190  LoweredMI = MCInstBuilder(SystemZ::CGRB)
191  .addReg(MI->getOperand(0).getReg())
192  .addReg(MI->getOperand(1).getReg())
193  .addImm(MI->getOperand(2).getImm())
194  .addReg(SystemZ::R14D)
195  .addImm(0);
196  break;
197 
198  case SystemZ::CIBReturn:
199  LoweredMI = MCInstBuilder(SystemZ::CIB)
200  .addReg(MI->getOperand(0).getReg())
201  .addImm(MI->getOperand(1).getImm())
202  .addImm(MI->getOperand(2).getImm())
203  .addReg(SystemZ::R14D)
204  .addImm(0);
205  break;
206 
207  case SystemZ::CGIBReturn:
208  LoweredMI = MCInstBuilder(SystemZ::CGIB)
209  .addReg(MI->getOperand(0).getReg())
210  .addImm(MI->getOperand(1).getImm())
211  .addImm(MI->getOperand(2).getImm())
212  .addReg(SystemZ::R14D)
213  .addImm(0);
214  break;
215 
216  case SystemZ::CLRBReturn:
217  LoweredMI = MCInstBuilder(SystemZ::CLRB)
218  .addReg(MI->getOperand(0).getReg())
219  .addReg(MI->getOperand(1).getReg())
220  .addImm(MI->getOperand(2).getImm())
221  .addReg(SystemZ::R14D)
222  .addImm(0);
223  break;
224 
225  case SystemZ::CLGRBReturn:
226  LoweredMI = MCInstBuilder(SystemZ::CLGRB)
227  .addReg(MI->getOperand(0).getReg())
228  .addReg(MI->getOperand(1).getReg())
229  .addImm(MI->getOperand(2).getImm())
230  .addReg(SystemZ::R14D)
231  .addImm(0);
232  break;
233 
234  case SystemZ::CLIBReturn:
235  LoweredMI = MCInstBuilder(SystemZ::CLIB)
236  .addReg(MI->getOperand(0).getReg())
237  .addImm(MI->getOperand(1).getImm())
238  .addImm(MI->getOperand(2).getImm())
239  .addReg(SystemZ::R14D)
240  .addImm(0);
241  break;
242 
243  case SystemZ::CLGIBReturn:
244  LoweredMI = MCInstBuilder(SystemZ::CLGIB)
245  .addReg(MI->getOperand(0).getReg())
246  .addImm(MI->getOperand(1).getImm())
247  .addImm(MI->getOperand(2).getImm())
248  .addReg(SystemZ::R14D)
249  .addImm(0);
250  break;
251 
252  case SystemZ::CallBRASL_XPLINK64:
254  MCInstBuilder(SystemZ::BRASL)
255  .addReg(SystemZ::R7D)
256  .addExpr(Lower.getExpr(MI->getOperand(0),
258  emitCallInformation(CallType::BRASL7);
259  return;
260 
261  case SystemZ::CallBASR_XPLINK64:
262  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)
263  .addReg(SystemZ::R7D)
264  .addReg(MI->getOperand(0).getReg()));
265  emitCallInformation(CallType::BASR76);
266  return;
267 
268  case SystemZ::CallBASR_STACKEXT:
269  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)
270  .addReg(SystemZ::R3D)
271  .addReg(MI->getOperand(0).getReg()));
272  emitCallInformation(CallType::BASR33);
273  return;
274 
275  case SystemZ::CallBRASL:
276  LoweredMI = MCInstBuilder(SystemZ::BRASL)
277  .addReg(SystemZ::R14D)
278  .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
279  break;
280 
281  case SystemZ::CallBASR:
282  LoweredMI = MCInstBuilder(SystemZ::BASR)
283  .addReg(SystemZ::R14D)
284  .addReg(MI->getOperand(0).getReg());
285  break;
286 
287  case SystemZ::CallJG:
288  LoweredMI = MCInstBuilder(SystemZ::JG)
289  .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
290  break;
291 
292  case SystemZ::CallBRCL:
293  LoweredMI = MCInstBuilder(SystemZ::BRCL)
294  .addImm(MI->getOperand(0).getImm())
295  .addImm(MI->getOperand(1).getImm())
296  .addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT));
297  break;
298 
299  case SystemZ::CallBR:
300  LoweredMI = MCInstBuilder(SystemZ::BR)
301  .addReg(MI->getOperand(0).getReg());
302  break;
303 
304  case SystemZ::CallBCR:
305  LoweredMI = MCInstBuilder(SystemZ::BCR)
306  .addImm(MI->getOperand(0).getImm())
307  .addImm(MI->getOperand(1).getImm())
308  .addReg(MI->getOperand(2).getReg());
309  break;
310 
311  case SystemZ::CRBCall:
312  LoweredMI = MCInstBuilder(SystemZ::CRB)
313  .addReg(MI->getOperand(0).getReg())
314  .addReg(MI->getOperand(1).getReg())
315  .addImm(MI->getOperand(2).getImm())
316  .addReg(MI->getOperand(3).getReg())
317  .addImm(0);
318  break;
319 
320  case SystemZ::CGRBCall:
321  LoweredMI = MCInstBuilder(SystemZ::CGRB)
322  .addReg(MI->getOperand(0).getReg())
323  .addReg(MI->getOperand(1).getReg())
324  .addImm(MI->getOperand(2).getImm())
325  .addReg(MI->getOperand(3).getReg())
326  .addImm(0);
327  break;
328 
329  case SystemZ::CIBCall:
330  LoweredMI = MCInstBuilder(SystemZ::CIB)
331  .addReg(MI->getOperand(0).getReg())
332  .addImm(MI->getOperand(1).getImm())
333  .addImm(MI->getOperand(2).getImm())
334  .addReg(MI->getOperand(3).getReg())
335  .addImm(0);
336  break;
337 
338  case SystemZ::CGIBCall:
339  LoweredMI = MCInstBuilder(SystemZ::CGIB)
340  .addReg(MI->getOperand(0).getReg())
341  .addImm(MI->getOperand(1).getImm())
342  .addImm(MI->getOperand(2).getImm())
343  .addReg(MI->getOperand(3).getReg())
344  .addImm(0);
345  break;
346 
347  case SystemZ::CLRBCall:
348  LoweredMI = MCInstBuilder(SystemZ::CLRB)
349  .addReg(MI->getOperand(0).getReg())
350  .addReg(MI->getOperand(1).getReg())
351  .addImm(MI->getOperand(2).getImm())
352  .addReg(MI->getOperand(3).getReg())
353  .addImm(0);
354  break;
355 
356  case SystemZ::CLGRBCall:
357  LoweredMI = MCInstBuilder(SystemZ::CLGRB)
358  .addReg(MI->getOperand(0).getReg())
359  .addReg(MI->getOperand(1).getReg())
360  .addImm(MI->getOperand(2).getImm())
361  .addReg(MI->getOperand(3).getReg())
362  .addImm(0);
363  break;
364 
365  case SystemZ::CLIBCall:
366  LoweredMI = MCInstBuilder(SystemZ::CLIB)
367  .addReg(MI->getOperand(0).getReg())
368  .addImm(MI->getOperand(1).getImm())
369  .addImm(MI->getOperand(2).getImm())
370  .addReg(MI->getOperand(3).getReg())
371  .addImm(0);
372  break;
373 
374  case SystemZ::CLGIBCall:
375  LoweredMI = MCInstBuilder(SystemZ::CLGIB)
376  .addReg(MI->getOperand(0).getReg())
377  .addImm(MI->getOperand(1).getImm())
378  .addImm(MI->getOperand(2).getImm())
379  .addReg(MI->getOperand(3).getReg())
380  .addImm(0);
381  break;
382 
383  case SystemZ::TLS_GDCALL:
384  LoweredMI = MCInstBuilder(SystemZ::BRASL)
385  .addReg(SystemZ::R14D)
387  .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSGD));
388  break;
389 
390  case SystemZ::TLS_LDCALL:
391  LoweredMI = MCInstBuilder(SystemZ::BRASL)
392  .addReg(SystemZ::R14D)
394  .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSLDM));
395  break;
396 
397  case SystemZ::GOT:
398  LoweredMI = MCInstBuilder(SystemZ::LARL)
399  .addReg(MI->getOperand(0).getReg())
401  break;
402 
403  case SystemZ::IILF64:
404  LoweredMI = MCInstBuilder(SystemZ::IILF)
405  .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
406  .addImm(MI->getOperand(2).getImm());
407  break;
408 
409  case SystemZ::IIHF64:
410  LoweredMI = MCInstBuilder(SystemZ::IIHF)
411  .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
412  .addImm(MI->getOperand(2).getImm());
413  break;
414 
415  case SystemZ::RISBHH:
416  case SystemZ::RISBHL:
417  LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG);
418  break;
419 
420  case SystemZ::RISBLH:
421  case SystemZ::RISBLL:
422  LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG);
423  break;
424 
425  case SystemZ::VLVGP32:
426  LoweredMI = MCInstBuilder(SystemZ::VLVGP)
427  .addReg(MI->getOperand(0).getReg())
428  .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
429  .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));
430  break;
431 
432  case SystemZ::VLR32:
433  case SystemZ::VLR64:
434  LoweredMI = MCInstBuilder(SystemZ::VLR)
435  .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
436  .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
437  break;
438 
439  case SystemZ::VL:
440  Lower.lower(MI, LoweredMI);
441  lowerAlignmentHint(MI, LoweredMI, SystemZ::VLAlign);
442  break;
443 
444  case SystemZ::VST:
445  Lower.lower(MI, LoweredMI);
446  lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTAlign);
447  break;
448 
449  case SystemZ::VLM:
450  Lower.lower(MI, LoweredMI);
451  lowerAlignmentHint(MI, LoweredMI, SystemZ::VLMAlign);
452  break;
453 
454  case SystemZ::VSTM:
455  Lower.lower(MI, LoweredMI);
456  lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTMAlign);
457  break;
458 
459  case SystemZ::VL32:
460  LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF);
461  break;
462 
463  case SystemZ::VL64:
464  LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPG);
465  break;
466 
467  case SystemZ::VST32:
468  LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEF);
469  break;
470 
471  case SystemZ::VST64:
472  LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEG);
473  break;
474 
475  case SystemZ::LFER:
476  LoweredMI = MCInstBuilder(SystemZ::VLGVF)
477  .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
478  .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
479  .addReg(0).addImm(0);
480  break;
481 
482  case SystemZ::LEFR:
483  LoweredMI = MCInstBuilder(SystemZ::VLVGF)
484  .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
485  .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
486  .addReg(MI->getOperand(1).getReg())
487  .addReg(0).addImm(0);
488  break;
489 
490 #define LOWER_LOW(NAME) \
491  case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
492 
493  LOWER_LOW(IILL);
494  LOWER_LOW(IILH);
495  LOWER_LOW(TMLL);
496  LOWER_LOW(TMLH);
497  LOWER_LOW(NILL);
498  LOWER_LOW(NILH);
499  LOWER_LOW(NILF);
500  LOWER_LOW(OILL);
501  LOWER_LOW(OILH);
502  LOWER_LOW(OILF);
503  LOWER_LOW(XILF);
504 
505 #undef LOWER_LOW
506 
507 #define LOWER_HIGH(NAME) \
508  case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
509 
510  LOWER_HIGH(IIHL);
511  LOWER_HIGH(IIHH);
512  LOWER_HIGH(TMHL);
513  LOWER_HIGH(TMHH);
514  LOWER_HIGH(NIHL);
515  LOWER_HIGH(NIHH);
516  LOWER_HIGH(NIHF);
517  LOWER_HIGH(OIHL);
518  LOWER_HIGH(OIHH);
519  LOWER_HIGH(OIHF);
520  LOWER_HIGH(XIHF);
521 
522 #undef LOWER_HIGH
523 
524  case SystemZ::Serialize:
526  LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
527  .addImm(14).addReg(SystemZ::R0D);
528  else
529  LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
530  .addImm(15).addReg(SystemZ::R0D);
531  break;
532 
533  // Emit nothing here but a comment if we can.
534  case SystemZ::MemBarrier:
535  OutStreamer->emitRawComment("MEMBARRIER");
536  return;
537 
538  // We want to emit "j .+2" for traps, jumping to the relative immediate field
539  // of the jump instruction, which is an illegal instruction. We cannot emit a
540  // "." symbol, so create and emit a temp label before the instruction and use
541  // that instead.
542  case SystemZ::Trap: {
544  OutStreamer->emitLabel(DotSym);
545 
546  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
547  const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
548  LoweredMI = MCInstBuilder(SystemZ::J)
549  .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
550  }
551  break;
552 
553  // Conditional traps will create a branch on condition instruction that jumps
554  // to the relative immediate field of the jump instruction. (eg. "jo .+2")
555  case SystemZ::CondTrap: {
557  OutStreamer->emitLabel(DotSym);
558 
559  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
560  const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
561  LoweredMI = MCInstBuilder(SystemZ::BRC)
562  .addImm(MI->getOperand(0).getImm())
563  .addImm(MI->getOperand(1).getImm())
564  .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
565  }
566  break;
567 
568  case TargetOpcode::FENTRY_CALL:
569  LowerFENTRY_CALL(*MI, Lower);
570  return;
571 
573  LowerSTACKMAP(*MI);
574  return;
575 
577  LowerPATCHPOINT(*MI, Lower);
578  return;
579 
580  case SystemZ::EXRL_Pseudo: {
581  unsigned TargetInsOpc = MI->getOperand(0).getImm();
582  Register LenMinus1Reg = MI->getOperand(1).getReg();
583  Register DestReg = MI->getOperand(2).getReg();
584  int64_t DestDisp = MI->getOperand(3).getImm();
585  Register SrcReg = MI->getOperand(4).getReg();
586  int64_t SrcDisp = MI->getOperand(5).getImm();
587 
588  SystemZTargetStreamer *TS = getTargetStreamer();
589  MCSymbol *DotSym = nullptr;
590  MCInst ET = MCInstBuilder(TargetInsOpc).addReg(DestReg)
591  .addImm(DestDisp).addImm(1).addReg(SrcReg).addImm(SrcDisp);
593  SystemZTargetStreamer::EXRLT2SymMap::iterator I =
594  TS->EXRLTargets2Sym.find(ET_STI);
595  if (I != TS->EXRLTargets2Sym.end())
596  DotSym = I->second;
597  else
598  TS->EXRLTargets2Sym[ET_STI] = DotSym = OutContext.createTempSymbol();
599  const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext);
601  *OutStreamer,
602  MCInstBuilder(SystemZ::EXRL).addReg(LenMinus1Reg).addExpr(Dot));
603  return;
604  }
605 
606  default:
607  Lower.lower(MI, LoweredMI);
608  break;
609  }
610  EmitToStreamer(*OutStreamer, LoweredMI);
611 }
612 
613 // Emit the largest nop instruction smaller than or equal to NumBytes
614 // bytes. Return the size of nop emitted.
615 static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer,
616  unsigned NumBytes, const MCSubtargetInfo &STI) {
617  if (NumBytes < 2) {
618  llvm_unreachable("Zero nops?");
619  return 0;
620  }
621  else if (NumBytes < 4) {
622  OutStreamer.emitInstruction(
623  MCInstBuilder(SystemZ::BCRAsm).addImm(0).addReg(SystemZ::R0D), STI);
624  return 2;
625  }
626  else if (NumBytes < 6) {
627  OutStreamer.emitInstruction(
628  MCInstBuilder(SystemZ::BCAsm).addImm(0).addReg(0).addImm(0).addReg(0),
629  STI);
630  return 4;
631  }
632  else {
633  MCSymbol *DotSym = OutContext.createTempSymbol();
634  const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext);
635  OutStreamer.emitLabel(DotSym);
636  OutStreamer.emitInstruction(
637  MCInstBuilder(SystemZ::BRCLAsm).addImm(0).addExpr(Dot), STI);
638  return 6;
639  }
640 }
641 
642 void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
643  SystemZMCInstLower &Lower) {
644  MCContext &Ctx = MF->getContext();
645  if (MF->getFunction().hasFnAttribute("mrecord-mcount")) {
647  OutStreamer->pushSection();
648  OutStreamer->switchSection(
649  Ctx.getELFSection("__mcount_loc", ELF::SHT_PROGBITS, ELF::SHF_ALLOC));
650  OutStreamer->emitSymbolValue(DotSym, 8);
651  OutStreamer->popSection();
652  OutStreamer->emitLabel(DotSym);
653  }
654 
655  if (MF->getFunction().hasFnAttribute("mnop-mcount")) {
656  EmitNop(Ctx, *OutStreamer, 6, getSubtargetInfo());
657  return;
658  }
659 
660  MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
661  const MCSymbolRefExpr *Op =
663  OutStreamer->emitInstruction(
664  MCInstBuilder(SystemZ::BRASL).addReg(SystemZ::R0D).addExpr(Op),
665  getSubtargetInfo());
666 }
667 
668 void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
669  auto *TII = MF->getSubtarget<SystemZSubtarget>().getInstrInfo();
670 
671  unsigned NumNOPBytes = MI.getOperand(1).getImm();
672 
673  auto &Ctx = OutStreamer->getContext();
674  MCSymbol *MILabel = Ctx.createTempSymbol();
675  OutStreamer->emitLabel(MILabel);
676 
677  SM.recordStackMap(*MILabel, MI);
678  assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");
679 
680  // Scan ahead to trim the shadow.
681  unsigned ShadowBytes = 0;
682  const MachineBasicBlock &MBB = *MI.getParent();
684  ++MII;
685  while (ShadowBytes < NumNOPBytes) {
686  if (MII == MBB.end() ||
687  MII->getOpcode() == TargetOpcode::PATCHPOINT ||
688  MII->getOpcode() == TargetOpcode::STACKMAP)
689  break;
690  ShadowBytes += TII->getInstSizeInBytes(*MII);
691  if (MII->isCall())
692  break;
693  ++MII;
694  }
695 
696  // Emit nops.
697  while (ShadowBytes < NumNOPBytes)
698  ShadowBytes += EmitNop(OutContext, *OutStreamer, NumNOPBytes - ShadowBytes,
699  getSubtargetInfo());
700 }
701 
702 // Lower a patchpoint of the form:
703 // [<def>], <id>, <numBytes>, <target>, <numArgs>
704 void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
705  SystemZMCInstLower &Lower) {
706  auto &Ctx = OutStreamer->getContext();
707  MCSymbol *MILabel = Ctx.createTempSymbol();
708  OutStreamer->emitLabel(MILabel);
709 
710  SM.recordPatchPoint(*MILabel, MI);
711  PatchPointOpers Opers(&MI);
712 
713  unsigned EncodedBytes = 0;
714  const MachineOperand &CalleeMO = Opers.getCallTarget();
715 
716  if (CalleeMO.isImm()) {
717  uint64_t CallTarget = CalleeMO.getImm();
718  if (CallTarget) {
719  unsigned ScratchIdx = -1;
720  unsigned ScratchReg = 0;
721  do {
722  ScratchIdx = Opers.getNextScratchIdx(ScratchIdx + 1);
723  ScratchReg = MI.getOperand(ScratchIdx).getReg();
724  } while (ScratchReg == SystemZ::R0D);
725 
726  // Materialize the call target address
727  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::LLILF)
728  .addReg(ScratchReg)
729  .addImm(CallTarget & 0xFFFFFFFF));
730  EncodedBytes += 6;
731  if (CallTarget >> 32) {
732  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::IIHF)
733  .addReg(ScratchReg)
734  .addImm(CallTarget >> 32));
735  EncodedBytes += 6;
736  }
737 
738  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)
739  .addReg(SystemZ::R14D)
740  .addReg(ScratchReg));
741  EncodedBytes += 2;
742  }
743  } else if (CalleeMO.isGlobal()) {
744  const MCExpr *Expr = Lower.getExpr(CalleeMO, MCSymbolRefExpr::VK_PLT);
745  EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BRASL)
746  .addReg(SystemZ::R14D)
747  .addExpr(Expr));
748  EncodedBytes += 6;
749  }
750 
751  // Emit padding.
752  unsigned NumBytes = Opers.getNumPatchBytes();
753  assert(NumBytes >= EncodedBytes &&
754  "Patchpoint can't request size less than the length of a call.");
755  assert((NumBytes - EncodedBytes) % 2 == 0 &&
756  "Invalid number of NOP bytes requested!");
757  while (EncodedBytes < NumBytes)
758  EncodedBytes += EmitNop(OutContext, *OutStreamer, NumBytes - EncodedBytes,
759  getSubtargetInfo());
760 }
761 
762 // Convert a SystemZ-specific constant pool modifier into the associated
763 // MCSymbolRefExpr variant kind.
766  switch (Modifier) {
771  }
772  llvm_unreachable("Invalid SystemCPModifier!");
773 }
774 
776  MachineConstantPoolValue *MCPV) {
777  auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
778 
779  const MCExpr *Expr =
780  MCSymbolRefExpr::create(getSymbol(ZCPV->getGlobalValue()),
781  getModifierVariantKind(ZCPV->getModifier()),
782  OutContext);
783  uint64_t Size = getDataLayout().getTypeAllocSize(ZCPV->getType());
784 
785  OutStreamer->emitValue(Expr, Size);
786 }
787 
788 static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo,
789  raw_ostream &OS) {
790  const char *RegName = SystemZInstPrinter::getRegisterName(RegNo);
791  if (MAI->getAssemblerDialect() == AD_HLASM) {
792  // Skip register prefix so that only register number is left
793  assert(isalpha(RegName[0]) && isdigit(RegName[1]));
794  OS << (RegName + 1);
795  } else
796  OS << '%' << RegName;
797 }
798 
799 static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI,
800  raw_ostream &OS) {
801  if (MCOp.isReg()) {
802  if (!MCOp.getReg())
803  OS << '0';
804  else
805  printFormattedRegName(MAI, MCOp.getReg(), OS);
806  } else if (MCOp.isImm())
807  OS << MCOp.getImm();
808  else if (MCOp.isExpr())
809  MCOp.getExpr()->print(OS, MAI);
810  else
811  llvm_unreachable("Invalid operand");
812 }
813 
814 static void printAddress(const MCAsmInfo *MAI, unsigned Base,
815  const MCOperand &DispMO, unsigned Index,
816  raw_ostream &OS) {
817  printOperand(DispMO, MAI, OS);
818  if (Base || Index) {
819  OS << '(';
820  if (Index) {
821  printFormattedRegName(MAI, Index, OS);
822  if (Base)
823  OS << ',';
824  }
825  if (Base)
826  printFormattedRegName(MAI, Base, OS);
827  OS << ')';
828  }
829 }
830 
832  const char *ExtraCode,
833  raw_ostream &OS) {
835  const MachineOperand &MO = MI->getOperand(OpNo);
836  MCOperand MCOp;
837  if (ExtraCode) {
838  if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() &&
839  SystemZ::GR128BitRegClass.contains(MO.getReg()))
840  MCOp =
841  MCOperand::createReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64));
842  else
843  return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
844  } else {
845  SystemZMCInstLower Lower(MF->getContext(), *this);
846  MCOp = Lower.lowerOperand(MO);
847  }
848  printOperand(MCOp, MAI, OS);
849  return false;
850 }
851 
853  unsigned OpNo,
854  const char *ExtraCode,
855  raw_ostream &OS) {
856  printAddress(MAI, MI->getOperand(OpNo).getReg(),
857  MCOperand::createImm(MI->getOperand(OpNo + 1).getImm()),
858  MI->getOperand(OpNo + 2).getReg(), OS);
859  return false;
860 }
861 
863  if (TM.getTargetTriple().isOSzOS()) {
864  // Emit symbol for the end of function if the z/OS target streamer
865  // is used. This is needed to calculate the size of the function.
866  MCSymbol *FnEndSym = createTempSymbol("func_end");
867  OutStreamer->emitLabel(FnEndSym);
868 
869  OutStreamer->pushSection();
870  OutStreamer->switchSection(getObjFileLowering().getPPA1Section());
871  emitPPA1(FnEndSym);
872  OutStreamer->popSection();
873 
874  CurrentFnPPA1Sym = nullptr;
875  CurrentFnEPMarkerSym = nullptr;
876  }
877 }
878 
879 static void emitPPA1Flags(std::unique_ptr<MCStreamer> &OutStreamer, bool VarArg,
880  bool StackProtector, bool FPRMask, bool VRMask) {
881  enum class PPA1Flag1 : uint8_t {
882  DSA64Bit = (0x80 >> 0),
883  VarArg = (0x80 >> 7),
884  LLVM_MARK_AS_BITMASK_ENUM(DSA64Bit)
885  };
886  enum class PPA1Flag2 : uint8_t {
887  ExternalProcedure = (0x80 >> 0),
888  STACKPROTECTOR = (0x80 >> 3),
889  LLVM_MARK_AS_BITMASK_ENUM(ExternalProcedure)
890  };
891  enum class PPA1Flag3 : uint8_t {
892  FPRMask = (0x80 >> 2),
894  };
895  enum class PPA1Flag4 : uint8_t {
896  EPMOffsetPresent = (0x80 >> 0),
897  VRMask = (0x80 >> 2),
898  ProcedureNamePresent = (0x80 >> 7),
899  LLVM_MARK_AS_BITMASK_ENUM(EPMOffsetPresent)
900  };
901 
902  // Declare optional section flags that can be modified.
903  auto Flags1 = PPA1Flag1(0);
904  auto Flags2 = PPA1Flag2::ExternalProcedure;
905  auto Flags3 = PPA1Flag3(0);
906  auto Flags4 = PPA1Flag4::EPMOffsetPresent | PPA1Flag4::ProcedureNamePresent;
907 
908  Flags1 |= PPA1Flag1::DSA64Bit;
909 
910  if (VarArg)
911  Flags1 |= PPA1Flag1::VarArg;
912 
913  if (StackProtector)
914  Flags2 |= PPA1Flag2::STACKPROTECTOR;
915 
916  // SavedGPRMask, SavedFPRMask, and SavedVRMask are precomputed in.
917  if (FPRMask)
918  Flags3 |= PPA1Flag3::FPRMask; // Add emit FPR mask flag.
919 
920  if (VRMask)
921  Flags4 |= PPA1Flag4::VRMask; // Add emit VR mask flag.
922 
923  OutStreamer->AddComment("PPA1 Flags 1");
924  if ((Flags1 & PPA1Flag1::DSA64Bit) == PPA1Flag1::DSA64Bit)
925  OutStreamer->AddComment(" Bit 0: 1 = 64-bit DSA");
926  else
927  OutStreamer->AddComment(" Bit 0: 0 = 32-bit DSA");
928  if ((Flags1 & PPA1Flag1::VarArg) == PPA1Flag1::VarArg)
929  OutStreamer->AddComment(" Bit 7: 1 = Vararg function");
930  OutStreamer->emitInt8(static_cast<uint8_t>(Flags1)); // Flags 1.
931 
932  OutStreamer->AddComment("PPA1 Flags 2");
933  if ((Flags2 & PPA1Flag2::ExternalProcedure) == PPA1Flag2::ExternalProcedure)
934  OutStreamer->AddComment(" Bit 0: 1 = External procedure");
935  if ((Flags2 & PPA1Flag2::STACKPROTECTOR) == PPA1Flag2::STACKPROTECTOR)
936  OutStreamer->AddComment(" Bit 3: 1 = STACKPROTECT is enabled");
937  else
938  OutStreamer->AddComment(" Bit 3: 0 = STACKPROTECT is not enabled");
939  OutStreamer->emitInt8(static_cast<uint8_t>(Flags2)); // Flags 2.
940 
941  OutStreamer->AddComment("PPA1 Flags 3");
942  if ((Flags3 & PPA1Flag3::FPRMask) == PPA1Flag3::FPRMask)
943  OutStreamer->AddComment(" Bit 2: 1 = FP Reg Mask is in optional area");
944  OutStreamer->emitInt8(
945  static_cast<uint8_t>(Flags3)); // Flags 3 (optional sections).
946 
947  OutStreamer->AddComment("PPA1 Flags 4");
948  if ((Flags4 & PPA1Flag4::VRMask) == PPA1Flag4::VRMask)
949  OutStreamer->AddComment(" Bit 2: 1 = Vector Reg Mask is in optional area");
950  OutStreamer->emitInt8(static_cast<uint8_t>(
951  Flags4)); // Flags 4 (optional sections, always emit these).
952 }
953 
954 void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
956  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
957  const auto TargetHasVector = Subtarget.hasVector();
958 
959  const SystemZMachineFunctionInfo *ZFI =
961  const auto *ZFL = static_cast<const SystemZXPLINKFrameLowering *>(
962  Subtarget.getFrameLowering());
963  const MachineFrameInfo &MFFrame = MF->getFrameInfo();
964 
965  // Get saved GPR/FPR/VPR masks.
966  const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
967  uint16_t SavedGPRMask = 0;
968  uint16_t SavedFPRMask = 0;
969  uint8_t SavedVRMask = 0;
970  int64_t OffsetFPR = 0;
971  int64_t OffsetVR = 0;
972  const int64_t TopOfStack =
973  MFFrame.getOffsetAdjustment() + MFFrame.getStackSize();
974 
975  // Loop over the spilled registers. The CalleeSavedInfo can't be used because
976  // it does not contain all spilled registers.
977  for (unsigned I = ZFI->getSpillGPRRegs().LowGPR,
978  E = ZFI->getSpillGPRRegs().HighGPR;
979  I && E && I <= E; ++I) {
980  unsigned V = TRI->getEncodingValue((Register)I);
981  assert(V < 16 && "GPR index out of range");
982  SavedGPRMask |= 1 << (15 - V);
983  }
984 
985  for (auto &CS : CSI) {
986  unsigned Reg = CS.getReg();
987  unsigned I = TRI->getEncodingValue(Reg);
988 
989  if (SystemZ::FP64BitRegClass.contains(Reg)) {
990  assert(I < 16 && "FPR index out of range");
991  SavedFPRMask |= 1 << (15 - I);
992  int64_t Temp = MFFrame.getObjectOffset(CS.getFrameIdx());
993  if (Temp < OffsetFPR)
994  OffsetFPR = Temp;
995  } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
996  assert(I >= 16 && I <= 23 && "VPR index out of range");
997  unsigned BitNum = I - 16;
998  SavedVRMask |= 1 << (7 - BitNum);
999  int64_t Temp = MFFrame.getObjectOffset(CS.getFrameIdx());
1000  if (Temp < OffsetVR)
1001  OffsetVR = Temp;
1002  }
1003  }
1004 
1005  // Adjust the offset.
1006  OffsetFPR += (OffsetFPR < 0) ? TopOfStack : 0;
1007  OffsetVR += (OffsetVR < 0) ? TopOfStack : 0;
1008 
1009  // Get alloca register.
1010  uint8_t FrameReg = TRI->getEncodingValue(TRI->getFrameRegister(*MF));
1011  uint8_t AllocaReg = ZFL->hasFP(*MF) ? FrameReg : 0;
1012  assert(AllocaReg < 16 && "Can't have alloca register larger than 15");
1013  (void)AllocaReg;
1014 
1015  // Build FPR save area offset.
1016  uint32_t FrameAndFPROffset = 0;
1017  if (SavedFPRMask) {
1018  uint64_t FPRSaveAreaOffset = OffsetFPR;
1019  assert(FPRSaveAreaOffset < 0x10000000 && "Offset out of range");
1020 
1021  FrameAndFPROffset = FPRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1022  FrameAndFPROffset |= FrameReg << 28; // Put into top 4 bits.
1023  }
1024 
1025  // Build VR save area offset.
1026  uint32_t FrameAndVROffset = 0;
1027  if (TargetHasVector && SavedVRMask) {
1028  uint64_t VRSaveAreaOffset = OffsetVR;
1029  assert(VRSaveAreaOffset < 0x10000000 && "Offset out of range");
1030 
1031  FrameAndVROffset = VRSaveAreaOffset & 0x0FFFFFFF; // Lose top 4 bits.
1032  FrameAndVROffset |= FrameReg << 28; // Put into top 4 bits.
1033  }
1034 
1035  // Emit PPA1 section.
1036  OutStreamer->AddComment("PPA1");
1037  OutStreamer->emitLabel(CurrentFnPPA1Sym);
1038  OutStreamer->AddComment("Version");
1039  OutStreamer->emitInt8(0x02); // Version.
1040  OutStreamer->AddComment("LE Signature X'CE'");
1041  OutStreamer->emitInt8(0xCE); // CEL signature.
1042  OutStreamer->AddComment("Saved GPR Mask");
1043  OutStreamer->emitInt16(SavedGPRMask);
1044 
1046  MFFrame.hasStackProtectorIndex(), SavedFPRMask != 0,
1047  TargetHasVector && SavedVRMask != 0);
1048 
1049  OutStreamer->AddComment("Length/4 of Parms");
1050  OutStreamer->emitInt16(
1051  static_cast<uint16_t>(MFFrame.getMaxCallFrameSize() / 4)); // Parms/4.
1052  OutStreamer->AddComment("Length of Code");
1053  OutStreamer->emitAbsoluteSymbolDiff(FnEndSym, CurrentFnEPMarkerSym, 4);
1054 
1055  // Emit saved FPR mask and offset to FPR save area (0x20 of flags 3).
1056  if (SavedFPRMask) {
1057  OutStreamer->AddComment("FPR mask");
1058  OutStreamer->emitInt16(SavedFPRMask);
1059  OutStreamer->AddComment("AR mask");
1060  OutStreamer->emitInt16(0); // AR Mask, unused currently.
1061  OutStreamer->AddComment("FPR Save Area Locator");
1062  OutStreamer->AddComment(Twine(" Bit 0-3: Register R")
1063  .concat(utostr(FrameAndFPROffset >> 28))
1064  .str());
1065  OutStreamer->AddComment(Twine(" Bit 4-31: Offset ")
1066  .concat(utostr(FrameAndFPROffset & 0x0FFFFFFF))
1067  .str());
1068  OutStreamer->emitInt32(FrameAndFPROffset); // Offset to FPR save area with
1069  // register to add value to
1070  // (alloca reg).
1071  }
1072 
1073  // Emit saved VR mask to VR save area.
1074  if (TargetHasVector && SavedVRMask) {
1075  OutStreamer->AddComment("VR mask");
1076  OutStreamer->emitInt8(SavedVRMask);
1077  OutStreamer->emitInt8(0); // Reserved.
1078  OutStreamer->emitInt16(0); // Also reserved.
1079  OutStreamer->AddComment("VR Save Area Locator");
1080  OutStreamer->AddComment(Twine(" Bit 0-3: Register R")
1081  .concat(utostr(FrameAndVROffset >> 28))
1082  .str());
1083  OutStreamer->AddComment(Twine(" Bit 4-31: Offset ")
1084  .concat(utostr(FrameAndVROffset & 0x0FFFFFFF))
1085  .str());
1086  OutStreamer->emitInt32(FrameAndVROffset);
1087  }
1088 
1089  // Emit offset to entry point optional section (0x80 of flags 4).
1090  OutStreamer->emitAbsoluteSymbolDiff(CurrentFnEPMarkerSym, CurrentFnPPA1Sym,
1091  4);
1092 }
1093 
1095  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
1096 
1097  if (Subtarget.getTargetTriple().isOSzOS()) {
1098  MCContext &OutContext = OutStreamer->getContext();
1099 
1100  // Save information for later use.
1101  std::string N(MF->getFunction().hasName()
1102  ? Twine(MF->getFunction().getName()).concat("_").str()
1103  : "");
1104 
1105  CurrentFnEPMarkerSym =
1106  OutContext.createTempSymbol(Twine("EPM_").concat(N).str(), true);
1107  CurrentFnPPA1Sym =
1108  OutContext.createTempSymbol(Twine("PPA1_").concat(N).str(), true);
1109 
1110  // EntryPoint Marker
1111  const MachineFrameInfo &MFFrame = MF->getFrameInfo();
1112  bool IsUsingAlloca = MFFrame.hasVarSizedObjects();
1113 
1114  // Set Flags
1115  uint8_t Flags = 0;
1116  if (IsUsingAlloca)
1117  Flags |= 0x04;
1118 
1119  uint32_t DSASize = MFFrame.getStackSize();
1120 
1121  // Combine into top 27 bits of DSASize and bottom 5 bits of Flags.
1122  uint32_t DSAAndFlags = DSASize & 0xFFFFFFE0; // (x/32) << 5
1123  DSAAndFlags |= Flags;
1124 
1125  // Emit entry point marker section.
1126  OutStreamer->AddComment("XPLINK Routine Layout Entry");
1127  OutStreamer->emitLabel(CurrentFnEPMarkerSym);
1128  OutStreamer->AddComment("Eyecatcher 0x00C300C500C500");
1129  OutStreamer->emitIntValueInHex(0x00C300C500C500, 7); // Eyecatcher.
1130  OutStreamer->AddComment("Mark Type C'1'");
1131  OutStreamer->emitInt8(0xF1); // Mark Type.
1132  OutStreamer->AddComment("Offset to PPA1");
1133  OutStreamer->emitAbsoluteSymbolDiff(CurrentFnPPA1Sym, CurrentFnEPMarkerSym,
1134  4);
1135  if (OutStreamer->isVerboseAsm()) {
1136  OutStreamer->AddComment("DSA Size 0x" + Twine::utohexstr(DSASize));
1137  OutStreamer->AddComment("Entry Flags");
1138  if (Flags & 0x04)
1139  OutStreamer->AddComment(" Bit 2: 1 = Uses alloca");
1140  else
1141  OutStreamer->AddComment(" Bit 2: 0 = Does not use alloca");
1142  }
1143  OutStreamer->emitInt32(DSAAndFlags);
1144  }
1145 
1147 }
1148 
1149 // Force static initialization.
1152 }
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
MachineModuleInfoImpls.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1299
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::SystemZMC::getRegAsGR32
unsigned getRegAsGR32(unsigned Reg)
Definition: SystemZMCTargetDesc.h:65
llvm::AsmPrinter::createTempSymbol
MCSymbol * createTempSymbol(const Twine &Name) const
Definition: AsmPrinter.cpp:3535
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static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::SystemZSubtarget::hasVector
bool hasVector() const
Definition: SystemZSubtarget.h:214
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:609
LLVM_MARK_AS_BITMASK_ENUM
#define LLVM_MARK_AS_BITMASK_ENUM(LargestValue)
LLVM_MARK_AS_BITMASK_ENUM lets you opt in an individual enum type so you can perform bitwise operatio...
Definition: BitmaskEnum.h:41
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const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:90
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static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
llvm::SystemZCP::NTPOFF
@ NTPOFF
Definition: SystemZConstantPoolValue.h:24
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCSectionELF.h
llvm::TargetMachine::getMCRegisterInfo
const MCRegisterInfo * getMCRegisterInfo() const
Definition: TargetMachine.h:206
llvm::Value::hasName
bool hasName() const
Definition: Value.h:261
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::MachineFrameInfo::getOffsetAdjustment
int getOffsetAdjustment() const
Return the correction for frame offsets.
Definition: MachineFrameInfo.h:594
MCInstBuilder.h
llvm::SystemZInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
llvm::MachineConstantPoolValue
Abstract base class for all machine specific constantpool value subclasses.
Definition: MachineConstantPool.h:35
llvm::SystemZCP::SystemZCPModifier
SystemZCPModifier
Definition: SystemZConstantPoolValue.h:20
llvm::SystemZMC::GR64Regs
const unsigned GR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:49
llvm::SystemZTargetStreamer
Definition: SystemZTargetStreamer.h:18
EmitNop
static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer, unsigned NumBytes, const MCSubtargetInfo &STI)
Definition: SystemZAsmPrinter.cpp:615
llvm::ELF::SHT_PROGBITS
@ SHT_PROGBITS
Definition: ELF.h:980
lowerAlignmentHint
static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:89
llvm::MCAsmInfo::getAssemblerDialect
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:686
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
printOperand
static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI, raw_ostream &OS)
Definition: SystemZAsmPrinter.cpp:799
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
SystemZAsmPrinter.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SystemZConstantPoolValue
A SystemZ-specific constant pool value.
Definition: SystemZConstantPoolValue.h:32
SystemZTargetInfo.h
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:654
SystemZInstPrinter.h
llvm::AsmPrinter::EmitToStreamer
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:403
llvm::StackMaps::recordStackMap
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:524
llvm::SystemZMCInstLower
Definition: SystemZMCInstLower.h:23
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
printAddress
static void printAddress(const MCAsmInfo *MAI, unsigned Base, const MCOperand &DispMO, unsigned Index, raw_ostream &OS)
Definition: SystemZAsmPrinter.cpp:814
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
lowerSubvectorLoad
static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:114
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
llvm::MCSymbolRefExpr::VK_NTPOFF
@ VK_NTPOFF
Definition: MCExpr.h:206
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
ELF.h
llvm::SystemZISD::TLS_LDCALL
@ TLS_LDCALL
Definition: SystemZISelLowering.h:41
llvm::getTheSystemZTarget
Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::SystemZISD::TLS_GDCALL
@ TLS_GDCALL
Definition: SystemZISelLowering.h:40
llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:99
SystemZConstantPoolValue.h
llvm::StackProtector
Definition: StackProtector.h:36
llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:423
llvm::AsmPrinter::emitFunctionEntryLabel
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: AsmPrinter.cpp:1043
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCContext::getELFSection
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:564
llvm::MCSymbolRefExpr::VK_TLSLDM
@ VK_TLSLDM
Definition: MCExpr.h:211
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::Triple::isOSzOS
bool isOSzOS() const
Definition: Triple.h:514
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
llvm::AsmPrinter::SM
StackMaps SM
Definition: AsmPrinter.h:210
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::Twine::str
std::string str() const
Return the twine contents as a std::string.
Definition: Twine.cpp:17
lowerRIHigh
static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:47
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::SystemZAsmPrinter::emitInstruction
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
Definition: SystemZAsmPrinter.cpp:145
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::LegacyLegalizeActions::Lower
@ Lower
The operation itself must be expressed in terms of simpler actions on this target.
Definition: LegacyLegalizerInfo.h:58
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
lowerSubvectorStore
static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:124
llvm::SystemZAsmPrinter::emitMachineConstantPoolValue
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
Definition: SystemZAsmPrinter.cpp:775
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::Twine::utohexstr
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:404
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::SystemZTargetStreamer::MCInstSTIPair
std::pair< MCInst, const MCSubtargetInfo * > MCInstSTIPair
Definition: SystemZTargetStreamer.h:22
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::SystemZCP::DTPOFF
@ DTPOFF
Definition: SystemZConstantPoolValue.h:23
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::MachineFrameInfo::hasStackProtectorIndex
bool hasStackProtectorIndex() const
Definition: MachineFrameInfo.h:360
llvm::SystemZAsmPrinter::emitFunctionEntryLabel
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: SystemZAsmPrinter.cpp:1094
llvm::SystemZAsmPrinter::PrintAsmMemoryOperand
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
Definition: SystemZAsmPrinter.cpp:852
lowerRIEfLow
static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:61
llvm::MCSymbolRefExpr::VK_PLT
@ VK_PLT
Definition: MCExpr.h:208
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1096
getTLSGetOffset
static const MCSymbolRefExpr * getTLSGetOffset(MCContext &Context)
Definition: SystemZAsmPrinter.cpp:71
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::concat
detail::concat_range< ValueT, RangeTs... > concat(RangeTs &&... Ranges)
Concatenated range across two or more ranges.
Definition: STLExtras.h:1208
llvm::ELF::SHF_ALLOC
@ SHF_ALLOC
Definition: ELF.h:1068
llvm::MachineInstr::mmo_iterator
ArrayRef< MachineMemOperand * >::iterator mmo_iterator
Definition: MachineInstr.h:70
llvm::SystemZMC::getRegAsGRH32
unsigned getRegAsGRH32(unsigned Reg)
Definition: SystemZMCTargetDesc.h:70
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AsmPrinter::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:656
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1293
llvm::AsmPrinter::MF
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:102
llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:94
llvm::SystemZCP::TLSLDM
@ TLSLDM
Definition: SystemZConstantPoolValue.h:22
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::SystemZXPLINKFrameLowering
Definition: SystemZFrameLowering.h:101
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
Mangler.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:525
llvm::SystemZSubtarget::hasFastSerialization
bool hasFastSerialization() const
Definition: SystemZSubtarget.h:173
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::SystemZ::GPRRegs::LowGPR
unsigned LowGPR
Definition: SystemZMachineFunctionInfo.h:20
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
uint32_t
llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:55
llvm::SystemZAsmPrinter::emitFunctionBodyEnd
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Definition: SystemZAsmPrinter.cpp:862
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:308
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:318
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AD_HLASM
@ AD_HLASM
Definition: SystemZMCAsmInfo.h:18
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SystemZCP::TLSGD
@ TLSGD
Definition: SystemZConstantPoolValue.h:21
getModifierVariantKind
static MCSymbolRefExpr::VariantKind getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier)
Definition: SystemZAsmPrinter.cpp:765
llvm::SystemZMachineFunctionInfo
Definition: SystemZMachineFunctionInfo.h:27
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
uint16_t
emitPPA1Flags
static void emitPPA1Flags(std::unique_ptr< MCStreamer > &OutStreamer, bool VarArg, bool StackProtector, bool FPRMask, bool VRMask)
Definition: SystemZAsmPrinter.cpp:879
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
lowerRILow
static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode)
Definition: SystemZAsmPrinter.cpp:33
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:982
llvm::AsmPrinter::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:398
getGlobalOffsetTable
static const MCSymbolRefExpr * getGlobalOffsetTable(MCContext &Context)
Definition: SystemZAsmPrinter.cpp:78
llvm::StackMaps::recordPatchPoint
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:534
llvm::SystemZMC::getRegAsVR128
unsigned getRegAsVR128(unsigned Reg)
Definition: SystemZMCTargetDesc.h:75
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
printFormattedRegName
static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo, raw_ostream &OS)
Definition: SystemZAsmPrinter.cpp:788
llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:209
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
llvm::SystemZMachineFunctionInfo::getSpillGPRRegs
SystemZ::GPRRegs getSpillGPRRegs() const
Definition: SystemZMachineFunctionInfo.h:52
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::SystemZTargetStreamer::EXRLTargets2Sym
EXRLT2SymMap EXRLTargets2Sym
Definition: SystemZTargetStreamer.h:47
LOWER_HIGH
#define LOWER_HIGH(NAME)
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:188
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
LLVMInitializeSystemZAsmPrinter
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmPrinter()
Definition: SystemZAsmPrinter.cpp:1150
llvm::MCExpr::print
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
llvm::AsmPrinter::TM
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:87
llvm::AsmPrinter::getObjFileLowering
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:384
N
#define N
MCStreamer.h
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:125
llvm::AsmPrinter::getDataLayout
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:388
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
RegName
#define RegName(no)
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::RegisterAsmPrinter
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Definition: TargetRegistry.h:1419
llvm::SystemZMC::getRegAsGR64
unsigned getRegAsGR64(unsigned Reg)
Definition: SystemZMCTargetDesc.h:60
llvm::SystemZ::GPRRegs::HighGPR
unsigned HighGPR
Definition: SystemZMachineFunctionInfo.h:21
llvm::SystemZSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition: SystemZSubtarget.h:105
llvm::MachineInstrBundleIterator< const MachineInstr >
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
LOWER_LOW
#define LOWER_LOW(NAME)
llvm::SystemZAsmPrinter::PrintAsmOperand
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: SystemZAsmPrinter.cpp:831
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::AsmPrinter::PrintAsmOperand
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: AsmPrinterInlineAsm.cpp:467
SystemZMCInstLower.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:338
llvm::MCSymbolRefExpr::VK_DTPOFF
@ VK_DTPOFF
Definition: MCExpr.h:213
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::Twine::concat
Twine concat(const Twine &Suffix) const
Definition: Twine.h:506
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
TargetLoweringObjectFileImpl.h