LLVM 17.0.0git
aarch64.h
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1//=== aarch64.h - Generic JITLink aarch64 edge kinds, utilities -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Generic utilities for graphs representing aarch64 objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_EXECUTIONENGINE_JITLINK_AARCH64_H
14#define LLVM_EXECUTIONENGINE_JITLINK_AARCH64_H
15
16#include "TableManager.h"
19
20namespace llvm {
21namespace jitlink {
22namespace aarch64 {
23
24/// Represents aarch64 fixups and other aarch64-specific edge kinds.
26
27 /// A plain 64-bit pointer value relocation.
28 ///
29 /// Fixup expression:
30 /// Fixup <- Target + Addend : uint64
31 ///
33
34 /// A plain 32-bit pointer value relocation.
35 ///
36 /// Fixup expression:
37 /// Fixup <- Target + Addend : uint32
38 ///
39 /// Errors:
40 /// - The target must reside in the low 32-bits of the address space,
41 /// otherwise an out-of-range error will be returned.
42 ///
44
45 /// A 64-bit delta.
46 ///
47 /// Delta from the fixup to the target.
48 ///
49 /// Fixup expression:
50 /// Fixup <- Target - Fixup + Addend : int64
51 ///
53
54 /// A 32-bit delta.
55 ///
56 /// Delta from the fixup to the target.
57 ///
58 /// Fixup expression:
59 /// Fixup <- Target - Fixup + Addend : int64
60 ///
61 /// Errors:
62 /// - The result of the fixup expression must fit into an int32, otherwise
63 /// an out-of-range error will be returned.
64 ///
66
67 /// A 64-bit negative delta.
68 ///
69 /// Delta from target back to the fixup.
70 ///
71 /// Fixup expression:
72 /// Fixup <- Fixup - Target + Addend : int64
73 ///
75
76 /// A 32-bit negative delta.
77 ///
78 /// Delta from the target back to the fixup.
79 ///
80 /// Fixup expression:
81 /// Fixup <- Fixup - Target + Addend : int32
82 ///
83 /// Errors:
84 /// - The result of the fixup expression must fit into an int32, otherwise
85 /// an out-of-range error will be returned.
87
88 /// A 26-bit PC-relative branch.
89 ///
90 /// Represents a PC-relative call or branch to a target within +/-128Mb. The
91 /// target must be 32-bit aligned.
92 ///
93 /// Fixup expression:
94 /// Fixup <- (Target - Fixup + Addend) >> 2 : int26
95 ///
96 /// Notes:
97 /// The '26' in the name refers to the number operand bits and follows the
98 /// naming convention used by the corresponding ELF and MachO relocations.
99 /// Since the low two bits must be zero (because of the 32-bit alignment of
100 /// the target) the operand is effectively a signed 28-bit number.
101 ///
102 ///
103 /// Errors:
104 /// - The result of the unshifted part of the fixup expression must be
105 /// 32-bit aligned otherwise an alignment error will be returned.
106 /// - The result of the fixup expression must fit into an int26 otherwise an
107 /// out-of-range error will be returned.
109
110 /// A 14-bit PC-relative test and branch.
111 ///
112 /// Represents a PC-relative test and branch to a target within +/-32Kb. The
113 /// target must be 32-bit aligned.
114 ///
115 /// Fixup expression:
116 /// Fixup <- (Target - Fixup + Addend) >> 2 : int14
117 ///
118 /// Notes:
119 /// The '14' in the name refers to the number operand bits and follows the
120 /// naming convention used by the corresponding ELF relocation.
121 /// Since the low two bits must be zero (because of the 32-bit alignment of
122 /// the target) the operand is effectively a signed 16-bit number.
123 ///
124 ///
125 /// Errors:
126 /// - The result of the unshifted part of the fixup expression must be
127 /// 32-bit aligned otherwise an alignment error will be returned.
128 /// - The result of the fixup expression must fit into an int14 otherwise an
129 /// out-of-range error will be returned.
131
132 /// A 19-bit PC-relative conditional branch.
133 ///
134 /// Represents a PC-relative conditional branch to a target within +/-1Mb. The
135 /// target must be 32-bit aligned.
136 ///
137 /// Fixup expression:
138 /// Fixup <- (Target - Fixup + Addend) >> 2 : int19
139 ///
140 /// Notes:
141 /// The '19' in the name refers to the number operand bits and follows the
142 /// naming convention used by the corresponding ELF relocation.
143 /// Since the low two bits must be zero (because of the 32-bit alignment of
144 /// the target) the operand is effectively a signed 21-bit number.
145 ///
146 ///
147 /// Errors:
148 /// - The result of the unshifted part of the fixup expression must be
149 /// 32-bit aligned otherwise an alignment error will be returned.
150 /// - The result of the fixup expression must fit into an int19 otherwise an
151 /// out-of-range error will be returned.
153
154 /// A 16-bit slice of the target address (which slice depends on the
155 /// instruction at the fixup location).
156 ///
157 /// Used to fix up MOVK/MOVN/MOVZ instructions.
158 ///
159 /// Fixup expression:
160 ///
161 /// Fixup <- (Target + Addend) >> Shift : uint16
162 ///
163 /// where Shift is encoded in the instruction at the fixup location.
164 ///
166
167 /// The signed 21-bit delta from the fixup to the target.
168 ///
169 /// Typically used to load a pointers at a PC-relative offset of +/- 1Mb. The
170 /// target must be 32-bit aligned.
171 ///
172 /// Fixup expression:
173 ///
174 /// Fixup <- (Target - Fixup) >> 2 : int19
175 ///
176 /// Errors:
177 /// - The result of the unshifted part of the fixup expression must be
178 /// 32-bit aligned otherwise an alignment error will be returned.
179 /// - The result of the fixup expression must fit into an an int19 or an
180 /// out-of-range error will be returned.
182
183 /// The signed 21-bit delta from the fixup page to the page containing the
184 /// target.
185 ///
186 /// Fixup expression:
187 ///
188 /// Fixup <- (((Target + Addend) & ~0xfff) - (Fixup & ~0xfff)) >> 12 : int21
189 ///
190 /// Notes:
191 /// For ADRP fixups.
192 ///
193 /// Errors:
194 /// - The result of the fixup expression must fit into an int21 otherwise an
195 /// out-of-range error will be returned.
197
198 /// The 12-bit (potentially shifted) offset of the target within its page.
199 ///
200 /// Typically used to fix up LDR immediates.
201 ///
202 /// Fixup expression:
203 ///
204 /// Fixup <- ((Target + Addend) >> Shift) & 0xfff : uint12
205 ///
206 /// where Shift is encoded in the size field of the instruction.
207 ///
208 /// Errors:
209 /// - The result of the unshifted part of the fixup expression must be
210 /// aligned otherwise an alignment error will be returned.
211 /// - The result of the fixup expression must fit into a uint12 otherwise an
212 /// out-of-range error will be returned.
214
215 /// A GOT entry getter/constructor, transformed to Page21 pointing at the GOT
216 /// entry for the original target.
217 ///
218 /// Indicates that this edge should be transformed into a Page21 targeting
219 /// the GOT entry for the edge's current target, maintaining the same addend.
220 /// A GOT entry for the target should be created if one does not already
221 /// exist.
222 ///
223 /// Edges of this kind are usually handled by a GOT builder pass inserted by
224 /// default.
225 ///
226 /// Fixup expression:
227 /// NONE
228 ///
229 /// Errors:
230 /// - *ASSERTION* Failure to handle edges of this kind prior to the fixup
231 /// phase will result in an assert/unreachable during the fixup phase.
232 ///
234
235 /// A GOT entry getter/constructor, transformed to Pageoffset12 pointing at
236 /// the GOT entry for the original target.
237 ///
238 /// Indicates that this edge should be transformed into a PageOffset12
239 /// targeting the GOT entry for the edge's current target, maintaining the
240 /// same addend. A GOT entry for the target should be created if one does not
241 /// already exist.
242 ///
243 /// Edges of this kind are usually handled by a GOT builder pass inserted by
244 /// default.
245 ///
246 /// Fixup expression:
247 /// NONE
248 ///
249 /// Errors:
250 /// - *ASSERTION* Failure to handle edges of this kind prior to the fixup
251 /// phase will result in an assert/unreachable during the fixup phase.
252 ///
254
255 /// A GOT entry getter/constructor, transformed to Delta32 pointing at the GOT
256 /// entry for the original target.
257 ///
258 /// Indicates that this edge should be transformed into a Delta32/ targeting
259 /// the GOT entry for the edge's current target, maintaining the same addend.
260 /// A GOT entry for the target should be created if one does not already
261 /// exist.
262 ///
263 /// Edges of this kind are usually handled by a GOT builder pass inserted by
264 /// default.
265 ///
266 /// Fixup expression:
267 /// NONE
268 ///
269 /// Errors:
270 /// - *ASSERTION* Failure to handle edges of this kind prior to the fixup
271 /// phase will result in an assert/unreachable during the fixup phase.
272 ///
274
275 /// A TLVP entry getter/constructor, transformed to Page21.
276 ///
277 /// Indicates that this edge should be transformed into a Page21 targeting the
278 /// TLVP entry for the edge's current target. A TLVP entry for the target
279 /// should be created if one does not already exist.
280 ///
281 /// Fixup expression:
282 /// NONE
283 ///
284 /// Errors:
285 /// - *ASSERTION* Failure to handle edges of this kind prior to the fixup
286 /// phase will result in an assert/unreachable during the fixup phase.
287 ///
289
290 /// A TLVP entry getter/constructor, transformed to PageOffset12.
291 ///
292 /// Indicates that this edge should be transformed into a PageOffset12
293 /// targeting the TLVP entry for the edge's current target. A TLVP entry for
294 /// the target should be created if one does not already exist.
295 ///
296 /// Fixup expression:
297 /// NONE
298 ///
299 /// Errors:
300 /// - *ASSERTION* Failure to handle edges of this kind prior to the fixup
301 /// phase will result in an assert/unreachable during the fixup phase.
302 ///
304
305 /// A TLSDesc entry getter/constructor, transformed to Page21.
306 ///
307 /// Indicates that this edge should be transformed into a Page21 targeting the
308 /// TLSDesc entry for the edge's current target. A TLSDesc entry for the
309 /// target should be created if one does not already exist.
310 ///
311 /// Fixup expression:
312 /// NONE
313 ///
314 /// Errors:
315 /// - *ASSERTION* Failure to handle edges of this kind prior to the fixup
316 /// phase will result in an assert/unreachable during the fixup phase.
317 ///
319
320 /// A TLSDesc entry getter/constructor, transformed to PageOffset12.
321 ///
322 /// Indicates that this edge should be transformed into a PageOffset12
323 /// targeting the TLSDesc entry for the edge's current target. A TLSDesc entry
324 /// for the target should be created if one does not already exist.
325 ///
326 /// Fixup expression:
327 /// NONE
328 ///
329 /// Errors:
330 /// - *ASSERTION* Failure to handle edges of this kind prior to the fixup
331 /// phase will result in an assert/unreachable during the fixup phase.
332 ///
334};
335
336/// Returns a string name for the given aarch64 edge. For debugging purposes
337/// only
338const char *getEdgeKindName(Edge::Kind K);
339
340// Returns whether the Instr is LD/ST (imm12)
341inline bool isLoadStoreImm12(uint32_t Instr) {
342 constexpr uint32_t LoadStoreImm12Mask = 0x3b000000;
343 return (Instr & LoadStoreImm12Mask) == 0x39000000;
344}
345
346inline bool isTestAndBranchImm14(uint32_t Instr) {
347 constexpr uint32_t TestAndBranchImm14Mask = 0x7e000000;
348 return (Instr & TestAndBranchImm14Mask) == 0x36000000;
349}
350
351inline bool isCondBranchImm19(uint32_t Instr) {
352 constexpr uint32_t CondBranchImm19Mask = 0xfe000000;
353 return (Instr & CondBranchImm19Mask) == 0x54000000;
354}
355
356inline bool isCompAndBranchImm19(uint32_t Instr) {
357 constexpr uint32_t CompAndBranchImm19Mask = 0x7e000000;
358 return (Instr & CompAndBranchImm19Mask) == 0x34000000;
359}
360
361// Returns the amount the address operand of LD/ST (imm12)
362// should be shifted right by.
363//
364// The shift value varies by the data size of LD/ST instruction.
365// For instance, LDH instructoin needs the address to be shifted
366// right by 1.
367inline unsigned getPageOffset12Shift(uint32_t Instr) {
368 constexpr uint32_t Vec128Mask = 0x04800000;
369
370 if (isLoadStoreImm12(Instr)) {
371 uint32_t ImplicitShift = Instr >> 30;
372 if (ImplicitShift == 0)
373 if ((Instr & Vec128Mask) == Vec128Mask)
374 ImplicitShift = 4;
375
376 return ImplicitShift;
377 }
378
379 return 0;
380}
381
382// Returns whether the Instr is MOVK/MOVZ (imm16) with a zero immediate field
383inline bool isMoveWideImm16(uint32_t Instr) {
384 constexpr uint32_t MoveWideImm16Mask = 0x5f9fffe0;
385 return (Instr & MoveWideImm16Mask) == 0x52800000;
386}
387
388// Returns the amount the address operand of MOVK/MOVZ (imm16)
389// should be shifted right by.
390//
391// The shift value is specfied in the assembly as LSL #<shift>.
392inline unsigned getMoveWide16Shift(uint32_t Instr) {
393 if (isMoveWideImm16(Instr)) {
394 uint32_t ImplicitShift = (Instr >> 21) & 0b11;
395 return ImplicitShift << 4;
396 }
397
398 return 0;
399}
400
401/// Apply fixup expression for edge to block content.
402inline Error applyFixup(LinkGraph &G, Block &B, const Edge &E) {
403 using namespace support;
404
405 char *BlockWorkingMem = B.getAlreadyMutableContent().data();
406 char *FixupPtr = BlockWorkingMem + E.getOffset();
407 orc::ExecutorAddr FixupAddress = B.getAddress() + E.getOffset();
408
409 switch (E.getKind()) {
410 case Pointer64: {
411 uint64_t Value = E.getTarget().getAddress().getValue() + E.getAddend();
412 *(ulittle64_t *)FixupPtr = Value;
413 break;
414 }
415 case Pointer32: {
416 uint64_t Value = E.getTarget().getAddress().getValue() + E.getAddend();
417 if (Value > std::numeric_limits<uint32_t>::max())
418 return makeTargetOutOfRangeError(G, B, E);
419 *(ulittle32_t *)FixupPtr = Value;
420 break;
421 }
422 case Delta32:
423 case Delta64:
424 case NegDelta32:
425 case NegDelta64: {
426 int64_t Value;
427 if (E.getKind() == Delta32 || E.getKind() == Delta64)
428 Value = E.getTarget().getAddress() - FixupAddress + E.getAddend();
429 else
430 Value = FixupAddress - E.getTarget().getAddress() + E.getAddend();
431
432 if (E.getKind() == Delta32 || E.getKind() == NegDelta32) {
433 if (Value < std::numeric_limits<int32_t>::min() ||
434 Value > std::numeric_limits<int32_t>::max())
435 return makeTargetOutOfRangeError(G, B, E);
436 *(little32_t *)FixupPtr = Value;
437 } else
438 *(little64_t *)FixupPtr = Value;
439 break;
440 }
441 case Branch26PCRel: {
442 assert((FixupAddress.getValue() & 0x3) == 0 &&
443 "Branch-inst is not 32-bit aligned");
444
445 int64_t Value = E.getTarget().getAddress() - FixupAddress + E.getAddend();
446
447 if (static_cast<uint64_t>(Value) & 0x3)
448 return make_error<JITLinkError>("BranchPCRel26 target is not 32-bit "
449 "aligned");
450
451 if (Value < -(1 << 27) || Value > ((1 << 27) - 1))
452 return makeTargetOutOfRangeError(G, B, E);
453
454 uint32_t RawInstr = *(little32_t *)FixupPtr;
455 assert((RawInstr & 0x7fffffff) == 0x14000000 &&
456 "RawInstr isn't a B or BR immediate instruction");
457 uint32_t Imm = (static_cast<uint32_t>(Value) & ((1 << 28) - 1)) >> 2;
458 uint32_t FixedInstr = RawInstr | Imm;
459 *(little32_t *)FixupPtr = FixedInstr;
460 break;
461 }
462 case MoveWide16: {
463 uint64_t TargetOffset =
464 (E.getTarget().getAddress() + E.getAddend()).getValue();
465
466 uint32_t RawInstr = *(ulittle32_t *)FixupPtr;
467 assert(isMoveWideImm16(RawInstr) &&
468 "RawInstr isn't a MOVK/MOVZ instruction");
469
470 unsigned ImmShift = getMoveWide16Shift(RawInstr);
471 uint32_t Imm = (TargetOffset >> ImmShift) & 0xffff;
472 uint32_t FixedInstr = RawInstr | (Imm << 5);
473 *(ulittle32_t *)FixupPtr = FixedInstr;
474 break;
475 }
476 case LDRLiteral19: {
477 assert((FixupAddress.getValue() & 0x3) == 0 && "LDR is not 32-bit aligned");
478 assert(E.getAddend() == 0 && "LDRLiteral19 with non-zero addend");
479 uint32_t RawInstr = *(ulittle32_t *)FixupPtr;
480 assert(RawInstr == 0x58000010 && "RawInstr isn't a 64-bit LDR literal");
481 int64_t Delta = E.getTarget().getAddress() - FixupAddress;
482 if (Delta & 0x3)
483 return make_error<JITLinkError>("LDR literal target is not 32-bit "
484 "aligned");
485 if (Delta < -(1 << 20) || Delta > ((1 << 20) - 1))
486 return makeTargetOutOfRangeError(G, B, E);
487
488 uint32_t EncodedImm = ((static_cast<uint32_t>(Delta) >> 2) & 0x7ffff) << 5;
489 uint32_t FixedInstr = RawInstr | EncodedImm;
490 *(ulittle32_t *)FixupPtr = FixedInstr;
491 break;
492 }
494 assert((FixupAddress.getValue() & 0x3) == 0 &&
495 "Test and branch is not 32-bit aligned");
496 uint32_t RawInstr = *(ulittle32_t *)FixupPtr;
497 assert(isTestAndBranchImm14(RawInstr) &&
498 "RawInstr is not a test and branch");
499 int64_t Delta = E.getTarget().getAddress() + E.getAddend() - FixupAddress;
500 if (Delta & 0x3)
501 return make_error<JITLinkError>(
502 "Test and branch literal target is not 32-bit aligned");
503 if (!isInt<16>(Delta))
504 return makeTargetOutOfRangeError(G, B, E);
505 uint32_t EncodedImm = ((static_cast<uint32_t>(Delta) >> 2) & 0x3fff) << 5;
506 uint32_t FixedInstr = RawInstr | EncodedImm;
507 *(ulittle32_t *)FixupPtr = FixedInstr;
508 break;
509 }
510 case CondBranch19PCRel: {
511 assert((FixupAddress.getValue() & 0x3) == 0 &&
512 "Conditional branch is not 32-bit aligned");
513 uint32_t RawInstr = *(ulittle32_t *)FixupPtr;
514 assert((isCondBranchImm19(RawInstr) || isCompAndBranchImm19(RawInstr)) &&
515 "RawInstr is not a conditional branch");
516 int64_t Delta = E.getTarget().getAddress() + E.getAddend() - FixupAddress;
517 if (Delta & 0x3)
518 return make_error<JITLinkError>(
519 "Conditional branch literal target is not 32-bit "
520 "aligned");
521 if (!isInt<21>(Delta))
522 return makeTargetOutOfRangeError(G, B, E);
523 uint32_t EncodedImm = ((static_cast<uint32_t>(Delta) >> 2) & 0x7ffff) << 5;
524 uint32_t FixedInstr = RawInstr | EncodedImm;
525 *(ulittle32_t *)FixupPtr = FixedInstr;
526 break;
527 }
528 case Page21: {
529 uint64_t TargetPage =
530 (E.getTarget().getAddress().getValue() + E.getAddend()) &
531 ~static_cast<uint64_t>(4096 - 1);
532 uint64_t PCPage =
533 FixupAddress.getValue() & ~static_cast<uint64_t>(4096 - 1);
534
535 int64_t PageDelta = TargetPage - PCPage;
536 if (!isInt<33>(PageDelta))
537 return makeTargetOutOfRangeError(G, B, E);
538
539 uint32_t RawInstr = *(ulittle32_t *)FixupPtr;
540 assert((RawInstr & 0xffffffe0) == 0x90000000 &&
541 "RawInstr isn't an ADRP instruction");
542 uint32_t ImmLo = (static_cast<uint64_t>(PageDelta) >> 12) & 0x3;
543 uint32_t ImmHi = (static_cast<uint64_t>(PageDelta) >> 14) & 0x7ffff;
544 uint32_t FixedInstr = RawInstr | (ImmLo << 29) | (ImmHi << 5);
545 *(ulittle32_t *)FixupPtr = FixedInstr;
546 break;
547 }
548 case PageOffset12: {
549 uint64_t TargetOffset =
550 (E.getTarget().getAddress() + E.getAddend()).getValue() & 0xfff;
551
552 uint32_t RawInstr = *(ulittle32_t *)FixupPtr;
553 unsigned ImmShift = getPageOffset12Shift(RawInstr);
554
555 if (TargetOffset & ((1 << ImmShift) - 1))
556 return make_error<JITLinkError>("PAGEOFF12 target is not aligned");
557
558 uint32_t EncodedImm = (TargetOffset >> ImmShift) << 10;
559 uint32_t FixedInstr = RawInstr | EncodedImm;
560 *(ulittle32_t *)FixupPtr = FixedInstr;
561 break;
562 }
563 default:
564 return make_error<JITLinkError>(
565 "In graph " + G.getName() + ", section " + B.getSection().getName() +
566 " unsupported edge kind " + getEdgeKindName(E.getKind()));
567 }
568
569 return Error::success();
570}
571
572/// aarch64 pointer size.
573constexpr uint64_t PointerSize = 8;
574
575/// AArch64 null pointer content.
576extern const char NullPointerContent[PointerSize];
577
578/// AArch64 pointer jump stub content.
579///
580/// Contains the instruction sequence for an indirect jump via an in-memory
581/// pointer:
582/// ADRP x16, ptr@page21
583/// LDR x16, [x16, ptr@pageoff12]
584/// BR x16
585extern const char PointerJumpStubContent[12];
586
587/// Creates a new pointer block in the given section and returns an
588/// Anonymous symobl pointing to it.
589///
590/// If InitialTarget is given then an Pointer64 relocation will be added to the
591/// block pointing at InitialTarget.
592///
593/// The pointer block will have the following default values:
594/// alignment: 64-bit
595/// alignment-offset: 0
596/// address: highest allowable (~7U)
598 Symbol *InitialTarget = nullptr,
599 uint64_t InitialAddend = 0) {
600 auto &B = G.createContentBlock(PointerSection, NullPointerContent,
601 orc::ExecutorAddr(~uint64_t(7)), 8, 0);
602 if (InitialTarget)
603 B.addEdge(Pointer64, 0, *InitialTarget, InitialAddend);
604 return G.addAnonymousSymbol(B, 0, 8, false, false);
605}
606
607/// Create a jump stub block that jumps via the pointer at the given symbol.
608///
609/// The stub block will have the following default values:
610/// alignment: 32-bit
611/// alignment-offset: 0
612/// address: highest allowable: (~11U)
614 Symbol &PointerSymbol) {
615 auto &B = G.createContentBlock(StubSection, PointerJumpStubContent,
616 orc::ExecutorAddr(~uint64_t(11)), 1, 0);
617 B.addEdge(Page21, 0, PointerSymbol, 0);
618 B.addEdge(PageOffset12, 4, PointerSymbol, 0);
619 return B;
620}
621
622/// Create a jump stub that jumps via the pointer at the given symbol and
623/// an anonymous symbol pointing to it. Return the anonymous symbol.
624///
625/// The stub block will be created by createPointerJumpStubBlock.
627 Section &StubSection,
628 Symbol &PointerSymbol) {
629 return G.addAnonymousSymbol(
630 createPointerJumpStubBlock(G, StubSection, PointerSymbol), 0,
631 sizeof(PointerJumpStubContent), true, false);
632}
633
634/// Global Offset Table Builder.
635class GOTTableManager : public TableManager<GOTTableManager> {
636public:
637 static StringRef getSectionName() { return "$__GOT"; }
638
640 Edge::Kind KindToSet = Edge::Invalid;
641 const char *BlockWorkingMem = B->getContent().data();
642 const char *FixupPtr = BlockWorkingMem + E.getOffset();
643
644 switch (E.getKind()) {
647 KindToSet = aarch64::Page21;
648 break;
649 }
652 KindToSet = aarch64::PageOffset12;
653 uint32_t RawInstr = *(const support::ulittle32_t *)FixupPtr;
654 (void)RawInstr;
655 assert(E.getAddend() == 0 &&
656 "GOTPageOffset12/TLVPageOffset12 with non-zero addend");
657 assert((RawInstr & 0xfffffc00) == 0xf9400000 &&
658 "RawInstr isn't a 64-bit LDR immediate");
659 break;
660 }
662 KindToSet = aarch64::Delta32;
663 break;
664 }
665 default:
666 return false;
667 }
668 assert(KindToSet != Edge::Invalid &&
669 "Fell through switch, but no new kind to set");
670 DEBUG_WITH_TYPE("jitlink", {
671 dbgs() << " Fixing " << G.getEdgeKindName(E.getKind()) << " edge at "
672 << B->getFixupAddress(E) << " (" << B->getAddress() << " + "
673 << formatv("{0:x}", E.getOffset()) << ")\n";
674 });
675 E.setKind(KindToSet);
676 E.setTarget(getEntryForTarget(G, E.getTarget()));
677 return true;
678 }
679
681 return createAnonymousPointer(G, getGOTSection(G), &Target);
682 }
683
684private:
685 Section &getGOTSection(LinkGraph &G) {
686 if (!GOTSection)
687 GOTSection = &G.createSection(getSectionName(),
689 return *GOTSection;
690 }
691
692 Section *GOTSection = nullptr;
693};
694
695/// Procedure Linkage Table Builder.
696class PLTTableManager : public TableManager<PLTTableManager> {
697public:
699
700 static StringRef getSectionName() { return "$__STUBS"; }
701
703 if (E.getKind() == aarch64::Branch26PCRel && !E.getTarget().isDefined()) {
704 DEBUG_WITH_TYPE("jitlink", {
705 dbgs() << " Fixing " << G.getEdgeKindName(E.getKind()) << " edge at "
706 << B->getFixupAddress(E) << " (" << B->getAddress() << " + "
707 << formatv("{0:x}", E.getOffset()) << ")\n";
708 });
709 E.setTarget(getEntryForTarget(G, E.getTarget()));
710 return true;
711 }
712 return false;
713 }
714
718 }
719
720public:
722 if (!StubsSection)
723 StubsSection = &G.createSection(getSectionName(),
725 return *StubsSection;
726 }
727
730};
731
732} // namespace aarch64
733} // namespace jitlink
734} // namespace llvm
735
736#endif // LLVM_EXECUTIONENGINE_JITLINK_AARCH64_H
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
#define G(x, y, z)
Definition: MD5.cpp:56
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
static ErrorSuccess success()
Create a success value.
Definition: Error.h:330
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
Represents an address in the executor process.
uint64_t getValue() const
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto formatv(const char *Fmt, Ts &&... Vals) -> formatv_object< decltype(std::make_tuple(detail::build_format_adapter(std::forward< Ts >(Vals))...))>
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163