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39 #define DEBUG_TYPE "mips-reg-info"
56 return &Mips::GPR32RegClass;
59 return &Mips::GPR64RegClass;
105 switch (ConstraintID) {
148 int64_t SPOffset)
const {
164 MinCSFI = CSI[0].getFrameIdx();
165 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
182 FrameReg =
ABI.GetStackPtr();
183 else if (RegInfo->hasStackRealignment(MF)) {
185 FrameReg =
ABI.GetBasePtr();
189 FrameReg =
ABI.GetStackPtr();
203 Offset = SPOffset + (int64_t)StackSize;
204 Offset +=
MI.getOperand(OpNo + 1).getImm();
209 if (!
MI.isDebugValue()) {
213 unsigned OffsetBitSize =
216 if (OffsetBitSize < 16 &&
isInt<16>(Offset) &&
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
245 unsigned Reg =
TII.loadImmediate(Offset,
MBB, II,
DL,
246 OffsetBitSize == 16 ? &NewImm :
nullptr);
251 Offset = SignExtend64<16>(NewImm);
256 MI.getOperand(OpNo).ChangeToRegister(FrameReg,
false,
false, IsKill);
257 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Generic address nodes are lowered to some combination of target independent and machine specific ABI
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual const TargetInstrInfo * getInstrInfo() const
Reg
All possible values of the reg field in the ModR/M byte.
const TargetRegisterClass * intRegClass(unsigned Size) const override
Return GPR register class.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static unsigned getLoadStoreOffsetAlign(const unsigned Opcode)
Get the scale factor applied to the immediate in the given load/store.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
@ INLINEASM
INLINEASM - Represents an inline asm block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Register getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
@ Kill
The last use of a register.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
bool isEhDataRegFI(int FI) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static unsigned getMemoryConstraintID(unsigned Flag)
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const MachineBasicBlock * getParent() const
bool isISRRegFI(int FI) const
Wrapper class representing virtual and physical registers.
bool inMicroMipsMode() const
constexpr bool isInt< 16 >(int64_t x)
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode, MachineOperand MO)
Get the size of the offset supported by the given load/store/inline asm.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool requiresRegisterScavenging(const MachineFunction &MF) const override