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45 assert(Stalls == 0 &&
"ARM hazards don't support scoreboard lookahead");
49 if (!
MI->isDebugInstr()) {
72 (
TII.canCauseFpMLxStall(
MI->getOpcode()) ||
91 if (!
MI->isDebugInstr()) {
98 if (FpMLxStalls && --FpMLxStalls == 0)
129 BaseOp = &
MI.getOperand(1);
134 ?
MI.getOperand(3).getImm()
135 :
MI.getOperand(2).getImm();
141 BaseOp = &
MI.getOperand(1);
142 Offset =
MI.getOperand(2).getImm();
146 BaseOp = &
MI.getOperand(2);
151 ?
MI.getOperand(4).getImm()
152 :
MI.getOperand(3).getImm();
160 BaseOp = &
MI.getOperand(1);
161 Offset =
MI.getOperand(2).isImm() ?
MI.getOperand(2).getImm() : 0;
162 return MI.getOperand(2).isImm();
168 const ScheduleDAG *DAG, int64_t CPUBankMask,
bool CPUAssumeITCMConflict)
169 : MF(DAG->MF),
DL(DAG->MF.getDataLayout()),
174 : CPUAssumeITCMConflict) {
179 ARMBankConflictHazardRecognizer::CheckOffsets(
unsigned O0,
unsigned O1) {
190 auto BaseVal0 = MO0->getValue();
191 auto BasePseudoVal0 = MO0->getPseudoValue();
194 if (MO0->getSize() > 4)
197 bool SPvalid =
false;
199 int64_t SPOffset0 = 0;
201 for (
auto L1 : Accesses) {
202 auto MO1 = *L1->memoperands().begin();
203 auto BaseVal1 = MO1->getValue();
204 auto BasePseudoVal1 = MO1->getPseudoValue();
208 if (BaseVal0 && BaseVal1) {
209 const Value *Ptr0, *Ptr1;
212 if (Ptr0 == Ptr1 && Ptr0)
213 return CheckOffsets(Offset0, Offset1);
216 if (BasePseudoVal0 && BasePseudoVal1 &&
217 BasePseudoVal0->kind() == BasePseudoVal1->kind() &&
220 auto FS0 = cast<FixedStackPseudoSourceValue>(BasePseudoVal0);
221 auto FS1 = cast<FixedStackPseudoSourceValue>(BasePseudoVal1);
224 return CheckOffsets(Offset0, Offset1);
228 if (BasePseudoVal0 && BasePseudoVal1 &&
229 BasePseudoVal0->kind() == BasePseudoVal1->kind() &&
230 BasePseudoVal0->isConstantPool() && AssumeITCMBankConflict)
247 return CheckOffsets(SPOffset0, SPOffset1);
258 if (!
MI.mayLoad() ||
MI.mayStore() ||
MI.getNumMemOperands() != 1)
261 auto MO = *
MI.memoperands().begin();
265 Accesses.push_back(&
MI);
unsigned getOpcode() const
Return the opcode number for this descriptor.
This is an optimization pass for GlobalISel generic memory operations.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
virtual const TargetInstrInfo * getInstrInfo() const
unsigned MaxLookAhead
MaxLookAhead - Indicate the number of cycles in the scoreboard state.
static cl::opt< bool > AssumeITCMConflict("arm-assume-itcm-bankconflict", cl::init(false), cl::Hidden)
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
static cl::opt< int > DataBankMask("arm-data-bank-mask", cl::init(-1), cl::Hidden)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
unsigned const TargetRegisterInfo * TRI
IndexMode
ARM Index Modes.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
const MachineOperand & getOperand(unsigned i) const
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
unsigned getNumMemOperands() const
Return the number of memory operands.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
Register getReg() const
getReg - Returns the register number.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ARMBankConflictHazardRecognizer(const ScheduleDAG *DAG, int64_t DDM, bool ABC)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const MachineBasicBlock * getParent() const
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI)
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
Value * GetPointerBaseWithConstantOffset(Value *Ptr, int64_t &Offset, const DataLayout &DL, bool AllowNonInbounds=true)
Analyze the specified pointer to see if it can be expressed as a base pointer plus a constant offset.
MachineInstrBuilder MachineInstrBuilder & DefMI
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Scheduling unit. This is a node in the scheduling DAG.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
LLVM Value Representation.