LLVM  13.0.0git
RegisterUsageInfo.cpp
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1 //===- RegisterUsageInfo.cpp - Register Usage Information Storage ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This pass is required to take advantage of the interprocedural register
10 /// allocation infrastructure.
11 ///
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/Module.h"
21 #include "llvm/Pass.h"
25 #include <algorithm>
26 #include <cassert>
27 #include <cstdint>
28 #include <utility>
29 #include <vector>
30 
31 using namespace llvm;
32 
34  "print-regusage", cl::init(false), cl::Hidden,
35  cl::desc("print register usage details collected for analysis."));
36 
38  "Register Usage Information Storage", false, true)
39 
41 
42 void PhysicalRegisterUsageInfo::setTargetMachine(const LLVMTargetMachine &TM) {
43  this->TM = &TM;
44 }
45 
47  RegMasks.grow(M.size());
48  return false;
49 }
50 
52  if (DumpRegUsage)
53  print(errs());
54 
55  RegMasks.shrink_and_clear();
56  return false;
57 }
58 
60  const Function &FP, ArrayRef<uint32_t> RegMask) {
61  RegMasks[&FP] = RegMask;
62 }
63 
66  auto It = RegMasks.find(&FP);
67  if (It != RegMasks.end())
68  return makeArrayRef<uint32_t>(It->second);
69  return ArrayRef<uint32_t>();
70 }
71 
73  using FuncPtrRegMaskPair = std::pair<const Function *, std::vector<uint32_t>>;
74 
76 
77  // Create a vector of pointer to RegMasks entries
78  for (const auto &RegMask : RegMasks)
79  FPRMPairVector.push_back(&RegMask);
80 
81  // sort the vector to print analysis in alphabatic order of function name.
82  llvm::sort(
83  FPRMPairVector,
84  [](const FuncPtrRegMaskPair *A, const FuncPtrRegMaskPair *B) -> bool {
85  return A->first->getName() < B->first->getName();
86  });
87 
88  for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
89  OS << FPRMPair->first->getName() << " "
90  << "Clobbered Registers: ";
91  const TargetRegisterInfo *TRI
92  = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
93  .getRegisterInfo();
94 
95  for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
96  if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
97  OS << printReg(PReg, TRI) << " ";
98  }
99  OS << "\n";
100  }
101 }
CmpMode::FP
@ FP
llvm
Definition: AllocatorList.h:23
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::PhysicalRegisterUsageInfo::print
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Definition: RegisterUsageInfo.cpp:72
llvm::Function
Definition: Function.h:61
Pass.h
DumpRegUsage
static cl::opt< bool > DumpRegUsage("print-regusage", cl::init(false), cl::Hidden, cl::desc("print register usage details collected for analysis."))
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
Module.h
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::PhysicalRegisterUsageInfo::getRegUsageInfo
ArrayRef< uint32_t > getRegUsageInfo(const Function &FP)
To query stored RegMask for given Function *, it will returns ane empty array if function is not know...
Definition: RegisterUsageInfo.cpp:65
llvm::PhysicalRegisterUsageInfo::doFinalization
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...
Definition: RegisterUsageInfo.cpp:51
CommandLine.h
TargetMachine.h
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo
void storeUpdateRegUsageInfo(const Function &FP, ArrayRef< uint32_t > RegMask)
To store RegMask for given Function *.
Definition: RegisterUsageInfo.cpp:59
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::cl::opt< bool >
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::PhysicalRegisterUsageInfo
Definition: RegisterUsageInfo.h:34
llvm::ArrayRef< uint32_t >
TargetSubtargetInfo.h
RegisterUsageInfo.h
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
Function.h
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1423
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:385
llvm::PhysicalRegisterUsageInfo::doInitialization
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
Definition: RegisterUsageInfo.cpp:46
SmallVector.h
llvm::TargetMachine::getSubtarget
const STC & getSubtarget(const Function &F) const
This method returns a pointer to the specified type of TargetSubtargetInfo.
Definition: TargetMachine.h:161
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::cl::desc
Definition: CommandLine.h:414
raw_ostream.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
TargetRegisterInfo.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38