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28 #define DEBUG_TYPE "regalloc"
48 assert(
MRI && Indexes &&
"call reset() first");
56 if (!MO.isDef() && !MO.readsReg())
59 unsigned SubReg = MO.getSubReg();
96 SubLIC.
reset(MF, Indexes, DomTree, Alloc);
97 SubLIC.extendToUses(
S,
Reg,
S.LaneMask, &LI);
111 "Expect empty main liverange");
115 for (
const VNInfo *VNI : SR.valnos) {
128 assert(
MRI && Indexes &&
"call reset() first");
145 bool IsSubRange = !
Mask.all();
156 if (!MO.readsReg() || (IsSubRange && MO.isDef()))
159 unsigned SubReg = MO.getSubReg();
165 if ((SLM &
Mask).none())
171 unsigned OpNo = (&MO - &
MI->getOperand(0));
174 assert(!MO.isDef() &&
"Cannot handle PHI def of partial register.");
177 UseIdx = Indexes->
getMBBEndIdx(
MI->getOperand(OpNo + 1).getMBB());
180 bool isEarlyClobber =
false;
184 else if (
MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
187 isEarlyClobber =
MI->getOperand(DefIdx).isEarlyClobber();
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
Reg
All possible values of the reg field in the ModR/M byte.
const TargetRegisterInfo * getTargetRegisterInfo() const
SlotIndex def
The index of the defining instruction.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static VNInfo UndefVNI(0xbad, SlotIndex())
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc, LiveRange &LR, const MachineOperand &MO)
unsigned const TargetRegisterInfo * TRI
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
void createDeadDefs(LiveRange &LR, Register Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
void resetLiveOutMap()
Reset Map and Seen fields.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
MachineOperand class - Representation of each machine instruction operand.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
LiveInterval - This class represents the liveness of a register, or stack slot.
SlotIndex - An opaque wrapper around machine indexes.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const MachineRegisterInfo * getRegInfo() const
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, std::function< void(LiveInterval::SubRange &)> Apply, const SlotIndexes &Indexes, const TargetRegisterInfo &TRI, unsigned ComposeSubRegIdx=0)
Refines the subranges to support LaneMask.
Representation of each machine instruction.
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
This class represents the liveness of a register, stack slot, etc.
Allocate memory in an ever growing pool, as if by bump-pointer.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isEarlyClobber() const
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
SlotIndexes * getIndexes()
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
const MachineFunction * getMachineFunction()
Some getters to expose in a read-only way some private fields to subclasses.
A live range for subregisters.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
iterator_range< def_iterator > def_operands(Register Reg) const
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
VNInfo - Value Number Information.
VNInfo::Allocator * getVNAlloc()
MachineDominatorTree * getDomTree()
bool hasSubRanges() const
Returns true if subregister liveness information is available.
void reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA)
reset - Prepare caches for a new set of non-overlapping live ranges.
bool isUnused() const
Returns true if this value is unused.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
static constexpr LaneBitmask getAll()
SubRange * createSubRangeFrom(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, const LiveRange &CopyFrom)
Like createSubRange() but the new range is filled with a copy of the liveness information in CopyFrom...
iterator_range< subrange_iterator > subranges()