LLVM  14.0.0git
X86OptimizeLEAs.cpp
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1 //===- X86OptimizeLEAs.cpp - optimize usage of LEA instructions -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the pass that performs some optimizations with LEA
10 // instructions in order to improve performance and code size.
11 // Currently, it does two things:
12 // 1) If there are two LEA instructions calculating addresses which only differ
13 // by displacement inside a basic block, one of them is removed.
14 // 2) Address calculations in load and store instructions are replaced by
15 // existing LEA def registers where possible.
16 //
17 //===----------------------------------------------------------------------===//
18 
20 #include "X86.h"
21 #include "X86InstrInfo.h"
22 #include "X86Subtarget.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/DenseMapInfo.h"
25 #include "llvm/ADT/Hashing.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Statistic.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/MC/MCInstrDesc.h"
45 #include "llvm/Support/Debug.h"
49 #include <cassert>
50 #include <cstdint>
51 #include <iterator>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "x86-optimize-LEAs"
56 
57 static cl::opt<bool>
58  DisableX86LEAOpt("disable-x86-lea-opt", cl::Hidden,
59  cl::desc("X86: Disable LEA optimizations."),
60  cl::init(false));
61 
62 STATISTIC(NumSubstLEAs, "Number of LEA instruction substitutions");
63 STATISTIC(NumRedundantLEAs, "Number of redundant LEA instructions removed");
64 
65 /// Returns true if two machine operands are identical and they are not
66 /// physical registers.
67 static inline bool isIdenticalOp(const MachineOperand &MO1,
68  const MachineOperand &MO2);
69 
70 /// Returns true if two address displacement operands are of the same
71 /// type and use the same symbol/index/address regardless of the offset.
72 static bool isSimilarDispOp(const MachineOperand &MO1,
73  const MachineOperand &MO2);
74 
75 /// Returns true if the instruction is LEA.
76 static inline bool isLEA(const MachineInstr &MI);
77 
78 namespace {
79 
80 /// A key based on instruction's memory operands.
81 class MemOpKey {
82 public:
83  MemOpKey(const MachineOperand *Base, const MachineOperand *Scale,
84  const MachineOperand *Index, const MachineOperand *Segment,
85  const MachineOperand *Disp)
86  : Disp(Disp) {
87  Operands[0] = Base;
88  Operands[1] = Scale;
89  Operands[2] = Index;
90  Operands[3] = Segment;
91  }
92 
93  bool operator==(const MemOpKey &Other) const {
94  // Addresses' bases, scales, indices and segments must be identical.
95  for (int i = 0; i < 4; ++i)
96  if (!isIdenticalOp(*Operands[i], *Other.Operands[i]))
97  return false;
98 
99  // Addresses' displacements don't have to be exactly the same. It only
100  // matters that they use the same symbol/index/address. Immediates' or
101  // offsets' differences will be taken care of during instruction
102  // substitution.
103  return isSimilarDispOp(*Disp, *Other.Disp);
104  }
105 
106  // Address' base, scale, index and segment operands.
107  const MachineOperand *Operands[4];
108 
109  // Address' displacement operand.
110  const MachineOperand *Disp;
111 };
112 
113 } // end anonymous namespace
114 
115 namespace llvm {
116 
117 /// Provide DenseMapInfo for MemOpKey.
118 template <> struct DenseMapInfo<MemOpKey> {
120 
121  static inline MemOpKey getEmptyKey() {
122  return MemOpKey(PtrInfo::getEmptyKey(), PtrInfo::getEmptyKey(),
123  PtrInfo::getEmptyKey(), PtrInfo::getEmptyKey(),
124  PtrInfo::getEmptyKey());
125  }
126 
127  static inline MemOpKey getTombstoneKey() {
128  return MemOpKey(PtrInfo::getTombstoneKey(), PtrInfo::getTombstoneKey(),
129  PtrInfo::getTombstoneKey(), PtrInfo::getTombstoneKey(),
130  PtrInfo::getTombstoneKey());
131  }
132 
133  static unsigned getHashValue(const MemOpKey &Val) {
134  // Checking any field of MemOpKey is enough to determine if the key is
135  // empty or tombstone.
136  assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key");
137  assert(Val.Disp != PtrInfo::getTombstoneKey() &&
138  "Cannot hash the tombstone key");
139 
140  hash_code Hash = hash_combine(*Val.Operands[0], *Val.Operands[1],
141  *Val.Operands[2], *Val.Operands[3]);
142 
143  // If the address displacement is an immediate, it should not affect the
144  // hash so that memory operands which differ only be immediate displacement
145  // would have the same hash. If the address displacement is something else,
146  // we should reflect symbol/index/address in the hash.
147  switch (Val.Disp->getType()) {
149  break;
152  Hash = hash_combine(Hash, Val.Disp->getIndex());
153  break;
155  Hash = hash_combine(Hash, Val.Disp->getSymbolName());
156  break;
158  Hash = hash_combine(Hash, Val.Disp->getGlobal());
159  break;
161  Hash = hash_combine(Hash, Val.Disp->getBlockAddress());
162  break;
164  Hash = hash_combine(Hash, Val.Disp->getMCSymbol());
165  break;
167  Hash = hash_combine(Hash, Val.Disp->getMBB());
168  break;
169  default:
170  llvm_unreachable("Invalid address displacement operand");
171  }
172 
173  return (unsigned)Hash;
174  }
175 
176  static bool isEqual(const MemOpKey &LHS, const MemOpKey &RHS) {
177  // Checking any field of MemOpKey is enough to determine if the key is
178  // empty or tombstone.
179  if (RHS.Disp == PtrInfo::getEmptyKey())
180  return LHS.Disp == PtrInfo::getEmptyKey();
181  if (RHS.Disp == PtrInfo::getTombstoneKey())
182  return LHS.Disp == PtrInfo::getTombstoneKey();
183  return LHS == RHS;
184  }
185 };
186 
187 } // end namespace llvm
188 
189 /// Returns a hash table key based on memory operands of \p MI. The
190 /// number of the first memory operand of \p MI is specified through \p N.
191 static inline MemOpKey getMemOpKey(const MachineInstr &MI, unsigned N) {
192  assert((isLEA(MI) || MI.mayLoadOrStore()) &&
193  "The instruction must be a LEA, a load or a store");
194  return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg),
195  &MI.getOperand(N + X86::AddrScaleAmt),
196  &MI.getOperand(N + X86::AddrIndexReg),
197  &MI.getOperand(N + X86::AddrSegmentReg),
198  &MI.getOperand(N + X86::AddrDisp));
199 }
200 
201 static inline bool isIdenticalOp(const MachineOperand &MO1,
202  const MachineOperand &MO2) {
203  return MO1.isIdenticalTo(MO2) &&
204  (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg()));
205 }
206 
207 #ifndef NDEBUG
208 static bool isValidDispOp(const MachineOperand &MO) {
209  return MO.isImm() || MO.isCPI() || MO.isJTI() || MO.isSymbol() ||
210  MO.isGlobal() || MO.isBlockAddress() || MO.isMCSymbol() || MO.isMBB();
211 }
212 #endif
213 
214 static bool isSimilarDispOp(const MachineOperand &MO1,
215  const MachineOperand &MO2) {
216  assert(isValidDispOp(MO1) && isValidDispOp(MO2) &&
217  "Address displacement operand is not valid");
218  return (MO1.isImm() && MO2.isImm()) ||
219  (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) ||
220  (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) ||
221  (MO1.isSymbol() && MO2.isSymbol() &&
222  MO1.getSymbolName() == MO2.getSymbolName()) ||
223  (MO1.isGlobal() && MO2.isGlobal() &&
224  MO1.getGlobal() == MO2.getGlobal()) ||
225  (MO1.isBlockAddress() && MO2.isBlockAddress() &&
226  MO1.getBlockAddress() == MO2.getBlockAddress()) ||
227  (MO1.isMCSymbol() && MO2.isMCSymbol() &&
228  MO1.getMCSymbol() == MO2.getMCSymbol()) ||
229  (MO1.isMBB() && MO2.isMBB() && MO1.getMBB() == MO2.getMBB());
230 }
231 
232 static inline bool isLEA(const MachineInstr &MI) {
233  unsigned Opcode = MI.getOpcode();
234  return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
235  Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
236 }
237 
238 namespace {
239 
240 class X86OptimizeLEAPass : public MachineFunctionPass {
241 public:
242  X86OptimizeLEAPass() : MachineFunctionPass(ID) {}
243 
244  StringRef getPassName() const override { return "X86 LEA Optimize"; }
245 
246  /// Loop over all of the basic blocks, replacing address
247  /// calculations in load and store instructions, if it's already
248  /// been calculated by LEA. Also, remove redundant LEAs.
249  bool runOnMachineFunction(MachineFunction &MF) override;
250 
251  static char ID;
252 
253  void getAnalysisUsage(AnalysisUsage &AU) const override {
257  }
258 
259 private:
261 
262  /// Returns a distance between two instructions inside one basic block.
263  /// Negative result means, that instructions occur in reverse order.
264  int calcInstrDist(const MachineInstr &First, const MachineInstr &Last);
265 
266  /// Choose the best \p LEA instruction from the \p List to replace
267  /// address calculation in \p MI instruction. Return the address displacement
268  /// and the distance between \p MI and the chosen \p BestLEA in
269  /// \p AddrDispShift and \p Dist.
270  bool chooseBestLEA(const SmallVectorImpl<MachineInstr *> &List,
271  const MachineInstr &MI, MachineInstr *&BestLEA,
272  int64_t &AddrDispShift, int &Dist);
273 
274  /// Returns the difference between addresses' displacements of \p MI1
275  /// and \p MI2. The numbers of the first memory operands for the instructions
276  /// are specified through \p N1 and \p N2.
277  int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
278  const MachineInstr &MI2, unsigned N2) const;
279 
280  /// Returns true if the \p Last LEA instruction can be replaced by the
281  /// \p First. The difference between displacements of the addresses calculated
282  /// by these LEAs is returned in \p AddrDispShift. It'll be used for proper
283  /// replacement of the \p Last LEA's uses with the \p First's def register.
284  bool isReplaceable(const MachineInstr &First, const MachineInstr &Last,
285  int64_t &AddrDispShift) const;
286 
287  /// Find all LEA instructions in the basic block. Also, assign position
288  /// numbers to all instructions in the basic block to speed up calculation of
289  /// distance between them.
290  void findLEAs(const MachineBasicBlock &MBB, MemOpMap &LEAs);
291 
292  /// Removes redundant address calculations.
293  bool removeRedundantAddrCalc(MemOpMap &LEAs);
294 
295  /// Replace debug value MI with a new debug value instruction using register
296  /// VReg with an appropriate offset and DIExpression to incorporate the
297  /// address displacement AddrDispShift. Return new debug value instruction.
298  MachineInstr *replaceDebugValue(MachineInstr &MI, unsigned OldReg,
299  unsigned NewReg, int64_t AddrDispShift);
300 
301  /// Removes LEAs which calculate similar addresses.
302  bool removeRedundantLEAs(MemOpMap &LEAs);
303 
305 
306  MachineRegisterInfo *MRI = nullptr;
307  const X86InstrInfo *TII = nullptr;
308  const X86RegisterInfo *TRI = nullptr;
309 };
310 
311 } // end anonymous namespace
312 
313 char X86OptimizeLEAPass::ID = 0;
314 
315 FunctionPass *llvm::createX86OptimizeLEAs() { return new X86OptimizeLEAPass(); }
316 INITIALIZE_PASS(X86OptimizeLEAPass, DEBUG_TYPE, "X86 optimize LEA pass", false,
317  false)
318 
319 int X86OptimizeLEAPass::calcInstrDist(const MachineInstr &First,
320  const MachineInstr &Last) {
321  // Both instructions must be in the same basic block and they must be
322  // presented in InstrPos.
323  assert(Last.getParent() == First.getParent() &&
324  "Instructions are in different basic blocks");
325  assert(InstrPos.find(&First) != InstrPos.end() &&
326  InstrPos.find(&Last) != InstrPos.end() &&
327  "Instructions' positions are undefined");
328 
329  return InstrPos[&Last] - InstrPos[&First];
330 }
331 
332 // Find the best LEA instruction in the List to replace address recalculation in
333 // MI. Such LEA must meet these requirements:
334 // 1) The address calculated by the LEA differs only by the displacement from
335 // the address used in MI.
336 // 2) The register class of the definition of the LEA is compatible with the
337 // register class of the address base register of MI.
338 // 3) Displacement of the new memory operand should fit in 1 byte if possible.
339 // 4) The LEA should be as close to MI as possible, and prior to it if
340 // possible.
341 bool X86OptimizeLEAPass::chooseBestLEA(
342  const SmallVectorImpl<MachineInstr *> &List, const MachineInstr &MI,
343  MachineInstr *&BestLEA, int64_t &AddrDispShift, int &Dist) {
344  const MachineFunction *MF = MI.getParent()->getParent();
345  const MCInstrDesc &Desc = MI.getDesc();
346  int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags) +
347  X86II::getOperandBias(Desc);
348 
349  BestLEA = nullptr;
350 
351  // Loop over all LEA instructions.
352  for (auto DefMI : List) {
353  // Get new address displacement.
354  int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1);
355 
356  // Make sure address displacement fits 4 bytes.
357  if (!isInt<32>(AddrDispShiftTemp))
358  continue;
359 
360  // Check that LEA def register can be used as MI address base. Some
361  // instructions can use a limited set of registers as address base, for
362  // example MOV8mr_NOREX. We could constrain the register class of the LEA
363  // def to suit MI, however since this case is very rare and hard to
364  // reproduce in a test it's just more reliable to skip the LEA.
365  if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=
367  continue;
368 
369  // Choose the closest LEA instruction from the list, prior to MI if
370  // possible. Note that we took into account resulting address displacement
371  // as well. Also note that the list is sorted by the order in which the LEAs
372  // occur, so the break condition is pretty simple.
373  int DistTemp = calcInstrDist(*DefMI, MI);
374  assert(DistTemp != 0 &&
375  "The distance between two different instructions cannot be zero");
376  if (DistTemp > 0 || BestLEA == nullptr) {
377  // Do not update return LEA, if the current one provides a displacement
378  // which fits in 1 byte, while the new candidate does not.
379  if (BestLEA != nullptr && !isInt<8>(AddrDispShiftTemp) &&
380  isInt<8>(AddrDispShift))
381  continue;
382 
383  BestLEA = DefMI;
384  AddrDispShift = AddrDispShiftTemp;
385  Dist = DistTemp;
386  }
387 
388  // FIXME: Maybe we should not always stop at the first LEA after MI.
389  if (DistTemp < 0)
390  break;
391  }
392 
393  return BestLEA != nullptr;
394 }
395 
396 // Get the difference between the addresses' displacements of the two
397 // instructions \p MI1 and \p MI2. The numbers of the first memory operands are
398 // passed through \p N1 and \p N2.
399 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1,
400  unsigned N1,
401  const MachineInstr &MI2,
402  unsigned N2) const {
403  const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp);
404  const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp);
405 
406  assert(isSimilarDispOp(Op1, Op2) &&
407  "Address displacement operands are not compatible");
408 
409  // After the assert above we can be sure that both operands are of the same
410  // valid type and use the same symbol/index/address, thus displacement shift
411  // calculation is rather simple.
412  if (Op1.isJTI())
413  return 0;
414  return Op1.isImm() ? Op1.getImm() - Op2.getImm()
415  : Op1.getOffset() - Op2.getOffset();
416 }
417 
418 // Check that the Last LEA can be replaced by the First LEA. To be so,
419 // these requirements must be met:
420 // 1) Addresses calculated by LEAs differ only by displacement.
421 // 2) Def registers of LEAs belong to the same class.
422 // 3) All uses of the Last LEA def register are replaceable, thus the
423 // register is used only as address base.
424 bool X86OptimizeLEAPass::isReplaceable(const MachineInstr &First,
425  const MachineInstr &Last,
426  int64_t &AddrDispShift) const {
427  assert(isLEA(First) && isLEA(Last) &&
428  "The function works only with LEA instructions");
429 
430  // Make sure that LEA def registers belong to the same class. There may be
431  // instructions (like MOV8mr_NOREX) which allow a limited set of registers to
432  // be used as their operands, so we must be sure that replacing one LEA
433  // with another won't lead to putting a wrong register in the instruction.
434  if (MRI->getRegClass(First.getOperand(0).getReg()) !=
435  MRI->getRegClass(Last.getOperand(0).getReg()))
436  return false;
437 
438  // Get new address displacement.
439  AddrDispShift = getAddrDispShift(Last, 1, First, 1);
440 
441  // Loop over all uses of the Last LEA to check that its def register is
442  // used only as address base for memory accesses. If so, it can be
443  // replaced, otherwise - no.
444  for (auto &MO : MRI->use_nodbg_operands(Last.getOperand(0).getReg())) {
445  MachineInstr &MI = *MO.getParent();
446 
447  // Get the number of the first memory operand.
448  const MCInstrDesc &Desc = MI.getDesc();
449  int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags);
450 
451  // If the use instruction has no memory operand - the LEA is not
452  // replaceable.
453  if (MemOpNo < 0)
454  return false;
455 
456  MemOpNo += X86II::getOperandBias(Desc);
457 
458  // If the address base of the use instruction is not the LEA def register -
459  // the LEA is not replaceable.
460  if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO))
461  return false;
462 
463  // If the LEA def register is used as any other operand of the use
464  // instruction - the LEA is not replaceable.
465  for (unsigned i = 0; i < MI.getNumOperands(); i++)
466  if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) &&
467  isIdenticalOp(MI.getOperand(i), MO))
468  return false;
469 
470  // Check that the new address displacement will fit 4 bytes.
471  if (MI.getOperand(MemOpNo + X86::AddrDisp).isImm() &&
472  !isInt<32>(MI.getOperand(MemOpNo + X86::AddrDisp).getImm() +
473  AddrDispShift))
474  return false;
475  }
476 
477  return true;
478 }
479 
480 void X86OptimizeLEAPass::findLEAs(const MachineBasicBlock &MBB,
481  MemOpMap &LEAs) {
482  unsigned Pos = 0;
483  for (auto &MI : MBB) {
484  // Assign the position number to the instruction. Note that we are going to
485  // move some instructions during the optimization however there will never
486  // be a need to move two instructions before any selected instruction. So to
487  // avoid multiple positions' updates during moves we just increase position
488  // counter by two leaving a free space for instructions which will be moved.
489  InstrPos[&MI] = Pos += 2;
490 
491  if (isLEA(MI))
492  LEAs[getMemOpKey(MI, 1)].push_back(const_cast<MachineInstr *>(&MI));
493  }
494 }
495 
496 // Try to find load and store instructions which recalculate addresses already
497 // calculated by some LEA and replace their memory operands with its def
498 // register.
499 bool X86OptimizeLEAPass::removeRedundantAddrCalc(MemOpMap &LEAs) {
500  bool Changed = false;
501 
502  assert(!LEAs.empty());
503  MachineBasicBlock *MBB = (*LEAs.begin()->second.begin())->getParent();
504 
505  // Process all instructions in basic block.
507  // Instruction must be load or store.
508  if (!MI.mayLoadOrStore())
509  continue;
510 
511  // Get the number of the first memory operand.
512  const MCInstrDesc &Desc = MI.getDesc();
513  int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags);
514 
515  // If instruction has no memory operand - skip it.
516  if (MemOpNo < 0)
517  continue;
518 
519  MemOpNo += X86II::getOperandBias(Desc);
520 
521  // Do not call chooseBestLEA if there was no matching LEA
522  auto Insns = LEAs.find(getMemOpKey(MI, MemOpNo));
523  if (Insns == LEAs.end())
524  continue;
525 
526  // Get the best LEA instruction to replace address calculation.
528  int64_t AddrDispShift;
529  int Dist;
530  if (!chooseBestLEA(Insns->second, MI, DefMI, AddrDispShift, Dist))
531  continue;
532 
533  // If LEA occurs before current instruction, we can freely replace
534  // the instruction. If LEA occurs after, we can lift LEA above the
535  // instruction and this way to be able to replace it. Since LEA and the
536  // instruction have similar memory operands (thus, the same def
537  // instructions for these operands), we can always do that, without
538  // worries of using registers before their defs.
539  if (Dist < 0) {
542  InstrPos[DefMI] = InstrPos[&MI] - 1;
543 
544  // Make sure the instructions' position numbers are sane.
545  assert(((InstrPos[DefMI] == 1 &&
547  InstrPos[DefMI] >
548  InstrPos[&*std::prev(MachineBasicBlock::iterator(DefMI))]) &&
549  "Instruction positioning is broken");
550  }
551 
552  // Since we can possibly extend register lifetime, clear kill flags.
554 
555  ++NumSubstLEAs;
556  LLVM_DEBUG(dbgs() << "OptimizeLEAs: Candidate to replace: "; MI.dump(););
557 
558  // Change instruction operands.
559  MI.getOperand(MemOpNo + X86::AddrBaseReg)
560  .ChangeToRegister(DefMI->getOperand(0).getReg(), false);
561  MI.getOperand(MemOpNo + X86::AddrScaleAmt).ChangeToImmediate(1);
562  MI.getOperand(MemOpNo + X86::AddrIndexReg)
563  .ChangeToRegister(X86::NoRegister, false);
564  MI.getOperand(MemOpNo + X86::AddrDisp).ChangeToImmediate(AddrDispShift);
565  MI.getOperand(MemOpNo + X86::AddrSegmentReg)
566  .ChangeToRegister(X86::NoRegister, false);
567 
568  LLVM_DEBUG(dbgs() << "OptimizeLEAs: Replaced by: "; MI.dump(););
569 
570  Changed = true;
571  }
572 
573  return Changed;
574 }
575 
576 MachineInstr *X86OptimizeLEAPass::replaceDebugValue(MachineInstr &MI,
577  unsigned OldReg,
578  unsigned NewReg,
579  int64_t AddrDispShift) {
580  const DIExpression *Expr = MI.getDebugExpression();
581  if (AddrDispShift != 0) {
582  if (MI.isNonListDebugValue()) {
583  Expr =
584  DIExpression::prepend(Expr, DIExpression::StackValue, AddrDispShift);
585  } else {
586  // Update the Expression, appending an offset of `AddrDispShift` to the
587  // Op corresponding to `OldReg`.
589  DIExpression::appendOffset(Ops, AddrDispShift);
590  for (MachineOperand &Op : MI.getDebugOperandsForReg(OldReg)) {
591  unsigned OpIdx = MI.getDebugOperandIndex(&Op);
592  Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
593  }
594  }
595  }
596 
597  // Replace DBG_VALUE instruction with modified version.
598  MachineBasicBlock *MBB = MI.getParent();
599  DebugLoc DL = MI.getDebugLoc();
600  bool IsIndirect = MI.isIndirectDebugValue();
601  const MDNode *Var = MI.getDebugVariable();
602  unsigned Opcode = MI.isNonListDebugValue() ? TargetOpcode::DBG_VALUE
603  : TargetOpcode::DBG_VALUE_LIST;
604  if (IsIndirect)
605  assert(MI.getDebugOffset().getImm() == 0 &&
606  "DBG_VALUE with nonzero offset");
608  // If we encounter an operand using the old register, replace it with an
609  // operand that uses the new register; otherwise keep the old operand.
610  auto replaceOldReg = [OldReg, NewReg](const MachineOperand &Op) {
611  if (Op.isReg() && Op.getReg() == OldReg)
612  return MachineOperand::CreateReg(NewReg, false, false, false, false,
613  false, false, false, false, 0,
614  /*IsRenamable*/ true);
615  return Op;
616  };
617  for (const MachineOperand &Op : MI.debug_operands())
618  NewOps.push_back(replaceOldReg(Op));
619  return BuildMI(*MBB, MBB->erase(&MI), DL, TII->get(Opcode), IsIndirect,
620  NewOps, Var, Expr);
621 }
622 
623 // Try to find similar LEAs in the list and replace one with another.
624 bool X86OptimizeLEAPass::removeRedundantLEAs(MemOpMap &LEAs) {
625  bool Changed = false;
626 
627  // Loop over all entries in the table.
628  for (auto &E : LEAs) {
629  auto &List = E.second;
630 
631  // Loop over all LEA pairs.
632  auto I1 = List.begin();
633  while (I1 != List.end()) {
634  MachineInstr &First = **I1;
635  auto I2 = std::next(I1);
636  while (I2 != List.end()) {
637  MachineInstr &Last = **I2;
638  int64_t AddrDispShift;
639 
640  // LEAs should be in occurrence order in the list, so we can freely
641  // replace later LEAs with earlier ones.
642  assert(calcInstrDist(First, Last) > 0 &&
643  "LEAs must be in occurrence order in the list");
644 
645  // Check that the Last LEA instruction can be replaced by the First.
646  if (!isReplaceable(First, Last, AddrDispShift)) {
647  ++I2;
648  continue;
649  }
650 
651  // Loop over all uses of the Last LEA and update their operands. Note
652  // that the correctness of this has already been checked in the
653  // isReplaceable function.
654  Register FirstVReg = First.getOperand(0).getReg();
655  Register LastVReg = Last.getOperand(0).getReg();
656  for (MachineOperand &MO :
658  MachineInstr &MI = *MO.getParent();
659 
660  if (MI.isDebugValue()) {
661  // Replace DBG_VALUE instruction with modified version using the
662  // register from the replacing LEA and the address displacement
663  // between the LEA instructions.
664  replaceDebugValue(MI, LastVReg, FirstVReg, AddrDispShift);
665  continue;
666  }
667 
668  // Get the number of the first memory operand.
669  const MCInstrDesc &Desc = MI.getDesc();
670  int MemOpNo =
672  X86II::getOperandBias(Desc);
673 
674  // Update address base.
675  MO.setReg(FirstVReg);
676 
677  // Update address disp.
678  MachineOperand &Op = MI.getOperand(MemOpNo + X86::AddrDisp);
679  if (Op.isImm())
680  Op.setImm(Op.getImm() + AddrDispShift);
681  else if (!Op.isJTI())
682  Op.setOffset(Op.getOffset() + AddrDispShift);
683  }
684 
685  // Since we can possibly extend register lifetime, clear kill flags.
686  MRI->clearKillFlags(FirstVReg);
687 
688  ++NumRedundantLEAs;
689  LLVM_DEBUG(dbgs() << "OptimizeLEAs: Remove redundant LEA: ";
690  Last.dump(););
691 
692  // By this moment, all of the Last LEA's uses must be replaced. So we
693  // can freely remove it.
694  assert(MRI->use_empty(LastVReg) &&
695  "The LEA's def register must have no uses");
696  Last.eraseFromParent();
697 
698  // Erase removed LEA from the list.
699  I2 = List.erase(I2);
700 
701  Changed = true;
702  }
703  ++I1;
704  }
705  }
706 
707  return Changed;
708 }
709 
710 bool X86OptimizeLEAPass::runOnMachineFunction(MachineFunction &MF) {
711  bool Changed = false;
712 
713  if (DisableX86LEAOpt || skipFunction(MF.getFunction()))
714  return false;
715 
716  MRI = &MF.getRegInfo();
717  TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
718  TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
719  auto *PSI =
720  &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
721  auto *MBFI = (PSI && PSI->hasProfileSummary()) ?
722  &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
723  nullptr;
724 
725  // Process all basic blocks.
726  for (auto &MBB : MF) {
727  MemOpMap LEAs;
728  InstrPos.clear();
729 
730  // Find all LEA instructions in basic block.
731  findLEAs(MBB, LEAs);
732 
733  // If current basic block has no LEAs, move on to the next one.
734  if (LEAs.empty())
735  continue;
736 
737  // Remove redundant LEA instructions.
738  Changed |= removeRedundantLEAs(LEAs);
739 
740  // Remove redundant address calculations. Do it only for -Os/-Oz since only
741  // a code size gain is expected from this part of the pass.
742  bool OptForSize = MF.getFunction().hasOptSize() ||
743  llvm::shouldOptimizeForSize(&MBB, PSI, MBFI);
744  if (OptForSize)
745  Changed |= removeRedundantAddrCalc(LEAs);
746  }
747 
748  return Changed;
749 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1305
i
i
Definition: README.txt:29
llvm::DenseMapInfo< MemOpKey >::getEmptyKey
static MemOpKey getEmptyKey()
Definition: X86OptimizeLEAs.cpp:121
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::X86II::getMemoryOperandNo
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
Definition: X86BaseInfo.h:1095
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:343
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
X86Subtarget.h
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Statistic.h
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:568
llvm::X86Subtarget
Definition: X86Subtarget.h:52
ErrorHandling.h
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineSizeOpts.h
MachineBasicBlock.h
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:341
llvm::MachineOperand::isJTI
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:337
llvm::MachineOperand::isMCSymbol
bool isMCSymbol() const
Definition: MachineOperand.h:350
DenseMap.h
llvm::MachineRegisterInfo::use_operands
iterator_range< use_iterator > use_operands(Register Reg) const
Definition: MachineRegisterInfo.h:469
Hashing.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:573
MachineRegisterInfo.h
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1301
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
isSimilarDispOp
static bool isSimilarDispOp(const MachineOperand &MO1, const MachineOperand &MO2)
Returns true if two address displacement operands are of the same type and use the same symbol/index/...
Definition: X86OptimizeLEAs.cpp:214
llvm::DenseMapInfo< MemOpKey >::getTombstoneKey
static MemOpKey getTombstoneKey()
Definition: X86OptimizeLEAs.cpp:127
CommandLine.h
llvm::DenseMapInfo
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: APInt.h:34
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1321
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
X86.h
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:526
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86OptimizeLEAs.cpp:55
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::X86::AddrScaleAmt
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
isLEA
static bool isLEA(const MachineInstr &MI)
Returns true if the instruction is LEA.
Definition: X86OptimizeLEAs.cpp:232
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:670
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:329
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
DebugLoc.h
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::isInt< 8 >
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:429
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::cl::opt< bool >
LazyMachineBlockFrequencyInfo.h
===- LazyMachineBlockFrequencyInfo.h - Lazy Block Frequency -*- C++ -*–===//
llvm::X86::AddrBaseReg
@ AddrBaseReg
Definition: X86BaseInfo.h:32
llvm::X86II::getOperandBias
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:1055
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
ProfileSummaryInfo.h
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::DIExpression::StackValue
@ StackValue
Definition: DebugInfoMetadata.h:2806
llvm::X86::AddrIndexReg
@ AddrIndexReg
Definition: X86BaseInfo.h:34
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:593
llvm::ProfileSummaryInfoWrapperPass
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
Definition: ProfileSummaryInfo.h:193
llvm::MachineOperand::isCPI
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
Definition: MachineOperand.h:333
MachineFunctionPass.h
getMemOpKey
static MemOpKey getMemOpKey(const MachineInstr &MI, unsigned N)
Returns a hash table key based on memory operands of MI.
Definition: X86OptimizeLEAs.cpp:191
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::IndexedInstrProf::HashT::Last
@ Last
llvm::operator==
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1979
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
INITIALIZE_PASS
INITIALIZE_PASS(X86OptimizeLEAPass, DEBUG_TYPE, "X86 optimize LEA pass", false, false) int X86OptimizeLEAPass
Definition: X86OptimizeLEAs.cpp:316
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::LazyMachineBlockFrequencyInfoPass
This is an alternative analysis pass to MachineBlockFrequencyInfo.
Definition: LazyMachineBlockFrequencyInfo.h:37
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::X86::AddrSegmentReg
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:870
isIdenticalOp
static bool isIdenticalOp(const MachineOperand &MO1, const MachineOperand &MO2)
Returns true if two machine operands are identical and they are not physical registers.
Definition: X86OptimizeLEAs.cpp:201
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:131
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
isValidDispOp
static bool isValidDispOp(const MachineOperand &MO)
Definition: X86OptimizeLEAs.cpp:208
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DenseMapInfo< MemOpKey >::getHashValue
static unsigned getHashValue(const MemOpKey &Val)
Definition: X86OptimizeLEAs.cpp:133
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1237
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::DenseMapInfo< MemOpKey >::isEqual
static bool isEqual(const MemOpKey &LHS, const MemOpKey &RHS)
Definition: X86OptimizeLEAs.cpp:176
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1314
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
Function.h
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
X86BaseInfo.h
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
DisableX86LEAOpt
static cl::opt< bool > DisableX86LEAOpt("disable-x86-lea-opt", cl::Hidden, cl::desc("X86: Disable LEA optimizations."), cl::init(false))
MachineInstrBuilder.h
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:605
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:608
List
const NodeList & List
Definition: RDFGraph.cpp:201
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::SmallVectorImpl< MachineInstr * >
MachineOperand.h
DenseMapInfo.h
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::createX86OptimizeLEAs
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
Definition: X86OptimizeLEAs.cpp:315
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
MachineFunction.h
X86InstrInfo.h
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegisterInfo.h
Debug.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1195
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:287
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:339
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:73
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58