LLVM  15.0.0git
X86FastTileConfig.cpp
Go to the documentation of this file.
1 //===-- X86FastTileConfig.cpp - Fast Tile Register Configure---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Pass to config the shape of AMX physical registers
10 /// AMX register need to be configured before use. Before FastRegAllocation pass
11 /// the ldtilecfg instruction is inserted, however at that time we don't
12 /// know the shape of each physical tile registers, because the register
13 /// allocation is not done yet. This pass runs after register allocation
14 /// pass. It collects the shape information of each physical tile register
15 /// and store the shape in the stack slot that is allocated for load config
16 /// to tile config register.
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #include "X86.h"
21 #include "X86InstrBuilder.h"
22 #include "X86MachineFunctionInfo.h"
23 #include "X86RegisterInfo.h"
24 #include "X86Subtarget.h"
29 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/InitializePasses.h"
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "fasttileconfig"
37 
38 namespace {
39 
40 class X86FastTileConfig : public MachineFunctionPass {
41  // context
42  MachineFunction *MF = nullptr;
43  const TargetInstrInfo *TII = nullptr;
44  MachineRegisterInfo *MRI = nullptr;
45  const TargetRegisterInfo *TRI = nullptr;
46  X86MachineFunctionInfo *X86FI = nullptr;
47 
48  bool configBasicBlock(MachineBasicBlock &MBB);
49 
50 public:
51  X86FastTileConfig() : MachineFunctionPass(ID) {}
52 
53  /// Return the pass name.
54  StringRef getPassName() const override {
55  return "Fast Tile Register Configure";
56  }
57 
58  void getAnalysisUsage(AnalysisUsage &AU) const override {
59  AU.setPreservesAll();
61  }
62 
63  /// Perform register allocation.
64  bool runOnMachineFunction(MachineFunction &MFunc) override;
65 
66  MachineFunctionProperties getRequiredProperties() const override {
69  }
70 
71  static char ID;
72 };
73 
74 } // end anonymous namespace
75 
76 char X86FastTileConfig::ID = 0;
77 
78 INITIALIZE_PASS_BEGIN(X86FastTileConfig, DEBUG_TYPE,
79  "Fast Tile Register Configure", false, false)
80 INITIALIZE_PASS_END(X86FastTileConfig, DEBUG_TYPE,
81  "Fast Tile Register Configure", false, false)
82 
84  // There is no phi instruction after register allocation.
85  assert(MI.isPHI() == false);
86  // The instruction must have 3 operands: tile def, row, col.
87  // It should be AMX pseudo instruction that have shape operand.
88  if (MI.isDebugInstr() || MI.isCopy() || MI.getNumOperands() < 3 ||
89  !MI.isPseudo())
90  return false;
91  MachineOperand &MO = MI.getOperand(0);
92 
93  if (MO.isReg()) {
94  Register Reg = MO.getReg();
95  // FIXME it may be used after Greedy RA and the physical
96  // register is not rewritten yet.
97  if (Reg.isVirtual() &&
98  MRI->getRegClass(Reg)->getID() == X86::TILERegClassID)
99  return true;
100  if (Reg >= X86::TMM0 && Reg <= X86::TMM7)
101  return true;
102  }
103 
104  return false;
105 }
106 
107 // PreTileConfig should configure the tile registers based on basic
108 // block.
109 bool X86FastTileConfig::configBasicBlock(MachineBasicBlock &MBB) {
110  bool Change = false;
112  for (MachineInstr &MI : reverse(MBB)) {
113  if (!isTileDef(MRI, MI) && MI.getOpcode() != X86::PLDTILECFGV)
114  continue;
115  // AMX instructions that define tile register.
116  if (MI.getOpcode() != X86::PLDTILECFGV) {
117  MachineOperand &Row = MI.getOperand(1);
118  MachineOperand &Col = MI.getOperand(2);
119  unsigned TMMIdx = MI.getOperand(0).getReg() - X86::TMM0;
120  ShapeInfos.push_back({TMMIdx, ShapeT(&Row, &Col)});
121  } else { // PLDTILECFGV
122  // Rewrite the shape information to memory. Stack slot should have
123  // been initialized to zero in pre config.
124  int SS = MI.getOperand(0).getIndex(); // tile config stack slot.
125  for (auto &ShapeInfo : ShapeInfos) {
126  DebugLoc DL;
127  unsigned TMMIdx = ShapeInfo.first;
128  Register RowReg = ShapeInfo.second.getRow()->getReg();
129  Register ColReg = ShapeInfo.second.getCol()->getReg();
130  // Here is the data format for the tile config.
131  // 0 palette
132  // 1 start_row
133  // 2-15 reserved, must be zero
134  // 16-17 tile0.colsb Tile 0 bytes per row.
135  // 18-19 tile1.colsb Tile 1 bytes per row.
136  // 20-21 tile2.colsb Tile 2 bytes per row.
137  // ... (sequence continues)
138  // 30-31 tile7.colsb Tile 7 bytes per row.
139  // 32-47 reserved, must be zero
140  // 48 tile0.rows Tile 0 rows.
141  // 49 tile1.rows Tile 1 rows.
142  // 50 tile2.rows Tile 2 rows.
143  // ... (sequence continues)
144  // 55 tile7.rows Tile 7 rows.
145  // 56-63 reserved, must be zero
146  int RowOffset = 48 + TMMIdx;
147  int ColOffset = 16 + TMMIdx * 2;
148 
149  Register SubRowReg = TRI->getSubReg(RowReg, X86::sub_8bit);
150  BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), SubRowReg);
151  MachineInstrBuilder StoreRow =
152  BuildMI(MBB, MI, DL, TII->get(X86::MOV8mr));
153  addFrameReference(StoreRow, SS, RowOffset).addReg(SubRowReg);
154 
155  MachineInstrBuilder StoreCol =
156  BuildMI(MBB, MI, DL, TII->get(X86::MOV16mr));
157  addFrameReference(StoreCol, SS, ColOffset).addReg(ColReg);
158  }
159  ShapeInfos.clear();
160  Change = true;
161  }
162  }
163 
164  if (Change)
165  X86FI->setHasVirtualTileReg(true);
166 
167  return Change;
168 }
169 
170 bool X86FastTileConfig::runOnMachineFunction(MachineFunction &MFunc) {
171  MF = &MFunc;
172  MRI = &MFunc.getRegInfo();
173  const TargetSubtargetInfo *ST = &MFunc.getSubtarget<X86Subtarget>();
174  TRI = ST->getRegisterInfo();
175  TII = MFunc.getSubtarget().getInstrInfo();
176  X86FI = MFunc.getInfo<X86MachineFunctionInfo>();
177  bool Change = false;
178 
179  // Loop over all of the basic blocks, eliminating virtual register references
180  for (MachineBasicBlock &MBB : MFunc)
181  Change |= configBasicBlock(MBB);
182 
183  return Change;
184 }
185 
187  return new X86FastTileConfig();
188 }
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(X86FastTileConfig, DEBUG_TYPE, "Fast Tile Register Configure", false, false) INITIALIZE_PASS_END(X86FastTileConfig
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
X86Subtarget.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
X86InstrBuilder.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
TargetInstrInfo.h
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:127
llvm::ShapeT
Definition: TileShapeInfo.h:30
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
MachineRegisterInfo.h
llvm::createX86FastTileConfigPass
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
Definition: X86FastTileConfig.cpp:186
X86MachineFunctionInfo.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
X86.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86FastTileConfig.cpp:36
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:196
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::X86AS::SS
@ SS
Definition: X86.h:193
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
MachineFunctionPass.h
Configure
Fast Tile Register Configure
Definition: X86FastTileConfig.cpp:81
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunctionProperties::Property::NoPHIs
@ NoPHIs
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
MachineFrameInfo.h
X86RegisterInfo.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
isTileDef
Fast Tile Register static false bool isTileDef(MachineRegisterInfo *MRI, MachineInstr &MI)
Definition: X86FastTileConfig.cpp:83
InitializePasses.h
TargetRegisterInfo.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38