LLVM  17.0.0git
RISCVTargetMachine.cpp
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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
15 #include "RISCV.h"
17 #include "RISCVMacroFusion.h"
18 #include "RISCVTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/InitializePasses.h"
34 #include "llvm/MC/TargetRegistry.h"
37 #include "llvm/Transforms/IPO.h"
38 #include <optional>
39 using namespace llvm;
40 
42  "riscv-enable-copyelim",
43  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
44  cl::Hidden);
45 
46 // FIXME: Unify control over GlobalMerge.
48  EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
49  cl::desc("Enable the global merge pass"));
50 
51 static cl::opt<bool>
52  EnableMachineCombiner("riscv-enable-machine-combiner",
53  cl::desc("Enable the machine combiner pass"),
54  cl::init(true), cl::Hidden);
55 
57  "riscv-v-vector-bits-max",
58  cl::desc("Assume V extension vector registers are at most this big, "
59  "with zero meaning no maximum size is assumed."),
60  cl::init(0), cl::Hidden);
61 
63  "riscv-v-vector-bits-min",
64  cl::desc("Assume V extension vector registers are at least this big, "
65  "with zero meaning no minimum size is assumed. A value of -1 "
66  "means use Zvl*b extension. This is primarily used to enable "
67  "autovectorization with fixed width vectors."),
68  cl::init(-1), cl::Hidden);
69 
73  auto *PR = PassRegistry::getPassRegistry();
85 }
86 
87 static StringRef computeDataLayout(const Triple &TT) {
88  if (TT.isArch64Bit())
89  return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
90  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
91  return "e-m:e-p:32:32-i64:64-n32-S128";
92 }
93 
95  std::optional<Reloc::Model> RM) {
96  return RM.value_or(Reloc::Static);
97 }
98 
100  StringRef CPU, StringRef FS,
101  const TargetOptions &Options,
102  std::optional<Reloc::Model> RM,
103  std::optional<CodeModel::Model> CM,
104  CodeGenOpt::Level OL, bool JIT)
105  : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
108  TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
109  initAsmInfo();
110 
111  // RISC-V supports the MachineOutliner.
112  setMachineOutliner(true);
114 }
115 
116 const RISCVSubtarget *
118  Attribute CPUAttr = F.getFnAttribute("target-cpu");
119  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
120  Attribute FSAttr = F.getFnAttribute("target-features");
121 
122  std::string CPU =
123  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
124  std::string TuneCPU =
125  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
126  std::string FS =
127  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
128 
129  unsigned RVVBitsMin = RVVVectorBitsMinOpt;
130  unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
131 
132  Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
133  if (VScaleRangeAttr.isValid()) {
134  if (!RVVVectorBitsMinOpt.getNumOccurrences())
135  RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
136  std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
137  if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
138  RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
139  }
140 
141  if (RVVBitsMin != -1U) {
142  // FIXME: Change to >= 32 when VLEN = 32 is supported.
143  assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
144  isPowerOf2_32(RVVBitsMin))) &&
145  "V or Zve* extension requires vector length to be in the range of "
146  "64 to 65536 and a power 2!");
147  assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
148  "Minimum V extension vector length should not be larger than its "
149  "maximum!");
150  }
151  assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
152  isPowerOf2_32(RVVBitsMax))) &&
153  "V or Zve* extension requires vector length to be in the range of "
154  "64 to 65536 and a power 2!");
155 
156  if (RVVBitsMin != -1U) {
157  if (RVVBitsMax != 0) {
158  RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
159  RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
160  }
161 
162  RVVBitsMin =
163  PowerOf2Floor((RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
164  }
165  RVVBitsMax =
166  PowerOf2Floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
167 
169  Key += "RVVMin";
170  Key += std::to_string(RVVBitsMin);
171  Key += "RVVMax";
172  Key += std::to_string(RVVBitsMax);
173  Key += CPU;
174  Key += TuneCPU;
175  Key += FS;
176  auto &I = SubtargetMap[Key];
177  if (!I) {
178  // This needs to be done before we create a new subtarget since any
179  // creation will depend on the TM and the code generation flags on the
180  // function that reside in TargetOptions.
182  auto ABIName = Options.MCOptions.getABIName();
183  if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
184  F.getParent()->getModuleFlag("target-abi"))) {
185  auto TargetABI = RISCVABI::getTargetABI(ABIName);
186  if (TargetABI != RISCVABI::ABI_Unknown &&
187  ModuleTargetABI->getString() != ABIName) {
188  report_fatal_error("-target-abi option != target-abi module flag");
189  }
190  ABIName = ModuleTargetABI->getString();
191  }
192  I = std::make_unique<RISCVSubtarget>(
193  TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
194  }
195  return I.get();
196 }
197 
200  const TargetSubtargetInfo *STI) const {
201  return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
202  F, STI);
203 }
204 
207  return TargetTransformInfo(RISCVTTIImpl(this, F));
208 }
209 
210 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
211 // for all memory accesses, so it is reasonable to assume that an
212 // implementation has no-op address space casts. If an implementation makes a
213 // change to this, they can override it here.
215  unsigned DstAS) const {
216  return true;
217 }
218 
219 namespace {
220 class RISCVPassConfig : public TargetPassConfig {
221 public:
222  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
223  : TargetPassConfig(TM, PM) {}
224 
225  RISCVTargetMachine &getRISCVTargetMachine() const {
226  return getTM<RISCVTargetMachine>();
227  }
228 
230  createMachineScheduler(MachineSchedContext *C) const override {
231  const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
232  if (ST.hasMacroFusion()) {
235  return DAG;
236  }
237  return nullptr;
238  }
239 
241  createPostMachineScheduler(MachineSchedContext *C) const override {
242  const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
243  if (ST.hasMacroFusion()) {
246  return DAG;
247  }
248  return nullptr;
249  }
250 
251  void addIRPasses() override;
252  bool addPreISel() override;
253  bool addInstSelector() override;
254  bool addIRTranslator() override;
255  bool addLegalizeMachineIR() override;
256  bool addRegBankSelect() override;
257  bool addGlobalInstructionSelect() override;
258  void addPreEmitPass() override;
259  void addPreEmitPass2() override;
260  void addPreSched2() override;
261  void addMachineSSAOptimization() override;
262  void addPreRegAlloc() override;
263  void addPostRegAlloc() override;
264 };
265 } // namespace
266 
268  return new RISCVPassConfig(*this, PM);
269 }
270 
271 void RISCVPassConfig::addIRPasses() {
272  addPass(createAtomicExpandPass());
273 
274  if (getOptLevel() != CodeGenOpt::None)
276 
277  if (getOptLevel() != CodeGenOpt::None)
279 
281 }
282 
283 bool RISCVPassConfig::addPreISel() {
284  if (TM->getOptLevel() != CodeGenOpt::None) {
285  // Add a barrier before instruction selection so that we will not get
286  // deleted block address after enabling default outlining. See D99707 for
287  // more details.
288  addPass(createBarrierNoopPass());
289  }
290 
292  addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
293  /* OnlyOptimizeForSize */ false,
294  /* MergeExternalByDefault */ true));
295  }
296 
297  return false;
298 }
299 
300 bool RISCVPassConfig::addInstSelector() {
301  addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
302 
303  return false;
304 }
305 
306 bool RISCVPassConfig::addIRTranslator() {
307  addPass(new IRTranslator(getOptLevel()));
308  return false;
309 }
310 
311 bool RISCVPassConfig::addLegalizeMachineIR() {
312  addPass(new Legalizer());
313  return false;
314 }
315 
316 bool RISCVPassConfig::addRegBankSelect() {
317  addPass(new RegBankSelect());
318  return false;
319 }
320 
321 bool RISCVPassConfig::addGlobalInstructionSelect() {
322  addPass(new InstructionSelect(getOptLevel()));
323  return false;
324 }
325 
326 void RISCVPassConfig::addPreSched2() {}
327 
328 void RISCVPassConfig::addPreEmitPass() {
329  addPass(&BranchRelaxationPassID);
331 }
332 
333 void RISCVPassConfig::addPreEmitPass2() {
334  addPass(createRISCVExpandPseudoPass());
335  // Schedule the expansion of AMOs at the last possible moment, avoiding the
336  // possibility for other passes to break the requirements for forward
337  // progress in the LR/SC block.
339 }
340 
341 void RISCVPassConfig::addMachineSSAOptimization() {
344  addPass(&MachineCombinerID);
345 
346  if (TM->getTargetTriple().getArch() == Triple::riscv64) {
347  addPass(createRISCVSExtWRemovalPass());
348  addPass(createRISCVStripWSuffixPass());
349  }
350 }
351 
352 void RISCVPassConfig::addPreRegAlloc() {
354  if (TM->getOptLevel() != CodeGenOpt::None)
356  addPass(createRISCVInsertVSETVLIPass());
357 }
358 
359 void RISCVPassConfig::addPostRegAlloc() {
360  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
362 }
363 
366  return new yaml::RISCVMachineFunctionInfo();
367 }
368 
371  const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
372  return new yaml::RISCVMachineFunctionInfo(*MFI);
373 }
374 
377  SMDiagnostic &Error, SMRange &SourceRange) const {
378  const auto &YamlMFI =
379  static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
380  PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
381  return false;
382 }
llvm::Triple::riscv64
@ riscv64
Definition: Triple.h:76
llvm::initializeRISCVCodeGenPreparePass
void initializeRISCVCodeGenPreparePass(PassRegistry &)
RISCVMacroFusion.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:185
llvm::RISCVTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: RISCVTargetMachine.cpp:375
llvm::TargetMachine::STI
std::unique_ptr< const MCSubtargetInfo > STI
Definition: TargetMachine.h:109
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:400
llvm::RISCVTargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: RISCVTargetMachine.cpp:370
llvm::RISCVTTIImpl
Definition: RISCVTargetTransformInfo.h:29
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:74
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::RISCVTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: RISCVTargetMachine.cpp:267
T
llvm::Function
Definition: Function.h:59
llvm::Attribute
Definition: Attributes.h:67
EnableRedundantCopyElimination
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
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Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:677
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::MCTargetOptions::getABIName
StringRef getABIName() const
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Definition: MCTargetOptions.cpp:23
llvm::createRISCVInsertVSETVLIPass
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
Definition: RISCVInsertVSETVLI.cpp:1453
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This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::createRISCVMergeBaseOffsetOptPass
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
Definition: RISCVMergeBaseOffset.cpp:453
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:24
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:138
llvm::createRISCVCodeGenPreparePass
FunctionPass * createRISCVCodeGenPreparePass()
Definition: RISCVCodeGenPrepare.cpp:176
llvm::createRISCVExpandAtomicPseudoPass
FunctionPass * createRISCVExpandAtomicPseudoPass()
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Definition: X86.h:201
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:264
InstructionSelect.h
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Definition: BarrierNoopPass.cpp:43
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
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Definition: FileCheck.cpp:337
llvm::RISCVTargetMachine::getSubtargetImpl
const RISCVSubtarget * getSubtargetImpl() const =delete
llvm::initializeRISCVMergeBaseOffsetOptPass
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
STLExtras.h
llvm::initializeRISCVExpandPseudoPass
void initializeRISCVExpandPseudoPass(PassRegistry &)
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:288
LegacyPassManager.h
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This implementation is used for RISCV ELF targets.
Definition: RISCVTargetObjectFile.h:17
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#define F(x, y, z)
Definition: MD5.cpp:55
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Definition: CodeGen.h:25
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: RISCVTargetMachine.cpp:87
llvm::RISCVTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: RISCVTargetMachine.cpp:365
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MIRYamlMapping.h
llvm::MSP430Attrs::CodeModel
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Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::PowerOf2Floor
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
Definition: MathExtras.h:449
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Definition: TargetMachine.h:261
llvm::MachineFunction::getInfo
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Definition: MachineFunction.h:770
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Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Y
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RISCVTargetObjectFile.h
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Definition: SourceMgr.h:281
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PAL metadata keys.
Definition: AMDGPUMetadata.h:486
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MCTargetOptions MCOptions
Machine level options.
Definition: TargetOptions.h:442
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Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
Definition: Attributes.cpp:375
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Definition: MachineScheduler.cpp:3835
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Definition: CodeGen.h:31
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
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unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:369
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Definition: InstructionSelect.h:33
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Definition: TargetRegistry.h:1354
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Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:325
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Definition: RISCVTargetMachine.cpp:70
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Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
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Definition: PassBuilderBindings.cpp:48
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Definition: TargetMachine.h:99
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Return the attribute's value as a string.
Definition: Attributes.cpp:312
X
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Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
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Definition: SmallString.h:26
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Definition: TargetPassConfig.h:84
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Definition: RISCVTargetParser.h:24
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Definition: RISCVISelDAGToDAG.cpp:2943
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Definition: TargetMachine.h:97
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Definition: TargetMachine.h:510
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Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3678
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@ JIT
Definition: ExecutionEngine.h:524
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Definition: Compiler.h:127
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Definition: ARMBaseInfo.h:73
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Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
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Definition: RISCVExpandPseudoInsts.cpp:399
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Definition: MachineScheduler.h:127
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I
#define I(x, y, z)
Definition: MD5.cpp:58
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virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:839
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Definition: CommandLine.h:445
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Definition: RISCVMachineFunctionInfo.h:47
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Definition: RISCVSubtarget.h:35
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Returns an instance of the Make Compressible Optimization pass.
Definition: RISCVMakeCompressible.cpp:389
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Definition: TargetMachine.h:119
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Definition: RISCVTargetMachine.cpp:99
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Definition: MachineScheduler.h:273
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@ None
-O0
Definition: CodeGen.h:58
EnableMachineCombiner
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RISCV.h
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Definition: MachineFunction.h:258
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static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:43
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:499
llvm::createRISCVGatherScatterLoweringPass
FunctionPass * createRISCVGatherScatterLoweringPass()
llvm::createRISCVMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
Definition: RISCVMacroFusion.cpp:71
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:25
IRTranslator.h
llvm::initializeRISCVPreRAExpandPseudoPass
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::createRISCVSExtWRemovalPass
FunctionPass * createRISCVSExtWRemovalPass()
std
Definition: BitVector.h:851
llvm::createRISCVRedundantCopyEliminationPass
FunctionPass * createRISCVRedundantCopyEliminationPass()
Definition: RISCVRedundantCopyElimination.cpp:179
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1282
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
RegBankSelect.h
llvm::yaml::RISCVMachineFunctionInfo
Definition: RISCVMachineFunctionInfo.h:26
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:417
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
RISCVBaseInfo.h
RVVVectorBitsMaxOpt
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:692
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:121
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:629
Legalizer.h
llvm::initializeRISCVInsertVSETVLIPass
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
llvm::RISCVTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: RISCVTargetMachine.cpp:206
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:390
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
RISCVMachineFunctionInfo.h
llvm::to_string
std::string to_string(const T &Value)
Definition: ScopedPrinter.h:85
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:130
TargetTransformInfo.h
llvm::RISCVTargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: RISCVTargetMachine.cpp:214
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
RISCVTargetInfo.h
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::CodeGenOpt::Level
Level
Code generation optimization level.
Definition: CodeGen.h:57
llvm::cl::desc
Definition: CommandLine.h:411
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:395
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:120
llvm::MDString
A single uniqued string.
Definition: Metadata.h:611
RISCVTargetTransformInfo.h
TargetRegistry.h
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
InitializePasses.h
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:98
llvm::RISCVTargetMachine::createMachineFunctionInfo
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
Definition: RISCVTargetMachine.cpp:198
MIParser.h
TargetLoweringObjectFileImpl.h
RISCVTargetMachine.h