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41 "riscv-enable-copyelim",
60 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
61 assert(TT.isArch32Bit() &&
"only RV32 and RV64 are currently supported");
62 return "e-m:e-p:32:32-i64:64-n32-S128";
89 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
90 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
91 Attribute FSAttr =
F.getFnAttribute(
"target-features");
99 std::string
Key = CPU + TuneCPU +
FS;
100 auto &
I = SubtargetMap[
Key];
107 if (
const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
108 F.getParent()->getModuleFlag(
"target-abi"))) {
111 ModuleTargetABI->getString() != ABIName) {
114 ABIName = ModuleTargetABI->getString();
116 I = std::make_unique<RISCVSubtarget>(
TargetTriple, CPU, TuneCPU,
FS, ABIName, *
this);
131 unsigned DstAS)
const {
142 return getTM<RISCVTargetMachine>();
148 if (
ST.hasMacroFusion()) {
159 if (
ST.hasMacroFusion()) {
167 void addIRPasses()
override;
168 bool addPreISel()
override;
169 bool addInstSelector()
override;
170 bool addIRTranslator()
override;
171 bool addLegalizeMachineIR()
override;
172 bool addRegBankSelect()
override;
173 bool addGlobalInstructionSelect()
override;
174 void addPreEmitPass()
override;
175 void addPreEmitPass2()
override;
176 void addPreSched2()
override;
177 void addMachineSSAOptimization()
override;
178 void addPreRegAlloc()
override;
179 void addPostRegAlloc()
override;
184 return new RISCVPassConfig(*
this, PM);
187 void RISCVPassConfig::addIRPasses() {
195 bool RISCVPassConfig::addPreISel() {
205 bool RISCVPassConfig::addInstSelector() {
211 bool RISCVPassConfig::addIRTranslator() {
216 bool RISCVPassConfig::addLegalizeMachineIR() {
221 bool RISCVPassConfig::addRegBankSelect() {
226 bool RISCVPassConfig::addGlobalInstructionSelect() {
231 void RISCVPassConfig::addPreSched2() {}
233 void RISCVPassConfig::addPreEmitPass() {
238 void RISCVPassConfig::addPreEmitPass2() {
246 void RISCVPassConfig::addMachineSSAOptimization() {
253 void RISCVPassConfig::addPreRegAlloc() {
259 void RISCVPassConfig::addPostRegAlloc() {
278 const auto &YamlMFI =
This is an optimization pass for GlobalISel generic memory operations.
bool isValid() const
Return true if the attribute is any kind of attribute.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Target & getTheRISCV64Target()
ABI getTargetABI(StringRef ABIName)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Target - Wrapper for Target specific information.
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
Triple - Helper class for working with autoconf configuration names.
FunctionPass * createRISCVExpandAtomicPseudoPass()
void setSupportsDefaultOutlining(bool Enable)
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
const RISCVSubtarget * getSubtargetImpl() const =delete
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This implementation is used for RISCV ELF targets.
static StringRef computeDataLayout(const Triple &TT)
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void setMachineOutliner(bool Enable)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
(vector float) vec_cmpeq(*A, *B) C
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
MCTargetOptions MCOptions
Machine level options.
void initializeRISCVSExtWRemovalPass(PassRegistry &)
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
This pass is responsible for selecting generic machine instructions to target-specific instructions.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
StringRef getValueAsString() const
Return the attribute's value as a string.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOpt::Level OptLevel)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
#define LLVM_EXTERNAL_VISIBILITY
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createRISCVExpandPseudoPass()
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
FunctionPass * createRISCVGatherScatterLoweringPass()
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
StringRef - Represent a constant reference to a string, i.e.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
FunctionPass * createRISCVSExtWRemovalPass()
FunctionPass * createRISCVRedundantCopyEliminationPass()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Lightweight error class with error context and mandatory checking.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Represents a range in source code.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
const char LLVMTargetMachineRef TM
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
A ScheduleDAG for scheduling lists of MachineInstr.
Target & getTheRISCV32Target()