Go to the documentation of this file.
42 "riscv-enable-copyelim",
49 cl::desc(
"Enable the global merge pass"));
53 cl::desc(
"Enable the machine combiner pass"),
57 "riscv-v-vector-bits-max",
58 cl::desc(
"Assume V extension vector registers are at most this big, "
59 "with zero meaning no maximum size is assumed."),
63 "riscv-v-vector-bits-min",
64 cl::desc(
"Assume V extension vector registers are at least this big, "
65 "with zero meaning no minimum size is assumed. A value of -1 "
66 "means use Zvl*b extension. This is primarily used to enable "
67 "autovectorization with fixed width vectors."),
89 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
90 assert(TT.isArch32Bit() &&
"only RV32 and RV64 are currently supported");
91 return "e-m:e-p:32:32-i64:64-n32-S128";
95 std::optional<Reloc::Model>
RM) {
102 std::optional<Reloc::Model>
RM,
103 std::optional<CodeModel::Model> CM,
118 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
119 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
120 Attribute FSAttr =
F.getFnAttribute(
"target-features");
124 std::string TuneCPU =
132 Attribute VScaleRangeAttr =
F.getFnAttribute(Attribute::VScaleRange);
133 if (VScaleRangeAttr.
isValid()) {
141 if (RVVBitsMin != -1U) {
143 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
145 "V or Zve* extension requires vector length to be in the range of "
146 "64 to 65536 and a power 2!");
147 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
148 "Minimum V extension vector length should not be larger than its "
151 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
153 "V or Zve* extension requires vector length to be in the range of "
154 "64 to 65536 and a power 2!");
156 if (RVVBitsMin != -1U) {
157 if (RVVBitsMax != 0) {
158 RVVBitsMin =
std::min(RVVBitsMin, RVVBitsMax);
159 RVVBitsMax =
std::max(RVVBitsMin, RVVBitsMax);
163 PowerOf2Floor((RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
166 PowerOf2Floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
176 auto &
I = SubtargetMap[
Key];
183 if (
const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
184 F.getParent()->getModuleFlag(
"target-abi"))) {
187 ModuleTargetABI->getString() != ABIName) {
190 ABIName = ModuleTargetABI->getString();
192 I = std::make_unique<RISCVSubtarget>(
193 TargetTriple, CPU, TuneCPU,
FS, ABIName, RVVBitsMin, RVVBitsMax, *
this);
201 return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(
Allocator,
215 unsigned DstAS)
const {
226 return getTM<RISCVTargetMachine>();
232 if (
ST.hasMacroFusion()) {
243 if (
ST.hasMacroFusion()) {
251 void addIRPasses()
override;
252 bool addPreISel()
override;
253 bool addInstSelector()
override;
254 bool addIRTranslator()
override;
255 bool addLegalizeMachineIR()
override;
256 bool addRegBankSelect()
override;
257 bool addGlobalInstructionSelect()
override;
258 void addPreEmitPass()
override;
259 void addPreEmitPass2()
override;
260 void addPreSched2()
override;
261 void addMachineSSAOptimization()
override;
262 void addPreRegAlloc()
override;
263 void addPostRegAlloc()
override;
268 return new RISCVPassConfig(*
this, PM);
271 void RISCVPassConfig::addIRPasses() {
283 bool RISCVPassConfig::addPreISel() {
300 bool RISCVPassConfig::addInstSelector() {
306 bool RISCVPassConfig::addIRTranslator() {
311 bool RISCVPassConfig::addLegalizeMachineIR() {
316 bool RISCVPassConfig::addRegBankSelect() {
321 bool RISCVPassConfig::addGlobalInstructionSelect() {
326 void RISCVPassConfig::addPreSched2() {}
328 void RISCVPassConfig::addPreEmitPass() {
333 void RISCVPassConfig::addPreEmitPass2() {
341 void RISCVPassConfig::addMachineSSAOptimization() {
352 void RISCVPassConfig::addPreRegAlloc() {
359 void RISCVPassConfig::addPostRegAlloc() {
378 const auto &YamlMFI =
void initializeRISCVCodeGenPreparePass(PassRegistry &)
This is an optimization pass for GlobalISel generic memory operations.
bool isValid() const
Return true if the attribute is any kind of attribute.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
std::unique_ptr< const MCSubtargetInfo > STI
FunctionPass * createRISCVPreRAExpandPseudoPass()
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Target & getTheRISCV64Target()
ABI getTargetABI(StringRef ABIName)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Target - Wrapper for Target specific information.
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
Triple - Helper class for working with autoconf configuration names.
FunctionPass * createRISCVCodeGenPreparePass()
FunctionPass * createRISCVExpandAtomicPseudoPass()
void initializeRISCVDAGToDAGISelPass(PassRegistry &)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
void setSupportsDefaultOutlining(bool Enable)
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
const RISCVSubtarget * getSubtargetImpl() const =delete
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
This implementation is used for RISCV ELF targets.
static StringRef computeDataLayout(const Triple &TT)
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
void setMachineOutliner(bool Enable)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
(vector float) vec_cmpeq(*A, *B) C
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionPass * createRISCVStripWSuffixPass()
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
MCTargetOptions MCOptions
Machine level options.
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
void initializeRISCVSExtWRemovalPass(PassRegistry &)
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
StringRef getValueAsString() const
Return the attribute's value as a string.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Target-Independent Code Generator Pass Configuration Options.
static constexpr unsigned RVVBitsPerBlock
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOpt::Level OptLevel)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
#define LLVM_EXTERNAL_VISIBILITY
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
Allocate memory in an ever growing pool, as if by bump-pointer.
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
FunctionPass * createRISCVExpandPseudoPass()
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
void initializeRISCVStripWSuffixPass(PassRegistry &)
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
FunctionPass * createRISCVGatherScatterLoweringPass()
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
StringRef - Represent a constant reference to a string, i.e.
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
TargetSubtargetInfo - Generic base class for all target subtargets.
FunctionPass * createRISCVSExtWRemovalPass()
FunctionPass * createRISCVRedundantCopyEliminationPass()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Lightweight error class with error context and mandatory checking.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Represents a range in source code.
std::string to_string(const T &Value)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
std::string str() const
str - Get the contents as an std::string.
const char LLVMTargetMachineRef TM
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Level
Code generation optimization level.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
A ScheduleDAG for scheduling lists of MachineInstr.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Target & getTheRISCV32Target()
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.