LLVM  12.0.0git
RISCVTargetMachine.cpp
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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
15 #include "RISCV.h"
16 #include "RISCVTargetObjectFile.h"
19 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/InitializePasses.h"
33 using namespace llvm;
34 
38  auto *PR = PassRegistry::getPassRegistry();
43 }
44 
45 static StringRef computeDataLayout(const Triple &TT) {
46  if (TT.isArch64Bit())
47  return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
48  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
49  return "e-m:e-p:32:32-i64:64-n32-S128";
50 }
51 
54  if (!RM.hasValue())
55  return Reloc::Static;
56  return *RM;
57 }
58 
60  StringRef CPU, StringRef FS,
61  const TargetOptions &Options,
64  CodeGenOpt::Level OL, bool JIT)
65  : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
67  getEffectiveCodeModel(CM, CodeModel::Small), OL),
68  TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
69  initAsmInfo();
70 
71  // RISC-V supports the MachineOutliner.
72  setMachineOutliner(true);
73 }
74 
75 const RISCVSubtarget *
77  Attribute CPUAttr = F.getFnAttribute("target-cpu");
78  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
79  Attribute FSAttr = F.getFnAttribute("target-features");
80 
81  std::string CPU =
82  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
83  std::string TuneCPU =
84  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
85  std::string FS =
86  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
87  std::string Key = CPU + TuneCPU + FS;
88  auto &I = SubtargetMap[Key];
89  if (!I) {
90  // This needs to be done before we create a new subtarget since any
91  // creation will depend on the TM and the code generation flags on the
92  // function that reside in TargetOptions.
94  auto ABIName = Options.MCOptions.getABIName();
95  if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
96  F.getParent()->getModuleFlag("target-abi"))) {
97  auto TargetABI = RISCVABI::getTargetABI(ABIName);
98  if (TargetABI != RISCVABI::ABI_Unknown &&
99  ModuleTargetABI->getString() != ABIName) {
100  report_fatal_error("-target-abi option != target-abi module flag");
101  }
102  ABIName = ModuleTargetABI->getString();
103  }
104  I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
105  }
106  return I.get();
107 }
108 
111  return TargetTransformInfo(RISCVTTIImpl(this, F));
112 }
113 
114 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
115 // for all memory accesses, so it is reasonable to assume that an
116 // implementation has no-op address space casts. If an implementation makes a
117 // change to this, they can override it here.
119  unsigned DstAS) const {
120  return true;
121 }
122 
123 namespace {
124 class RISCVPassConfig : public TargetPassConfig {
125 public:
126  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
127  : TargetPassConfig(TM, PM) {}
128 
129  RISCVTargetMachine &getRISCVTargetMachine() const {
130  return getTM<RISCVTargetMachine>();
131  }
132 
133  void addIRPasses() override;
134  bool addInstSelector() override;
135  bool addIRTranslator() override;
136  bool addLegalizeMachineIR() override;
137  bool addRegBankSelect() override;
138  bool addGlobalInstructionSelect() override;
139  void addPreEmitPass() override;
140  void addPreEmitPass2() override;
141  void addPreSched2() override;
142  void addPreRegAlloc() override;
143 };
144 } // namespace
145 
147  return new RISCVPassConfig(*this, PM);
148 }
149 
150 void RISCVPassConfig::addIRPasses() {
151  addPass(createAtomicExpandPass());
153 }
154 
155 bool RISCVPassConfig::addInstSelector() {
156  addPass(createRISCVISelDag(getRISCVTargetMachine()));
157 
158  return false;
159 }
160 
161 bool RISCVPassConfig::addIRTranslator() {
162  addPass(new IRTranslator(getOptLevel()));
163  return false;
164 }
165 
166 bool RISCVPassConfig::addLegalizeMachineIR() {
167  addPass(new Legalizer());
168  return false;
169 }
170 
171 bool RISCVPassConfig::addRegBankSelect() {
172  addPass(new RegBankSelect());
173  return false;
174 }
175 
176 bool RISCVPassConfig::addGlobalInstructionSelect() {
177  addPass(new InstructionSelect());
178  return false;
179 }
180 
181 void RISCVPassConfig::addPreSched2() {}
182 
183 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
184 
185 void RISCVPassConfig::addPreEmitPass2() {
186  addPass(createRISCVExpandPseudoPass());
187  // Schedule the expansion of AMOs at the last possible moment, avoiding the
188  // possibility for other passes to break the requirements for forward
189  // progress in the LR/SC block.
191 }
192 
193 void RISCVPassConfig::addPreRegAlloc() {
194  if (TM->getOptLevel() != CodeGenOpt::None) {
197  }
198 }
const RISCVSubtarget * getSubtargetImpl() const =delete
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:248
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeRISCVExpandPseudoPass(PassRegistry &)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
F(f)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
Definition: BitVector.h:941
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target & getTheRISCV32Target()
FunctionPass * createRISCVExpandAtomicPseudoPass()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM)
Key
PAL metadata keys.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:151
void initializeRISCVCleanupVSETVLIPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
Target & getTheRISCV64Target()
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
ABI getTargetABI(StringRef ABIName)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Target - Wrapper for Target specific information.
std::string TargetCPU
Definition: TargetMachine.h:97
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:275
static StringRef computeDataLayout(const Triple &TT)
TargetOptions Options
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
#define I(x, y, z)
Definition: MD5.cpp:59
FunctionPass * createRISCVCleanupVSETVLIPass()
Returns an instance of the Cleanup VSETVLI pass.
FunctionPass * createRISCVExpandPseudoPass()
std::string TargetFS
Definition: TargetMachine.h:98
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
A single uniqued string.
Definition: Metadata.h:602
This implementation is used for RISCV ELF targets.
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18