LLVM  10.0.0svn
RISCVTargetMachine.cpp
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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
14 #include "RISCV.h"
15 #include "RISCVTargetObjectFile.h"
18 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/Passes.h"
31 using namespace llvm;
32 
33 extern "C" void LLVMInitializeRISCVTarget() {
39 }
40 
42  if (TT.isArch64Bit()) {
43  return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
44  } else {
45  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
46  return "e-m:e-p:32:32-i64:64-n32-S128";
47  }
48 }
49 
52  if (!RM.hasValue())
53  return Reloc::Static;
54  return *RM;
55 }
56 
58  StringRef CPU, StringRef FS,
59  const TargetOptions &Options,
62  CodeGenOpt::Level OL, bool JIT)
63  : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
64  getEffectiveRelocModel(TT, RM),
65  getEffectiveCodeModel(CM, CodeModel::Small), OL),
66  TLOF(std::make_unique<RISCVELFTargetObjectFile>()),
67  Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
68  initAsmInfo();
69 }
70 
73  return TargetTransformInfo(RISCVTTIImpl(this, F));
74 }
75 
76 namespace {
77 class RISCVPassConfig : public TargetPassConfig {
78 public:
79  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
80  : TargetPassConfig(TM, PM) {}
81 
82  RISCVTargetMachine &getRISCVTargetMachine() const {
83  return getTM<RISCVTargetMachine>();
84  }
85 
86  void addIRPasses() override;
87  bool addInstSelector() override;
88  bool addIRTranslator() override;
89  bool addLegalizeMachineIR() override;
90  bool addRegBankSelect() override;
91  bool addGlobalInstructionSelect() override;
92  void addPreEmitPass() override;
93  void addPreEmitPass2() override;
94  void addPreRegAlloc() override;
95 };
96 }
97 
99  return new RISCVPassConfig(*this, PM);
100 }
101 
102 void RISCVPassConfig::addIRPasses() {
103  addPass(createAtomicExpandPass());
105 }
106 
107 bool RISCVPassConfig::addInstSelector() {
108  addPass(createRISCVISelDag(getRISCVTargetMachine()));
109 
110  return false;
111 }
112 
113 bool RISCVPassConfig::addIRTranslator() {
114  addPass(new IRTranslator());
115  return false;
116 }
117 
118 bool RISCVPassConfig::addLegalizeMachineIR() {
119  addPass(new Legalizer());
120  return false;
121 }
122 
123 bool RISCVPassConfig::addRegBankSelect() {
124  addPass(new RegBankSelect());
125  return false;
126 }
127 
128 bool RISCVPassConfig::addGlobalInstructionSelect() {
129  addPass(new InstructionSelect());
130  return false;
131 }
132 
133 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
134 
135 void RISCVPassConfig::addPreEmitPass2() {
136  // Schedule the expansion of AMOs at the last possible moment, avoiding the
137  // possibility for other passes to break the requirements for forward
138  // progress in the LR/SC block.
139  addPass(createRISCVExpandPseudoPass());
140 }
141 
142 void RISCVPassConfig::addPreRegAlloc() {
144 }
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeRISCVExpandPseudoPass(PassRegistry &)
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
F(f)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Definition: BitVector.h:937
Target & getTheRISCV32Target()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1296
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
void LLVMInitializeRISCVTarget()
Target & getTheRISCV64Target()
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
bool hasValue() const
Definition: Optional.h:259
This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
static StringRef computeDataLayout(const Triple &TT)
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
FunctionPass * createRISCVExpandPseudoPass()
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This implementation is used for RISCV ELF targets.
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18