47 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
48 assert(TT.isArch32Bit() &&
"only RV32 and RV64 are currently supported");
49 return "e-m:e-p:32:32-i64:64-n32-S128";
77 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
78 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
79 Attribute FSAttr =
F.getFnAttribute(
"target-features");
87 std::string
Key = CPU + TuneCPU +
FS;
88 auto &
I = SubtargetMap[
Key];
95 if (
const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
96 F.getParent()->getModuleFlag(
"target-abi"))) {
99 ModuleTargetABI->getString() != ABIName) {
102 ABIName = ModuleTargetABI->getString();
104 I = std::make_unique<RISCVSubtarget>(
TargetTriple, CPU, TuneCPU,
FS, ABIName, *
this);
119 unsigned DstAS)
const {
130 return getTM<RISCVTargetMachine>();
133 void addIRPasses()
override;
134 bool addInstSelector()
override;
135 bool addIRTranslator()
override;
136 bool addLegalizeMachineIR()
override;
137 bool addRegBankSelect()
override;
138 bool addGlobalInstructionSelect()
override;
139 void addPreEmitPass()
override;
140 void addPreEmitPass2()
override;
141 void addPreSched2()
override;
142 void addPreRegAlloc()
override;
147 return new RISCVPassConfig(*
this, PM);
150 void RISCVPassConfig::addIRPasses() {
155 bool RISCVPassConfig::addInstSelector() {
161 bool RISCVPassConfig::addIRTranslator() {
166 bool RISCVPassConfig::addLegalizeMachineIR() {
171 bool RISCVPassConfig::addRegBankSelect() {
176 bool RISCVPassConfig::addGlobalInstructionSelect() {
181 void RISCVPassConfig::addPreSched2() {}
185 void RISCVPassConfig::addPreEmitPass2() {
193 void RISCVPassConfig::addPreRegAlloc() {
const RISCVSubtarget * getSubtargetImpl() const =delete
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeRISCVExpandPseudoPass(PassRegistry &)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target & getTheRISCV32Target()
FunctionPass * createRISCVExpandAtomicPseudoPass()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM)
RegisterTargetMachine - Helper template for registering a target machine implementation,...
bool isValid() const
Return true if the attribute is any kind of attribute.
void initializeRISCVCleanupVSETVLIPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Target & getTheRISCV64Target()
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
ABI getTargetABI(StringRef ABIName)
Triple - Helper class for working with autoconf configuration names.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
#define LLVM_EXTERNAL_VISIBILITY
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Target - Wrapper for Target specific information.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
StringRef getValueAsString() const
Return the attribute's value as a string.
static StringRef computeDataLayout(const Triple &TT)
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
FunctionPass * createRISCVCleanupVSETVLIPass()
Returns an instance of the Cleanup VSETVLI pass.
FunctionPass * createRISCVExpandPseudoPass()
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
This implementation is used for RISCV ELF targets.
FunctionPass * createAtomicExpandPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.