LLVM 19.0.0git
RISCVTargetMachine.cpp
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1//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about RISC-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetMachine.h"
15#include "RISCV.h"
20#include "llvm/ADT/STLExtras.h"
30#include "llvm/CodeGen/Passes.h"
38#include "llvm/Transforms/IPO.h"
40#include <optional>
41using namespace llvm;
42
44 "riscv-enable-copyelim",
45 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
47
48// FIXME: Unify control over GlobalMerge.
50 EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
51 cl::desc("Enable the global merge pass"));
52
53static cl::opt<bool>
54 EnableMachineCombiner("riscv-enable-machine-combiner",
55 cl::desc("Enable the machine combiner pass"),
56 cl::init(true), cl::Hidden);
57
59 "riscv-v-vector-bits-max",
60 cl::desc("Assume V extension vector registers are at most this big, "
61 "with zero meaning no maximum size is assumed."),
63
65 "riscv-v-vector-bits-min",
66 cl::desc("Assume V extension vector registers are at least this big, "
67 "with zero meaning no minimum size is assumed. A value of -1 "
68 "means use Zvl*b extension. This is primarily used to enable "
69 "autovectorization with fixed width vectors."),
70 cl::init(-1), cl::Hidden);
71
73 "riscv-enable-copy-propagation",
74 cl::desc("Enable the copy propagation with RISC-V copy instr"),
75 cl::init(true), cl::Hidden);
76
78 "riscv-enable-dead-defs", cl::Hidden,
79 cl::desc("Enable the pass that removes dead"
80 " definitons and replaces stores to"
81 " them with stores to x0"),
82 cl::init(true));
83
84static cl::opt<bool>
85 EnableSinkFold("riscv-enable-sink-fold",
86 cl::desc("Enable sinking and folding of instruction copies"),
87 cl::init(true), cl::Hidden);
88
89static cl::opt<bool>
90 EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden,
91 cl::desc("Enable the loop data prefetch pass"),
92 cl::init(true));
93
94static cl::opt<bool>
95 EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
96 cl::desc("Enable Split RegisterAlloc for RVV"),
97 cl::init(true));
98
100 "riscv-misched-load-clustering", cl::Hidden,
101 cl::desc("Enable load clustering in the machine scheduler"),
102 cl::init(false));
103
129}
130
132 const TargetOptions &Options) {
133 StringRef ABIName = Options.MCOptions.getABIName();
134 if (TT.isArch64Bit()) {
135 if (ABIName == "lp64e")
136 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S64";
137
138 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
139 }
140 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
141
142 if (ABIName == "ilp32e")
143 return "e-m:e-p:32:32-i64:64-n32-S32";
144
145 return "e-m:e-p:32:32-i64:64-n32-S128";
146}
147
149 std::optional<Reloc::Model> RM) {
150 return RM.value_or(Reloc::Static);
151}
152
154 StringRef CPU, StringRef FS,
155 const TargetOptions &Options,
156 std::optional<Reloc::Model> RM,
157 std::optional<CodeModel::Model> CM,
158 CodeGenOptLevel OL, bool JIT)
161 getEffectiveCodeModel(CM, CodeModel::Small), OL),
162 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
163 initAsmInfo();
164
165 // RISC-V supports the MachineOutliner.
166 setMachineOutliner(true);
168
169 if (TT.isOSFuchsia() && !TT.isArch64Bit())
170 report_fatal_error("Fuchsia is only supported for 64-bit");
171}
172
173const RISCVSubtarget *
175 Attribute CPUAttr = F.getFnAttribute("target-cpu");
176 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
177 Attribute FSAttr = F.getFnAttribute("target-features");
178
179 std::string CPU =
180 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
181 std::string TuneCPU =
182 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
183 std::string FS =
184 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
185
186 unsigned RVVBitsMin = RVVVectorBitsMinOpt;
187 unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
188
189 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
190 if (VScaleRangeAttr.isValid()) {
191 if (!RVVVectorBitsMinOpt.getNumOccurrences())
192 RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
193 std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
194 if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
195 RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
196 }
197
198 if (RVVBitsMin != -1U) {
199 // FIXME: Change to >= 32 when VLEN = 32 is supported.
200 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
201 isPowerOf2_32(RVVBitsMin))) &&
202 "V or Zve* extension requires vector length to be in the range of "
203 "64 to 65536 and a power 2!");
204 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
205 "Minimum V extension vector length should not be larger than its "
206 "maximum!");
207 }
208 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
209 isPowerOf2_32(RVVBitsMax))) &&
210 "V or Zve* extension requires vector length to be in the range of "
211 "64 to 65536 and a power 2!");
212
213 if (RVVBitsMin != -1U) {
214 if (RVVBitsMax != 0) {
215 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
216 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
217 }
218
219 RVVBitsMin = llvm::bit_floor(
220 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
221 }
222 RVVBitsMax =
223 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
224
226 raw_svector_ostream(Key) << "RVVMin" << RVVBitsMin << "RVVMax" << RVVBitsMax
227 << CPU << TuneCPU << FS;
228 auto &I = SubtargetMap[Key];
229 if (!I) {
230 // This needs to be done before we create a new subtarget since any
231 // creation will depend on the TM and the code generation flags on the
232 // function that reside in TargetOptions.
234 auto ABIName = Options.MCOptions.getABIName();
235 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
236 F.getParent()->getModuleFlag("target-abi"))) {
237 auto TargetABI = RISCVABI::getTargetABI(ABIName);
238 if (TargetABI != RISCVABI::ABI_Unknown &&
239 ModuleTargetABI->getString() != ABIName) {
240 report_fatal_error("-target-abi option != target-abi module flag");
241 }
242 ABIName = ModuleTargetABI->getString();
243 }
244 I = std::make_unique<RISCVSubtarget>(
245 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
246 }
247 return I.get();
248}
249
251 BumpPtrAllocator &Allocator, const Function &F,
252 const TargetSubtargetInfo *STI) const {
253 return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
254 F, STI);
255}
256
259 return TargetTransformInfo(RISCVTTIImpl(this, F));
260}
261
262// A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
263// for all memory accesses, so it is reasonable to assume that an
264// implementation has no-op address space casts. If an implementation makes a
265// change to this, they can override it here.
267 unsigned DstAS) const {
268 return true;
269}
270
271namespace {
272
273class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
274public:
275 RVVRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
276 : RegisterRegAllocBase(N, D, C) {}
277};
278
279static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
280 const TargetRegisterClass &RC) {
281 return RISCV::VRRegClass.hasSubClassEq(&RC) ||
282 RISCV::VRM2RegClass.hasSubClassEq(&RC) ||
283 RISCV::VRM4RegClass.hasSubClassEq(&RC) ||
284 RISCV::VRM8RegClass.hasSubClassEq(&RC) ||
285 RISCV::VRN2M1RegClass.hasSubClassEq(&RC) ||
286 RISCV::VRN2M2RegClass.hasSubClassEq(&RC) ||
287 RISCV::VRN2M4RegClass.hasSubClassEq(&RC) ||
288 RISCV::VRN3M1RegClass.hasSubClassEq(&RC) ||
289 RISCV::VRN3M2RegClass.hasSubClassEq(&RC) ||
290 RISCV::VRN4M1RegClass.hasSubClassEq(&RC) ||
291 RISCV::VRN4M2RegClass.hasSubClassEq(&RC) ||
292 RISCV::VRN5M1RegClass.hasSubClassEq(&RC) ||
293 RISCV::VRN6M1RegClass.hasSubClassEq(&RC) ||
294 RISCV::VRN7M1RegClass.hasSubClassEq(&RC) ||
295 RISCV::VRN8M1RegClass.hasSubClassEq(&RC);
296}
297
298static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
299
300static llvm::once_flag InitializeDefaultRVVRegisterAllocatorFlag;
301
302/// -riscv-rvv-regalloc=<fast|basic|greedy> command line option.
303/// This option could designate the rvv register allocator only.
304/// For example: -riscv-rvv-regalloc=basic
305static cl::opt<RVVRegisterRegAlloc::FunctionPassCtor, false,
307 RVVRegAlloc("riscv-rvv-regalloc", cl::Hidden,
309 cl::desc("Register allocator to use for RVV register."));
310
311static void initializeDefaultRVVRegisterAllocatorOnce() {
312 RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
313
314 if (!Ctor) {
315 Ctor = RVVRegAlloc;
316 RVVRegisterRegAlloc::setDefault(RVVRegAlloc);
317 }
318}
319
320static FunctionPass *createBasicRVVRegisterAllocator() {
321 return createBasicRegisterAllocator(onlyAllocateRVVReg);
322}
323
324static FunctionPass *createGreedyRVVRegisterAllocator() {
325 return createGreedyRegisterAllocator(onlyAllocateRVVReg);
326}
327
328static FunctionPass *createFastRVVRegisterAllocator() {
329 return createFastRegisterAllocator(onlyAllocateRVVReg, false);
330}
331
332static RVVRegisterRegAlloc basicRegAllocRVVReg("basic",
333 "basic register allocator",
334 createBasicRVVRegisterAllocator);
335static RVVRegisterRegAlloc
336 greedyRegAllocRVVReg("greedy", "greedy register allocator",
337 createGreedyRVVRegisterAllocator);
338
339static RVVRegisterRegAlloc fastRegAllocRVVReg("fast", "fast register allocator",
340 createFastRVVRegisterAllocator);
341
342class RISCVPassConfig : public TargetPassConfig {
343public:
344 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
345 : TargetPassConfig(TM, PM) {
346 if (TM.getOptLevel() != CodeGenOptLevel::None)
347 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
348 setEnableSinkAndFold(EnableSinkFold);
349 }
350
351 RISCVTargetMachine &getRISCVTargetMachine() const {
352 return getTM<RISCVTargetMachine>();
353 }
354
356 createMachineScheduler(MachineSchedContext *C) const override {
357 ScheduleDAGMILive *DAG = nullptr;
361 DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
362 }
363 return DAG;
364 }
365
366 void addIRPasses() override;
367 bool addPreISel() override;
368 void addCodeGenPrepare() override;
369 bool addInstSelector() override;
370 bool addIRTranslator() override;
371 void addPreLegalizeMachineIR() override;
372 bool addLegalizeMachineIR() override;
373 void addPreRegBankSelect() override;
374 bool addRegBankSelect() override;
375 bool addGlobalInstructionSelect() override;
376 void addPreEmitPass() override;
377 void addPreEmitPass2() override;
378 void addPreSched2() override;
379 void addMachineSSAOptimization() override;
380 FunctionPass *createRVVRegAllocPass(bool Optimized);
381 bool addRegAssignAndRewriteFast() override;
382 bool addRegAssignAndRewriteOptimized() override;
383 void addPreRegAlloc() override;
384 void addPostRegAlloc() override;
385 void addFastRegAlloc() override;
386};
387} // namespace
388
390 return new RISCVPassConfig(*this, PM);
391}
392
393FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {
394 // Initialize the global default.
395 llvm::call_once(InitializeDefaultRVVRegisterAllocatorFlag,
396 initializeDefaultRVVRegisterAllocatorOnce);
397
398 RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
399 if (Ctor != useDefaultRegisterAllocator)
400 return Ctor();
401
402 if (Optimized)
403 return createGreedyRVVRegisterAllocator();
404
405 return createFastRVVRegisterAllocator();
406}
407
408bool RISCVPassConfig::addRegAssignAndRewriteFast() {
410 addPass(createRVVRegAllocPass(false));
412}
413
414bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
416 addPass(createRVVRegAllocPass(true));
417 addPass(createVirtRegRewriter(false));
418 }
420}
421
422void RISCVPassConfig::addIRPasses() {
424
425 if (getOptLevel() != CodeGenOptLevel::None) {
428
432 }
433
435}
436
437bool RISCVPassConfig::addPreISel() {
438 if (TM->getOptLevel() != CodeGenOptLevel::None) {
439 // Add a barrier before instruction selection so that we will not get
440 // deleted block address after enabling default outlining. See D99707 for
441 // more details.
442 addPass(createBarrierNoopPass());
443 }
444
446 addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
447 /* OnlyOptimizeForSize */ false,
448 /* MergeExternalByDefault */ true));
449 }
450
451 return false;
452}
453
454void RISCVPassConfig::addCodeGenPrepare() {
455 if (getOptLevel() != CodeGenOptLevel::None)
458}
459
460bool RISCVPassConfig::addInstSelector() {
461 addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
462
463 return false;
464}
465
466bool RISCVPassConfig::addIRTranslator() {
467 addPass(new IRTranslator(getOptLevel()));
468 return false;
469}
470
471void RISCVPassConfig::addPreLegalizeMachineIR() {
472 if (getOptLevel() == CodeGenOptLevel::None) {
474 } else {
476 }
477}
478
479bool RISCVPassConfig::addLegalizeMachineIR() {
480 addPass(new Legalizer());
481 return false;
482}
483
484void RISCVPassConfig::addPreRegBankSelect() {
485 if (getOptLevel() != CodeGenOptLevel::None)
487}
488
489bool RISCVPassConfig::addRegBankSelect() {
490 addPass(new RegBankSelect());
491 return false;
492}
493
494bool RISCVPassConfig::addGlobalInstructionSelect() {
495 addPass(new InstructionSelect(getOptLevel()));
496 return false;
497}
498
499void RISCVPassConfig::addPreSched2() {
501
502 // Emit KCFI checks for indirect calls.
503 addPass(createKCFIPass());
504}
505
506void RISCVPassConfig::addPreEmitPass() {
507 addPass(&BranchRelaxationPassID);
509
510 // TODO: It would potentially be better to schedule copy propagation after
511 // expanding pseudos (in addPreEmitPass2). However, performing copy
512 // propagation after the machine outliner (which runs after addPreEmitPass)
513 // currently leads to incorrect code-gen, where copies to registers within
514 // outlined functions are removed erroneously.
515 if (TM->getOptLevel() >= CodeGenOptLevel::Default &&
518}
519
520void RISCVPassConfig::addPreEmitPass2() {
521 if (TM->getOptLevel() != CodeGenOptLevel::None) {
522 addPass(createRISCVMoveMergePass());
523 // Schedule PushPop Optimization before expansion of Pseudo instruction,
524 // ensuring return instruction is detected correctly.
526 }
528
529 // Schedule the expansion of AMOs at the last possible moment, avoiding the
530 // possibility for other passes to break the requirements for forward
531 // progress in the LR/SC block.
533
534 // KCFI indirect call checks are lowered to a bundle.
535 addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
536 return MF.getFunction().getParent()->getModuleFlag("kcfi");
537 }));
538}
539
540void RISCVPassConfig::addMachineSSAOptimization() {
541 addPass(createRISCVFoldMasksPass());
542
544
546 addPass(&MachineCombinerID);
547
548 if (TM->getTargetTriple().isRISCV64()) {
549 addPass(createRISCVOptWInstrsPass());
550 }
551}
552
553void RISCVPassConfig::addPreRegAlloc() {
555 if (TM->getOptLevel() != CodeGenOptLevel::None)
558 if (TM->getOptLevel() != CodeGenOptLevel::None &&
563}
564
565void RISCVPassConfig::addFastRegAlloc() {
566 addPass(&InitUndefID);
568}
569
570
571void RISCVPassConfig::addPostRegAlloc() {
572 if (TM->getOptLevel() != CodeGenOptLevel::None &&
575}
576
580}
581
584 const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
585 return new yaml::RISCVMachineFunctionInfo(*MFI);
586}
587
590 SMDiagnostic &Error, SMRange &SourceRange) const {
591 const auto &YamlMFI =
592 static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
593 PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
594 return false;
595}
static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static const Function * getParent(const Value *V)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool > EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden, cl::desc("Enable Split RegisterAlloc for RVV"), cl::init(true))
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMISchedLoadClustering("riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), cl::init(false))
This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
Definition: Attributes.cpp:381
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:375
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
A single uniqued string.
Definition: Metadata.h:720
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This implementation is used for RISC-V ELF targets.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
const RISCVSubtarget * getSubtargetImpl() const =delete
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
RegisterPassParser class - Handle the addition of new machine passes.
RegisterRegAllocBase class - Track the registration of register allocators.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:557
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:558
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:95
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::string TargetFS
Definition: TargetMachine.h:97
std::string TargetCPU
Definition: TargetMachine.h:96
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
MCTargetOptions MCOptions
Machine level options.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:690
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
ABI getTargetABI(StringRef ABIName)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
FunctionPass * createRISCVPostLegalizerCombiner()
void initializeRISCVPushPopOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
void initializeRISCVFoldMasksPass(PassRegistry &)
FunctionPass * createRISCVMoveMergePass()
createRISCVMoveMergePass - returns an instance of the move merge pass.
char & InitUndefID
Definition: InitUndef.cpp:98
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
FunctionPass * createRISCVPostRAExpandPseudoPass()
FunctionPass * createRISCVInsertReadWriteCSRPass()
Target & getTheRISCV32Target()
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
void initializeRISCVDAGToDAGISelPass(PassRegistry &)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeRISCVPostRAExpandPseudoPass(PassRegistry &)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
FunctionPass * createRISCVPreLegalizerCombiner()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createRISCVO0PreLegalizerCombiner()
FunctionPass * createRISCVPushPopOptimizationPass()
createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
void initializeRISCVInsertWriteVXRMPass(PassRegistry &)
FunctionPass * createRISCVFoldMasksPass()
FunctionPass * createLoopDataPrefetchPass()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createRISCVOptWInstrsPass()
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
void initializeRISCVOptWInstrsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeRISCVCodeGenPreparePass(PassRegistry &)
Target & getTheRISCV64Target()
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)
void initializeKCFIPass(PassRegistry &)
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)
FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
Definition: VirtRegMap.cpp:645
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
Definition: bit.h:327
FunctionPass * createRISCVInsertWriteVXRMPass()
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
void initializeRISCVPostLegalizerCombinerPass(PassRegistry &)
void initializeRISCVMoveMergePass(PassRegistry &)
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
#define N
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
The llvm::once_flag structure.
Definition: Threading.h:68
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.