46 "riscv-enable-copyelim",
53 cl::desc(
"Enable the global merge pass"));
57 cl::desc(
"Enable the machine combiner pass"),
61 "riscv-v-vector-bits-max",
62 cl::desc(
"Assume V extension vector registers are at most this big, "
63 "with zero meaning no maximum size is assumed."),
67 "riscv-v-vector-bits-min",
68 cl::desc(
"Assume V extension vector registers are at least this big, "
69 "with zero meaning no minimum size is assumed. A value of -1 "
70 "means use Zvl*b extension. This is primarily used to enable "
71 "autovectorization with fixed width vectors."),
75 "riscv-enable-copy-propagation",
76 cl::desc(
"Enable the copy propagation with RISC-V copy instr"),
81 cl::desc(
"Enable the pass that removes dead"
82 " definitons and replaces stores to"
83 " them with stores to x0"),
88 cl::desc(
"Enable sinking and folding of instruction copies"),
93 cl::desc(
"Enable the loop data prefetch pass"),
98 cl::desc(
"Enable load clustering in the machine scheduler"),
102 "riscv-vsetvl-after-rvv-regalloc",
cl::Hidden,
103 cl::desc(
"Insert vsetvls after vector register allocation"),
136 if (TT.isArch64Bit()) {
137 if (ABIName ==
"lp64e")
138 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S64";
140 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
142 assert(TT.isArch32Bit() &&
"only RV32 and RV64 are currently supported");
144 if (ABIName ==
"ilp32e")
145 return "e-m:e-p:32:32-i64:64-n32-S32";
147 return "e-m:e-p:32:32-i64:64-n32-S128";
151 std::optional<Reloc::Model> RM) {
158 std::optional<Reloc::Model> RM,
159 std::optional<CodeModel::Model> CM,
171 if (TT.isOSFuchsia() && !TT.isArch64Bit())
177 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
178 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
179 Attribute FSAttr =
F.getFnAttribute(
"target-features");
183 std::string TuneCPU =
191 Attribute VScaleRangeAttr =
F.getFnAttribute(Attribute::VScaleRange);
192 if (VScaleRangeAttr.
isValid()) {
200 if (RVVBitsMin != -1U) {
202 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
204 "V or Zve* extension requires vector length to be in the range of "
205 "64 to 65536 and a power 2!");
206 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
207 "Minimum V extension vector length should not be larger than its "
210 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
212 "V or Zve* extension requires vector length to be in the range of "
213 "64 to 65536 and a power 2!");
215 if (RVVBitsMin != -1U) {
216 if (RVVBitsMax != 0) {
217 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
218 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
222 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
225 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
229 << CPU << TuneCPU << FS;
230 auto &
I = SubtargetMap[Key];
237 if (
const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
238 F.getParent()->getModuleFlag(
"target-abi"))) {
241 ModuleTargetABI->getString() != ABIName) {
244 ABIName = ModuleTargetABI->getString();
246 I = std::make_unique<RISCVSubtarget>(
247 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *
this);
255 return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(
Allocator,
269 unsigned DstAS)
const {
295static cl::opt<RVVRegisterRegAlloc::FunctionPassCtor,
false,
299 cl::desc(
"Register allocator to use for RVV register."));
301static void initializeDefaultRVVRegisterAllocatorOnce() {
306 RVVRegisterRegAlloc::setDefault(RVVRegAlloc);
314static FunctionPass *createGreedyRVVRegisterAllocator() {
322static RVVRegisterRegAlloc basicRegAllocRVVReg(
"basic",
323 "basic register allocator",
324 createBasicRVVRegisterAllocator);
325static RVVRegisterRegAlloc
326 greedyRegAllocRVVReg(
"greedy",
"greedy register allocator",
327 createGreedyRVVRegisterAllocator);
329static RVVRegisterRegAlloc fastRegAllocRVVReg(
"fast",
"fast register allocator",
330 createFastRVVRegisterAllocator);
336 if (
TM.getOptLevel() != CodeGenOptLevel::None)
342 return getTM<RISCVTargetMachine>();
351 DAG->
TII, DAG->
TRI,
true));
356 void addIRPasses()
override;
357 bool addPreISel()
override;
358 void addCodeGenPrepare()
override;
359 bool addInstSelector()
override;
360 bool addIRTranslator()
override;
361 void addPreLegalizeMachineIR()
override;
362 bool addLegalizeMachineIR()
override;
363 void addPreRegBankSelect()
override;
364 bool addRegBankSelect()
override;
365 bool addGlobalInstructionSelect()
override;
366 void addPreEmitPass()
override;
367 void addPreEmitPass2()
override;
368 void addPreSched2()
override;
369 void addMachineSSAOptimization()
override;
371 bool addRegAssignAndRewriteFast()
override;
372 bool addRegAssignAndRewriteOptimized()
override;
373 void addPreRegAlloc()
override;
374 void addPostRegAlloc()
override;
375 void addFastRegAlloc()
override;
380 return new RISCVPassConfig(*
this, PM);
383FunctionPass *RISCVPassConfig::createRVVRegAllocPass(
bool Optimized) {
386 initializeDefaultRVVRegisterAllocatorOnce);
393 return createGreedyRVVRegisterAllocator();
395 return createFastRVVRegisterAllocator();
398bool RISCVPassConfig::addRegAssignAndRewriteFast() {
399 addPass(createRVVRegAllocPass(
false));
408bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
409 addPass(createRVVRegAllocPass(
true));
419void RISCVPassConfig::addIRPasses() {
434bool RISCVPassConfig::addPreISel() {
451void RISCVPassConfig::addCodeGenPrepare() {
457bool RISCVPassConfig::addInstSelector() {
463bool RISCVPassConfig::addIRTranslator() {
468void RISCVPassConfig::addPreLegalizeMachineIR() {
476bool RISCVPassConfig::addLegalizeMachineIR() {
481void RISCVPassConfig::addPreRegBankSelect() {
486bool RISCVPassConfig::addRegBankSelect() {
491bool RISCVPassConfig::addGlobalInstructionSelect() {
496void RISCVPassConfig::addPreSched2() {
503void RISCVPassConfig::addPreEmitPass() {
516void RISCVPassConfig::addPreEmitPass2() {
537void RISCVPassConfig::addMachineSSAOptimization() {
545 if (
TM->getTargetTriple().isRISCV64()) {
550void RISCVPassConfig::addPreRegAlloc() {
569void RISCVPassConfig::addFastRegAlloc() {
575void RISCVPassConfig::addPostRegAlloc() {
602 const auto &YamlMFI =
unsigned const MachineRegisterInfo * MRI
static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static const Function * getParent(const Value *V)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static std::string computeDataLayout()
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool > EnableVSETVLIAfterRVVRegAlloc("riscv-vsetvl-after-rvv-regalloc", cl::Hidden, cl::desc("Insert vsetvls after vector register allocation"), cl::init(true))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMISchedLoadClustering("riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), cl::init(false))
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Target-Independent Code Generator Pass Configuration Options pass.
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isValid() const
Return true if the attribute is any kind of attribute.
Allocate memory in an ever growing pool, as if by bump-pointer.
Lightweight error class with error context and mandatory checking.
FunctionPass class - This class is used to implement most global optimizations.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This class provides access to building LLVM's passes.
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This implementation is used for RISC-V ELF targets.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
const RISCVSubtarget * getSubtargetImpl() const =delete
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
RegisterPassParser class - Handle the addition of new machine passes.
RegisterRegAllocBase class - Track the registration of register allocators.
FunctionPass *(*)() FunctionPassCtor
Wrapper class representing virtual and physical registers.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
const TargetInstrInfo * TII
Target instruction information.
const TargetRegisterInfo * TRI
Target processor register info.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
MCTargetOptions MCOptions
Machine level options.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
A raw_ostream that writes to an SmallVector or SmallString.
Interfaces for registering analysis passes, producing common pass manager configurations,...
@ C
The default llvm calling convention, compatible with C.
ABI getTargetABI(StringRef ABIName)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createRISCVLandingPadSetupPass()
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
FunctionPass * createRISCVPostLegalizerCombiner()
void initializeRISCVPushPopOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
FunctionPass * createRISCVMoveMergePass()
createRISCVMoveMergePass - returns an instance of the move merge pass.
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
FunctionPass * createRISCVPostRAExpandPseudoPass()
FunctionPass * createRISCVInsertReadWriteCSRPass()
Target & getTheRISCV32Target()
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeRISCVPostRAExpandPseudoPass(PassRegistry &)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
FunctionPass * createRISCVPreLegalizerCombiner()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createRISCVO0PreLegalizerCombiner()
void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &)
FunctionPass * createRISCVPushPopOptimizationPass()
createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
void initializeRISCVInsertWriteVXRMPass(PassRegistry &)
FunctionPass * createLoopDataPrefetchPass()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
CodeGenOptLevel
Code generation optimization level.
FunctionPass * createRISCVIndirectBranchTrackingPass()
FunctionPass * createRISCVOptWInstrsPass()
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
void initializeRISCVOptWInstrsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeRISCVCodeGenPreparePass(PassRegistry &)
Target & getTheRISCV64Target()
char & RISCVInsertVSETVLIID
FunctionPass * createRISCVVectorPeepholePass()
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)
void initializeKCFIPass(PassRegistry &)
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)
FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false, bool MergeConstantByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
FunctionPass * createRISCVPreRAExpandPseudoPass()
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
FunctionPass * createRISCVInsertWriteVXRMPass()
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeRISCVVectorPeepholePass(PassRegistry &)
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
void initializeRISCVPostLegalizerCombinerPass(PassRegistry &)
void initializeRISCVMoveMergePass(PassRegistry &)
Implement std::hash so that hash_code can be used in STL containers.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
static bool isRVVRegClass(const TargetRegisterClass *RC)
RegisterTargetMachine - Helper template for registering a target machine implementation,...
The llvm::once_flag structure.
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.