RISCVTargetMachine.cpp File Reference

#include "RISCVTargetMachine.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVMacroFusion.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/IPO.h"
#include <optional>

Go to the source code of this file.

Functions
LLVM_EXTERNAL_VISIBILITY void	LLVMInitializeRISCVTarget ()
static StringRef	computeDataLayout (const Triple &TT)
static Reloc::Model	getEffectiveRelocModel (const Triple &TT, std::optional< Reloc::Model > RM)

Variables
static cl::opt< bool >	EnableRedundantCopyElimination ("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< cl::boolOrDefault >	EnableGlobalMerge ("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool >	EnableMachineCombiner ("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< unsigned >	RVVVectorBitsMaxOpt ("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< int >	RVVVectorBitsMinOpt ("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static cl::opt< bool >	EnableRISCVCopyPropagation ("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)

Function Documentation

computeDataLayout()

static StringRef computeDataLayout ( const Triple &  TT )

static

Definition at line 91 of file RISCVTargetMachine.cpp.

References assert().

getEffectiveRelocModel()

static Reloc::Model getEffectiveRelocModel ( const Triple &  TT, std::optional< Reloc::Model >  RM  )

static

Definition at line 98 of file RISCVTargetMachine.cpp.

References llvm::Reloc::Static.

LLVMInitializeRISCVTarget()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget

(

)

Definition at line 74 of file RISCVTargetMachine.cpp.

References llvm::PassRegistry::getPassRegistry(), llvm::getTheRISCV32Target(), llvm::getTheRISCV64Target(), llvm::initializeGlobalISel(), llvm::initializeRISCVCodeGenPreparePass(), llvm::initializeRISCVDAGToDAGISelPass(), llvm::initializeRISCVExpandPseudoPass(), llvm::initializeRISCVGatherScatterLoweringPass(), llvm::initializeRISCVInitUndefPass(), llvm::initializeRISCVInsertVSETVLIPass(), llvm::initializeRISCVMakeCompressibleOptPass(), llvm::initializeRISCVMergeBaseOffsetOptPass(), llvm::initializeRISCVOptWInstrsPass(), llvm::initializeRISCVPreRAExpandPseudoPass(), X, and Y.

Variable Documentation

EnableGlobalMerge

cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass")) ( "riscv-enable-global-merge"  , cl::Hidden  , cl::desc("Enable the global merge pass")    )

static

EnableMachineCombiner

cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden) ( "riscv-enable-machine-combiner"  , cl::desc("Enable the machine combiner pass")  , cl::init(true)  , cl::Hidden    )

static

EnableRedundantCopyElimination

cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden) ( "riscv-enable-copyelim"  , cl::desc("Enable the redundant copy elimination pass")  , cl::init(true)  , cl::Hidden    )

static

EnableRISCVCopyPropagation

cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden) ( "riscv-enable-copy-propagation"  , cl::desc("Enable the copy propagation with RISC-V copy instr")  , cl::init(true)  , cl::Hidden    )

static

RVVVectorBitsMaxOpt

cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden) ( "riscv-v-vector-bits-max"  , cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed.")  , cl::init(0)  , cl::Hidden    )

static

Referenced by llvm::RISCVTargetMachine::getSubtargetImpl().

RVVVectorBitsMinOpt

cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden) ( "riscv-v-vector-bits-min"  , cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors.")  , cl::init(-1)  , cl::Hidden    )

static

Referenced by llvm::RISCVTargetMachine::getSubtargetImpl().