LLVM  17.0.0git
LanaiTargetMachine.cpp
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1 //===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Lanai target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "LanaiTargetMachine.h"
14 
15 #include "Lanai.h"
17 #include "LanaiTargetObjectFile.h"
21 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/MC/TargetRegistry.h"
27 #include <optional>
28 
29 using namespace llvm;
30 
31 namespace llvm {
33 } // namespace llvm
34 
36  // Register the target.
41 }
42 
43 static std::string computeDataLayout() {
44  // Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
45  return "E" // Big endian
46  "-m:e" // ELF name manging
47  "-p:32:32" // 32-bit pointers, 32 bit aligned
48  "-i64:64" // 64 bit integers, 64 bit aligned
49  "-a:0:32" // 32 bit alignment of objects of aggregate type
50  "-n32" // 32 bit native integer width
51  "-S64"; // 64 bit natural stack alignment
52 }
53 
54 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
55  return RM.value_or(Reloc::PIC_);
56 }
57 
59  const Target &T, const Triple &TT, StringRef Cpu, StringRef FeatureString,
60  const TargetOptions &Options, std::optional<Reloc::Model> RM,
61  std::optional<CodeModel::Model> CodeModel, CodeGenOpt::Level OptLevel,
62  bool JIT)
63  : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
66  OptLevel),
67  Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(),
68  OptLevel),
69  TLOF(new LanaiTargetObjectFile()) {
70  initAsmInfo();
71 }
72 
75  return TargetTransformInfo(LanaiTTIImpl(this, F));
76 }
77 
80  const TargetSubtargetInfo *STI) const {
81  return LanaiMachineFunctionInfo::create<LanaiMachineFunctionInfo>(Allocator,
82  F, STI);
83 }
84 
85 namespace {
86 // Lanai Code Generator Pass Configuration Options.
87 class LanaiPassConfig : public TargetPassConfig {
88 public:
91 
92  LanaiTargetMachine &getLanaiTargetMachine() const {
93  return getTM<LanaiTargetMachine>();
94  }
95 
96  bool addInstSelector() override;
97  void addPreSched2() override;
98  void addPreEmitPass() override;
99 };
100 } // namespace
101 
104  return new LanaiPassConfig(*this, &PassManager);
105 }
106 
107 // Install an instruction selector pass.
108 bool LanaiPassConfig::addInstSelector() {
109  addPass(createLanaiISelDag(getLanaiTargetMachine()));
110  return false;
111 }
112 
113 // Implemented by targets that want to run passes immediately before
114 // machine code is emitted.
115 void LanaiPassConfig::addPreEmitPass() {
116  addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine()));
117 }
118 
119 // Run passes after prolog-epilog insertion and before the second instruction
120 // scheduling pass.
121 void LanaiPassConfig::addPreSched2() {
123 }
llvm::createLanaiDelaySlotFillerPass
FunctionPass * createLanaiDelaySlotFillerPass(const LanaiTargetMachine &TM)
Definition: LanaiDelaySlotFiller.cpp:84
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LanaiTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &pass_manager) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: LanaiTargetMachine.cpp:103
llvm::TargetMachine::STI
std::unique_ptr< const MCSubtargetInfo > STI
Definition: TargetMachine.h:109
llvm::TargetOptions
Definition: TargetOptions.h:124
T
llvm::Function
Definition: Function.h:59
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:31
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
computeDataLayout
static std::string computeDataLayout()
Definition: LanaiTargetMachine.cpp:43
Lanai.h
llvm::LanaiTTIImpl
Definition: LanaiTargetTransformInfo.h:28
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
LLVMInitializeLanaiTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget()
Definition: LanaiTargetMachine.cpp:35
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Reloc::Model
Model
Definition: CodeGen.h:25
FormattedStream.h
llvm::getTheLanaiTarget
Target & getTheLanaiTarget()
Definition: LanaiTargetInfo.cpp:14
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::initializeLanaiDAGToDAGISelPass
void initializeLanaiDAGToDAGISelPass(PassRegistry &)
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1354
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::LanaiTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: LanaiTargetMachine.cpp:74
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::createLanaiMemAluCombinerPass
FunctionPass * createLanaiMemAluCombinerPass()
Definition: LanaiMemAluCombiner.cpp:421
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:510
LanaiTargetInfo.h
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
TargetPassConfig.h
LanaiTargetTransformInfo.h
llvm::LanaiTargetMachine::createMachineFunctionInfo
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
Definition: LanaiTargetMachine.cpp:78
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:43
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:499
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:25
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::initializeLanaiMemAluCombinerPass
void initializeLanaiMemAluCombinerPass(PassRegistry &)
llvm::createLanaiISelDag
FunctionPass * createLanaiISelDag(LanaiTargetMachine &TM)
Definition: LanaiISelDAGToDAG.cpp:335
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
LanaiTargetObjectFile.h
llvm::PassManager
Manages a sequence of passes over a particular unit of IR.
Definition: PassManager.h:469
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:417
llvm::LanaiTargetMachine
Definition: LanaiTargetMachine.h:25
LanaiMachineFunctionInfo.h
llvm::LanaiTargetObjectFile
Definition: LanaiTargetObjectFile.h:15
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
LanaiTargetMachine.h
llvm::CodeGenOpt::Level
Level
Code generation optimization level.
Definition: CodeGen.h:57
llvm::LanaiTargetMachine::LanaiTargetMachine
LanaiTargetMachine(const Target &TheTarget, const Triple &TargetTriple, StringRef Cpu, StringRef FeatureString, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CodeModel, CodeGenOpt::Level OptLevel, bool JIT)
Definition: LanaiTargetMachine.cpp:58
TargetRegistry.h
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
llvm::codegen::getCodeModel
CodeModel::Model getCodeModel()
TargetLoweringObjectFileImpl.h