36#define DEBUG_TYPE "lanai-isel"
37#define PASS_NAME "Lanai DAG->DAG Pattern Instruction Selection"
53 LanaiDAGToDAGISel() =
delete;
64 std::vector<SDValue> &OutOps)
override;
68#include "LanaiGenDAGISel.inc"
75 void selectFrameIndex(
SDNode *
N);
87 return CurDAG->getTargetConstant(Imm,
DL, MVT::i32);
102char LanaiDAGToDAGISel::ID = 0;
112 if (canBeRepresentedAsSls(*CN)) {
113 int32_t
Imm = CN->getSExtValue();
114 Offset = CurDAG->getTargetConstant(Imm,
DL, CN->getValueType(0));
134 if (isInt<16>(CN->getSExtValue())) {
135 int16_t
Imm = CN->getSExtValue();
136 Offset = CurDAG->getTargetConstant(Imm,
DL, CN->getValueType(0));
137 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
138 AluOp = CurDAG->getTargetConstant(
LPAC::ADD,
DL, MVT::i32);
143 if (canBeRepresentedAsSls(*CN))
147 if (isInt<10>(CN->getSExtValue())) {
148 int16_t
Imm = CN->getSExtValue();
149 Offset = CurDAG->getTargetConstant(Imm,
DL, CN->getValueType(0));
150 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
151 AluOp = CurDAG->getTargetConstant(
LPAC::ADD,
DL, MVT::i32);
159 Base = CurDAG->getTargetFrameIndex(
161 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
162 Offset = CurDAG->getTargetConstant(0,
DL, MVT::i32);
163 AluOp = CurDAG->getTargetConstant(
LPAC::ADD,
DL, MVT::i32);
175 AluOp = CurDAG->getTargetConstant(
LPAC::ADD,
DL, MVT::i32);
178 if ((RiMode && isInt<16>(CN->getSExtValue())) ||
179 (!RiMode && isInt<10>(CN->getSExtValue()))) {
182 dyn_cast<FrameIndexSDNode>(
Addr.getOperand(0))) {
183 Base = CurDAG->getTargetFrameIndex(
185 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
190 Offset = CurDAG->getTargetConstant(CN->getSExtValue(),
DL, MVT::i32);
196 if (AluOperator ==
ISD::OR && RiMode &&
201 Offset = CurDAG->getTargetConstant(0,
DL, MVT::i32);
202 AluOp = CurDAG->getTargetConstant(
LPAC::ADD,
DL, MVT::i32);
264 if (isInt<16>(CN->getSExtValue()))
277 R1 =
Addr.getOperand(0);
279 AluOp = CurDAG->getTargetConstant(AluCode,
SDLoc(
Addr), MVT::i32);
287bool LanaiDAGToDAGISel::SelectInlineAsmMemoryOperand(
289 std::vector<SDValue> &OutOps) {
291 switch (ConstraintCode) {
294 case InlineAsm::ConstraintCode::m:
295 if (!selectAddrRr(
Op, Op0, Op1, AluOp) &&
296 !selectAddrRi(
Op, Op0, Op1, AluOp))
301 OutOps.push_back(Op0);
302 OutOps.push_back(Op1);
303 OutOps.push_back(AluOp);
313 if (
Node->isMachineOpcode()) {
320 EVT VT =
Node->getValueType(0);
323 if (VT == MVT::i32) {
327 if (ConstNode->
isZero()) {
328 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
330 return ReplaceNode(
Node,
New.getNode());
335 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
337 return ReplaceNode(
Node,
New.getNode());
342 selectFrameIndex(
Node);
352void LanaiDAGToDAGISel::selectFrameIndex(
SDNode *
Node) {
354 SDValue Imm = CurDAG->getTargetConstant(0,
DL, MVT::i32);
355 int FI = cast<FrameIndexSDNode>(
Node)->getIndex();
356 EVT VT =
Node->getValueType(0);
357 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
358 unsigned Opc = Lanai::ADD_I_LO;
359 if (
Node->hasOneUse()) {
360 CurDAG->SelectNodeTo(
Node, Opc, VT, TFI, Imm);
363 ReplaceNode(
Node, CurDAG->getMachineNode(Opc,
DL, VT, TFI, Imm));
369 return new LanaiDAGToDAGISel(
TM);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static constexpr uint32_t Opcode
DEMANGLE_DUMP_METHOD void dump() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Primary interface to the complete machine description for the target machine.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ ADD
Simple integer binary arithmetic operators.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ SHL
Shift and rotation operations.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
static AluCode isdToLanaiAluCode(ISD::NodeType Node_type)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createLanaiISelDag(LanaiTargetMachine &TM)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.