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RISCVAsmBackend.h
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1 //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
11 
14 #include "Utils/RISCVBaseInfo.h"
15 #include "llvm/MC/MCAsmBackend.h"
18 
19 namespace llvm {
20 class MCAssembler;
21 class MCObjectTargetWriter;
22 class raw_ostream;
23 
24 class RISCVAsmBackend : public MCAsmBackend {
25  const MCSubtargetInfo &STI;
26  uint8_t OSABI;
27  bool Is64Bit;
28  bool ForceRelocs = false;
31 
32 public:
33  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
34  const MCTargetOptions &Options)
35  : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
36  TargetOptions(Options) {
37  TargetABI = RISCVABI::computeTargetABI(
38  STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName());
40  }
41  ~RISCVAsmBackend() override {}
42 
43  void setForceRelocs() { ForceRelocs = true; }
44 
45  // Returns true if relocations will be forced for shouldForceRelocation by
46  // default. This will be true if relaxation is enabled or had previously
47  // been enabled.
48  bool willForceRelocations() const {
49  return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax];
50  }
51 
52  // Generate diff expression relocations if the relax feature is enabled or had
53  // previously been enabled, otherwise it is safe for the assembler to
54  // calculate these internally.
55  bool requiresDiffExpressionRelocations() const override {
56  return willForceRelocations();
57  }
58 
59  // Return Size with extra Nop Bytes for alignment directive in code section.
61  unsigned &Size) override;
62 
63  // Insert target specific fixup type for alignment directive in code section.
65  const MCAsmLayout &Layout,
66  MCAlignFragment &AF) override;
67 
68  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
70  uint64_t Value, bool IsResolved,
71  const MCSubtargetInfo *STI) const override;
72 
73  std::unique_ptr<MCObjectTargetWriter>
74  createObjectTargetWriter() const override;
75 
76  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
77  const MCValue &Target) override;
78 
79  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
80  const MCRelaxableFragment *DF,
81  const MCAsmLayout &Layout) const override {
82  llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
83  }
84 
85  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
86  uint64_t Value,
87  const MCRelaxableFragment *DF,
88  const MCAsmLayout &Layout,
89  const bool WasForced) const override;
90 
91  unsigned getNumFixupKinds() const override {
93  }
94 
96  const static MCFixupKindInfo Infos[] = {
97  // This table *must* be in the order that the fixup_* kinds are defined in
98  // RISCVFixupKinds.h.
99  //
100  // name offset bits flags
101  { "fixup_riscv_hi20", 12, 20, 0 },
102  { "fixup_riscv_lo12_i", 20, 12, 0 },
103  { "fixup_riscv_lo12_s", 0, 32, 0 },
104  { "fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
105  { "fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsPCRel },
106  { "fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
107  { "fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
108  { "fixup_riscv_tprel_hi20", 12, 20, 0 },
109  { "fixup_riscv_tprel_lo12_i", 20, 12, 0 },
110  { "fixup_riscv_tprel_lo12_s", 0, 32, 0 },
111  { "fixup_riscv_tprel_add", 0, 0, 0 },
112  { "fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
113  { "fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
114  { "fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
115  { "fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116  { "fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel },
117  { "fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
118  { "fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel },
119  { "fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel },
120  { "fixup_riscv_relax", 0, 0, 0 },
121  { "fixup_riscv_align", 0, 0, 0 }
122  };
123  static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
124  "Not all fixup kinds added to Infos array");
125 
126  if (Kind < FirstTargetFixupKind)
127  return MCAsmBackend::getFixupKindInfo(Kind);
128 
129  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
130  "Invalid kind!");
131  return Infos[Kind - FirstTargetFixupKind];
132  }
133 
134  bool mayNeedRelaxation(const MCInst &Inst,
135  const MCSubtargetInfo &STI) const override;
136  unsigned getRelaxedOpcode(unsigned Op) const;
137 
138  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
139  MCInst &Res) const override;
140 
141 
142  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
143 
144  const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
145  RISCVABI::ABI getTargetABI() const { return TargetABI; }
146 };
147 }
148 
149 #endif
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This represents an "assembler immediate".
Definition: MCValue.h:39
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:77
const Triple & getTargetTriple() const
RISCVABI::ABI getTargetABI() const
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
const FeatureBitset & getFeatureBits() const
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
bool willForceRelocations() const
bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) override
Hook to check if extra nop bytes must be inserted for alignment directive.
unsigned getRelaxedOpcode(unsigned Op) const
bool writeNopData(raw_ostream &OS, uint64_t Count) const override
Write an (optimal) nop sequence of Count bytes to the given output.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:272
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) override
Hook which indicates if the target requires a fixup to be generated when handling an align directive ...
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
const MCTargetOptions & getTargetOptions() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
PowerPC TLS Dynamic Call Fixup
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
Target - Wrapper for Target specific information.
bool requiresDiffExpressionRelocations() const override
Check whether the given target requires emitting differences of two symbols as a set of relocations...
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const override
Relax the instruction in the given fragment to the next wider instruction.
Target independent information on a fixup kind.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:74
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)