#include "Target/RISCV/MCTargetDesc/RISCVAsmBackend.h"

Inheritance diagram for llvm::RISCVAsmBackend:

Public Member Functions
	RISCVAsmBackend (const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)

	~RISCVAsmBackend () override=default

void	setForceRelocs ()

bool	shouldInsertExtraNopBytesForCodeAlign (const MCAlignFragment &AF, unsigned &Size) override
	Hook to check if extra nop bytes must be inserted for alignment directive.

bool	shouldInsertFixupForCodeAlign (MCAssembler &Asm, MCAlignFragment &AF) override
	Hook which indicates if the target requires a fixup to be generated when handling an align directive in an executable section.

bool	evaluateTargetFixup (const MCAssembler &Asm, const MCFixup &Fixup, const MCFragment DF, const MCValue &Target, const MCSubtargetInfo STI, uint64_t &Value, bool &WasForced) override

bool	handleAddSubRelocations (const MCAssembler &Asm, const MCFragment &F, const MCFixup &Fixup, const MCValue &Target, uint64_t &FixedValue) const override

void	applyFixup (const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
	Apply the `Value` for given `Fixup` into the provided data fragment, at the offset specified by the fixup and following the fixup kind as appropriate.

std::unique_ptr< MCObjectTargetWriter >	createObjectTargetWriter () const override

bool	shouldForceRelocation (const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI) override
	Hook to check if a relocation is needed for some target specific reason.

bool	fixupNeedsRelaxationAdvanced (const MCAssembler &Asm, const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const bool WasForced) const override
	Target specific predicate for whether a given fixup requires the associated instruction to be relaxed.

unsigned	getNumFixupKinds () const override
	Get the number of target specific fixup kinds.

std::optional< MCFixupKind >	getFixupKind (StringRef Name) const override
	Map a relocation name used in .reloc to a fixup kind.

const MCFixupKindInfo &	getFixupKindInfo (MCFixupKind Kind) const override
	Get information on a fixup kind.

bool	mayNeedRelaxation (const MCInst &Inst, const MCSubtargetInfo &STI) const override
	Check whether the given instruction may need relaxation.

unsigned	getRelaxedOpcode (unsigned Op) const

void	relaxInstruction (MCInst &Inst, const MCSubtargetInfo &STI) const override
	Relax the instruction in the given fragment to the next wider instruction.

bool	relaxDwarfLineAddr (const MCAssembler &Asm, MCDwarfLineAddrFragment &DF, bool &WasRelaxed) const override

bool	relaxDwarfCFA (const MCAssembler &Asm, MCDwarfCallFrameFragment &DF, bool &WasRelaxed) const override

std::pair< bool, bool >	relaxLEB128 (const MCAssembler &Asm, MCLEBFragment &LF, int64_t &Value) const override

bool	writeNopData (raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
	Write an (optimal) nop sequence of Count bytes to the given output.

const MCTargetOptions &	getTargetOptions () const

Public Member Functions inherited from llvm::MCAsmBackend
	MCAsmBackend (const MCAsmBackend &)=delete

MCAsmBackend &	operator= (const MCAsmBackend &)=delete

virtual	~MCAsmBackend ()

bool	allowLinkerRelaxation () const

virtual bool	allowAutoPadding () const
	Return true if this target might automatically pad instructions and thus need to emit padding enable/disable directives around sensative code.

virtual bool	allowEnhancedRelaxation () const
	Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and then we can increase its size in a tricky way for optimization.

virtual void	reset ()
	lifetime management

std::unique_ptr< MCObjectWriter >	createObjectWriter (raw_pwrite_stream &OS) const
	Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file.

std::unique_ptr< MCObjectWriter >	createDwoObjectWriter (raw_pwrite_stream &OS, raw_pwrite_stream &DwoOS) const
	Create an MCObjectWriter that writes two object files: a .o file which is linked into the final program and a .dwo file which is used by debuggers.

virtual std::unique_ptr< MCObjectTargetWriter >	createObjectTargetWriter () const =0

virtual unsigned	getMinimumNopSize () const
	Returns the minimum size of a nop in bytes on this target.

virtual unsigned	getMaximumNopSize (const MCSubtargetInfo &STI) const
	Returns the maximum size of a nop in bytes on this target.

virtual bool	writeNopData (raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
	Write an (optimal) nop sequence of Count bytes to the given output.

virtual void	finishLayout (MCAssembler const &Asm) const
	Give backend an opportunity to finish layout after relaxation.

virtual void	handleAssemblerFlag (MCAssemblerFlag Flag)
	Handle any target-specific assembler flags. By default, do nothing.

virtual uint64_t	generateCompactUnwindEncoding (const MCDwarfFrameInfo FI, const MCContext Ctxt) const
	Generate the compact unwind encoding for the CFI instructions.

virtual bool	isMicroMips (const MCSymbol *Sym) const
	Check whether a given symbol has been flagged with MICROMIPS flag.

bool	isDarwinCanonicalPersonality (const MCSymbol *Sym) const

virtual bool	fixupNeedsRelaxation (const MCFixup &Fixup, uint64_t Value) const
	Simple predicate for targets where !Resolved implies requiring relaxation.

Additional Inherited Members
Public Attributes inherited from llvm::MCAsmBackend
const llvm::endianness	Endian

const unsigned	RelaxFixupKind
	Fixup kind used for linker relaxation.

Protected Member Functions inherited from llvm::MCAsmBackend
	MCAsmBackend (llvm::endianness Endian, unsigned RelaxFixupKind=MaxFixupKind)

Detailed Description

Definition at line 24 of file RISCVAsmBackend.h.

Constructor & Destructor Documentation

◆ RISCVAsmBackend()

llvm::RISCVAsmBackend::RISCVAsmBackend	(	const MCSubtargetInfo &	STI,
		uint8_t	OSABI,
		bool	Is64Bit,
		const MCTargetOptions &	Options
	)

inline

Definition at line 32 of file RISCVAsmBackend.h.

References llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCSubtargetInfo::getTargetTriple(), and llvm::RISCVFeatures::validate().

◆ ~RISCVAsmBackend()

llvm::RISCVAsmBackend::~RISCVAsmBackend ( )

overridedefault

Member Function Documentation

◆ applyFixup()

void RISCVAsmBackend::applyFixup	(	const MCAssembler &	Asm,
		const MCFixup &	Fixup,
		const MCValue &	Target,
		MutableArrayRef< char >	Data,
		uint64_t	Value,
		bool	IsResolved,
		const MCSubtargetInfo *	STI
	)		const

overridevirtual

Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup and following the fixup kind as appropriate.

Errors (such as an out of range fixup value) should be reported via Ctx. The STI is present only for fragments of type MCRelaxableFragment and MCDataFragment with hasInstructions() == true.

Implements llvm::MCAsmBackend.

Definition at line 624 of file RISCVAsmBackend.cpp.

References adjustFixupValue(), llvm::alignTo(), assert(), llvm::Data, llvm::FirstLiteralRelocationKind, Fixup, getFixupKindInfo(), Info, and llvm::Offset.

◆ createObjectTargetWriter()

std::unique_ptr< MCObjectTargetWriter > RISCVAsmBackend::createObjectTargetWriter ( ) const

overridevirtual

Implements llvm::MCAsmBackend.

Definition at line 710 of file RISCVAsmBackend.cpp.

References llvm::createRISCVELFObjectWriter().

◆ evaluateTargetFixup()

bool RISCVAsmBackend::evaluateTargetFixup	(	const MCAssembler &	Asm,
		const MCFixup &	Fixup,
		const MCFragment *	DF,
		const MCValue &	Target,
		const MCSubtargetInfo *	STI,
		uint64_t &	Value,
		bool &	WasForced
	)

overridevirtual

◆ fixupNeedsRelaxationAdvanced()

bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced	(	const MCAssembler &	Asm,
		const MCFixup &	Fixup,
		bool	Resolved,
		uint64_t	Value,
		const MCRelaxableFragment *	DF,
		const bool	WasForced
	)		const

overridevirtual

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed.

Reimplemented from llvm::MCAsmBackend.

Definition at line 139 of file RISCVAsmBackend.cpp.

References Fixup, llvm::RISCV::fixup_riscv_branch, llvm::RISCV::fixup_riscv_rvc_branch, llvm::RISCV::fixup_riscv_rvc_jump, llvm::Offset, and RelaxBranches.

◆ getFixupKind()

std::optional< MCFixupKind > RISCVAsmBackend::getFixupKind ( StringRef Name ) const

overridevirtual

Map a relocation name used in .reloc to a fixup kind.

Reimplemented from llvm::MCAsmBackend.

Definition at line 37 of file RISCVAsmBackend.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), llvm::FirstLiteralRelocationKind, llvm::MCSubtargetInfo::getTargetTriple(), llvm::Triple::isOSBinFormatELF(), and Name.

◆ getFixupKindInfo()

const MCFixupKindInfo & RISCVAsmBackend::getFixupKindInfo ( MCFixupKind Kind ) const

overridevirtual

Get information on a fixup kind.

Reimplemented from llvm::MCAsmBackend.

Definition at line 55 of file RISCVAsmBackend.cpp.

References assert(), llvm::FirstLiteralRelocationKind, llvm::FirstTargetFixupKind, llvm::FK_NONE, llvm::MCFixupKindInfo::FKF_IsPCRel, llvm::MCFixupKindInfo::FKF_IsTarget, llvm::MCAsmBackend::getFixupKindInfo(), getNumFixupKinds(), and llvm::RISCV::NumTargetFixupKinds.

Referenced by applyFixup().

◆ getNumFixupKinds()

unsigned llvm::RISCVAsmBackend::getNumFixupKinds ( ) const

inlineoverridevirtual

Get the number of target specific fixup kinds.

Implements llvm::MCAsmBackend.

Definition at line 77 of file RISCVAsmBackend.h.

References llvm::RISCV::NumTargetFixupKinds.

Referenced by getFixupKindInfo().

◆ getRelaxedOpcode()

unsigned RISCVAsmBackend::getRelaxedOpcode ( unsigned Op ) const

Definition at line 345 of file RISCVAsmBackend.cpp.

Referenced by mayNeedRelaxation(), and relaxInstruction().

◆ getTargetOptions()

const MCTargetOptions & llvm::RISCVAsmBackend::getTargetOptions ( ) const

inline

Definition at line 102 of file RISCVAsmBackend.h.

◆ handleAddSubRelocations()

bool RISCVAsmBackend::handleAddSubRelocations	(	const MCAssembler &	Asm,
		const MCFragment &	F,
		const MCFixup &	Fixup,
		const MCValue &	Target,
		uint64_t &	FixedValue
	)		const

overridevirtual

Reimplemented from llvm::MCAsmBackend.

Definition at line 578 of file RISCVAsmBackend.cpp.

References A, B, llvm::MCFixup::create(), F, llvm::FirstLiteralRelocationKind, Fixup, llvm::FK_Data_1, llvm::FK_Data_2, llvm::FK_Data_4, llvm::FK_Data_8, llvm::FK_Data_leb128, llvm::MCValue::get(), and llvm_unreachable.

◆ mayNeedRelaxation()

bool RISCVAsmBackend::mayNeedRelaxation	(	const MCInst &	Inst,
		const MCSubtargetInfo &	STI
	)		const

overridevirtual

Check whether the given instruction may need relaxation.

Parameters

Inst	- The instruction to test.
STI	- The MCSubtargetInfo in effect when the instruction was encoded.

Reimplemented from llvm::MCAsmBackend.

Definition at line 371 of file RISCVAsmBackend.cpp.

References llvm::MCInst::getOpcode(), and getRelaxedOpcode().

◆ relaxDwarfCFA()

bool RISCVAsmBackend::relaxDwarfCFA	(	const MCAssembler &	Asm,
		MCDwarfCallFrameFragment &	DF,
		bool &	WasRelaxed
	)		const

overridevirtual

Reimplemented from llvm::MCAsmBackend.

Definition at line 268 of file RISCVAsmBackend.cpp.

References assert(), llvm::MCFixup::create(), llvm::Data, DF, llvm::MCExpr::evaluateKnownAbsolute(), llvm::FirstLiteralRelocationKind, Fixup, llvm::MCBinaryExpr::getLHS(), llvm::MCBinaryExpr::getRHS(), llvm::isUIntN(), llvm::little, llvm_unreachable, llvm::Offset, and OS.

◆ relaxDwarfLineAddr()

bool RISCVAsmBackend::relaxDwarfLineAddr	(	const MCAssembler &	Asm,
		MCDwarfLineAddrFragment &	DF,
		bool &	WasRelaxed
	)		const

overridevirtual

Reimplemented from llvm::MCAsmBackend.

Definition at line 202 of file RISCVAsmBackend.cpp.

References assert(), llvm::CallingConv::C, llvm::MCFixup::create(), llvm::Data, DF, llvm::encodeSLEB128(), llvm::encodeULEB128(), llvm::MCExpr::evaluateKnownAbsolute(), Fixup, llvm::MCBinaryExpr::getLHS(), llvm::RISCV::getRelocPairForSize(), llvm::MCBinaryExpr::getRHS(), INT64_MAX, llvm::little, llvm::Offset, OS, llvm::raw_ostream::tell(), and llvm::raw_ostream::write_zeros().

◆ relaxInstruction()

void RISCVAsmBackend::relaxInstruction	(	MCInst &	Inst,
		const MCSubtargetInfo &	STI
	)		const

overridevirtual

Relax the instruction in the given fragment to the next wider instruction.

Parameters

[out]	Inst	The instruction to relax, which is also the relaxed instruction.
	STI	the subtarget information for the associated instruction.

Reimplemented from llvm::MCAsmBackend.

Definition at line 173 of file RISCVAsmBackend.cpp.

References llvm::MCInst::addOperand(), assert(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), getRelaxedOpcode(), llvm_unreachable, llvm::MCInst::setOpcode(), Success, and llvm::RISCVRVC::uncompress().

◆ relaxLEB128()

std::pair< bool, bool > RISCVAsmBackend::relaxLEB128	(	const MCAssembler &	Asm,
		MCLEBFragment &	LF,
		int64_t &	Value
	)		const

overridevirtual

Reimplemented from llvm::MCAsmBackend.

Definition at line 330 of file RISCVAsmBackend.cpp.

References llvm::MCFixup::create(), llvm::MCExpr::evaluateKnownAbsolute(), llvm::FK_Data_leb128, llvm::MCEncodedFragmentWithFixups< ContentsSize, FixupsSize >::getFixups(), llvm::MCExpr::getLoc(), llvm::MCLEBFragment::getValue(), llvm::MCLEBFragment::isSigned(), and ULEB128Reloc.

◆ setForceRelocs()

void llvm::RISCVAsmBackend::setForceRelocs ( )

inline

Definition at line 40 of file RISCVAsmBackend.h.

◆ shouldForceRelocation()

bool RISCVAsmBackend::shouldForceRelocation	(	const MCAssembler &	Asm,
		const MCFixup &	Fixup,
		const MCValue &	Target,
		const MCSubtargetInfo *	STI
	)

overridevirtual

Hook to check if a relocation is needed for some target specific reason.

Reimplemented from llvm::MCAsmBackend.

Definition at line 112 of file RISCVAsmBackend.cpp.

References llvm::FirstLiteralRelocationKind, Fixup, llvm::RISCV::fixup_riscv_got_hi20, llvm::RISCV::fixup_riscv_tls_gd_hi20, llvm::RISCV::fixup_riscv_tls_got_hi20, llvm::RISCV::fixup_riscv_tlsdesc_hi20, llvm::FK_Data_1, llvm::FK_Data_2, llvm::FK_Data_4, llvm::FK_Data_8, llvm::FK_Data_leb128, and llvm::MCSubtargetInfo::hasFeature().

Referenced by evaluateTargetFixup().

◆ shouldInsertExtraNopBytesForCodeAlign()

bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign	(	const MCAlignFragment &	AF,
		unsigned &	Size
	)

overridevirtual

Hook to check if extra nop bytes must be inserted for alignment directive.

For some targets this may be necessary in order to support linker relaxation. The number of bytes to insert are returned in Size.

Reimplemented from llvm::MCAsmBackend.

Definition at line 658 of file RISCVAsmBackend.cpp.

References llvm::MCAlignFragment::getAlignment(), llvm::MCAlignFragment::getSubtargetInfo(), llvm::MCSubtargetInfo::hasFeature(), Size, and llvm::Align::value().

Referenced by shouldInsertFixupForCodeAlign().

◆ shouldInsertFixupForCodeAlign()

bool RISCVAsmBackend::shouldInsertFixupForCodeAlign	(	MCAssembler &	Asm,
		MCAlignFragment &	AF
	)

overridevirtual

Hook which indicates if the target requires a fixup to be generated when handling an align directive in an executable section.

Reimplemented from llvm::MCAsmBackend.

Definition at line 682 of file RISCVAsmBackend.cpp.

References llvm::MCConstantExpr::create(), llvm::MCFixup::create(), Fixup, llvm::RISCV::fixup_riscv_align, llvm::MCValue::get(), llvm::MCAlignFragment::getSubtargetInfo(), llvm::MCSubtargetInfo::hasFeature(), and shouldInsertExtraNopBytesForCodeAlign().

◆ writeNopData()

bool RISCVAsmBackend::writeNopData	(	raw_ostream &	OS,
		uint64_t	Count,
		const MCSubtargetInfo *	STI
	)		const

overridevirtual

Write an (optimal) nop sequence of Count bytes to the given output.

If the target cannot generate such a sequence, it should return an error.

Returns: - True on success.

Implements llvm::MCAsmBackend.

Definition at line 376 of file RISCVAsmBackend.cpp.

References llvm::MCSubtargetInfo::hasFeature(), OS, and llvm::raw_ostream::write().

The documentation for this class was generated from the following files:

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

Public Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ RISCVAsmBackend()

◆ ~RISCVAsmBackend()

Member Function Documentation

◆ applyFixup()

◆ createObjectTargetWriter()

◆ evaluateTargetFixup()

◆ fixupNeedsRelaxationAdvanced()

◆ getFixupKind()

◆ getFixupKindInfo()

◆ getNumFixupKinds()

◆ getRelaxedOpcode()

◆ getTargetOptions()

◆ handleAddSubRelocations()

◆ mayNeedRelaxation()

◆ relaxDwarfCFA()

◆ relaxDwarfLineAddr()

◆ relaxInstruction()

◆ relaxLEB128()

◆ setForceRelocs()

◆ shouldForceRelocation()

◆ shouldInsertExtraNopBytesForCodeAlign()

◆ shouldInsertFixupForCodeAlign()

◆ writeNopData()