19#define DEBUG_TYPE "csky-asmbackend"
23std::unique_ptr<MCObjectTargetWriter>
38 {
"fixup_csky_pcrel_uimm16_scale4", 0, 32,
42 {
"fixup_csky_pcrel_uimm8_scale4", 0, 32,
51 {
"fixup_csky_got_imm18_scale4", 0, 32, 0}},
57 {
"fixup_csky_plt_imm18_scale4", 0, 32, 0}},
61 {
"fixup_csky_pcrel_uimm7_scale4", 0, 16,
65 {
"fixup_csky_doffset_imm18", 0, 18, 0}},
67 {
"fixup_csky_doffset_imm18_scale2", 0, 18, 0}},
69 {
"fixup_csky_doffset_imm18_scale4", 0, 18, 0}}};
72 "Not all fixup kinds added to Infos array");
88 switch (
Fixup.getTargetKind()) {
104 return Value & 0xffffffff;
111 return (
Value >> 1) & 0xffff;
118 return (
Value >> 2) & 0xffff;
125 return (
Value >> 1) & 0x3ffffff;
132 return (
Value >> 1) & 0x3ffff;
139 unsigned IMM4L = (
Value >> 2) & 0xf;
140 unsigned IMM4H = (
Value >> 6) & 0xf;
142 Value = (IMM4H << 21) | (IMM4L << 4);
151 return (
Value >> 1) & 0x3ff;
153 if ((
Value >> 2) > 0xfe)
158 if ((
Value >> 2) <= 0x7f) {
159 unsigned IMM5L = (
Value >> 2) & 0x1f;
160 unsigned IMM2H = (
Value >> 7) & 0x3;
162 Value = (1 << 12) | (IMM2H << 8) | IMM5L;
164 unsigned IMM5L = (
~Value >> 2) & 0x1f;
165 unsigned IMM2H = (
~Value >> 7) & 0x3;
167 Value = (IMM2H << 8) | IMM5L;
178 const bool WasForced)
const {
183 if (!Resolved && !WasForced)
187 switch (
Fixup.getTargetKind()) {
191 return !isShiftedInt<10, 1>(
Offset);
193 return !isShiftedInt<16, 1>(
Offset);
195 return !isShiftedInt<26, 1>(
Offset);
197 return ((
Value >> 2) > 0xfe) || (
Value & 0x3);
220 unsigned NumBytes =
alignTo(
Info.TargetSize +
Info.TargetOffset, 8) / 8;
229 if (IsLittleEndian && IsInstFixup && (NumBytes == 4)) {
235 for (
unsigned I = 0;
I != NumBytes;
I++) {
236 unsigned Idx = IsLittleEndian ?
I : (NumBytes - 1 -
I);
268 switch (
Fixup.getTargetKind()) {
334 opcode = Inst.
getOpcode() == CSKY::JBT16 ? CSKY::JBT32 : CSKY::JBF32;
336 opcode = Inst.
getOpcode() == CSKY::JBT16 ? CSKY::JBT_E : CSKY::JBF_E;
344 Inst = std::move(Res);
unsigned const MachineRegisterInfo * MRI
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
This file defines the DenseMap class.
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
unsigned int getNumFixupKinds() const override
Get the number of target specific fixup kinds.
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
Generic interface to target specific assembler backends.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
const support::endianness Endian
Encapsulates the layout of an assembly file at a particular point in time.
Context object for machine code objects.
void reportError(SMLoc L, const Twine &Msg)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Target - Wrapper for Target specific information.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_csky_pcrel_imm10_scale2
@ fixup_csky_pcrel_uimm7_scale4
@ fixup_csky_doffset_imm18_scale2
@ fixup_csky_pcrel_imm16_scale2
@ fixup_csky_pcrel_imm18_scale2
@ fixup_csky_doffset_imm18_scale4
@ fixup_csky_pcrel_uimm16_scale4
@ fixup_csky_plt_imm18_scale4
@ fixup_csky_pcrel_imm26_scale2
@ fixup_csky_got_imm18_scale4
@ fixup_csky_pcrel_uimm8_scale4
@ fixup_csky_doffset_imm18
This is an optimization pass for GlobalISel generic memory operations.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
MCAsmBackend * createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createCSKYELFObjectWriter()
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_Data_2
A two-byte fixup.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...