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28 #define DEBUG_TYPE "avr-disassembler"
39 virtual ~AVRDisassembler() {}
50 return new AVRDisassembler(STI, Ctx);
61 AVR::R0, AVR::R1,
AVR::R2, AVR::R3,
63 AVR::R8, AVR::R9, AVR::R10, AVR::R11,
64 AVR::R12, AVR::R13, AVR::R14, AVR::R15,
65 AVR::R16, AVR::R17, AVR::R18, AVR::R19,
66 AVR::R20, AVR::R21, AVR::R22, AVR::R23,
67 AVR::R24, AVR::R25, AVR::R26, AVR::R27,
68 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
72 uint64_t Address,
const void *Decoder) {
82 uint64_t Address,
const void *Decoder) {
92 uint64_t Address,
const void *Decoder) {
94 assert(
false &&
"unimplemented: PTRREGS register class");
99 uint64_t Address,
const void *Decoder);
102 uint64_t Address,
const void *Decoder);
105 uint64_t Address,
const void *Decoder);
108 uint64_t Address,
const void *Decoder);
111 uint64_t Address,
const void *Decoder);
114 uint64_t Address,
const void *Decoder);
117 uint64_t Address,
const void *Decoder);
120 uint64_t Address,
const void *Decoder);
123 uint64_t Address,
const void *Decoder);
126 uint64_t Address,
const void *Decoder);
128 #include "AVRGenDisassemblerTables.inc"
131 uint64_t Address,
const void *Decoder) {
133 addr |= fieldFromInstruction(Insn, 0, 4);
134 addr |= fieldFromInstruction(Insn, 9, 2) << 4;
135 unsigned reg = fieldFromInstruction(Insn, 4, 5);
143 uint64_t Address,
const void *Decoder) {
145 addr |= fieldFromInstruction(Insn, 0, 4);
146 addr |= fieldFromInstruction(Insn, 9, 2) << 4;
147 unsigned reg = fieldFromInstruction(Insn, 4, 5);
155 uint64_t Address,
const void *Decoder) {
156 unsigned addr = fieldFromInstruction(Insn, 3, 5);
157 unsigned b = fieldFromInstruction(Insn, 0, 3);
164 uint64_t Address,
const void *Decoder) {
172 uint64_t Address,
const void *Decoder) {
173 unsigned d = fieldFromInstruction(Insn, 4, 5);
180 uint64_t Address,
const void *Decoder) {
188 uint64_t Address,
const void *Decoder) {
189 unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
190 unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
199 uint64_t Address,
const void *Decoder) {
200 unsigned r = fieldFromInstruction(Insn, 4, 4) * 2;
201 unsigned d = fieldFromInstruction(Insn, 0, 4) * 2;
210 uint64_t Address,
const void *Decoder) {
211 unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24;
213 k |= fieldFromInstruction(Insn, 0, 4);
214 k |= fieldFromInstruction(Insn, 6, 2) << 4;
224 uint64_t Address,
const void *Decoder) {
225 unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;
226 unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;
236 if (Bytes.
size() < 2) {
242 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
250 if (Bytes.
size() < 4) {
256 Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
264 case 2:
return DecoderTable16;
265 case 4:
return DecoderTable32;
286 Insn, Address,
this, STI);
310 const void *Decoder);
This class represents lattice values for constants.
static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static MCOperand createImm(int64_t Val)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRDisassembler()
Context object for machine code objects.
Target - Wrapper for Target specific information.
DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const uint8_t * getDecoderTable(uint64_t Size)
static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Target & getTheAVRTarget()
This class implements an extremely fast bulk output stream that can only output to a stream.
DecodeStatus
Ternary decode status.
void addOperand(const MCOperand Op)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
#define LLVM_EXTERNAL_VISIBILITY
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Superclass for all disassemblers.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCOperand createReg(unsigned Reg)
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCDisassembler * createAVRDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Wrapper class representing virtual and physical registers.
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int int d
Generic base class for all target subtargets.