LLVM 18.0.0git
M68kDisassembler.cpp
Go to the documentation of this file.
1//===-- M68kDisassembler.cpp - Disassembler for M68k ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the M68k Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "M68k.h"
14#include "M68kRegisterInfo.h"
15#include "M68kSubtarget.h"
19
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCInst.h"
26#include "llvm/Support/Endian.h"
28
29using namespace llvm;
30
31#define DEBUG_TYPE "m68k-disassembler"
32
34
35static const unsigned RegisterDecode[] = {
36 M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
37 M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
38 M68k::A4, M68k::A5, M68k::A6, M68k::SP, M68k::FP0, M68k::FP1,
39 M68k::FP2, M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7};
40
42 uint64_t Address, const void *Decoder) {
43 if (RegNo >= 24)
44 return DecodeStatus::Fail;
46 return DecodeStatus::Success;
47}
48
50 uint64_t Address,
51 const void *Decoder) {
52 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
53}
54
56 uint64_t Address,
57 const void *Decoder) {
58 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
59}
60
62 uint64_t Address,
63 const void *Decoder) {
64 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
65}
66
68 uint64_t Address,
69 const void *Decoder) {
70 return DecodeRegisterClass(Inst, RegNo | 8ULL, Address, Decoder);
71}
72
74 uint64_t Address,
75 const void *Decoder) {
76 return DecodeRegisterClass(Inst, RegNo | 8ULL, Address, Decoder);
77}
78
80 uint64_t Address,
81 const void *Decoder) {
82 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
83}
84
86 uint64_t Address,
87 const void *Decoder) {
88 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
89}
90
92 uint64_t Address,
93 const void *Decoder) {
94 return DecodeRegisterClass(Inst, RegNo | 16ULL, Address, Decoder);
95}
96#define DecodeFPDR32RegisterClass DecodeFPDRRegisterClass
97#define DecodeFPDR64RegisterClass DecodeFPDRRegisterClass
98#define DecodeFPDR80RegisterClass DecodeFPDRRegisterClass
99
101 uint64_t Address,
102 const void *Decoder) {
103 llvm_unreachable("unimplemented");
104}
105
107 const void *Decoder) {
108 Inst.addOperand(MCOperand::createImm(M68k::swapWord<uint32_t>(Imm)));
109 return DecodeStatus::Success;
110}
111
112#include "M68kGenDisassemblerTable.inc"
113
114#undef DecodeFPDR32RegisterClass
115#undef DecodeFPDR64RegisterClass
116#undef DecodeFPDR80RegisterClass
117
118/// A disassembler class for M68k.
121 : MCDisassembler(STI, Ctx) {}
122 virtual ~M68kDisassembler() {}
123
125 ArrayRef<uint8_t> Bytes, uint64_t Address,
126 raw_ostream &CStream) const override;
127};
128
130 ArrayRef<uint8_t> Bytes,
131 uint64_t Address,
132 raw_ostream &CStream) const {
133 DecodeStatus Result;
134 auto MakeUp = [&](APInt &Insn, unsigned InstrBits) {
135 unsigned Idx = Insn.getBitWidth() >> 3;
136 unsigned RoundUp = alignTo(InstrBits, Align(16));
137 if (RoundUp > Insn.getBitWidth())
138 Insn = Insn.zext(RoundUp);
139 RoundUp = RoundUp >> 3;
140 for (; Idx < RoundUp; Idx += 2) {
141 Insn.insertBits(support::endian::read16be(&Bytes[Idx]), Idx * 8, 16);
142 }
143 };
145 // 2 bytes of data are consumed, so set Size to 2
146 // If we don't do this, disassembler may generate result even
147 // the encoding is invalid. We need to let it fail correctly.
148 Size = 2;
149 Result = decodeInstruction(DecoderTable80, Instr, Insn, Address, this, STI,
150 MakeUp);
151 if (Result == DecodeStatus::Success)
152 Size = InstrLenTable[Instr.getOpcode()] >> 3;
153 return Result;
154}
155
157 const MCSubtargetInfo &STI,
158 MCContext &Ctx) {
159 return new M68kDisassembler(STI, Ctx);
160}
161
163 // Register the disassembler.
166}
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
static const unsigned RegisterDecode[]
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeXR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPDRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createM68kDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kDisassembler()
static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDR8RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeXR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
This file contains the declarations for the code emitter which are useful outside of the emitter itse...
This file provides M68k specific target descriptions.
This file contains the M68k implementation of the TargetRegisterInfo class.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file contains the entry points for global functions defined in the M68k target library,...
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
const T * data() const
Definition: ArrayRef.h:162
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
const MCSubtargetInfo & STI
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint16_t read16be(const void *P)
Definition: Endian.h:379
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
Target & getTheM68kTarget()
A disassembler class for M68k.
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
M68kDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.