LLVM 20.0.0git
M68kDisassembler.cpp
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1//===-- M68kDisassembler.cpp - Disassembler for M68k ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the M68k Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "M68k.h"
14#include "M68kRegisterInfo.h"
15#include "M68kSubtarget.h"
19
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCInst.h"
26#include "llvm/Support/Endian.h"
28
29using namespace llvm;
30
31#define DEBUG_TYPE "m68k-disassembler"
32
34
35static const unsigned RegisterDecode[] = {
36 M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
37 M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
38 M68k::A4, M68k::A5, M68k::A6, M68k::SP, M68k::FP0, M68k::FP1,
39 M68k::FP2, M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7,
40 M68k::FPIAR, M68k::FPS, M68k::FPC};
41
43 uint64_t Address, const void *Decoder) {
44 if (RegNo >= 24)
45 return DecodeStatus::Fail;
47 return DecodeStatus::Success;
48}
49
51 uint64_t Address,
52 const void *Decoder) {
53 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
54}
55
57 uint64_t Address,
58 const void *Decoder) {
59 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
60}
61
63 uint64_t Address,
64 const void *Decoder) {
65 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
66}
67
69 uint64_t Address,
70 const void *Decoder) {
71 return DecodeRegisterClass(Inst, RegNo | 8ULL, Address, Decoder);
72}
73
75 uint64_t Address,
76 const void *Decoder) {
77 return DecodeRegisterClass(Inst, RegNo | 8ULL, Address, Decoder);
78}
79
81 uint64_t Address,
82 const void *Decoder) {
83 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
84}
85
87 uint64_t Address,
88 const void *Decoder) {
89 return DecodeRegisterClass(Inst, RegNo.getZExtValue(), Address, Decoder);
90}
91
93 uint64_t Address,
94 const void *Decoder) {
95 return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
96}
97
99 uint64_t Address,
100 const void *Decoder) {
101 return DecodeRegisterClass(Inst, RegNo | 16ULL, Address, Decoder);
102}
103#define DecodeFPDR32RegisterClass DecodeFPDRRegisterClass
104#define DecodeFPDR64RegisterClass DecodeFPDRRegisterClass
105#define DecodeFPDR80RegisterClass DecodeFPDRRegisterClass
106
108 uint64_t Address,
109 const void *Decoder) {
110 return DecodeRegisterClass(Inst, (RegNo >> 1) + 24, Address, Decoder);
111}
112#define DecodeFPICRegisterClass DecodeFPCSCRegisterClass
113
115 uint64_t Address,
116 const void *Decoder) {
117 llvm_unreachable("unimplemented");
118}
119
121 const void *Decoder) {
122 Inst.addOperand(MCOperand::createImm(M68k::swapWord<uint32_t>(Imm)));
123 return DecodeStatus::Success;
124}
125
126#include "M68kGenDisassemblerTable.inc"
127
128#undef DecodeFPDR32RegisterClass
129#undef DecodeFPDR64RegisterClass
130#undef DecodeFPDR80RegisterClass
131#undef DecodeFPICRegisterClass
132
133/// A disassembler class for M68k.
136 : MCDisassembler(STI, Ctx) {}
137 virtual ~M68kDisassembler() {}
138
140 ArrayRef<uint8_t> Bytes, uint64_t Address,
141 raw_ostream &CStream) const override;
142};
143
145 ArrayRef<uint8_t> Bytes,
146 uint64_t Address,
147 raw_ostream &CStream) const {
148 DecodeStatus Result;
149 auto MakeUp = [&](APInt &Insn, unsigned InstrBits) {
150 unsigned Idx = Insn.getBitWidth() >> 3;
151 unsigned RoundUp = alignTo(InstrBits, Align(16));
152 if (RoundUp > Insn.getBitWidth())
153 Insn = Insn.zext(RoundUp);
154 RoundUp = RoundUp >> 3;
155 for (; Idx < RoundUp; Idx += 2) {
156 Insn.insertBits(support::endian::read16be(&Bytes[Idx]), Idx * 8, 16);
157 }
158 };
160 // 2 bytes of data are consumed, so set Size to 2
161 // If we don't do this, disassembler may generate result even
162 // the encoding is invalid. We need to let it fail correctly.
163 Size = 2;
164 Result = decodeInstruction(DecoderTable80, Instr, Insn, Address, this, STI,
165 MakeUp);
166 if (Result == DecodeStatus::Success)
167 Size = InstrLenTable[Instr.getOpcode()] >> 3;
168 return Result;
169}
170
172 const MCSubtargetInfo &STI,
173 MCContext &Ctx) {
174 return new M68kDisassembler(STI, Ctx);
175}
176
178 // Register the disassembler.
181}
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
static const unsigned RegisterDecode[]
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeXR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPDRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createM68kDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kDisassembler()
static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDR8RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPCSCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeXR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
This file contains the declarations for the code emitter which are useful outside of the emitter itse...
This file provides M68k specific target descriptions.
This file contains the M68k implementation of the TargetRegisterInfo class.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file contains the entry points for global functions defined in the M68k target library,...
Class for arbitrary precision integers.
Definition: APInt.h:78
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1520
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
const T * data() const
Definition: ArrayRef.h:165
Context object for machine code objects.
Definition: MCContext.h:83
Superclass for all disassemblers.
const MCSubtargetInfo & STI
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:142
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint16_t read16be(const void *P)
Definition: Endian.h:431
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
Target & getTheM68kTarget()
A disassembler class for M68k.
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
M68kDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.