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22 #define DEBUG_TYPE "ppc-disassembler"
44 return new PPCDisassembler(STI, Ctx,
false);
50 return new PPCDisassembler(STI, Ctx,
true);
83 template <std::
size_t N>
86 assert(RegNo <
N &&
"Invalid register number");
175 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
176 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
192 const void *Decoder) {
198 const void *Decoder) {
206 const void *Decoder) {
212 const void *Decoder) {
218 const void *Decoder) {
225 uint64_t Address,
const void *Decoder) {
235 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
236 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
238 template <
unsigned N>
242 assert(isUInt<N>(
Imm) &&
"Invalid immediate");
247 template <
unsigned N>
251 assert(isUInt<N>(
Imm) &&
"Invalid immediate");
340 const int64_t Disp = SignExtend64<7>((
Imm & 0x3F) + 64) * 8;
448 assert(Zeros < 8 &&
"Invalid CR bit value");
454 #include "PPCGenDisassemblerTables.inc"
471 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.
size() >= 8) {
485 if (Bytes.
size() < 4) {
493 if (STI.getFeatureBits()[PPC::FeatureSPE]) {
495 decodeInstruction(DecoderTableSPE32,
MI, Inst, Address,
this, STI);
500 return decodeInstruction(DecoderTable32,
MI, Inst, Address,
this, STI);
static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
This is an optimization pass for GlobalISel generic memory operations.
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
iterator insert(iterator I, const MCOperand &Op)
static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Target - Wrapper for Target specific information.
static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
uint32_t read32be(const void *P)
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler()
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s result
Target & getThePPC64LETarget()
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream.
static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
unsigned countTrailingZeros(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus
Ternary decode status.
void addOperand(const MCOperand Op)
static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_EXTERNAL_VISIBILITY
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
static MCOperand createReg(unsigned Reg)
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Target & getThePPC64Target()
static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
#define DEFINE_PPC_REGCLASSES
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
unsigned getOpcode() const
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Target & getThePPC32LETarget()
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg(&Regs)[N])
uint32_t read32le(const void *P)
size_t size() const
size - Get the array size.
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Generic base class for all target subtargets.
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Target & getThePPC32Target()