LLVM 20.0.0git
PPCDisassembler.cpp
Go to the documentation of this file.
1//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
13#include "llvm/MC/MCInst.h"
16#include "llvm/Support/Endian.h"
17
18using namespace llvm;
19
21
22#define DEBUG_TYPE "ppc-disassembler"
23
25
26namespace {
27class PPCDisassembler : public MCDisassembler {
28 bool IsLittleEndian;
29
30public:
31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32 bool IsLittleEndian)
33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34
36 ArrayRef<uint8_t> Bytes, uint64_t Address,
37 raw_ostream &CStream) const override;
38};
39} // end anonymous namespace
40
42 const MCSubtargetInfo &STI,
43 MCContext &Ctx) {
44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45}
46
48 const MCSubtargetInfo &STI,
49 MCContext &Ctx) {
50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51}
52
54 // Register the disassembler for each target.
63}
64
65static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
66 uint64_t /*Address*/,
67 const MCDisassembler * /*Decoder*/) {
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
70}
71
72static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
73 uint64_t /*Address*/,
74 const MCDisassembler * /*Decoder*/) {
75 int32_t Offset = SignExtend32<24>(Imm);
78}
79
80// FIXME: These can be generated by TableGen from the existing register
81// encoding values!
82
83template <std::size_t N>
85 const MCPhysReg (&Regs)[N]) {
86 if (RegNo >= N)
88 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
90}
91
93 uint64_t Address,
94 const MCDisassembler *Decoder) {
95 return decodeRegisterClass(Inst, RegNo, CRRegs);
96}
97
99 uint64_t Address,
100 const MCDisassembler *Decoder) {
101 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
102}
103
105 uint64_t Address,
106 const MCDisassembler *Decoder) {
107 return decodeRegisterClass(Inst, RegNo, FRegs);
108}
109
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 return decodeRegisterClass(Inst, RegNo, FRegs);
114}
115
117 uint64_t Address,
118 const MCDisassembler *Decoder) {
119 if (RegNo > 30 || (RegNo & 1))
121 return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
122}
123
125 uint64_t Address,
126 const MCDisassembler *Decoder) {
127 return decodeRegisterClass(Inst, RegNo, VFRegs);
128}
129
131 uint64_t Address,
132 const MCDisassembler *Decoder) {
133 return decodeRegisterClass(Inst, RegNo, VRegs);
134}
135
137 uint64_t Address,
138 const MCDisassembler *Decoder) {
139 return decodeRegisterClass(Inst, RegNo, VSRegs);
140}
141
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 return decodeRegisterClass(Inst, RegNo, VSFRegs);
146}
147
149 uint64_t Address,
150 const MCDisassembler *Decoder) {
151 return decodeRegisterClass(Inst, RegNo, VSSRegs);
152}
153
155 uint64_t Address,
156 const MCDisassembler *Decoder) {
157 return decodeRegisterClass(Inst, RegNo, RRegs);
158}
159
160static DecodeStatus
162 const MCDisassembler *Decoder) {
163 return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
164}
165
167 uint64_t Address,
168 const MCDisassembler *Decoder) {
169 return decodeRegisterClass(Inst, RegNo, XRegs);
170}
171
173 uint64_t Address,
174 const MCDisassembler *Decoder) {
175 return decodeRegisterClass(Inst, RegNo, XRegs);
176}
177
178static DecodeStatus
180 const MCDisassembler *Decoder) {
181 return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
182}
183
184#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
185#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
186
188 uint64_t Address,
189 const MCDisassembler *Decoder) {
190 return decodeRegisterClass(Inst, RegNo, SPERegs);
191}
192
194 uint64_t Address,
195 const MCDisassembler *Decoder) {
196 return decodeRegisterClass(Inst, RegNo, ACCRegs);
197}
198
200 uint64_t Address,
201 const void *Decoder) {
202 return decodeRegisterClass(Inst, RegNo, WACCRegs);
203}
204
206 uint64_t Address,
207 const void *Decoder) {
208 return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
209}
210
211// TODO: Make this function static when the register class is used by a new
212// instruction.
214 uint64_t Address,
215 const void *Decoder) {
216 return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
217}
218
220 uint64_t Address,
221 const void *Decoder) {
222 return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
223}
224
226 uint64_t Address,
227 const void *Decoder) {
228 return decodeRegisterClass(Inst, RegNo, DMRRegs);
229}
230
231// TODO: Make this function static when the register class is used by a new
232// instruction.
234 uint64_t Address, const void *Decoder) {
235 return decodeRegisterClass(Inst, RegNo, DMRpRegs);
236}
237
239 uint64_t Address,
240 const MCDisassembler *Decoder) {
241 return decodeRegisterClass(Inst, RegNo, VSRpRegs);
242}
243
244#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
245#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
246
247template <unsigned N>
249 int64_t Address,
250 const MCDisassembler *Decoder) {
251 if (!isUInt<N>(Imm))
255}
256
257template <unsigned N>
259 int64_t Address,
260 const MCDisassembler *Decoder) {
261 if (!isUInt<N>(Imm))
263 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
265}
266
268 int64_t Address,
269 const MCDisassembler *Decoder) {
270 if (Imm != 0)
274}
275
277 uint64_t Address,
278 const MCDisassembler *Decoder) {
279 if (RegNo & 1)
281 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
283}
284
286 int64_t Address,
287 const MCDisassembler *Decoder) {
288 // The rix displacement is an immediate shifted by 2
289 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2)));
291}
292
294 int64_t Address,
295 const MCDisassembler *Decoder) {
296 // Decode the disp field for a hash store or hash check operation.
297 // The field is composed of an immediate value that is 6 bits
298 // and covers the range -8 to -512. The immediate is always negative and 2s
299 // complement which is why we sign extend a 7 bit value.
300 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
301
304}
305
307 int64_t Address,
308 const MCDisassembler *Decoder) {
309 // The rix16 displacement has 12-bits which are shifted by 4.
310 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4)));
312}
313
315 int64_t Address,
316 const MCDisassembler *Decoder) {
317 // Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
318
319 uint64_t Disp = Imm & 0x1F;
320
321 Inst.addOperand(MCOperand::createImm(Disp << 3));
323}
324
326 int64_t Address,
327 const MCDisassembler *Decoder) {
328 // Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
329
330 uint64_t Disp = Imm & 0x1F;
331
332 Inst.addOperand(MCOperand::createImm(Disp << 2));
334}
335
337 int64_t Address,
338 const MCDisassembler *Decoder) {
339 // Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
340
341 uint64_t Disp = Imm & 0x1F;
342 Inst.addOperand(MCOperand::createImm(Disp << 1));
344}
345
347 int64_t Address,
348 const MCDisassembler *Decoder) {
349 // The cr bit encoding is 0x80 >> cr_reg_num.
350
351 unsigned Zeros = llvm::countr_zero(Imm);
352 if (Zeros >= 8)
354
355 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
357}
358
359#include "PPCGenDisassemblerTables.inc"
360
361DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
362 ArrayRef<uint8_t> Bytes,
363 uint64_t Address,
364 raw_ostream &CS) const {
365 auto *ReadFunc = IsLittleEndian ? support::endian::read32le
367
368 // If this is an 8-byte prefixed instruction, handle it here.
369 // Note: prefixed instructions aren't technically 8-byte entities - the prefix
370 // appears in memory at an address 4 bytes prior to that of the base
371 // instruction regardless of endianness. So we read the two pieces and
372 // rebuild the 8-byte instruction.
373 // TODO: In this function we call decodeInstruction several times with
374 // different decoder tables. It may be possible to only call once by
375 // looking at the top 6 bits of the instruction.
376 if (STI.hasFeature(PPC::FeaturePrefixInstrs) && Bytes.size() >= 8) {
377 uint32_t Prefix = ReadFunc(Bytes.data());
378 uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
379 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
380 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
381 this, STI);
382 if (result != MCDisassembler::Fail) {
383 Size = 8;
384 return result;
385 }
386 }
387
388 // Get the four bytes of the instruction.
389 Size = 4;
390 if (Bytes.size() < 4) {
391 Size = 0;
393 }
394
395 // Read the instruction in the proper endianness.
396 uint64_t Inst = ReadFunc(Bytes.data());
397
398 if (STI.hasFeature(PPC::FeatureSPE)) {
399 DecodeStatus result =
400 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
401 if (result != MCDisassembler::Fail)
402 return result;
403 }
404
405 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
406}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
uint64_t Size
IRTranslator LLVM IR MI
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg(&Regs)[N])
static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler()
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
static DecodeStatus decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeDispRIXOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
#define DEFINE_PPC_REGCLASSES
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
const T * data() const
Definition: ArrayRef.h:162
Context object for machine code objects.
Definition: MCContext.h:83
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t read32be(const void *P)
Definition: Endian.h:434
uint32_t read32le(const void *P)
Definition: Endian.h:425
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
Target & getThePPC64LETarget()
Target & getThePPC32Target()
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:215
Target & getThePPC64Target()
Target & getThePPC32LETarget()
#define N
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.