LLVM  17.0.0git
PPCDisassembler.cpp
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1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "llvm/MC/MCDecoderOps.h"
13 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/TargetRegistry.h"
16 #include "llvm/Support/Endian.h"
17 
18 using namespace llvm;
19 
21 
22 #define DEBUG_TYPE "ppc-disassembler"
23 
25 
26 namespace {
27 class PPCDisassembler : public MCDisassembler {
28  bool IsLittleEndian;
29 
30 public:
31  PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32  bool IsLittleEndian)
33  : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34 
35  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
36  ArrayRef<uint8_t> Bytes, uint64_t Address,
37  raw_ostream &CStream) const override;
38 };
39 } // end anonymous namespace
40 
42  const MCSubtargetInfo &STI,
43  MCContext &Ctx) {
44  return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45 }
46 
48  const MCSubtargetInfo &STI,
49  MCContext &Ctx) {
50  return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51 }
52 
54  // Register the disassembler for each target.
63 }
64 
65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
66  uint64_t /*Address*/,
67  const MCDisassembler * /*Decoder*/) {
68  Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
70 }
71 
73  uint64_t /*Address*/,
74  const MCDisassembler * /*Decoder*/) {
75  int32_t Offset = SignExtend32<24>(Imm);
78 }
79 
80 // FIXME: These can be generated by TableGen from the existing register
81 // encoding values!
82 
83 template <std::size_t N>
85  const MCPhysReg (&Regs)[N]) {
86  assert(RegNo < N && "Invalid register number");
87  Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
89 }
90 
92  uint64_t Address,
93  const MCDisassembler *Decoder) {
94  return decodeRegisterClass(Inst, RegNo, CRRegs);
95 }
96 
98  uint64_t Address,
99  const MCDisassembler *Decoder) {
100  return decodeRegisterClass(Inst, RegNo, CRBITRegs);
101 }
102 
104  uint64_t Address,
105  const MCDisassembler *Decoder) {
106  return decodeRegisterClass(Inst, RegNo, FRegs);
107 }
108 
110  uint64_t Address,
111  const MCDisassembler *Decoder) {
112  return decodeRegisterClass(Inst, RegNo, FRegs);
113 }
114 
116  uint64_t Address,
117  const MCDisassembler *Decoder) {
118  return decodeRegisterClass(Inst, RegNo, VFRegs);
119 }
120 
122  uint64_t Address,
123  const MCDisassembler *Decoder) {
124  return decodeRegisterClass(Inst, RegNo, VRegs);
125 }
126 
128  uint64_t Address,
129  const MCDisassembler *Decoder) {
130  return decodeRegisterClass(Inst, RegNo, VSRegs);
131 }
132 
134  uint64_t Address,
135  const MCDisassembler *Decoder) {
136  return decodeRegisterClass(Inst, RegNo, VSFRegs);
137 }
138 
140  uint64_t Address,
141  const MCDisassembler *Decoder) {
142  return decodeRegisterClass(Inst, RegNo, VSSRegs);
143 }
144 
146  uint64_t Address,
147  const MCDisassembler *Decoder) {
148  return decodeRegisterClass(Inst, RegNo, RRegs);
149 }
150 
151 static DecodeStatus
153  const MCDisassembler *Decoder) {
154  return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
155 }
156 
158  uint64_t Address,
159  const MCDisassembler *Decoder) {
160  return decodeRegisterClass(Inst, RegNo, XRegs);
161 }
162 
164  uint64_t Address,
165  const MCDisassembler *Decoder) {
166  return decodeRegisterClass(Inst, RegNo, XRegs);
167 }
168 
169 static DecodeStatus
171  const MCDisassembler *Decoder) {
172  return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
173 }
174 
175 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
176 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
177 
179  uint64_t Address,
180  const MCDisassembler *Decoder) {
181  return decodeRegisterClass(Inst, RegNo, SPERegs);
182 }
183 
185  uint64_t Address,
186  const MCDisassembler *Decoder) {
187  return decodeRegisterClass(Inst, RegNo, ACCRegs);
188 }
189 
191  uint64_t Address,
192  const void *Decoder) {
193  return decodeRegisterClass(Inst, RegNo, WACCRegs);
194 }
195 
197  uint64_t Address,
198  const void *Decoder) {
199  return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
200 }
201 
202 // TODO: Make this function static when the register class is used by a new
203 // instruction.
205  uint64_t Address,
206  const void *Decoder) {
207  return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
208 }
209 
211  uint64_t Address,
212  const void *Decoder) {
213  return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
214 }
215 
217  uint64_t Address,
218  const void *Decoder) {
219  return decodeRegisterClass(Inst, RegNo, DMRRegs);
220 }
221 
222 // TODO: Make this function static when the register class is used by a new
223 // instruction.
225  uint64_t Address, const void *Decoder) {
226  return decodeRegisterClass(Inst, RegNo, DMRpRegs);
227 }
228 
230  uint64_t Address,
231  const MCDisassembler *Decoder) {
232  return decodeRegisterClass(Inst, RegNo, VSRpRegs);
233 }
234 
235 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
236 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
237 
238 template <unsigned N>
240  int64_t Address,
241  const MCDisassembler *Decoder) {
242  assert(isUInt<N>(Imm) && "Invalid immediate");
245 }
246 
247 template <unsigned N>
249  int64_t Address,
250  const MCDisassembler *Decoder) {
251  assert(isUInt<N>(Imm) && "Invalid immediate");
252  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
254 }
255 
257  int64_t Address,
258  const MCDisassembler *Decoder) {
259  if (Imm != 0)
260  return MCDisassembler::Fail;
263 }
264 
266  uint64_t Address,
267  const MCDisassembler *Decoder) {
268  if (RegNo & 1)
269  return MCDisassembler::Fail;
270  Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
272 }
273 
275  int64_t Address,
276  const MCDisassembler *Decoder) {
277  // Decode the memri field (imm, reg), which has the low 16-bits as the
278  // displacement and the next 5 bits as the register #.
279 
280  uint64_t Base = Imm >> 16;
281  uint64_t Disp = Imm & 0xFFFF;
282 
283  assert(Base < 32 && "Invalid base register");
284 
285  switch (Inst.getOpcode()) {
286  default: break;
287  case PPC::LBZU:
288  case PPC::LHAU:
289  case PPC::LHZU:
290  case PPC::LWZU:
291  case PPC::LFSU:
292  case PPC::LFDU:
293  // Add the tied output operand.
294  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
295  break;
296  case PPC::STBU:
297  case PPC::STHU:
298  case PPC::STWU:
299  case PPC::STFSU:
300  case PPC::STFDU:
301  Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
302  break;
303  }
304 
305  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
306  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
308 }
309 
311  int64_t Address,
312  const MCDisassembler *Decoder) {
313  // Decode the memrix field (imm, reg), which has the low 14-bits as the
314  // displacement and the next 5 bits as the register #.
315 
316  uint64_t Base = Imm >> 14;
317  uint64_t Disp = Imm & 0x3FFF;
318 
319  assert(Base < 32 && "Invalid base register");
320 
321  if (Inst.getOpcode() == PPC::LDU)
322  // Add the tied output operand.
323  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
324  else if (Inst.getOpcode() == PPC::STDU)
325  Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
326 
327  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
328  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
330 }
331 
333  int64_t Address,
334  const MCDisassembler *Decoder) {
335  // Decode the memrix field for a hash store or hash check operation.
336  // The field is composed of a register and an immediate value that is 6 bits
337  // and covers the range -8 to -512. The immediate is always negative and 2s
338  // complement which is why we sign extend a 7 bit value.
339  const uint64_t Base = Imm >> 6;
340  const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
341 
342  assert(Base < 32 && "Invalid base register");
343 
344  Inst.addOperand(MCOperand::createImm(Disp));
345  Inst.addOperand(MCOperand::createReg(RRegs[Base]));
347 }
348 
350  int64_t Address,
351  const MCDisassembler *Decoder) {
352  // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
353  // displacement with 16-byte aligned, and the next 5 bits as the register #.
354 
355  uint64_t Base = Imm >> 12;
356  uint64_t Disp = Imm & 0xFFF;
357 
358  assert(Base < 32 && "Invalid base register");
359 
360  Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
361  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
363 }
364 
366  int64_t Address,
367  const MCDisassembler *Decoder) {
368  // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
369  // displacement, and the next 5 bits as an immediate 0.
370  uint64_t Base = Imm >> 34;
371  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
372 
373  assert(Base < 32 && "Invalid base register");
374 
375  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
376  return decodeImmZeroOperand(Inst, Base, Address, Decoder);
377 }
378 
380  int64_t Address,
381  const MCDisassembler *Decoder) {
382  // Decode the memri34 field (imm, reg), which has the low 34-bits as the
383  // displacement, and the next 5 bits as the register #.
384  uint64_t Base = Imm >> 34;
385  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
386 
387  assert(Base < 32 && "Invalid base register");
388 
389  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
390  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
392 }
393 
395  int64_t Address,
396  const MCDisassembler *Decoder) {
397  // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
398  // displacement with 8-byte aligned, and the next 5 bits as the register #.
399 
400  uint64_t Base = Imm >> 5;
401  uint64_t Disp = Imm & 0x1F;
402 
403  assert(Base < 32 && "Invalid base register");
404 
405  Inst.addOperand(MCOperand::createImm(Disp << 3));
406  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
408 }
409 
411  int64_t Address,
412  const MCDisassembler *Decoder) {
413  // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
414  // displacement with 4-byte aligned, and the next 5 bits as the register #.
415 
416  uint64_t Base = Imm >> 5;
417  uint64_t Disp = Imm & 0x1F;
418 
419  assert(Base < 32 && "Invalid base register");
420 
421  Inst.addOperand(MCOperand::createImm(Disp << 2));
422  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
424 }
425 
427  int64_t Address,
428  const MCDisassembler *Decoder) {
429  // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
430  // displacement with 2-byte aligned, and the next 5 bits as the register #.
431 
432  uint64_t Base = Imm >> 5;
433  uint64_t Disp = Imm & 0x1F;
434 
435  assert(Base < 32 && "Invalid base register");
436 
437  Inst.addOperand(MCOperand::createImm(Disp << 1));
438  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
440 }
441 
443  int64_t Address,
444  const MCDisassembler *Decoder) {
445  // The cr bit encoding is 0x80 >> cr_reg_num.
446 
447  unsigned Zeros = countTrailingZeros(Imm);
448  assert(Zeros < 8 && "Invalid CR bit value");
449 
450  Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
452 }
453 
454 #include "PPCGenDisassemblerTables.inc"
455 
456 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
457  ArrayRef<uint8_t> Bytes,
458  uint64_t Address,
459  raw_ostream &CS) const {
460  auto *ReadFunc = IsLittleEndian ? support::endian::read32le
462 
463  // If this is an 8-byte prefixed instruction, handle it here.
464  // Note: prefixed instructions aren't technically 8-byte entities - the prefix
465  // appears in memory at an address 4 bytes prior to that of the base
466  // instruction regardless of endianness. So we read the two pieces and
467  // rebuild the 8-byte instruction.
468  // TODO: In this function we call decodeInstruction several times with
469  // different decoder tables. It may be possible to only call once by
470  // looking at the top 6 bits of the instruction.
471  if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
472  uint32_t Prefix = ReadFunc(Bytes.data());
473  uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
474  uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
475  DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
476  this, STI);
477  if (result != MCDisassembler::Fail) {
478  Size = 8;
479  return result;
480  }
481  }
482 
483  // Get the four bytes of the instruction.
484  Size = 4;
485  if (Bytes.size() < 4) {
486  Size = 0;
487  return MCDisassembler::Fail;
488  }
489 
490  // Read the instruction in the proper endianness.
491  uint64_t Inst = ReadFunc(Bytes.data());
492 
493  if (STI.getFeatureBits()[PPC::FeatureSPE]) {
495  decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
497  return result;
498  }
499 
500  return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
501 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
DecodeDMRROWpRCRegisterClass
static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:210
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCDisassembler.h
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:159
DecodeVRRCRegisterClass
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:121
T
DecodeG8pRCRegisterClass
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:163
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:248
llvm::MCInst::insert
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:224
decodeSPE4Operands
static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:410
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
decodeMemRI34PCRelOperands
static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:365
decodeCRBitMOperand
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:442
DecodeGPRC_NOR0RegisterClass
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:152
decodeImmZeroOperand
static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:256
DecodeG8RCRegisterClass
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:157
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:972
llvm::support::endian::read32be
uint32_t read32be(const void *P)
Definition: Endian.h:384
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCDecoderOps.h
PPCMCTargetDesc.h
DecodeCRBITRCRegisterClass
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:97
LLVMInitializePowerPCDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler()
Definition: PPCDisassembler.cpp:53
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:160
result
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s result
Definition: README_P9.txt:256
llvm::getThePPC64LETarget
Target & getThePPC64LETarget()
Definition: PowerPCTargetInfo.cpp:25
DecodeVSRpRCRegisterClass
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:229
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:106
MCInst.h
MCSubtargetInfo.h
decodeMemRIXOperands
static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:310
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
createPPCLEDisassembler
static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: PPCDisassembler.cpp:47
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:69
DecodeF4RCRegisterClass
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:103
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:103
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
DecodeWACC_HIRCRegisterClass
static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:196
decodeSPE8Operands
static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:394
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: PPCDisassembler.cpp:24
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:239
decodeVSRpEvenOperands
static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:265
decodeSPE2Operands
static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:426
uint64_t
DecodeDMRpRCRegisterClass
DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:224
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:145
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
DecodeVSRCRegisterClass
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:127
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:79
llvm::MCInst::begin
iterator begin()
Definition: MCInst.h:219
DecodeSPERCRegisterClass
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:178
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
PowerPCTargetInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
decodeMemRIOperands
static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:274
decodeMemRIX16Operands
static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:349
decodeMemRIHashOperands
static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:332
llvm::ArrayRef< uint8_t >
decodeCondBrTarget
static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
Definition: PPCDisassembler.cpp:65
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
uint32_t
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:104
createPPCDisassembler
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: PPCDisassembler.cpp:41
llvm::getThePPC64Target
Target & getThePPC64Target()
Definition: PowerPCTargetInfo.cpp:21
decodeMemRI34Operands
static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:379
decodeDirectBrTarget
static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)
Definition: PPCDisassembler.cpp:72
DEFINE_PPC_REGCLASSES
#define DEFINE_PPC_REGCLASSES
Definition: PPCMCTargetDesc.h:181
DecodeF8RCRegisterClass
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:109
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
DecodeVSFRCRegisterClass
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:133
llvm::getThePPC32LETarget
Target & getThePPC32LETarget()
Definition: PowerPCTargetInfo.cpp:17
decodeRegisterClass
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg(&Regs)[N])
Definition: PPCDisassembler.cpp:84
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@ Imm
Definition: RISCVMatInt.h:23
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
N
#define N
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
DecodeVSSRCRegisterClass
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:139
DecodeDMRROWRCRegisterClass
DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:204
DecodeACCRCRegisterClass
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:184
DecodeCRRCRegisterClass
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:91
DecodeWACCRCRegisterClass
static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:190
DecodeG8RC_NOX0RegisterClass
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:170
Endian.h
TargetRegistry.h
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Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
DecodeVFRCRegisterClass
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: PPCDisassembler.cpp:115
DecodeDMRRCRegisterClass
static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: PPCDisassembler.cpp:216
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
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Definition: PowerPCTargetInfo.cpp:13