LLVM 20.0.0git
SparcAsmPrinter.cpp
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1//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format SPARC assembly language.
11//
12//===----------------------------------------------------------------------===//
13
18#include "Sparc.h"
19#include "SparcInstrInfo.h"
20#include "SparcTargetMachine.h"
27#include "llvm/IR/Mangler.h"
28#include "llvm/MC/MCAsmInfo.h"
29#include "llvm/MC/MCContext.h"
30#include "llvm/MC/MCInst.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSymbol.h"
35using namespace llvm;
36
37#define DEBUG_TYPE "asm-printer"
38
39namespace {
40 class SparcAsmPrinter : public AsmPrinter {
41 SparcTargetStreamer &getTargetStreamer() {
42 return static_cast<SparcTargetStreamer &>(
43 *OutStreamer->getTargetStreamer());
44 }
45 public:
46 explicit SparcAsmPrinter(TargetMachine &TM,
47 std::unique_ptr<MCStreamer> Streamer)
48 : AsmPrinter(TM, std::move(Streamer)) {}
49
50 StringRef getPassName() const override { return "Sparc Assembly Printer"; }
51
52 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
53 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
54
55 void emitFunctionBodyStart() override;
56 void emitInstruction(const MachineInstr *MI) override;
57
58 static const char *getRegisterName(MCRegister Reg) {
60 }
61
62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
63 const char *ExtraCode, raw_ostream &O) override;
64 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
65 const char *ExtraCode, raw_ostream &O) override;
66
67 void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
68 const MCSubtargetInfo &STI);
69
70 };
71} // end of anonymous namespace
72
74 MCSymbol *Sym, MCContext &OutContext) {
76 OutContext);
77 const SparcMCExpr *expr = SparcMCExpr::create(Kind, MCSym, OutContext);
78 return MCOperand::createExpr(expr);
79
80}
82 MCContext &OutContext) {
83 return createSparcMCOperand(SparcMCExpr::VK_Sparc_WDISP30, Label, OutContext);
84}
85
87 MCSymbol *GOTLabel, MCSymbol *StartLabel,
88 MCSymbol *CurLabel,
89 MCContext &OutContext)
90{
91 const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
92 const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
93 OutContext);
94 const MCSymbolRefExpr *Cur = MCSymbolRefExpr::create(CurLabel,
95 OutContext);
96
97 const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
98 const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
99 const SparcMCExpr *expr = SparcMCExpr::create(Kind,
100 Add, OutContext);
101 return MCOperand::createExpr(expr);
102}
103
104static void EmitCall(MCStreamer &OutStreamer,
105 MCOperand &Callee,
106 const MCSubtargetInfo &STI)
107{
109 CallInst.setOpcode(SP::CALL);
110 CallInst.addOperand(Callee);
111 OutStreamer.emitInstruction(CallInst, STI);
112}
113
114static void EmitRDPC(MCStreamer &OutStreamer, MCOperand &RD,
115 const MCSubtargetInfo &STI) {
116 MCInst RDPCInst;
117 RDPCInst.setOpcode(SP::RDASR);
118 RDPCInst.addOperand(RD);
119 RDPCInst.addOperand(MCOperand::createReg(SP::ASR5));
120 OutStreamer.emitInstruction(RDPCInst, STI);
121}
122
123static void EmitSETHI(MCStreamer &OutStreamer,
124 MCOperand &Imm, MCOperand &RD,
125 const MCSubtargetInfo &STI)
126{
127 MCInst SETHIInst;
128 SETHIInst.setOpcode(SP::SETHIi);
129 SETHIInst.addOperand(RD);
130 SETHIInst.addOperand(Imm);
131 OutStreamer.emitInstruction(SETHIInst, STI);
132}
133
134static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
135 MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
136 const MCSubtargetInfo &STI)
137{
138 MCInst Inst;
139 Inst.setOpcode(Opcode);
140 Inst.addOperand(RD);
141 Inst.addOperand(RS1);
142 Inst.addOperand(Src2);
143 OutStreamer.emitInstruction(Inst, STI);
144}
145
146static void EmitOR(MCStreamer &OutStreamer,
147 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
148 const MCSubtargetInfo &STI) {
149 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
150}
151
152static void EmitADD(MCStreamer &OutStreamer,
153 MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
154 const MCSubtargetInfo &STI) {
155 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
156}
157
158static void EmitSHL(MCStreamer &OutStreamer,
159 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
160 const MCSubtargetInfo &STI) {
161 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
162}
163
164
165static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
168 MCOperand &RD,
169 MCContext &OutContext,
170 const MCSubtargetInfo &STI) {
171
172 MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
173 MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
174 EmitSETHI(OutStreamer, hi, RD, STI);
175 EmitOR(OutStreamer, RD, lo, RD, STI);
176}
177
178void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
179 const MCSubtargetInfo &STI)
180{
181 MCSymbol *GOTLabel =
182 OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
183
184 const MachineOperand &MO = MI->getOperand(0);
185 assert(MO.getReg() != SP::O7 &&
186 "%o7 is assigned as destination for getpcx!");
187
188 MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
189
190
191 if (!isPositionIndependent()) {
192 // Just load the address of GOT to MCRegOP.
193 switch(TM.getCodeModel()) {
194 default:
195 llvm_unreachable("Unsupported absolute code model");
196 case CodeModel::Small:
197 EmitHiLo(*OutStreamer, GOTLabel,
199 MCRegOP, OutContext, STI);
200 break;
201 case CodeModel::Medium: {
202 EmitHiLo(*OutStreamer, GOTLabel,
204 MCRegOP, OutContext, STI);
206 OutContext));
207 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
209 GOTLabel, OutContext);
210 EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI);
211 break;
212 }
213 case CodeModel::Large: {
214 EmitHiLo(*OutStreamer, GOTLabel,
216 MCRegOP, OutContext, STI);
218 OutContext));
219 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
220 // Use register %o7 to load the lower 32 bits.
221 MCOperand RegO7 = MCOperand::createReg(SP::O7);
222 EmitHiLo(*OutStreamer, GOTLabel,
224 RegO7, OutContext, STI);
225 EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
226 }
227 }
228 return;
229 }
230
231 MCSymbol *StartLabel = OutContext.createTempSymbol();
232 MCSymbol *EndLabel = OutContext.createTempSymbol();
233 MCSymbol *SethiLabel = OutContext.createTempSymbol();
234
235 MCOperand RegO7 = MCOperand::createReg(SP::O7);
236
237 // <StartLabel>:
238 // <GET-PC> // This will be either `call <EndLabel>` or `rd %pc, %o7`.
239 // <SethiLabel>:
240 // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
241 // <EndLabel>:
242 // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
243 // add <MO>, %o7, <MO>
244
245 OutStreamer->emitLabel(StartLabel);
246 if (!STI.getTargetTriple().isSPARC64() ||
247 STI.hasFeature(Sparc::TuneSlowRDPC)) {
248 MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
249 EmitCall(*OutStreamer, Callee, STI);
250 } else {
251 // TODO find out whether it is possible to store PC
252 // in other registers, to enable leaf function optimization.
253 // (On the other hand, approx. over 97.8% of GETPCXes happen
254 // in non-leaf functions, so would this be worth the effort?)
255 EmitRDPC(*OutStreamer, RegO7, STI);
256 }
257 OutStreamer->emitLabel(SethiLabel);
259 GOTLabel, StartLabel, SethiLabel,
260 OutContext);
261 EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
262 OutStreamer->emitLabel(EndLabel);
264 GOTLabel, StartLabel, EndLabel,
265 OutContext);
266 EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
267 EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
268}
269
270void SparcAsmPrinter::emitInstruction(const MachineInstr *MI) {
271 Sparc_MC::verifyInstructionPredicates(MI->getOpcode(),
272 getSubtargetInfo().getFeatureBits());
273
274 switch (MI->getOpcode()) {
275 default: break;
276 case TargetOpcode::DBG_VALUE:
277 // FIXME: Debug Value.
278 return;
279 case SP::CASArr:
280 case SP::SWAPrr:
281 case SP::SWAPri:
282 if (MF->getSubtarget<SparcSubtarget>().fixTN0011())
283 OutStreamer->emitCodeAlignment(Align(16), &getSubtargetInfo());
284 break;
285 case SP::GETPCX:
286 LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
287 return;
288 }
290 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
291 do {
292 MCInst TmpInst;
293 LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
294 EmitToStreamer(*OutStreamer, TmpInst);
295 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
296}
297
298void SparcAsmPrinter::emitFunctionBodyStart() {
299 if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
300 return;
301
302 const MachineRegisterInfo &MRI = MF->getRegInfo();
303 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
304 for (unsigned i = 0; globalRegs[i] != 0; ++i) {
305 unsigned reg = globalRegs[i];
306 if (MRI.use_empty(reg))
307 continue;
308
309 if (reg == SP::G6 || reg == SP::G7)
310 getTargetStreamer().emitSparcRegisterIgnore(reg);
311 else
312 getTargetStreamer().emitSparcRegisterScratch(reg);
313 }
314}
315
316void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
317 raw_ostream &O) {
318 const DataLayout &DL = getDataLayout();
319 const MachineOperand &MO = MI->getOperand (opNum);
321
322 bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
323
324 switch (MO.getType()) {
326 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
327 break;
328
330 O << MO.getImm();
331 break;
333 MO.getMBB()->getSymbol()->print(O, MAI);
334 return;
336 PrintSymbolOperand(MO, O);
337 break;
339 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
340 break;
342 O << MO.getSymbolName();
343 break;
345 O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
346 << MO.getIndex();
347 break;
349 MO.getMetadata()->printAsOperand(O, MMI->getModule());
350 break;
351 default:
352 llvm_unreachable("<unknown operand type>");
353 }
354 if (CloseParen) O << ")";
355}
356
357void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
358 raw_ostream &O) {
359 printOperand(MI, opNum, O);
360
361 if (MI->getOperand(opNum+1).isReg() &&
362 MI->getOperand(opNum+1).getReg() == SP::G0)
363 return; // don't print "+%g0"
364 if (MI->getOperand(opNum+1).isImm() &&
365 MI->getOperand(opNum+1).getImm() == 0)
366 return; // don't print "+0"
367
368 O << "+";
369 printOperand(MI, opNum+1, O);
370}
371
372/// PrintAsmOperand - Print out an operand for an inline asm expression.
373///
374bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
375 const char *ExtraCode,
376 raw_ostream &O) {
377 if (ExtraCode && ExtraCode[0]) {
378 if (ExtraCode[1] != 0) return true; // Unknown modifier.
379
380 switch (ExtraCode[0]) {
381 default:
382 // See if this is a generic print operand
383 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
384 case 'L': // Low order register of a twin word register operand
385 case 'H': // High order register of a twin word register operand
386 {
387 const SparcSubtarget &Subtarget = MF->getSubtarget<SparcSubtarget>();
388 const MachineOperand &MO = MI->getOperand(OpNo);
389 const SparcRegisterInfo *RegisterInfo = Subtarget.getRegisterInfo();
390 Register MOReg = MO.getReg();
391
392 Register HiReg, LoReg;
393 if (!SP::IntPairRegClass.contains(MOReg)) {
394 // If we aren't given a register pair already, find out which pair it
395 // belongs to. Note that here, the specified register operand, which
396 // refers to the high part of the twinword, needs to be an even-numbered
397 // register.
398 MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even,
399 &SP::IntPairRegClass);
400 if (!MOReg) {
401 SMLoc Loc;
402 OutContext.reportError(
403 Loc, "Hi part of pair should point to an even-numbered register");
404 OutContext.reportError(
405 Loc, "(note that in some cases it might be necessary to manually "
406 "bind the input/output registers instead of relying on "
407 "automatic allocation)");
408 return true;
409 }
410 }
411
412 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even);
413 LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd);
414
416 switch (ExtraCode[0]) {
417 case 'L':
418 Reg = LoReg;
419 break;
420 case 'H':
421 Reg = HiReg;
422 break;
423 }
424
426 return false;
427 }
428 case 'f':
429 case 'r':
430 break;
431 }
432 }
433
434 printOperand(MI, OpNo, O);
435
436 return false;
437}
438
439bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
440 unsigned OpNo,
441 const char *ExtraCode,
442 raw_ostream &O) {
443 if (ExtraCode && ExtraCode[0])
444 return true; // Unknown modifier
445
446 O << '[';
447 printMemOperand(MI, OpNo, O);
448 O << ']';
449
450 return false;
451}
452
453// Force static initialization.
458}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
Symbol * Sym
Definition: ELF_riscv.cpp:479
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Definition: MIParser.cpp:1416
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO, const MachineFunction *MF, const Module *M, const MachineFrameInfo *MFI, const TargetInstrInfo *TII, LLVMContext &Ctx)
static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, MCSymbol *Sym, MCContext &OutContext)
static MCOperand createPCXCallOP(MCSymbol *Label, MCContext &OutContext)
static void EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcAsmPrinter()
static void EmitCall(MCStreamer &OutStreamer, MCOperand &Callee, const MCSubtargetInfo &STI)
static void EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static void EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI)
static void EmitRDPC(MCStreamer &OutStreamer, MCOperand &RD, const MCSubtargetInfo &STI)
static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, MCSymbol *GOTLabel, MCSymbol *StartLabel, MCSymbol *CurLabel, MCContext &OutContext)
static void EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI)
static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI)
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:86
virtual void emitInstruction(const MachineInstr *)
Targets should implement this to emit instructions.
Definition: AsmPrinter.h:561
virtual void emitFunctionBodyStart()
Targets can override this to emit stuff before the first basic block in the function.
Definition: AsmPrinter.h:545
virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
This class represents a function call, abstracting a target machine's calling convention.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
Binary assembler expressions.
Definition: MCExpr.h:493
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:537
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:622
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:222
Context object for machine code objects.
Definition: MCContext.h:83
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
void setOpcode(unsigned Op)
Definition: MCInst.h:198
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:163
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:213
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:398
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:58
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Instructions::const_iterator const_instr_iterator
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
const MDNode * getMetadata() const
MachineBasicBlock * getMBB() const
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_Metadata
Metadata reference (for debug info)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:5250
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents a location in source code.
Definition: SMLoc.h:23
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=SP::NoRegAltName)
static const SparcMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: SparcMCExpr.cpp:27
static bool printVariantKind(raw_ostream &OS, VariantKind Kind)
Definition: SparcMCExpr.cpp:43
const SparcRegisterInfo * getRegisterInfo() const override
bool is64Bit() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
std::string lower() const
Definition: StringRef.cpp:113
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
bool isSPARC64() const
Tests whether the target is 64-bit SPARC (big endian).
Definition: Triple.h:1017
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSparcTarget()
Target & getTheSparcV9Target()
void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
@ Add
Sum of integers.
Target & getTheSparcelTarget()
ArrayRef< int > lo(ArrayRef< int > Vuu)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...