LLVM 18.0.0git
SparcAsmPrinter.cpp
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1//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format SPARC assembly language.
11//
12//===----------------------------------------------------------------------===//
13
17#include "Sparc.h"
18#include "SparcInstrInfo.h"
19#include "SparcTargetMachine.h"
26#include "llvm/IR/Mangler.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/MC/MCContext.h"
29#include "llvm/MC/MCInst.h"
30#include "llvm/MC/MCStreamer.h"
31#include "llvm/MC/MCSymbol.h"
34using namespace llvm;
35
36#define DEBUG_TYPE "asm-printer"
37
38namespace {
39 class SparcAsmPrinter : public AsmPrinter {
40 SparcTargetStreamer &getTargetStreamer() {
41 return static_cast<SparcTargetStreamer &>(
42 *OutStreamer->getTargetStreamer());
43 }
44 public:
45 explicit SparcAsmPrinter(TargetMachine &TM,
46 std::unique_ptr<MCStreamer> Streamer)
47 : AsmPrinter(TM, std::move(Streamer)) {}
48
49 StringRef getPassName() const override { return "Sparc Assembly Printer"; }
50
51 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
52 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
53 const char *Modifier = nullptr);
54
55 void emitFunctionBodyStart() override;
56 void emitInstruction(const MachineInstr *MI) override;
57
58 static const char *getRegisterName(MCRegister Reg) {
60 }
61
62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
63 const char *ExtraCode, raw_ostream &O) override;
64 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
65 const char *ExtraCode, raw_ostream &O) override;
66
67 void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
68 const MCSubtargetInfo &STI);
69
70 };
71} // end of anonymous namespace
72
74 MCSymbol *Sym, MCContext &OutContext) {
76 OutContext);
77 const SparcMCExpr *expr = SparcMCExpr::create(Kind, MCSym, OutContext);
78 return MCOperand::createExpr(expr);
79
80}
82 MCContext &OutContext) {
83 return createSparcMCOperand(SparcMCExpr::VK_Sparc_WDISP30, Label, OutContext);
84}
85
87 MCSymbol *GOTLabel, MCSymbol *StartLabel,
88 MCSymbol *CurLabel,
89 MCContext &OutContext)
90{
91 const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
92 const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
93 OutContext);
94 const MCSymbolRefExpr *Cur = MCSymbolRefExpr::create(CurLabel,
95 OutContext);
96
97 const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
98 const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
99 const SparcMCExpr *expr = SparcMCExpr::create(Kind,
100 Add, OutContext);
101 return MCOperand::createExpr(expr);
102}
103
104static void EmitCall(MCStreamer &OutStreamer,
105 MCOperand &Callee,
106 const MCSubtargetInfo &STI)
107{
109 CallInst.setOpcode(SP::CALL);
110 CallInst.addOperand(Callee);
111 OutStreamer.emitInstruction(CallInst, STI);
112}
113
114static void EmitSETHI(MCStreamer &OutStreamer,
115 MCOperand &Imm, MCOperand &RD,
116 const MCSubtargetInfo &STI)
117{
118 MCInst SETHIInst;
119 SETHIInst.setOpcode(SP::SETHIi);
120 SETHIInst.addOperand(RD);
121 SETHIInst.addOperand(Imm);
122 OutStreamer.emitInstruction(SETHIInst, STI);
123}
124
125static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
127 const MCSubtargetInfo &STI)
128{
129 MCInst Inst;
130 Inst.setOpcode(Opcode);
131 Inst.addOperand(RD);
132 Inst.addOperand(RS1);
133 Inst.addOperand(Src2);
134 OutStreamer.emitInstruction(Inst, STI);
135}
136
137static void EmitOR(MCStreamer &OutStreamer,
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
139 const MCSubtargetInfo &STI) {
140 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
141}
142
143static void EmitADD(MCStreamer &OutStreamer,
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
145 const MCSubtargetInfo &STI) {
146 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
147}
148
149static void EmitSHL(MCStreamer &OutStreamer,
150 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
151 const MCSubtargetInfo &STI) {
152 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
153}
154
155
156static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
159 MCOperand &RD,
160 MCContext &OutContext,
161 const MCSubtargetInfo &STI) {
162
163 MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
164 MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
165 EmitSETHI(OutStreamer, hi, RD, STI);
166 EmitOR(OutStreamer, RD, lo, RD, STI);
167}
168
169void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
170 const MCSubtargetInfo &STI)
171{
172 MCSymbol *GOTLabel =
173 OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
174
175 const MachineOperand &MO = MI->getOperand(0);
176 assert(MO.getReg() != SP::O7 &&
177 "%o7 is assigned as destination for getpcx!");
178
179 MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
180
181
182 if (!isPositionIndependent()) {
183 // Just load the address of GOT to MCRegOP.
184 switch(TM.getCodeModel()) {
185 default:
186 llvm_unreachable("Unsupported absolute code model");
187 case CodeModel::Small:
188 EmitHiLo(*OutStreamer, GOTLabel,
190 MCRegOP, OutContext, STI);
191 break;
192 case CodeModel::Medium: {
193 EmitHiLo(*OutStreamer, GOTLabel,
195 MCRegOP, OutContext, STI);
197 OutContext));
198 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
200 GOTLabel, OutContext);
201 EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI);
202 break;
203 }
204 case CodeModel::Large: {
205 EmitHiLo(*OutStreamer, GOTLabel,
207 MCRegOP, OutContext, STI);
209 OutContext));
210 EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
211 // Use register %o7 to load the lower 32 bits.
212 MCOperand RegO7 = MCOperand::createReg(SP::O7);
213 EmitHiLo(*OutStreamer, GOTLabel,
215 RegO7, OutContext, STI);
216 EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
217 }
218 }
219 return;
220 }
221
222 MCSymbol *StartLabel = OutContext.createTempSymbol();
223 MCSymbol *EndLabel = OutContext.createTempSymbol();
224 MCSymbol *SethiLabel = OutContext.createTempSymbol();
225
226 MCOperand RegO7 = MCOperand::createReg(SP::O7);
227
228 // <StartLabel>:
229 // call <EndLabel>
230 // <SethiLabel>:
231 // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
232 // <EndLabel>:
233 // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
234 // add <MO>, %o7, <MO>
235
236 OutStreamer->emitLabel(StartLabel);
237 MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
238 EmitCall(*OutStreamer, Callee, STI);
239 OutStreamer->emitLabel(SethiLabel);
241 GOTLabel, StartLabel, SethiLabel,
242 OutContext);
243 EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
244 OutStreamer->emitLabel(EndLabel);
246 GOTLabel, StartLabel, EndLabel,
247 OutContext);
248 EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
249 EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
250}
251
252void SparcAsmPrinter::emitInstruction(const MachineInstr *MI) {
253 Sparc_MC::verifyInstructionPredicates(MI->getOpcode(),
254 getSubtargetInfo().getFeatureBits());
255
256 switch (MI->getOpcode()) {
257 default: break;
258 case TargetOpcode::DBG_VALUE:
259 // FIXME: Debug Value.
260 return;
261 case SP::GETPCX:
262 LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
263 return;
264 }
266 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
267 do {
268 MCInst TmpInst;
269 LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
270 EmitToStreamer(*OutStreamer, TmpInst);
271 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
272}
273
274void SparcAsmPrinter::emitFunctionBodyStart() {
275 if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
276 return;
277
278 const MachineRegisterInfo &MRI = MF->getRegInfo();
279 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
280 for (unsigned i = 0; globalRegs[i] != 0; ++i) {
281 unsigned reg = globalRegs[i];
282 if (MRI.use_empty(reg))
283 continue;
284
285 if (reg == SP::G6 || reg == SP::G7)
286 getTargetStreamer().emitSparcRegisterIgnore(reg);
287 else
288 getTargetStreamer().emitSparcRegisterScratch(reg);
289 }
290}
291
292void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
293 raw_ostream &O) {
294 const DataLayout &DL = getDataLayout();
295 const MachineOperand &MO = MI->getOperand (opNum);
297
298#ifndef NDEBUG
299 // Verify the target flags.
300 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
301 if (MI->getOpcode() == SP::CALL)
303 "Cannot handle target flags on call address");
304 else if (MI->getOpcode() == SP::SETHIi)
314 "Invalid target flags for address operand on sethi");
315 else if (MI->getOpcode() == SP::TLS_CALL)
319 "Cannot handle target flags on tls call address");
320 else if (MI->getOpcode() == SP::TLS_ADDrr)
325 "Cannot handle target flags on add for TLS");
326 else if (MI->getOpcode() == SP::TLS_LDrr)
328 "Cannot handle target flags on ld for TLS");
329 else if (MI->getOpcode() == SP::TLS_LDXrr)
331 "Cannot handle target flags on ldx for TLS");
332 else if (MI->getOpcode() == SP::XORri)
335 "Cannot handle target flags on xor for TLS");
336 else
344 "Invalid target flags for small address operand");
345 }
346#endif
347
348
349 bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
350
351 switch (MO.getType()) {
353 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
354 break;
355
357 O << MO.getImm();
358 break;
360 MO.getMBB()->getSymbol()->print(O, MAI);
361 return;
363 PrintSymbolOperand(MO, O);
364 break;
366 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
367 break;
369 O << MO.getSymbolName();
370 break;
372 O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
373 << MO.getIndex();
374 break;
376 MO.getMetadata()->printAsOperand(O, MMI->getModule());
377 break;
378 default:
379 llvm_unreachable("<unknown operand type>");
380 }
381 if (CloseParen) O << ")";
382}
383
384void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
385 raw_ostream &O, const char *Modifier) {
386 printOperand(MI, opNum, O);
387
388 // If this is an ADD operand, emit it like normal operands.
389 if (Modifier && !strcmp(Modifier, "arith")) {
390 O << ", ";
391 printOperand(MI, opNum+1, O);
392 return;
393 }
394
395 if (MI->getOperand(opNum+1).isReg() &&
396 MI->getOperand(opNum+1).getReg() == SP::G0)
397 return; // don't print "+%g0"
398 if (MI->getOperand(opNum+1).isImm() &&
399 MI->getOperand(opNum+1).getImm() == 0)
400 return; // don't print "+0"
401
402 O << "+";
403 printOperand(MI, opNum+1, O);
404}
405
406/// PrintAsmOperand - Print out an operand for an inline asm expression.
407///
408bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
409 const char *ExtraCode,
410 raw_ostream &O) {
411 if (ExtraCode && ExtraCode[0]) {
412 if (ExtraCode[1] != 0) return true; // Unknown modifier.
413
414 switch (ExtraCode[0]) {
415 default:
416 // See if this is a generic print operand
417 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
418 case 'f':
419 case 'r':
420 break;
421 }
422 }
423
424 printOperand(MI, OpNo, O);
425
426 return false;
427}
428
429bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
430 unsigned OpNo,
431 const char *ExtraCode,
432 raw_ostream &O) {
433 if (ExtraCode && ExtraCode[0])
434 return true; // Unknown modifier
435
436 O << '[';
437 printMemOperand(MI, OpNo, O);
438 O << ']';
439
440 return false;
441}
442
443// Force static initialization.
448}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
Symbol * Sym
Definition: ELF_riscv.cpp:477
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Definition: MIParser.cpp:1414
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO, const MachineFunction *MF, const Module *M, const MachineFrameInfo *MFI, const TargetInstrInfo *TII, LLVMContext &Ctx)
static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, MCSymbol *Sym, MCContext &OutContext)
static MCOperand createPCXCallOP(MCSymbol *Label, MCContext &OutContext)
static void EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcAsmPrinter()
static void EmitCall(MCStreamer &OutStreamer, MCOperand &Callee, const MCSubtargetInfo &STI)
static void EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static void EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI)
static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, MCSymbol *GOTLabel, MCSymbol *StartLabel, MCSymbol *CurLabel, MCContext &OutContext)
static void EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI)
static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI)
static constexpr uint32_t Opcode
Definition: aarch32.h:200
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:84
virtual void emitInstruction(const MachineInstr *)
Targets should implement this to emit instructions.
Definition: AsmPrinter.h:571
virtual void emitFunctionBodyStart()
Targets can override this to emit stuff before the first basic block in the function.
Definition: AsmPrinter.h:555
virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
This class represents a function call, abstracting a target machine's calling convention.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Binary assembler expressions.
Definition: MCExpr.h:484
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:528
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:613
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:389
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:58
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Instructions::const_iterator const_instr_iterator
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
const MDNode * getMetadata() const
MachineBasicBlock * getMBB() const
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_Metadata
Metadata reference (for debug info)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:5046
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=SP::NoRegAltName)
static const SparcMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: SparcMCExpr.cpp:27
static bool printVariantKind(raw_ostream &OS, VariantKind Kind)
Definition: SparcMCExpr.cpp:43
bool is64Bit() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string lower() const
Definition: StringRef.cpp:111
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSparcTarget()
Target & getTheSparcV9Target()
void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
@ Add
Sum of integers.
Target & getTheSparcelTarget()
ArrayRef< int > lo(ArrayRef< int > Vuu)
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...