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28 #define DEBUG_TYPE "loongarch-disassembler"
47 return new LoongArchDisassembler(STI, Ctx);
103 template <
unsigned N,
int P = 0>
107 assert(isUInt<N>(
Imm) &&
"Invalid immediate");
112 template <
unsigned N,
unsigned S = 0>
116 assert(isUInt<N>(
Imm) &&
"Invalid immediate");
123 #include "LoongArchGenDisassemblerTables.inc"
134 if (Bytes.
size() < 4) {
141 Result = decodeInstruction(DecoderTable32,
MI,
Insn, Address,
this, STI);
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheLoongArch32Target()
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Target - Wrapper for Target specific information.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Instances of this class represent a single low-level machine instruction.
MCDisassembler::DecodeStatus DecodeStatus
This class implements an extremely fast bulk output stream that can only output to a stream.
DecodeStatus
Ternary decode status.
void addOperand(const MCOperand Op)
static MCDisassembler * createLoongArchDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeFCSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_EXTERNAL_VISIBILITY
Superclass for all disassemblers.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static MCOperand createReg(unsigned Reg)
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchDisassembler()
uint32_t read32le(const void *P)
static DecodeStatus DecodeCFRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
size_t size() const
size - Get the array size.
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Generic base class for all target subtargets.
Target & getTheLoongArch64Target()
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)