33 #define DEBUG_TYPE "hexagon-disassembler"
36 using namespace Hexagon;
45 std::unique_ptr<MCInstrInfo const>
const MCII;
46 std::unique_ptr<MCInst *> CurrentBundle;
47 mutable MCInst const *CurrentExtender;
52 CurrentExtender(
nullptr) {}
60 void remapInstruction(
MCInst &Instr)
const;
63 static uint64_t fullValue(HexagonDisassembler
const &Disassembler,
MCInst &
MI,
66 if (!Disassembler.CurrentExtender ||
73 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
81 static HexagonDisassembler
const &disassembler(
const MCDisassembler *Decoder) {
82 return *
static_cast<HexagonDisassembler
const *
>(Decoder);
87 HexagonDisassembler
const &Disassembler = disassembler(Decoder);
88 int64_t FullValue = fullValue(Disassembler,
MI, SignExtend64<T>(
tmp));
89 int64_t Extended = SignExtend64<32>(FullValue);
160 #include "HexagonGenDisassemblerTables.inc"
165 return new HexagonDisassembler(STI, Ctx,
T.createMCInstrInfo());
178 bool Complete =
false;
181 *CurrentBundle = &
MI;
182 MI.setOpcode(Hexagon::BUNDLE);
184 while (Result ==
Success && !Complete) {
187 MCInst *Inst = getContext().createMCInst();
188 Result = getSingleInstruction(*Inst,
MI, Bytes, Address, cs, Complete);
199 const auto STI_ = (ArchSTI !=
nullptr) ? *ArchSTI : STI;
201 *getContext().getRegisterInfo(),
false);
202 if (!Checker.check())
204 remapInstruction(
MI);
208 void HexagonDisassembler::remapInstruction(
MCInst &Instr)
const {
210 auto &
MI =
const_cast<MCInst &
>(*
I.getInst());
211 switch (
MI.getOpcode()) {
212 case Hexagon::S2_allocframe:
213 if (
MI.getOperand(0).getReg() == Hexagon::R29) {
214 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
215 MI.erase(
MI.begin () + 1);
216 MI.erase(
MI.begin ());
219 case Hexagon::L2_deallocframe:
220 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
221 MI.getOperand(1).getReg() == Hexagon::R30) {
222 MI.setOpcode(L6_deallocframe_map_to_raw);
223 MI.erase(
MI.begin () + 1);
224 MI.erase(
MI.begin ());
227 case Hexagon::L4_return:
228 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
229 MI.getOperand(1).getReg() == Hexagon::R30) {
230 MI.setOpcode(L6_return_map_to_raw);
231 MI.erase(
MI.begin () + 1);
232 MI.erase(
MI.begin ());
235 case Hexagon::L4_return_t:
236 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
237 MI.getOperand(2).getReg() == Hexagon::R30) {
238 MI.setOpcode(L4_return_map_to_raw_t);
239 MI.erase(
MI.begin () + 2);
240 MI.erase(
MI.begin ());
243 case Hexagon::L4_return_f:
244 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
245 MI.getOperand(2).getReg() == Hexagon::R30) {
246 MI.setOpcode(L4_return_map_to_raw_f);
247 MI.erase(
MI.begin () + 2);
248 MI.erase(
MI.begin ());
251 case Hexagon::L4_return_tnew_pt:
252 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
253 MI.getOperand(2).getReg() == Hexagon::R30) {
254 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
255 MI.erase(
MI.begin () + 2);
256 MI.erase(
MI.begin ());
259 case Hexagon::L4_return_fnew_pt:
260 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
261 MI.getOperand(2).getReg() == Hexagon::R30) {
262 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
263 MI.erase(
MI.begin () + 2);
264 MI.erase(
MI.begin ());
267 case Hexagon::L4_return_tnew_pnt:
268 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
269 MI.getOperand(2).getReg() == Hexagon::R30) {
270 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
271 MI.erase(
MI.begin () + 2);
272 MI.erase(
MI.begin ());
275 case Hexagon::L4_return_fnew_pnt:
276 if (
MI.getOperand(0).getReg() == Hexagon::D15 &&
277 MI.getOperand(2).getReg() == Hexagon::R30) {
278 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
279 MI.erase(
MI.begin () + 2);
280 MI.erase(
MI.begin ());
288 switch (
MI.getOpcode()) {
289 case Hexagon::SA1_setin1:
290 MI.insert(
MI.begin() + 1,
293 case Hexagon::SA1_dec:
294 MI.insert(
MI.begin() + 2,
306 bool &Complete)
const {
316 else if (BundleSize == 1)
328 unsigned duplexIClass;
329 uint8_t
const *DecodeLow, *DecodeHigh;
331 switch (duplexIClass) {
335 DecodeLow = DecoderTableSUBINSN_L132;
336 DecodeHigh = DecoderTableSUBINSN_L132;
339 DecodeLow = DecoderTableSUBINSN_L232;
340 DecodeHigh = DecoderTableSUBINSN_L132;
343 DecodeLow = DecoderTableSUBINSN_L232;
344 DecodeHigh = DecoderTableSUBINSN_L232;
347 DecodeLow = DecoderTableSUBINSN_A32;
348 DecodeHigh = DecoderTableSUBINSN_A32;
351 DecodeLow = DecoderTableSUBINSN_L132;
352 DecodeHigh = DecoderTableSUBINSN_A32;
355 DecodeLow = DecoderTableSUBINSN_L232;
356 DecodeHigh = DecoderTableSUBINSN_A32;
359 DecodeLow = DecoderTableSUBINSN_S132;
360 DecodeHigh = DecoderTableSUBINSN_A32;
363 DecodeLow = DecoderTableSUBINSN_S232;
364 DecodeHigh = DecoderTableSUBINSN_A32;
367 DecodeLow = DecoderTableSUBINSN_S132;
368 DecodeHigh = DecoderTableSUBINSN_L132;
371 DecodeLow = DecoderTableSUBINSN_S132;
372 DecodeHigh = DecoderTableSUBINSN_L232;
375 DecodeLow = DecoderTableSUBINSN_S132;
376 DecodeHigh = DecoderTableSUBINSN_S132;
379 DecodeLow = DecoderTableSUBINSN_S232;
380 DecodeHigh = DecoderTableSUBINSN_S132;
383 DecodeLow = DecoderTableSUBINSN_S232;
384 DecodeHigh = DecoderTableSUBINSN_L132;
387 DecodeLow = DecoderTableSUBINSN_S232;
388 DecodeHigh = DecoderTableSUBINSN_L232;
391 DecodeLow = DecoderTableSUBINSN_S232;
392 DecodeHigh = DecoderTableSUBINSN_S232;
395 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
396 MCInst *MILow = getContext().createMCInst();
397 MCInst *MIHigh = getContext().createMCInst();
398 auto TmpExtender = CurrentExtender;
403 CurrentExtender = TmpExtender;
407 Result = decodeInstruction(
408 DecodeHigh, *MIHigh, (
Instruction >> 16) & 0x1fff, Address,
this, STI);
414 MI.addOperand(OPLow);
415 MI.addOperand(OPHigh);
422 if (CurrentExtender !=
nullptr)
431 STI.getFeatureBits()[Hexagon::ExtensionHVX])
437 switch (
MI.getOpcode()) {
438 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
439 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
440 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
441 case Hexagon::J4_cmpeqn1_fp0_jump_t:
442 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
443 case Hexagon::J4_cmpeqn1_fp1_jump_t:
444 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
445 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
446 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
447 case Hexagon::J4_cmpeqn1_tp0_jump_t:
448 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
449 case Hexagon::J4_cmpeqn1_tp1_jump_t:
450 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
451 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
452 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
453 case Hexagon::J4_cmpgtn1_fp0_jump_t:
454 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
455 case Hexagon::J4_cmpgtn1_fp1_jump_t:
456 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
457 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
458 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
459 case Hexagon::J4_cmpgtn1_tp0_jump_t:
460 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
461 case Hexagon::J4_cmpgtn1_tp1_jump_t:
462 MI.insert(
MI.begin() + 1,
472 assert(MCO.
isReg() &&
"New value consumers must be registers");
474 getContext().getRegisterInfo()->getEncodingValue(MCO.
getReg());
478 unsigned Lookback = (
Register & 0x6) >> 1;
481 bool PrevVector =
false;
489 if (Vector && !CurrentVector)
494 PrevVector = CurrentVector;
495 if (Offset == Lookback)
498 auto const &Inst = *
i->getInst();
499 bool SubregBit = (
Register & 0x1) != 0;
505 assert(Producer != Hexagon::NoRegister);
513 const unsigned ProdPairIndex =
515 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
516 }
else if (SubregBit)
520 assert(Producer != Hexagon::NoRegister);
526 if (CurrentExtender !=
nullptr) {
528 ? *
MI.getOperand(1).getInst()
539 if (RegNo < Table.
size()) {
558 Hexagon::R5,
Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
559 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
560 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
561 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
562 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
563 Hexagon::R30, Hexagon::R31};
572 static const MCPhysReg GeneralSubRegDecoderTable[] = {
573 Hexagon::R0, Hexagon::R1,
Hexagon::R2, Hexagon::R3,
575 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
576 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
585 static const MCPhysReg HvxVRDecoderTable[] = {
587 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
588 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
589 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
590 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
591 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
592 Hexagon::V30, Hexagon::V31};
601 static const MCPhysReg DoubleRegDecoderTable[] = {
602 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
603 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
604 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
605 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
614 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
615 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
616 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
624 static const MCPhysReg HvxWRDecoderTable[] = {
625 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
626 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
627 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
628 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
629 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
630 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
631 Hexagon::W15, Hexagon::WR15,
642 static const MCPhysReg HvxVQRDecoderTable[] = {
643 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
644 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
652 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
661 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
662 Hexagon::Q2, Hexagon::Q3};
670 using namespace Hexagon;
672 static const MCPhysReg CtrlRegDecoderTable[] = {
676 CS0, CS1, UPCYCLELO, UPCYCLEHI,
677 FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
680 0, 0, UTIMERLO, UTIMERHI
683 if (RegNo >=
std::size(CtrlRegDecoderTable))
686 static_assert(NoRegister == 0,
"Expecting NoRegister to be 0");
687 if (CtrlRegDecoderTable[RegNo] == NoRegister)
690 unsigned Register = CtrlRegDecoderTable[RegNo];
698 using namespace Hexagon;
700 static const MCPhysReg CtrlReg64DecoderTable[] = {
705 C17_16, 0, PKTCOUNT, 0,
711 if (RegNo >=
std::size(CtrlReg64DecoderTable))
714 static_assert(NoRegister == 0,
"Expecting NoRegister to be 0");
715 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
718 unsigned Register = CtrlReg64DecoderTable[RegNo];
744 HexagonDisassembler
const &Disassembler = disassembler(Decoder);
745 int64_t FullValue = fullValue(Disassembler,
MI,
tmp);
746 assert(FullValue >= 0 &&
"Negative in unsigned decoder");
754 HexagonDisassembler
const &Disassembler = disassembler(Decoder);
757 signedDecoder<32>(
MI,
tmp, Decoder);
764 HexagonDisassembler
const &Disassembler = disassembler(Decoder);
770 uint32_t Extended = FullValue + Address;
771 if (!Disassembler.tryAddingSymbolicOperand(
MI, Extended, Address,
true, 0, 0,
778 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
779 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
780 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
781 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
782 Hexagon::S12, Hexagon::S13, Hexagon::S14,
783 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
784 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
785 Hexagon::VID, Hexagon::S22, Hexagon::S23,
786 Hexagon::S24, Hexagon::S25, Hexagon::S26,
787 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
788 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
789 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
790 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
791 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
792 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
793 Hexagon::S45, Hexagon::S46, Hexagon::S47,
794 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
795 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
796 Hexagon::S54, Hexagon::S55, Hexagon::S56,
797 Hexagon::S57, Hexagon::S58, Hexagon::S59,
798 Hexagon::S60, Hexagon::S61, Hexagon::S62,
799 Hexagon::S63, Hexagon::S64, Hexagon::S65,
800 Hexagon::S66, Hexagon::S67, Hexagon::S68,
801 Hexagon::S69, Hexagon::S70, Hexagon::S71,
802 Hexagon::S72, Hexagon::S73, Hexagon::S74,
803 Hexagon::S75, Hexagon::S76, Hexagon::S77,
804 Hexagon::S78, Hexagon::S79, Hexagon::S80,
822 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
823 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
824 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
825 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
826 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
827 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
828 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
829 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
830 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
831 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
852 using namespace Hexagon;
854 static const MCPhysReg GuestRegDecoderTable[] = {
859 GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
861 GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
862 GPMUCNT2, GPMUCNT3, G30, G31
865 if (RegNo >=
std::size(GuestRegDecoderTable))
867 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
870 unsigned Register = GuestRegDecoderTable[RegNo];
879 using namespace Hexagon;
881 static const MCPhysReg GuestReg64DecoderTable[] = {
885 G13_12, 0, G15_14, 0,
886 G17_16, 0, G19_18, 0,
887 G21_20, 0, G23_22, 0,
888 G25_24, 0, G27_26, 0,
892 if (RegNo >=
std::size(GuestReg64DecoderTable))
894 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
897 unsigned Register = GuestReg64DecoderTable[RegNo];