LLVM  14.0.0git
HexagonDisassembler.cpp
Go to the documentation of this file.
1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/TargetRegistry.h"
25 #include "llvm/Support/Endian.h"
28 #include <cassert>
29 #include <cstddef>
30 #include <cstdint>
31 #include <memory>
32 
33 #define DEBUG_TYPE "hexagon-disassembler"
34 
35 using namespace llvm;
36 using namespace Hexagon;
37 
39 
40 namespace {
41 
42 /// Hexagon disassembler for all Hexagon platforms.
43 class HexagonDisassembler : public MCDisassembler {
44 public:
45  std::unique_ptr<MCInstrInfo const> const MCII;
46  std::unique_ptr<MCInst *> CurrentBundle;
47  mutable MCInst const *CurrentExtender;
48 
49  HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
50  MCInstrInfo const *MCII)
51  : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
52  CurrentExtender(nullptr) {}
53 
54  DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
56  raw_ostream &CStream, bool &Complete) const;
57  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
59  raw_ostream &CStream) const override;
60  void remapInstruction(MCInst &Instr) const;
61 };
62 
63 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
64  int64_t Value) {
65  MCInstrInfo MCII = *Disassembler.MCII;
66  if (!Disassembler.CurrentExtender ||
67  MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
68  return Value;
69  unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
70  uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
71  int64_t Bits;
72  bool Success =
73  Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
74  Bits);
75  assert(Success);
76  (void)Success;
77  uint64_t Upper26 = static_cast<uint64_t>(Bits);
78  uint64_t Operand = Upper26 | Lower6;
79  return Operand;
80 }
81 static HexagonDisassembler const &disassembler(void const *Decoder) {
82  return *static_cast<HexagonDisassembler const *>(Decoder);
83 }
84 template <size_t T>
85 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
86  HexagonDisassembler const &Disassembler = disassembler(Decoder);
87  int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
88  int64_t Extended = SignExtend64<32>(FullValue);
89  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
90 }
91 }
92 
93 // Forward declare these because the auto-generated code will reference them.
94 // Definitions are further down.
95 
96 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
97  uint64_t Address,
98  const void *Decoder);
100  unsigned RegNo,
101  uint64_t Address,
102  const void *Decoder);
103 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
104  uint64_t Address,
105  const void *Decoder);
106 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
107  uint64_t Address,
108  const void *Decoder);
109 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
110  uint64_t Address,
111  const void *Decoder);
112 static DecodeStatus
114  uint64_t Address, const void *Decoder);
115 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
116  uint64_t Address,
117  const void *Decoder);
119  unsigned RegNo,
120  uint64_t Address,
121  const void *Decoder);
122 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
123  uint64_t Address,
124  const void *Decoder);
125 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
126  uint64_t Address,
127  const void *Decoder);
128 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
129  uint64_t Address,
130  const void *Decoder);
131 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
132  uint64_t Address,
133  const void *Decoder);
134 static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
135  uint64_t Address,
136  const void *Decoder);
137 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
138  uint64_t Address,
139  const void *Decoder);
140 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
141  uint64_t Address,
142  const void *Decoder);
143 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
144  uint64_t Address,
145  const void *Decoder);
146 static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
147  uint64_t Address,
148  const void *Decoder);
149 
150 
151 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
152  uint64_t Address, const void *Decoder);
153 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
154  uint64_t /*Address*/, const void *Decoder);
155 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
156  const void *Decoder);
157 #include "HexagonDepDecoders.inc"
158 #include "HexagonGenDisassemblerTables.inc"
159 
161  const MCSubtargetInfo &STI,
162  MCContext &Ctx) {
163  return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
164 }
165 
169 }
170 
171 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
172  ArrayRef<uint8_t> Bytes,
173  uint64_t Address,
174  raw_ostream &cs) const {
176  bool Complete = false;
177  Size = 0;
178 
179  *CurrentBundle = &MI;
180  MI.setOpcode(Hexagon::BUNDLE);
181  MI.addOperand(MCOperand::createImm(0));
182  while (Result == Success && !Complete) {
183  if (Bytes.size() < HEXAGON_INSTR_SIZE)
184  return MCDisassembler::Fail;
185  MCInst *Inst = getContext().createMCInst();
186  Result = getSingleInstruction(*Inst, MI, Bytes, Address, cs, Complete);
187  MI.addOperand(MCOperand::createInst(Inst));
189  Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
190  }
191  if (Result == MCDisassembler::Fail)
192  return Result;
194  return MCDisassembler::Fail;
195 
196  const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
197  const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
198  HexagonMCChecker Checker(getContext(), *MCII, STI_, MI,
199  *getContext().getRegisterInfo(), false);
200  if (!Checker.check())
201  return MCDisassembler::Fail;
202  remapInstruction(MI);
204 }
205 
206 void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
207  for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
208  auto &MI = const_cast<MCInst &>(*I.getInst());
209  switch (MI.getOpcode()) {
210  case Hexagon::S2_allocframe:
211  if (MI.getOperand(0).getReg() == Hexagon::R29) {
212  MI.setOpcode(Hexagon::S6_allocframe_to_raw);
213  MI.erase(MI.begin () + 1);
214  MI.erase(MI.begin ());
215  }
216  break;
217  case Hexagon::L2_deallocframe:
218  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
219  MI.getOperand(1).getReg() == Hexagon::R30) {
220  MI.setOpcode(L6_deallocframe_map_to_raw);
221  MI.erase(MI.begin () + 1);
222  MI.erase(MI.begin ());
223  }
224  break;
225  case Hexagon::L4_return:
226  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
227  MI.getOperand(1).getReg() == Hexagon::R30) {
228  MI.setOpcode(L6_return_map_to_raw);
229  MI.erase(MI.begin () + 1);
230  MI.erase(MI.begin ());
231  }
232  break;
233  case Hexagon::L4_return_t:
234  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
235  MI.getOperand(2).getReg() == Hexagon::R30) {
236  MI.setOpcode(L4_return_map_to_raw_t);
237  MI.erase(MI.begin () + 2);
238  MI.erase(MI.begin ());
239  }
240  break;
241  case Hexagon::L4_return_f:
242  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
243  MI.getOperand(2).getReg() == Hexagon::R30) {
244  MI.setOpcode(L4_return_map_to_raw_f);
245  MI.erase(MI.begin () + 2);
246  MI.erase(MI.begin ());
247  }
248  break;
249  case Hexagon::L4_return_tnew_pt:
250  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
251  MI.getOperand(2).getReg() == Hexagon::R30) {
252  MI.setOpcode(L4_return_map_to_raw_tnew_pt);
253  MI.erase(MI.begin () + 2);
254  MI.erase(MI.begin ());
255  }
256  break;
257  case Hexagon::L4_return_fnew_pt:
258  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
259  MI.getOperand(2).getReg() == Hexagon::R30) {
260  MI.setOpcode(L4_return_map_to_raw_fnew_pt);
261  MI.erase(MI.begin () + 2);
262  MI.erase(MI.begin ());
263  }
264  break;
265  case Hexagon::L4_return_tnew_pnt:
266  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
267  MI.getOperand(2).getReg() == Hexagon::R30) {
268  MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
269  MI.erase(MI.begin () + 2);
270  MI.erase(MI.begin ());
271  }
272  break;
273  case Hexagon::L4_return_fnew_pnt:
274  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
275  MI.getOperand(2).getReg() == Hexagon::R30) {
276  MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
277  MI.erase(MI.begin () + 2);
278  MI.erase(MI.begin ());
279  }
280  break;
281  }
282  }
283 }
284 
286  switch (MI.getOpcode()) {
287  case Hexagon::SA1_setin1:
288  MI.insert(MI.begin() + 1,
290  break;
291  case Hexagon::SA1_dec:
292  MI.insert(MI.begin() + 2,
294  break;
295  default:
296  break;
297  }
298 }
299 
300 DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
301  ArrayRef<uint8_t> Bytes,
302  uint64_t Address,
303  raw_ostream &cs,
304  bool &Complete) const {
305  assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
306 
308 
309  auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
312  if (BundleSize == 0)
314  else if (BundleSize == 1)
316  else
317  return DecodeStatus::Fail;
318  }
319 
320  CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
322 
326  unsigned duplexIClass;
327  uint8_t const *DecodeLow, *DecodeHigh;
328  duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
329  switch (duplexIClass) {
330  default:
331  return MCDisassembler::Fail;
332  case 0:
333  DecodeLow = DecoderTableSUBINSN_L132;
334  DecodeHigh = DecoderTableSUBINSN_L132;
335  break;
336  case 1:
337  DecodeLow = DecoderTableSUBINSN_L232;
338  DecodeHigh = DecoderTableSUBINSN_L132;
339  break;
340  case 2:
341  DecodeLow = DecoderTableSUBINSN_L232;
342  DecodeHigh = DecoderTableSUBINSN_L232;
343  break;
344  case 3:
345  DecodeLow = DecoderTableSUBINSN_A32;
346  DecodeHigh = DecoderTableSUBINSN_A32;
347  break;
348  case 4:
349  DecodeLow = DecoderTableSUBINSN_L132;
350  DecodeHigh = DecoderTableSUBINSN_A32;
351  break;
352  case 5:
353  DecodeLow = DecoderTableSUBINSN_L232;
354  DecodeHigh = DecoderTableSUBINSN_A32;
355  break;
356  case 6:
357  DecodeLow = DecoderTableSUBINSN_S132;
358  DecodeHigh = DecoderTableSUBINSN_A32;
359  break;
360  case 7:
361  DecodeLow = DecoderTableSUBINSN_S232;
362  DecodeHigh = DecoderTableSUBINSN_A32;
363  break;
364  case 8:
365  DecodeLow = DecoderTableSUBINSN_S132;
366  DecodeHigh = DecoderTableSUBINSN_L132;
367  break;
368  case 9:
369  DecodeLow = DecoderTableSUBINSN_S132;
370  DecodeHigh = DecoderTableSUBINSN_L232;
371  break;
372  case 10:
373  DecodeLow = DecoderTableSUBINSN_S132;
374  DecodeHigh = DecoderTableSUBINSN_S132;
375  break;
376  case 11:
377  DecodeLow = DecoderTableSUBINSN_S232;
378  DecodeHigh = DecoderTableSUBINSN_S132;
379  break;
380  case 12:
381  DecodeLow = DecoderTableSUBINSN_S232;
382  DecodeHigh = DecoderTableSUBINSN_L132;
383  break;
384  case 13:
385  DecodeLow = DecoderTableSUBINSN_S232;
386  DecodeHigh = DecoderTableSUBINSN_L232;
387  break;
388  case 14:
389  DecodeLow = DecoderTableSUBINSN_S232;
390  DecodeHigh = DecoderTableSUBINSN_S232;
391  break;
392  }
393  MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
394  MCInst *MILow = getContext().createMCInst();
395  MCInst *MIHigh = getContext().createMCInst();
396  auto TmpExtender = CurrentExtender;
397  CurrentExtender =
398  nullptr; // constant extenders in duplex must always be in slot 1
399  Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
400  this, STI);
401  CurrentExtender = TmpExtender;
402  if (Result != DecodeStatus::Success)
403  return DecodeStatus::Fail;
404  adjustDuplex(*MILow, getContext());
405  Result = decodeInstruction(
406  DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
407  if (Result != DecodeStatus::Success)
408  return DecodeStatus::Fail;
409  adjustDuplex(*MIHigh, getContext());
410  MCOperand OPLow = MCOperand::createInst(MILow);
411  MCOperand OPHigh = MCOperand::createInst(MIHigh);
412  MI.addOperand(OPLow);
413  MI.addOperand(OPHigh);
414  Complete = true;
415  } else {
418  Complete = true;
419 
420  if (CurrentExtender != nullptr)
421  Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
422  Address, this, STI);
423 
424  if (Result != MCDisassembler::Success)
425  Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
426  STI);
427 
428  if (Result != MCDisassembler::Success &&
429  STI.getFeatureBits()[Hexagon::ExtensionHVX])
430  Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
431  Address, this, STI);
432 
433  }
434 
435  switch (MI.getOpcode()) {
436  case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
437  case Hexagon::J4_cmpeqn1_f_jumpnv_t:
438  case Hexagon::J4_cmpeqn1_fp0_jump_nt:
439  case Hexagon::J4_cmpeqn1_fp0_jump_t:
440  case Hexagon::J4_cmpeqn1_fp1_jump_nt:
441  case Hexagon::J4_cmpeqn1_fp1_jump_t:
442  case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
443  case Hexagon::J4_cmpeqn1_t_jumpnv_t:
444  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
445  case Hexagon::J4_cmpeqn1_tp0_jump_t:
446  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
447  case Hexagon::J4_cmpeqn1_tp1_jump_t:
448  case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
449  case Hexagon::J4_cmpgtn1_f_jumpnv_t:
450  case Hexagon::J4_cmpgtn1_fp0_jump_nt:
451  case Hexagon::J4_cmpgtn1_fp0_jump_t:
452  case Hexagon::J4_cmpgtn1_fp1_jump_nt:
453  case Hexagon::J4_cmpgtn1_fp1_jump_t:
454  case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
455  case Hexagon::J4_cmpgtn1_t_jumpnv_t:
456  case Hexagon::J4_cmpgtn1_tp0_jump_nt:
457  case Hexagon::J4_cmpgtn1_tp0_jump_t:
458  case Hexagon::J4_cmpgtn1_tp1_jump_nt:
459  case Hexagon::J4_cmpgtn1_tp1_jump_t:
460  MI.insert(MI.begin() + 1,
461  MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
462  break;
463  default:
464  break;
465  }
466 
467  if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
468  unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
469  MCOperand &MCO = MI.getOperand(OpIndex);
470  assert(MCO.isReg() && "New value consumers must be registers");
471  unsigned Register =
472  getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
473  if ((Register & 0x6) == 0)
474  // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
475  return MCDisassembler::Fail;
476  unsigned Lookback = (Register & 0x6) >> 1;
477  unsigned Offset = 1;
478  bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
479  bool PrevVector = false;
481  auto i = Instructions.end() - 1;
482  for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
483  if (i == n)
484  // Couldn't find producer
485  return MCDisassembler::Fail;
486  bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
487  if (Vector && !CurrentVector)
488  // Skip scalars when calculating distances for vectors
489  ++Lookback;
490  if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
491  ++Lookback;
492  PrevVector = CurrentVector;
493  if (Offset == Lookback)
494  break;
495  }
496  auto const &Inst = *i->getInst();
497  bool SubregBit = (Register & 0x1) != 0;
498  if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
499  // If subreg bit is set we're selecting the second produced newvalue
500  unsigned Producer = SubregBit ?
503  assert(Producer != Hexagon::NoRegister);
504  MCO.setReg(Producer);
505  } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
506  unsigned Producer =
508 
509  if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
510  const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
511  const unsigned ProdPairIndex =
512  Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
513  Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
514  } else if (SubregBit)
515  // Hexagon PRM 10.11 New-value operands
516  // Nt[0] is reserved and should always be encoded as zero.
517  return MCDisassembler::Fail;
518  assert(Producer != Hexagon::NoRegister);
519  MCO.setReg(Producer);
520  } else
521  return MCDisassembler::Fail;
522  }
523 
524  if (CurrentExtender != nullptr) {
525  MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
526  ? *MI.getOperand(1).getInst()
527  : MI;
528  if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
529  !HexagonMCInstrInfo::isExtended(*MCII, Inst))
530  return MCDisassembler::Fail;
531  }
532  return Result;
533 }
534 
535 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
536  ArrayRef<MCPhysReg> Table) {
537  if (RegNo < Table.size()) {
538  Inst.addOperand(MCOperand::createReg(Table[RegNo]));
540  }
541 
542  return MCDisassembler::Fail;
543 }
544 
546  uint64_t Address,
547  const void *Decoder) {
548  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
549 }
550 
551 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
552  uint64_t Address,
553  const void *Decoder) {
554  static const MCPhysReg IntRegDecoderTable[] = {
555  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
556  Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
557  Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
558  Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
559  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
560  Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
561  Hexagon::R30, Hexagon::R31};
562 
563  return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
564 }
565 
567  unsigned RegNo,
568  uint64_t Address,
569  const void *Decoder) {
570  static const MCPhysReg GeneralSubRegDecoderTable[] = {
571  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
572  Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
573  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
574  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
575  };
576 
577  return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
578 }
579 
580 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
581  uint64_t /*Address*/,
582  const void *Decoder) {
583  static const MCPhysReg HvxVRDecoderTable[] = {
584  Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
585  Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
586  Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
587  Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
588  Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
589  Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
590  Hexagon::V30, Hexagon::V31};
591 
592  return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
593 }
594 
595 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
596  uint64_t /*Address*/,
597  const void *Decoder) {
598  static const MCPhysReg DoubleRegDecoderTable[] = {
599  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
600  Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
601  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
602  Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
603 
604  return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
605 }
606 
608  MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
609  static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
610  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
611  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
612 
613  return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
614 }
615 
616 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
617  uint64_t /*Address*/,
618  const void *Decoder) {
619  static const MCPhysReg HvxWRDecoderTable[] = {
620  Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
621  Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
622  Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
623  Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
624  Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
625  Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
626  Hexagon::W15, Hexagon::WR15,
627  };
628 
629  return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
630 }
631 
632 LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
634  unsigned RegNo,
635  uint64_t /*Address*/,
636  const void *Decoder) {
637  static const MCPhysReg HvxVQRDecoderTable[] = {
638  Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
639  Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
640 
641  return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
642 }
643 
644 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
645  uint64_t /*Address*/,
646  const void *Decoder) {
647  static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
648  Hexagon::P2, Hexagon::P3};
649 
650  return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
651 }
652 
653 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
654  uint64_t /*Address*/,
655  const void *Decoder) {
656  static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
657  Hexagon::Q2, Hexagon::Q3};
658 
659  return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
660 }
661 
662 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
663  uint64_t /*Address*/,
664  const void *Decoder) {
665  using namespace Hexagon;
666 
667  static const MCPhysReg CtrlRegDecoderTable[] = {
668  /* 0 */ SA0, LC0, SA1, LC1,
669  /* 4 */ P3_0, C5, M0, M1,
670  /* 8 */ USR, PC, UGP, GP,
671  /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
672  /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
673  /* 20 */ 0, 0, 0, 0,
674  /* 24 */ 0, 0, 0, 0,
675  /* 28 */ 0, 0, UTIMERLO, UTIMERHI
676  };
677 
678  if (RegNo >= array_lengthof(CtrlRegDecoderTable))
679  return MCDisassembler::Fail;
680 
681  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
682  if (CtrlRegDecoderTable[RegNo] == NoRegister)
683  return MCDisassembler::Fail;
684 
685  unsigned Register = CtrlRegDecoderTable[RegNo];
688 }
689 
690 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
691  uint64_t /*Address*/,
692  const void *Decoder) {
693  using namespace Hexagon;
694 
695  static const MCPhysReg CtrlReg64DecoderTable[] = {
696  /* 0 */ C1_0, 0, C3_2, 0,
697  /* 4 */ C5_4, 0, C7_6, 0,
698  /* 8 */ C9_8, 0, C11_10, 0,
699  /* 12 */ CS, 0, UPCYCLE, 0,
700  /* 16 */ C17_16, 0, PKTCOUNT, 0,
701  /* 20 */ 0, 0, 0, 0,
702  /* 24 */ 0, 0, 0, 0,
703  /* 28 */ 0, 0, UTIMER, 0
704  };
705 
706  if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
707  return MCDisassembler::Fail;
708 
709  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
710  if (CtrlReg64DecoderTable[RegNo] == NoRegister)
711  return MCDisassembler::Fail;
712 
713  unsigned Register = CtrlReg64DecoderTable[RegNo];
716 }
717 
718 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
719  uint64_t /*Address*/,
720  const void *Decoder) {
721  unsigned Register = 0;
722  switch (RegNo) {
723  case 0:
725  break;
726  case 1:
728  break;
729  default:
730  return MCDisassembler::Fail;
731  }
734 }
735 
737  uint64_t /*Address*/,
738  const void *Decoder) {
739  HexagonDisassembler const &Disassembler = disassembler(Decoder);
740  int64_t FullValue = fullValue(Disassembler, MI, tmp);
741  assert(FullValue >= 0 && "Negative in unsigned decoder");
742  HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
744 }
745 
747  uint64_t /*Address*/, const void *Decoder) {
748  HexagonDisassembler const &Disassembler = disassembler(Decoder);
749  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
750  tmp = SignExtend64(tmp, Bits);
751  signedDecoder<32>(MI, tmp, Decoder);
753 }
754 
755 // custom decoder for various jump/call immediates
756 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
757  const void *Decoder) {
758  HexagonDisassembler const &Disassembler = disassembler(Decoder);
759  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
760  // r13_2 is not extendable, so if there are no extent bits, it's r13_2
761  if (Bits == 0)
762  Bits = 15;
763  uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
764  uint32_t Extended = FullValue + Address;
765  if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
766  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
768 }
769 
770 static const uint16_t SysRegDecoderTable[] = {
771  Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
772  Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
773  Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
774  Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
775  Hexagon::S12, Hexagon::S13, Hexagon::S14,
776  Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
777  Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
778  Hexagon::VID, Hexagon::S22, Hexagon::S23,
779  Hexagon::S24, Hexagon::S25, Hexagon::S26,
780  Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
781  Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
782  Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
783  Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
784  Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
785  Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
786  Hexagon::S45, Hexagon::S46, Hexagon::S47,
787  Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
788  Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
789  Hexagon::S54, Hexagon::S55, Hexagon::S56,
790  Hexagon::S57, Hexagon::S58, Hexagon::S59,
791  Hexagon::S60, Hexagon::S61, Hexagon::S62,
792  Hexagon::S63, Hexagon::S64, Hexagon::S65,
793  Hexagon::S66, Hexagon::S67, Hexagon::S68,
794  Hexagon::S69, Hexagon::S70, Hexagon::S71,
795  Hexagon::S72, Hexagon::S73, Hexagon::S74,
796  Hexagon::S75, Hexagon::S76, Hexagon::S77,
797  Hexagon::S78, Hexagon::S79, Hexagon::S80,
798 };
799 
800 static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
801  uint64_t /*Address*/,
802  const void *Decoder) {
803  if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0]))
804  return MCDisassembler::Fail;
805 
806  if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
807  return MCDisassembler::Fail;
808 
809  unsigned Register = SysRegDecoderTable[RegNo];
812 }
813 
814 static const uint16_t SysReg64DecoderTable[] = {
815  Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
816  Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
817  Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
818  Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
819  Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
820  Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
821  Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
822  Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
823  Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
824  Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
825 };
826 
827 static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
828  uint64_t /*Address*/,
829  const void *Decoder) {
830  RegNo = RegNo >> 1;
831  if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0]))
832  return MCDisassembler::Fail;
833 
834  if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
835  return MCDisassembler::Fail;
836 
837  unsigned Register = SysReg64DecoderTable[RegNo];
840 }
841 
842 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
843  uint64_t /*Address*/,
844  const void *Decoder) {
845  using namespace Hexagon;
846 
847  static const MCPhysReg GuestRegDecoderTable[] = {
848  /* 0 */ GELR, GSR, GOSP, G3,
849  /* 4 */ G4, G5, G6, G7,
850  /* 8 */ G8, G9, G10, G11,
851  /* 12 */ G12, G13, G14, G15,
852  /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
853  /* 20 */ G20, G21, G22, G23,
854  /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
855  /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
856  };
857 
858  if (RegNo >= array_lengthof(GuestRegDecoderTable))
859  return MCDisassembler::Fail;
860  if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
861  return MCDisassembler::Fail;
862 
863  unsigned Register = GuestRegDecoderTable[RegNo];
866 }
867 
869  uint64_t /*Address*/,
870  const void *Decoder) {
871  using namespace Hexagon;
872 
873  static const MCPhysReg GuestReg64DecoderTable[] = {
874  /* 0 */ G1_0, 0, G3_2, 0,
875  /* 4 */ G5_4, 0, G7_6, 0,
876  /* 8 */ G9_8, 0, G11_10, 0,
877  /* 12 */ G13_12, 0, G15_14, 0,
878  /* 16 */ G17_16, 0, G19_18, 0,
879  /* 20 */ G21_20, 0, G23_22, 0,
880  /* 24 */ G25_24, 0, G27_26, 0,
881  /* 28 */ G29_28, 0, G31_30, 0
882  };
883 
884  if (RegNo >= array_lengthof(GuestReg64DecoderTable))
885  return MCDisassembler::Fail;
886  if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
887  return MCDisassembler::Fail;
888 
889  unsigned Register = GuestReg64DecoderTable[RegNo];
892 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
HexagonTargetInfo.h
llvm::HexagonII::INST_PARSE_PACKET_END
@ INST_PARSE_PACKET_END
Definition: HexagonBaseInfo.h:243
DecodeHvxQRRegisterClass
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:653
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
MCFixedLenDisassembler.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MathExtras.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
SysRegDecoderTable
static const uint16_t SysRegDecoderTable[]
Definition: HexagonDisassembler.cpp:770
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
DecodeModRegsRegisterClass
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:718
MCDisassembler.h
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
DecodeGeneralDoubleLow8RegsRegisterClass
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:607
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:33
Fail
#define Fail
Definition: AArch64Disassembler.cpp:261
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:372
R4
#define R4(n)
Instructions
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place Instructions
Definition: MSA.txt:11
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:327
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
adjustDuplex
static void adjustDuplex(MCInst &MI, MCContext &Context)
Definition: HexagonDisassembler.cpp:285
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:635
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::HexagonMCInstrInfo::extenderForIndex
const MCInst * extenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:215
llvm::HexagonMCInstrInfo::setInnerLoop
void setInnerLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:989
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
tmp
alloca< 16 x float >, align 16 %tmp2=alloca< 16 x float >, align 16 store< 16 x float > %A,< 16 x float > *%tmp %s=bitcast< 16 x float > *%tmp to i8 *%s2=bitcast< 16 x float > *%tmp2 to i8 *call void @llvm.memcpy.i64(i8 *%s, i8 *%s2, i64 64, i32 16) %R=load< 16 x float > *%tmp2 ret< 16 x float > %R } declare void @llvm.memcpy.i64(i8 *nocapture, i8 *nocapture, i64, i32) nounwind which compiles to:_foo:subl $140, %esp movaps %xmm3, 112(%esp) movaps %xmm2, 96(%esp) movaps %xmm1, 80(%esp) movaps %xmm0, 64(%esp) movl 60(%esp), %eax movl %eax, 124(%esp) movl 56(%esp), %eax movl %eax, 120(%esp) movl 52(%esp), %eax< many many more 32-bit copies > movaps(%esp), %xmm0 movaps 16(%esp), %xmm1 movaps 32(%esp), %xmm2 movaps 48(%esp), %xmm3 addl $140, %esp ret On Nehalem, it may even be cheaper to just use movups when unaligned than to fall back to lower-granularity chunks. Implement processor-specific optimizations for parity with GCC on these processors. GCC does two optimizations:1. ix86_pad_returns inserts a noop before ret instructions if immediately preceded by a conditional branch or is the target of a jump. 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of code contains more than 3 branches. The first one is done for all AMDs, Core2, and "Generic" The second one is done for:Atom, Pentium Pro, all AMDs, Pentium 4, Nocona, Core 2, and "Generic" Testcase:int x(int a) { return(a &0xf0)> >4 tmp
Definition: README.txt:1347
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:188
llvm::Hexagon_MC::getArchSubtarget
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
Definition: HexagonMCTargetDesc.cpp:411
HexagonBaseInfo.h
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:162
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
R2
#define R2(n)
DecodeCtrRegsRegisterClass
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:662
createHexagonDisassembler
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: HexagonDisassembler.cpp:160
HexagonMCChecker.h
DecodeIntRegsLow8RegisterClass
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:545
HexagonDepDecoders.inc
P2
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill if only one byte chunk is bring in zeros the one element instead of elements This can be used to simplify a variety of shuffle where the elements are fixed zeros This code generates ugly probably due to costs being off or< 4 x float > * P2
Definition: README-SSE.txt:278
HexagonMCInstrInfo.h
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:513
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:655
llvm::HexagonII::INST_PARSE_DUPLEX
@ INST_PARSE_DUPLEX
Definition: HexagonBaseInfo.h:246
MCContext.h
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:854
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
DecodeGuestRegsRegisterClass
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:842
MCInst.h
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
MCSubtargetInfo.h
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:371
llvm::Instruction
Definition: Instruction.h:45
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:333
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
DecodeSysRegsRegisterClass
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:800
SysReg64DecoderTable
static const uint16_t SysReg64DecoderTable[]
Definition: HexagonDisassembler.cpp:814
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition: HexagonMCInstrInfo.cpp:506
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1394
HEXAGON_MAX_PACKET_SIZE
#define HEXAGON_MAX_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:37
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:82
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:195
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
brtargetDecoder
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:756
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::NVPTX::PTXLdStInstCode::V4
@ V4
Definition: NVPTX.h:124
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
MCRegisterInfo.h
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:609
ArrayRef.h
DecodeHvxWRRegisterClass
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:616
llvm::HighlightColor::Address
@ Address
s32_0ImmDecoder
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
Definition: HexagonDisassembler.cpp:746
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:684
LLVMInitializeHexagonDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()
Definition: HexagonDisassembler.cpp:166
llvm::HexagonMCInstrInfo::IsVecRegPair
bool IsVecRegPair(unsigned VecReg)
Definition: HexagonMCInstrInfo.cpp:679
DecodeCtrRegs64RegisterClass
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:690
R6
#define R6(n)
llvm::HexagonII::INST_PARSE_MASK
@ INST_PARSE_MASK
Definition: HexagonBaseInfo.h:242
DecodeGuestRegs64RegisterClass
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:868
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:13
llvm::ArrayRef< uint8_t >
unsignedImmDecoder
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:736
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:551
uint32_t
llvm::HexagonMCInstrInfo::getNewValueOperand
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:378
DecodePredRegsRegisterClass
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:644
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:309
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
llvm::HexagonMCInstrInfo::setOuterLoop
void setOuterLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:1002
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:777
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::HexagonMCInstrInfo::getNewValueOperand2
const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:404
llvm::NVPTX::PTXLdStInstCode::V2
@ V2
Definition: NVPTX.h:123
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
DecodeSysRegs64RegisterClass
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:827
DecodeHvxVRRegisterClass
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:580
DecodeDoubleRegsRegisterClass
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:595
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:34
uint16_t
Success
#define Success
Definition: AArch64Disassembler.cpp:260
LC0
into eax xorps xmm0 xmm0 eax xmm0 eax xmm0 ret esp eax movdqa LC0
Definition: README-SSE.txt:632
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
DecodeGeneralSubRegsRegisterClass
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:566
IntRegDecoderTable
static const unsigned IntRegDecoderTable[]
Definition: SparcDisassembler.cpp:60
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
DecodeRegisterClass
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
Definition: HexagonDisassembler.cpp:535
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::HexagonII::INST_PARSE_LOOP_END
@ INST_PARSE_LOOP_END
Definition: HexagonBaseInfo.h:244
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:619
llvm::MCOperand::setReg
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:75
DecodeHvxVQRRegisterClass
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: HexagonDisassembler.cpp:633
llvm::M1
unsigned M1(unsigned Val)
Definition: VE.h:372
raw_ostream.h
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
Endian.h
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:613
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69