LLVM 17.0.0git
SparcDisassembler.cpp
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1//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Sparc Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCInst.h"
21
22using namespace llvm;
23
24#define DEBUG_TYPE "sparc-disassembler"
25
27
28namespace {
29
30/// A disassembler class for Sparc.
31class SparcDisassembler : public MCDisassembler {
32public:
33 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
34 : MCDisassembler(STI, Ctx) {}
35 virtual ~SparcDisassembler() = default;
36
38 ArrayRef<uint8_t> Bytes, uint64_t Address,
39 raw_ostream &CStream) const override;
40};
41}
42
44 const MCSubtargetInfo &STI,
45 MCContext &Ctx) {
46 return new SparcDisassembler(STI, Ctx);
47}
48
49
51 // Register the disassembler.
58}
59
60static const unsigned IntRegDecoderTable[] = {
61 SP::G0, SP::G1, SP::G2, SP::G3,
62 SP::G4, SP::G5, SP::G6, SP::G7,
63 SP::O0, SP::O1, SP::O2, SP::O3,
64 SP::O4, SP::O5, SP::O6, SP::O7,
65 SP::L0, SP::L1, SP::L2, SP::L3,
66 SP::L4, SP::L5, SP::L6, SP::L7,
67 SP::I0, SP::I1, SP::I2, SP::I3,
68 SP::I4, SP::I5, SP::I6, SP::I7 };
69
70static const unsigned FPRegDecoderTable[] = {
71 SP::F0, SP::F1, SP::F2, SP::F3,
72 SP::F4, SP::F5, SP::F6, SP::F7,
73 SP::F8, SP::F9, SP::F10, SP::F11,
74 SP::F12, SP::F13, SP::F14, SP::F15,
75 SP::F16, SP::F17, SP::F18, SP::F19,
76 SP::F20, SP::F21, SP::F22, SP::F23,
77 SP::F24, SP::F25, SP::F26, SP::F27,
78 SP::F28, SP::F29, SP::F30, SP::F31 };
79
80static const unsigned DFPRegDecoderTable[] = {
81 SP::D0, SP::D16, SP::D1, SP::D17,
82 SP::D2, SP::D18, SP::D3, SP::D19,
83 SP::D4, SP::D20, SP::D5, SP::D21,
84 SP::D6, SP::D22, SP::D7, SP::D23,
85 SP::D8, SP::D24, SP::D9, SP::D25,
86 SP::D10, SP::D26, SP::D11, SP::D27,
87 SP::D12, SP::D28, SP::D13, SP::D29,
88 SP::D14, SP::D30, SP::D15, SP::D31 };
89
90static const unsigned QFPRegDecoderTable[] = {
91 SP::Q0, SP::Q8, ~0U, ~0U,
92 SP::Q1, SP::Q9, ~0U, ~0U,
93 SP::Q2, SP::Q10, ~0U, ~0U,
94 SP::Q3, SP::Q11, ~0U, ~0U,
95 SP::Q4, SP::Q12, ~0U, ~0U,
96 SP::Q5, SP::Q13, ~0U, ~0U,
97 SP::Q6, SP::Q14, ~0U, ~0U,
98 SP::Q7, SP::Q15, ~0U, ~0U } ;
99
100static const unsigned FCCRegDecoderTable[] = {
101 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
102
103static const unsigned ASRRegDecoderTable[] = {
104 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
105 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
106 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
107 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
108 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
109 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
110 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
111 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
112
113static const unsigned PRRegDecoderTable[] = {
114 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
115 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
116 SP::OTHERWIN, SP::WSTATE, SP::PC
117};
118
120 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
121 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
122 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
123 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
124};
125
126static const unsigned CPRegDecoderTable[] = {
127 SP::C0, SP::C1, SP::C2, SP::C3,
128 SP::C4, SP::C5, SP::C6, SP::C7,
129 SP::C8, SP::C9, SP::C10, SP::C11,
130 SP::C12, SP::C13, SP::C14, SP::C15,
131 SP::C16, SP::C17, SP::C18, SP::C19,
132 SP::C20, SP::C21, SP::C22, SP::C23,
133 SP::C24, SP::C25, SP::C26, SP::C27,
134 SP::C28, SP::C29, SP::C30, SP::C31
135};
136
137
138static const uint16_t CPPairDecoderTable[] = {
139 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
140 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
141 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
142 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
143};
144
145static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
146 uint64_t Address,
147 const MCDisassembler *Decoder) {
148 if (RegNo > 31)
150 unsigned Reg = IntRegDecoderTable[RegNo];
153}
154
155static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address,
157 const MCDisassembler *Decoder) {
158 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
159}
160
161// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
162// depending on SparcRegisterInfo::getPointerRegClass.
163static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo,
164 uint64_t Address,
165 const MCDisassembler *Decoder) {
166 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
167}
168
169static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address,
171 const MCDisassembler *Decoder) {
172 if (RegNo > 31)
174 unsigned Reg = FPRegDecoderTable[RegNo];
177}
178
179static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
180 uint64_t Address,
181 const MCDisassembler *Decoder) {
182 if (RegNo > 31)
184 unsigned Reg = DFPRegDecoderTable[RegNo];
187}
188
189static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
190 uint64_t Address,
191 const MCDisassembler *Decoder) {
192 if (RegNo > 31)
194
195 unsigned Reg = QFPRegDecoderTable[RegNo];
196 if (Reg == ~0U)
200}
201
202static DecodeStatus
203DecodeCoprocRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
204 const MCDisassembler *Decoder) {
205 if (RegNo > 31)
207 unsigned Reg = CPRegDecoderTable[RegNo];
210}
211
212static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
213 uint64_t Address,
214 const MCDisassembler *Decoder) {
215 if (RegNo > 3)
219}
220
221static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
222 uint64_t Address,
223 const MCDisassembler *Decoder) {
224 if (RegNo > 31)
228}
229
230static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
231 uint64_t Address,
232 const MCDisassembler *Decoder) {
233 if (RegNo >= std::size(PRRegDecoderTable))
237}
238
239static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
240 uint64_t Address,
241 const MCDisassembler *Decoder) {
243
244 if (RegNo > 31)
246
247 if ((RegNo & 1))
249
250 unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
251 Inst.addOperand(MCOperand::createReg(RegisterPair));
252 return S;
253}
254
255static DecodeStatus
256DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
257 const MCDisassembler *Decoder) {
258 if (RegNo > 31)
260
261 unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
262 Inst.addOperand(MCOperand::createReg(RegisterPair));
264}
265
266static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
267 const MCDisassembler *Decoder);
268static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
269 const MCDisassembler *Decoder);
270
271#include "SparcGenDisassemblerTables.inc"
272
273/// Read four bytes from the ArrayRef and return 32 bit word.
276 bool IsLittleEndian) {
277 // We want to read exactly 4 Bytes of data.
278 if (Bytes.size() < 4) {
279 Size = 0;
281 }
282
283 Insn = IsLittleEndian
284 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
285 (Bytes[3] << 24)
286 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
287 (Bytes[0] << 24);
288
290}
291
292DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
293 ArrayRef<uint8_t> Bytes,
294 uint64_t Address,
295 raw_ostream &CStream) const {
297 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
299 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
300 if (Result == MCDisassembler::Fail)
302
303 // Calling the auto-generated decoder function.
304
305 if (STI.hasFeature(Sparc::FeatureV9))
306 {
307 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
308 }
309 else
310 {
311 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
312 }
313 if (Result != MCDisassembler::Fail)
314 return Result;
315
316 Result =
317 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
318
319 if (Result != MCDisassembler::Fail) {
320 Size = 4;
321 return Result;
322 }
323
325}
326
327static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
328 uint64_t Address, uint64_t Offset,
329 uint64_t Width, MCInst &MI,
330 const MCDisassembler *Decoder) {
331 return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
332 Width, /*InstSize=*/4);
333}
334
335static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
336 const MCDisassembler *Decoder) {
337 unsigned tgt = fieldFromInstruction(insn, 0, 30);
338 tgt <<= 2;
339 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
340 0, 30, MI, Decoder))
341 MI.addOperand(MCOperand::createImm(tgt));
343}
344
345static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
346 const MCDisassembler *Decoder) {
347 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
348 MI.addOperand(MCOperand::createImm(tgt));
350}
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
uint64_t Size
IRTranslator LLVM IR MI
#define DecodePointerLikeRegClass0
static bool isBranch(unsigned Opcode)
static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned FPRegDecoderTable[]
static MCDisassembler * createSparcDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static const unsigned CPRegDecoderTable[]
static const uint16_t IntPairDecoderTable[]
static DecodeStatus DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned PRRegDecoderTable[]
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcDisassembler()
static const uint16_t CPPairDecoderTable[]
static const unsigned IntRegDecoderTable[]
static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned QFPRegDecoderTable[]
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian)
Read four bytes from the ArrayRef and return 32 bit word.
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCoprocRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Decoder)
static const unsigned FCCRegDecoderTable[]
static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned DFPRegDecoderTable[]
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const unsigned ASRRegDecoderTable[]
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
Target & getTheSparcTarget()
Target & getTheSparcV9Target()
Target & getTheSparcelTarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.