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SparcDisassembler.cpp
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1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Sparc Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12 
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCDecoderOps.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "sparc-disassembler"
25 
27 
28 namespace {
29 
30 /// A disassembler class for Sparc.
31 class SparcDisassembler : public MCDisassembler {
32 public:
33  SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
34  : MCDisassembler(STI, Ctx) {}
35  virtual ~SparcDisassembler() = default;
36 
37  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
38  ArrayRef<uint8_t> Bytes, uint64_t Address,
39  raw_ostream &CStream) const override;
40 };
41 }
42 
44  const MCSubtargetInfo &STI,
45  MCContext &Ctx) {
46  return new SparcDisassembler(STI, Ctx);
47 }
48 
49 
51  // Register the disassembler.
58 }
59 
60 static const unsigned IntRegDecoderTable[] = {
61  SP::G0, SP::G1, SP::G2, SP::G3,
62  SP::G4, SP::G5, SP::G6, SP::G7,
63  SP::O0, SP::O1, SP::O2, SP::O3,
64  SP::O4, SP::O5, SP::O6, SP::O7,
65  SP::L0, SP::L1, SP::L2, SP::L3,
67  SP::I0, SP::I1, SP::I2, SP::I3,
68  SP::I4, SP::I5, SP::I6, SP::I7 };
69 
70 static const unsigned FPRegDecoderTable[] = {
71  SP::F0, SP::F1, SP::F2, SP::F3,
72  SP::F4, SP::F5, SP::F6, SP::F7,
73  SP::F8, SP::F9, SP::F10, SP::F11,
74  SP::F12, SP::F13, SP::F14, SP::F15,
75  SP::F16, SP::F17, SP::F18, SP::F19,
76  SP::F20, SP::F21, SP::F22, SP::F23,
77  SP::F24, SP::F25, SP::F26, SP::F27,
78  SP::F28, SP::F29, SP::F30, SP::F31 };
79 
80 static const unsigned DFPRegDecoderTable[] = {
81  SP::D0, SP::D16, SP::D1, SP::D17,
82  SP::D2, SP::D18, SP::D3, SP::D19,
83  SP::D4, SP::D20, SP::D5, SP::D21,
84  SP::D6, SP::D22, SP::D7, SP::D23,
85  SP::D8, SP::D24, SP::D9, SP::D25,
86  SP::D10, SP::D26, SP::D11, SP::D27,
87  SP::D12, SP::D28, SP::D13, SP::D29,
88  SP::D14, SP::D30, SP::D15, SP::D31 };
89 
90 static const unsigned QFPRegDecoderTable[] = {
91  SP::Q0, SP::Q8, ~0U, ~0U,
92  SP::Q1, SP::Q9, ~0U, ~0U,
93  SP::Q2, SP::Q10, ~0U, ~0U,
94  SP::Q3, SP::Q11, ~0U, ~0U,
95  SP::Q4, SP::Q12, ~0U, ~0U,
96  SP::Q5, SP::Q13, ~0U, ~0U,
97  SP::Q6, SP::Q14, ~0U, ~0U,
98  SP::Q7, SP::Q15, ~0U, ~0U } ;
99 
100 static const unsigned FCCRegDecoderTable[] = {
101  SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
102 
103 static const unsigned ASRRegDecoderTable[] = {
104  SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
105  SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
106  SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
107  SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
108  SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
109  SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
110  SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
111  SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
112 
113 static const unsigned PRRegDecoderTable[] = {
114  SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
115  SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
116  SP::OTHERWIN, SP::WSTATE, SP::PC
117 };
118 
119 static const uint16_t IntPairDecoderTable[] = {
120  SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
121  SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
122  SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
123  SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
124 };
125 
126 static const unsigned CPRegDecoderTable[] = {
127  SP::C0, SP::C1, SP::C2, SP::C3,
128  SP::C4, SP::C5, SP::C6, SP::C7,
129  SP::C8, SP::C9, SP::C10, SP::C11,
130  SP::C12, SP::C13, SP::C14, SP::C15,
131  SP::C16, SP::C17, SP::C18, SP::C19,
132  SP::C20, SP::C21, SP::C22, SP::C23,
133  SP::C24, SP::C25, SP::C26, SP::C27,
134  SP::C28, SP::C29, SP::C30, SP::C31
135 };
136 
137 
138 static const uint16_t CPPairDecoderTable[] = {
139  SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
140  SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
141  SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
142  SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
143 };
144 
145 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
146  uint64_t Address,
147  const MCDisassembler *Decoder) {
148  if (RegNo > 31)
149  return MCDisassembler::Fail;
150  unsigned Reg = IntRegDecoderTable[RegNo];
153 }
154 
155 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo,
156  uint64_t Address,
157  const MCDisassembler *Decoder) {
158  if (RegNo > 31)
159  return MCDisassembler::Fail;
160  unsigned Reg = IntRegDecoderTable[RegNo];
163 }
164 
165 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
166  uint64_t Address,
167  const MCDisassembler *Decoder) {
168  if (RegNo > 31)
169  return MCDisassembler::Fail;
170  unsigned Reg = FPRegDecoderTable[RegNo];
173 }
174 
175 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
176  uint64_t Address,
177  const MCDisassembler *Decoder) {
178  if (RegNo > 31)
179  return MCDisassembler::Fail;
180  unsigned Reg = DFPRegDecoderTable[RegNo];
183 }
184 
185 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
186  uint64_t Address,
187  const MCDisassembler *Decoder) {
188  if (RegNo > 31)
189  return MCDisassembler::Fail;
190 
191  unsigned Reg = QFPRegDecoderTable[RegNo];
192  if (Reg == ~0U)
193  return MCDisassembler::Fail;
196 }
197 
198 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
199  uint64_t Address,
200  const MCDisassembler *Decoder) {
201  if (RegNo > 31)
202  return MCDisassembler::Fail;
203  unsigned Reg = CPRegDecoderTable[RegNo];
206 }
207 
208 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
209  uint64_t Address,
210  const MCDisassembler *Decoder) {
211  if (RegNo > 3)
212  return MCDisassembler::Fail;
215 }
216 
217 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
218  uint64_t Address,
219  const MCDisassembler *Decoder) {
220  if (RegNo > 31)
221  return MCDisassembler::Fail;
224 }
225 
226 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
227  uint64_t Address,
228  const MCDisassembler *Decoder) {
229  if (RegNo >= array_lengthof(PRRegDecoderTable))
230  return MCDisassembler::Fail;
233 }
234 
235 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
236  uint64_t Address,
237  const MCDisassembler *Decoder) {
239 
240  if (RegNo > 31)
241  return MCDisassembler::Fail;
242 
243  if ((RegNo & 1))
245 
246  unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
247  Inst.addOperand(MCOperand::createReg(RegisterPair));
248  return S;
249 }
250 
251 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
252  uint64_t Address,
253  const MCDisassembler *Decoder) {
254  if (RegNo > 31)
255  return MCDisassembler::Fail;
256 
257  unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
258  Inst.addOperand(MCOperand::createReg(RegisterPair));
260 }
261 
262 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
263  const MCDisassembler *Decoder);
264 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn,
265  uint64_t Address,
266  const MCDisassembler *Decoder);
267 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
268  const MCDisassembler *Decoder);
269 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
270  const MCDisassembler *Decoder);
271 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
272  const MCDisassembler *Decoder);
273 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
274  const MCDisassembler *Decoder);
275 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn,
276  uint64_t Address,
277  const MCDisassembler *Decoder);
278 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
279  uint64_t Address,
280  const MCDisassembler *Decoder);
281 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
282  uint64_t Address,
283  const MCDisassembler *Decoder);
284 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
285  const MCDisassembler *Decoder);
286 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
287  uint64_t Address,
288  const MCDisassembler *Decoder);
289 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
290  uint64_t Address,
291  const MCDisassembler *Decoder);
292 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address,
293  const MCDisassembler *Decoder);
294 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
295  uint64_t Address,
296  const MCDisassembler *Decoder);
297 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
298  const MCDisassembler *Decoder);
299 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
300  const MCDisassembler *Decoder);
301 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
302  const MCDisassembler *Decoder);
303 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
304  const MCDisassembler *Decoder);
305 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
306  const MCDisassembler *Decoder);
307 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
308  const MCDisassembler *Decoder);
309 
310 #include "SparcGenDisassemblerTables.inc"
311 
312 /// Read four bytes from the ArrayRef and return 32 bit word.
314  uint64_t &Size, uint32_t &Insn,
315  bool IsLittleEndian) {
316  // We want to read exactly 4 Bytes of data.
317  if (Bytes.size() < 4) {
318  Size = 0;
319  return MCDisassembler::Fail;
320  }
321 
322  Insn = IsLittleEndian
323  ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
324  (Bytes[3] << 24)
325  : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
326  (Bytes[0] << 24);
327 
329 }
330 
331 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
332  ArrayRef<uint8_t> Bytes,
333  uint64_t Address,
334  raw_ostream &CStream) const {
335  uint32_t Insn;
336  bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
338  readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
339  if (Result == MCDisassembler::Fail)
340  return MCDisassembler::Fail;
341 
342  // Calling the auto-generated decoder function.
343 
344  if (STI.getFeatureBits()[Sparc::FeatureV9])
345  {
346  Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
347  }
348  else
349  {
350  Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
351  }
352  if (Result != MCDisassembler::Fail)
353  return Result;
354 
355  Result =
356  decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
357 
358  if (Result != MCDisassembler::Fail) {
359  Size = 4;
360  return Result;
361  }
362 
363  return MCDisassembler::Fail;
364 }
365 
366 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
367  const MCDisassembler *Decoder);
368 
369 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
370  const MCDisassembler *Decoder, bool isLoad,
371  DecodeFunc DecodeRD) {
372  unsigned rd = fieldFromInstruction(insn, 25, 5);
373  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
374  bool isImm = fieldFromInstruction(insn, 13, 1);
375  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
376  unsigned asi = fieldFromInstruction(insn, 5, 8);
377  unsigned rs2 = 0;
378  unsigned simm13 = 0;
379  if (isImm)
380  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
381  else
382  rs2 = fieldFromInstruction(insn, 0, 5);
383 
385  if (isLoad) {
386  status = DecodeRD(MI, rd, Address, Decoder);
388  return status;
389  }
390 
391  // Decode rs1.
392  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
394  return status;
395 
396  // Decode imm|rs2.
397  if (isImm)
398  MI.addOperand(MCOperand::createImm(simm13));
399  else {
400  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
402  return status;
403  }
404 
405  if (hasAsi)
406  MI.addOperand(MCOperand::createImm(asi));
407 
408  if (!isLoad) {
409  status = DecodeRD(MI, rd, Address, Decoder);
411  return status;
412  }
414 }
415 
416 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
417  const MCDisassembler *Decoder) {
418  return DecodeMem(Inst, insn, Address, Decoder, true,
420 }
421 
422 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn,
423  uint64_t Address,
424  const MCDisassembler *Decoder) {
425  return DecodeMem(Inst, insn, Address, Decoder, true,
427 }
428 
429 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
430  const MCDisassembler *Decoder) {
431  return DecodeMem(Inst, insn, Address, Decoder, true,
433 }
434 
435 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
436  const MCDisassembler *Decoder) {
437  return DecodeMem(Inst, insn, Address, Decoder, true,
439 }
440 
441 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
442  const MCDisassembler *Decoder) {
443  return DecodeMem(Inst, insn, Address, Decoder, true,
445 }
446 
447 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
448  const MCDisassembler *Decoder) {
449  return DecodeMem(Inst, insn, Address, Decoder, true,
451 }
452 
453 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn,
454  uint64_t Address,
455  const MCDisassembler *Decoder) {
456  return DecodeMem(Inst, insn, Address, Decoder, true,
458 }
459 
460 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
461  uint64_t Address,
462  const MCDisassembler *Decoder) {
463  return DecodeMem(Inst, insn, Address, Decoder, false,
465 }
466 
467 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
468  uint64_t Address,
469  const MCDisassembler *Decoder) {
470  return DecodeMem(Inst, insn, Address, Decoder, false,
472 }
473 
474 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
475  const MCDisassembler *Decoder) {
476  return DecodeMem(Inst, insn, Address, Decoder, false,
478 }
479 
480 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
481  uint64_t Address,
482  const MCDisassembler *Decoder) {
483  return DecodeMem(Inst, insn, Address, Decoder, false,
485 }
486 
487 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
488  uint64_t Address,
489  const MCDisassembler *Decoder) {
490  return DecodeMem(Inst, insn, Address, Decoder, false,
492 }
493 
494 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address,
495  const MCDisassembler *Decoder) {
496  return DecodeMem(Inst, insn, Address, Decoder, false,
498 }
499 
500 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
501  uint64_t Address,
502  const MCDisassembler *Decoder) {
503  return DecodeMem(Inst, insn, Address, Decoder, false,
505 }
506 
507 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
508  uint64_t Address, uint64_t Offset,
510  const MCDisassembler *Decoder) {
511  return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
512  Width);
513 }
514 
515 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
516  const MCDisassembler *Decoder) {
517  unsigned tgt = fieldFromInstruction(insn, 0, 30);
518  tgt <<= 2;
519  if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
520  0, 30, MI, Decoder))
521  MI.addOperand(MCOperand::createImm(tgt));
523 }
524 
525 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
526  const MCDisassembler *Decoder) {
527  unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
528  MI.addOperand(MCOperand::createImm(tgt));
530 }
531 
532 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
533  const MCDisassembler *Decoder) {
534 
535  unsigned rd = fieldFromInstruction(insn, 25, 5);
536  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
537  unsigned isImm = fieldFromInstruction(insn, 13, 1);
538  unsigned rs2 = 0;
539  unsigned simm13 = 0;
540  if (isImm)
541  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
542  else
543  rs2 = fieldFromInstruction(insn, 0, 5);
544 
545  // Decode RD.
546  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
548  return status;
549 
550  // Decode RS1.
551  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
553  return status;
554 
555  // Decode RS1 | SIMM13.
556  if (isImm)
557  MI.addOperand(MCOperand::createImm(simm13));
558  else {
559  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
561  return status;
562  }
564 }
565 
566 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
567  const MCDisassembler *Decoder) {
568 
569  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
570  unsigned isImm = fieldFromInstruction(insn, 13, 1);
571  unsigned rs2 = 0;
572  unsigned simm13 = 0;
573  if (isImm)
574  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
575  else
576  rs2 = fieldFromInstruction(insn, 0, 5);
577 
578  // Decode RS1.
579  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
581  return status;
582 
583  // Decode RS2 | SIMM13.
584  if (isImm)
585  MI.addOperand(MCOperand::createImm(simm13));
586  else {
587  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
589  return status;
590  }
592 }
593 
594 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
595  const MCDisassembler *Decoder) {
596 
597  unsigned rd = fieldFromInstruction(insn, 25, 5);
598  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
599  unsigned isImm = fieldFromInstruction(insn, 13, 1);
600  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
601  unsigned asi = fieldFromInstruction(insn, 5, 8);
602  unsigned rs2 = 0;
603  unsigned simm13 = 0;
604  if (isImm)
605  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
606  else
607  rs2 = fieldFromInstruction(insn, 0, 5);
608 
609  // Decode RD.
610  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
612  return status;
613 
614  // Decode RS1.
615  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
617  return status;
618 
619  // Decode RS1 | SIMM13.
620  if (isImm)
621  MI.addOperand(MCOperand::createImm(simm13));
622  else {
623  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
625  return status;
626  }
627 
628  if (hasAsi)
629  MI.addOperand(MCOperand::createImm(asi));
630 
632 }
633 
634 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
635  const MCDisassembler *Decoder) {
636 
637  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
638  unsigned isImm = fieldFromInstruction(insn, 13, 1);
639  unsigned cc =fieldFromInstruction(insn, 25, 4);
640  unsigned rs2 = 0;
641  unsigned imm7 = 0;
642  if (isImm)
643  imm7 = fieldFromInstruction(insn, 0, 7);
644  else
645  rs2 = fieldFromInstruction(insn, 0, 5);
646 
647  // Decode RS1.
648  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
650  return status;
651 
652  // Decode RS1 | IMM7.
653  if (isImm)
654  MI.addOperand(MCOperand::createImm(imm7));
655  else {
656  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
658  return status;
659  }
660 
661  // Decode CC
662  MI.addOperand(MCOperand::createImm(cc));
663 
665 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
L5
to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 L5
Definition: README.txt:656
DecodeStoreIntPair
static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:467
SparcTargetInfo.h
DecodeTRAP
static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:634
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
DecodeLoadDFP
static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:435
DecodeFCCRegsRegisterClass
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:208
IntPairDecoderTable
static const uint16_t IntPairDecoderTable[]
Definition: SparcDisassembler.cpp:119
MCDisassembler.h
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
SparcMCTargetDesc.h
DecodeStoreInt
static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:460
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
DecodeFunc
DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:366
DecodeLoadQFP
static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:441
DecodeCPRegsRegisterClass
static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:198
DecodeCPPairRegisterClass
static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:251
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
DecodeMem
static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder, bool isLoad, DecodeFunc DecodeRD)
Definition: SparcDisassembler.cpp:369
llvm::getTheSparcTarget
Target & getTheSparcTarget()
Definition: SparcTargetInfo.cpp:13
llvm::MCDisassembler::SoftFail
@ SoftFail
Definition: MCDisassembler.h:111
DecodeASRRegsRegisterClass
static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:217
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:933
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
DecodeI64RegsRegisterClass
static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:155
MCDecoderOps.h
DecodeReturn
static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:566
I1
@ I1
Definition: DXILOpLowering.cpp:37
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:982
DecodeSWAP
static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:594
PRRegDecoderTable
static const unsigned PRRegDecoderTable[]
Definition: SparcDisassembler.cpp:113
DecodeLoadIntPair
static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:422
DecodeJMPL
static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:532
L2
add sub stmia L5 ldr L2
Definition: README.txt:201
DecodeQFPRegsRegisterClass
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:185
L3
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx L3
Definition: README-X86-64.txt:22
CPPairDecoderTable
static const uint16_t CPPairDecoderTable[]
Definition: SparcDisassembler.cpp:138
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:112
MCInst.h
llvm::getTheSparcelTarget
Target & getTheSparcelTarget()
Definition: SparcTargetInfo.cpp:21
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian)
Read four bytes from the ArrayRef and return 32 bit word.
Definition: SparcDisassembler.cpp:313
DecodeStoreFP
static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:474
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
DecodeLoadCPPair
static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:453
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLArrayExtras.h:29
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: SparcDisassembler.cpp:26
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
L6
gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movq rsp movq rsp movq rsp movq rsp movq rsp rax movq rsp rax movq rsp rsp rsp eax eax jbe LBB1_3 rcx rax movq rsp eax rsp ret ecx eax rcx movl rsp jmp LBB1_2 gcc rsp rax movq rsp rsp movq rsp rax movq rsp eax eax jb L6 rdx eax rsp ret p2align L6
Definition: README.txt:1168
DecodePRRegsRegisterClass
static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:226
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
LLVMInitializeSparcDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcDisassembler()
Definition: SparcDisassembler.cpp:50
uint64_t
DecodeStoreQFP
static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:487
tryAddingSymbolicOperand
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:507
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
DecodeLoadFP
static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:429
FCCRegDecoderTable
static const unsigned FCCRegDecoderTable[]
Definition: SparcDisassembler.cpp:100
isBranch
static bool isBranch(unsigned Opcode)
Definition: R600InstrInfo.cpp:642
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:145
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
Definition: MCDisassembler.cpp:23
DecodeStoreDFP
static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:480
DecodeFPRegsRegisterClass
static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:165
llvm::ArrayRef< uint8_t >
MCAsmInfo.h
isLoad
static bool isLoad(int Opcode)
Definition: ARCInstrInfo.cpp:53
DecodeIntPairRegisterClass
static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:235
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
uint32_t
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:110
ASRRegDecoderTable
static const unsigned ASRRegDecoderTable[]
Definition: SparcDisassembler.cpp:103
FPRegDecoderTable
static const unsigned FPRegDecoderTable[]
Definition: SparcDisassembler.cpp:70
CPRegDecoderTable
static const unsigned CPRegDecoderTable[]
Definition: SparcDisassembler.cpp:126
L4
to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret eax ja L5 L4
Definition: README.txt:662
DFPRegDecoderTable
static const unsigned DFPRegDecoderTable[]
Definition: SparcDisassembler.cpp:80
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:132
uint16_t
DecodeSIMM13
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:525
DecodeLoadInt
static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:416
IntRegDecoderTable
static const unsigned IntRegDecoderTable[]
Definition: SparcDisassembler.cpp:60
DecodeDFPRegsRegisterClass
static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:175
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:429
DecodeCall
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:515
L7
to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp which is much esp edx eax decl edx jle L7 esp ret L7
Definition: README.txt:658
QFPRegDecoderTable
static const unsigned QFPRegDecoderTable[]
Definition: SparcDisassembler.cpp:90
llvm::sys::fs::status
std::error_code status(const Twine &path, file_status &result, bool follow=true)
Get file status as if by POSIX stat().
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
DecodeStoreCP
static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:494
DecodeStoreCPPair
static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:500
DecodeLoadCP
static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: SparcDisassembler.cpp:447
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::getTheSparcV9Target
Target & getTheSparcV9Target()
Definition: SparcTargetInfo.cpp:17
createSparcDisassembler
static MCDisassembler * createSparcDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: SparcDisassembler.cpp:43