LLVM  14.0.0git
AMDGPUCustomBehaviour.cpp
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1 //===------------------ AMDGPUCustomBehaviour.cpp ---------------*-C++ -* -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file implements methods from the AMDGPUCustomBehaviour class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUCustomBehaviour.h"
16 #include "SIInstrInfo.h"
18 #include "llvm/MC/TargetRegistry.h"
19 #include "llvm/Support/WithColor.h"
20 
21 namespace llvm {
22 namespace mca {
23 
25  std::unique_ptr<Instruction> &Inst, const MCInst &MCI) {
26  switch (MCI.getOpcode()) {
27  case AMDGPU::S_WAITCNT:
28  case AMDGPU::S_WAITCNT_EXPCNT:
29  case AMDGPU::S_WAITCNT_LGKMCNT:
30  case AMDGPU::S_WAITCNT_VMCNT:
31  case AMDGPU::S_WAITCNT_VSCNT:
32  case AMDGPU::S_WAITCNT_EXPCNT_gfx10:
33  case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:
34  case AMDGPU::S_WAITCNT_VMCNT_gfx10:
35  case AMDGPU::S_WAITCNT_VSCNT_gfx10:
36  case AMDGPU::S_WAITCNT_gfx10:
37  case AMDGPU::S_WAITCNT_gfx6_gfx7:
38  case AMDGPU::S_WAITCNT_vi:
39  return processWaitCnt(Inst, MCI);
40  }
41 }
42 
43 // s_waitcnt instructions encode important information as immediate operands
44 // which are lost during the MCInst -> mca::Instruction lowering.
45 void AMDGPUInstrPostProcess::processWaitCnt(std::unique_ptr<Instruction> &Inst,
46  const MCInst &MCI) {
47  for (int Idx = 0, N = MCI.size(); Idx < N; Idx++) {
48  MCAOperand Op;
49  const MCOperand &MCOp = MCI.getOperand(Idx);
50  if (MCOp.isReg()) {
52  } else if (MCOp.isImm()) {
54  }
55  Op.setIndex(Idx);
56  Inst->addOperand(Op);
57  }
58 }
59 
61  const mca::SourceMgr &SrcMgr,
62  const MCInstrInfo &MCII)
63  : CustomBehaviour(STI, SrcMgr, MCII) {
64  generateWaitCntInfo();
65 }
66 
68  const InstRef &IR) {
69  const Instruction &Inst = *IR.getInstruction();
70  unsigned Opcode = Inst.getOpcode();
71 
72  // llvm-mca is generally run on fully compiled assembly so we wouldn't see any
73  // pseudo instructions here. However, there are plans for the future to make
74  // it possible to use mca within backend passes. As such, I have left the
75  // pseudo version of s_waitcnt within this switch statement.
76  switch (Opcode) {
77  default:
78  return 0;
79  case AMDGPU::S_WAITCNT: // This instruction
80  case AMDGPU::S_WAITCNT_EXPCNT:
81  case AMDGPU::S_WAITCNT_LGKMCNT:
82  case AMDGPU::S_WAITCNT_VMCNT:
83  case AMDGPU::S_WAITCNT_VSCNT: // to this instruction are all pseudo.
84  case AMDGPU::S_WAITCNT_EXPCNT_gfx10:
85  case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:
86  case AMDGPU::S_WAITCNT_VMCNT_gfx10:
87  case AMDGPU::S_WAITCNT_VSCNT_gfx10:
88  case AMDGPU::S_WAITCNT_gfx10:
89  case AMDGPU::S_WAITCNT_gfx6_gfx7:
90  case AMDGPU::S_WAITCNT_vi:
91  // s_endpgm also behaves as if there is an implicit
92  // s_waitcnt 0, but I'm not sure if it would be appropriate
93  // to model this in llvm-mca based on how the iterations work
94  // while simulating the pipeline over and over.
95  return handleWaitCnt(IssuedInst, IR);
96  }
97 
98  return 0;
99 }
100 
101 unsigned AMDGPUCustomBehaviour::handleWaitCnt(ArrayRef<InstRef> IssuedInst,
102  const InstRef &IR) {
103  // Currently, all s_waitcnt instructions are handled except s_waitcnt_depctr.
104  // I do not know how that instruction works so I did not attempt to model it.
105  // set the max values to begin
106  unsigned Vmcnt = 63;
107  unsigned Expcnt = 7;
108  unsigned Lgkmcnt = 31;
109  unsigned Vscnt = 63;
110  unsigned CurrVmcnt = 0;
111  unsigned CurrExpcnt = 0;
112  unsigned CurrLgkmcnt = 0;
113  unsigned CurrVscnt = 0;
114  unsigned CyclesToWaitVm = ~0U;
115  unsigned CyclesToWaitExp = ~0U;
116  unsigned CyclesToWaitLgkm = ~0U;
117  unsigned CyclesToWaitVs = ~0U;
118 
119  computeWaitCnt(IR, Vmcnt, Expcnt, Lgkmcnt, Vscnt);
120 
121  // We will now look at each of the currently executing instructions
122  // to find out if this wait instruction still needs to wait.
123  for (auto I = IssuedInst.begin(), E = IssuedInst.end(); I != E; I++) {
124  const InstRef &PrevIR = *I;
125  const Instruction &PrevInst = *PrevIR.getInstruction();
126  const unsigned PrevInstIndex = PrevIR.getSourceIndex() % SrcMgr.size();
127  const WaitCntInfo &PrevInstWaitInfo = InstrWaitCntInfo[PrevInstIndex];
128  const int CyclesLeft = PrevInst.getCyclesLeft();
129  assert(CyclesLeft != UNKNOWN_CYCLES &&
130  "We should know how many cycles are left for this instruction");
131  if (PrevInstWaitInfo.VmCnt) {
132  CurrVmcnt++;
133  if ((unsigned)CyclesLeft < CyclesToWaitVm)
134  CyclesToWaitVm = CyclesLeft;
135  }
136  if (PrevInstWaitInfo.ExpCnt) {
137  CurrExpcnt++;
138  if ((unsigned)CyclesLeft < CyclesToWaitExp)
139  CyclesToWaitExp = CyclesLeft;
140  }
141  if (PrevInstWaitInfo.LgkmCnt) {
142  CurrLgkmcnt++;
143  if ((unsigned)CyclesLeft < CyclesToWaitLgkm)
144  CyclesToWaitLgkm = CyclesLeft;
145  }
146  if (PrevInstWaitInfo.VsCnt) {
147  CurrVscnt++;
148  if ((unsigned)CyclesLeft < CyclesToWaitVs)
149  CyclesToWaitVs = CyclesLeft;
150  }
151  }
152 
153  unsigned CyclesToWait = ~0U;
154  if (CurrVmcnt > Vmcnt && CyclesToWaitVm < CyclesToWait)
155  CyclesToWait = CyclesToWaitVm;
156  if (CurrExpcnt > Expcnt && CyclesToWaitExp < CyclesToWait)
157  CyclesToWait = CyclesToWaitExp;
158  if (CurrLgkmcnt > Lgkmcnt && CyclesToWaitLgkm < CyclesToWait)
159  CyclesToWait = CyclesToWaitLgkm;
160  if (CurrVscnt > Vscnt && CyclesToWaitVs < CyclesToWait)
161  CyclesToWait = CyclesToWaitVs;
162 
163  // We may underestimate how many cycles we need to wait, but this
164  // isn't a big deal. Our return value is just how many cycles until
165  // this function gets run again. So as long as we don't overestimate
166  // the wait time, we'll still end up stalling at this instruction
167  // for the correct number of cycles.
168 
169  if (CyclesToWait == ~0U)
170  return 0;
171  return CyclesToWait;
172 }
173 
174 void AMDGPUCustomBehaviour::computeWaitCnt(const InstRef &IR, unsigned &Vmcnt,
175  unsigned &Expcnt, unsigned &Lgkmcnt,
176  unsigned &Vscnt) {
178  const Instruction &Inst = *IR.getInstruction();
179  unsigned Opcode = Inst.getOpcode();
180 
181  switch (Opcode) {
182  case AMDGPU::S_WAITCNT_EXPCNT_gfx10:
183  case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:
184  case AMDGPU::S_WAITCNT_VMCNT_gfx10:
185  case AMDGPU::S_WAITCNT_VSCNT_gfx10: {
186  // Should probably be checking for nullptr
187  // here, but I'm not sure how I should handle the case
188  // where we see a nullptr.
189  const MCAOperand *OpReg = Inst.getOperand(0);
190  const MCAOperand *OpImm = Inst.getOperand(1);
191  assert(OpReg && OpReg->isReg() && "First operand should be a register.");
192  assert(OpImm && OpImm->isImm() && "Second operand should be an immediate.");
193  if (OpReg->getReg() != AMDGPU::SGPR_NULL) {
194  // Instruction is using a real register.
195  // Since we can't know what value this register will have,
196  // we can't compute what the value of this wait should be.
197  WithColor::warning() << "The register component of "
198  << MCII.getName(Opcode) << " will be completely "
199  << "ignored. So the wait may not be accurate.\n";
200  }
201  switch (Opcode) {
202  // Redundant switch so I don't have to repeat the code above
203  // for each case. There are more clever ways to avoid this
204  // extra switch and anyone can feel free to implement one of them.
205  case AMDGPU::S_WAITCNT_EXPCNT_gfx10:
206  Expcnt = OpImm->getImm();
207  break;
208  case AMDGPU::S_WAITCNT_LGKMCNT_gfx10:
209  Lgkmcnt = OpImm->getImm();
210  break;
211  case AMDGPU::S_WAITCNT_VMCNT_gfx10:
212  Vmcnt = OpImm->getImm();
213  break;
214  case AMDGPU::S_WAITCNT_VSCNT_gfx10:
215  Vscnt = OpImm->getImm();
216  break;
217  }
218  return;
219  }
220  case AMDGPU::S_WAITCNT_gfx10:
221  case AMDGPU::S_WAITCNT_gfx6_gfx7:
222  case AMDGPU::S_WAITCNT_vi:
223  unsigned WaitCnt = Inst.getOperand(0)->getImm();
224  AMDGPU::decodeWaitcnt(IV, WaitCnt, Vmcnt, Expcnt, Lgkmcnt);
225  return;
226  }
227 }
228 
229 void AMDGPUCustomBehaviour::generateWaitCntInfo() {
230  // The core logic from this function is taken from
231  // SIInsertWaitcnts::updateEventWaitcntAfter() In that pass, the instructions
232  // that are being looked at are in the MachineInstr format, whereas we have
233  // access to the MCInst format. The side effects of this are that we can't use
234  // the mayAccessVMEMThroughFlat(Inst) or mayAccessLDSThroughFlat(Inst)
235  // functions. Therefore, we conservatively assume that these functions will
236  // return true. This may cause a few instructions to be incorrectly tagged
237  // with an extra CNT. However, these are instructions that do interact with at
238  // least one CNT so giving them an extra CNT shouldn't cause issues in most
239  // scenarios.
241  InstrWaitCntInfo.resize(SrcMgr.size());
242 
243  int Index = 0;
244  for (auto I = SrcMgr.begin(), E = SrcMgr.end(); I != E; ++I, ++Index) {
245  const std::unique_ptr<Instruction> &Inst = *I;
246  unsigned Opcode = Inst->getOpcode();
247  const MCInstrDesc &MCID = MCII.get(Opcode);
248  if ((MCID.TSFlags & SIInstrFlags::DS) &&
249  (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) {
250  InstrWaitCntInfo[Index].LgkmCnt = true;
251  if (isAlwaysGDS(Opcode) || hasModifiersSet(Inst, AMDGPU::OpName::gds))
252  InstrWaitCntInfo[Index].ExpCnt = true;
253  } else if (MCID.TSFlags & SIInstrFlags::FLAT) {
254  // We conservatively assume that mayAccessVMEMThroughFlat(Inst)
255  // and mayAccessLDSThroughFlat(Inst) would both return true for this
256  // instruction. We have to do this because those functions use
257  // information about the memory operands that we don't have access to.
258  InstrWaitCntInfo[Index].LgkmCnt = true;
259  if (!STI.hasFeature(AMDGPU::FeatureVscnt))
260  InstrWaitCntInfo[Index].VmCnt = true;
261  else if (MCID.mayLoad() && !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet))
262  InstrWaitCntInfo[Index].VmCnt = true;
263  else
264  InstrWaitCntInfo[Index].VsCnt = true;
265  } else if (isVMEM(MCID) && !AMDGPU::getMUBUFIsBufferInv(Opcode)) {
266  if (!STI.hasFeature(AMDGPU::FeatureVscnt))
267  InstrWaitCntInfo[Index].VmCnt = true;
268  else if ((MCID.mayLoad() &&
270  ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() &&
271  !MCID.mayStore()))
272  InstrWaitCntInfo[Index].VmCnt = true;
273  else if (MCID.mayStore())
274  InstrWaitCntInfo[Index].VsCnt = true;
275 
276  // (IV.Major < 7) is meant to represent
277  // GCNTarget.vmemWriteNeedsExpWaitcnt()
278  // which is defined as
279  // { return getGeneration() < SEA_ISLANDS; }
280  if (IV.Major < 7 &&
281  (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet)))
282  InstrWaitCntInfo[Index].ExpCnt = true;
283  } else if (MCID.TSFlags & SIInstrFlags::SMRD) {
284  InstrWaitCntInfo[Index].LgkmCnt = true;
285  } else if (MCID.TSFlags & SIInstrFlags::EXP) {
286  InstrWaitCntInfo[Index].ExpCnt = true;
287  } else {
288  switch (Opcode) {
289  case AMDGPU::S_SENDMSG:
290  case AMDGPU::S_SENDMSGHALT:
291  case AMDGPU::S_MEMTIME:
292  case AMDGPU::S_MEMREALTIME:
293  InstrWaitCntInfo[Index].LgkmCnt = true;
294  break;
295  }
296  }
297  }
298 }
299 
300 // taken from SIInstrInfo::isVMEM()
301 bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) {
302  return MCID.TSFlags & SIInstrFlags::MUBUF ||
303  MCID.TSFlags & SIInstrFlags::MTBUF ||
305 }
306 
307 // taken from SIInstrInfo::hasModifiersSet()
308 bool AMDGPUCustomBehaviour::hasModifiersSet(
309  const std::unique_ptr<Instruction> &Inst, unsigned OpName) const {
310  int Idx = AMDGPU::getNamedOperandIdx(Inst->getOpcode(), OpName);
311  if (Idx == -1)
312  return false;
313 
314  const MCAOperand *Op = Inst->getOperand(Idx);
315  if (Op == nullptr || !Op->isImm() || !Op->getImm())
316  return false;
317 
318  return true;
319 }
320 
321 // taken from SIInstrInfo::isAlwaysGDS()
322 bool AMDGPUCustomBehaviour::isAlwaysGDS(uint16_t Opcode) const {
323  return Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::DS_GWS_INIT ||
324  Opcode == AMDGPU::DS_GWS_SEMA_V || Opcode == AMDGPU::DS_GWS_SEMA_BR ||
325  Opcode == AMDGPU::DS_GWS_SEMA_P ||
326  Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||
327  Opcode == AMDGPU::DS_GWS_BARRIER;
328 }
329 
330 } // namespace mca
331 } // namespace llvm
332 
333 using namespace llvm;
334 using namespace mca;
335 
336 static CustomBehaviour *
338  const mca::SourceMgr &SrcMgr,
339  const MCInstrInfo &MCII) {
340  return new AMDGPUCustomBehaviour(STI, SrcMgr, MCII);
341 }
342 
343 static InstrPostProcess *
345  const MCInstrInfo &MCII) {
346  return new AMDGPUInstrPostProcess(STI, MCII);
347 }
348 
349 /// Extern function to initialize the targets for the AMDGPU backend
350 
356 
361 }
llvm::AMDGPU::getMUBUFIsBufferInv
bool getMUBUFIsBufferInv(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:289
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:58
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::AMDGPU::getIsaVersion
IsaVersion getIsaVersion(StringRef GPU)
Definition: TargetParser.cpp:189
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::mca::AMDGPUCustomBehaviour::checkCustomHazard
unsigned checkCustomHazard(ArrayRef< InstRef > IssuedInst, const InstRef &IR) override
This method is used to determine if an instruction should be allowed to be dispatched.
Definition: AMDGPUCustomBehaviour.cpp:67
llvm::mca::SourceMgr::size
unsigned size() const
Definition: SourceMgr.h:40
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:54
llvm::SIInstrFlags::IsAtomicNoRet
@ IsAtomicNoRet
Definition: SIDefines.h:120
llvm::SIInstrFlags::LGKM_CNT
@ LGKM_CNT
Definition: SIDefines.h:69
llvm::mca::Instruction::getCyclesLeft
int getCyclesLeft() const
Definition: Instruction.h:630
llvm::mca::SourceMgr::end
const_iterator end() const
Definition: SourceMgr.h:51
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::mca::Instruction
An instruction propagated through the simulated instruction pipeline.
Definition: Instruction.h:569
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::AMDGPU::IsaVersion::Major
unsigned Major
Definition: TargetParser.h:106
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:55
llvm::mca::InstRef::getInstruction
Instruction * getInstruction()
Definition: Instruction.h:700
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition: TargetParser.h:105
llvm::Instruction::getOpcode
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:160
llvm::mca::WaitCntInfo::VmCnt
bool VmCnt
Definition: AMDGPUCustomBehaviour.h:41
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::mca::MCAOperand::isImm
bool isImm() const
Definition: Instruction.h:69
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:118
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
llvm::mca::MCAOperand
A representation of an mca::Instruction operand for use in mca::CustomBehaviour.
Definition: Instruction.h:38
llvm::mca::MCAOperand::isReg
bool isReg() const
Definition: Instruction.h:68
AMDGPUTargetInfo.h
llvm::AMDGPUISD::DS_ORDERED_COUNT
@ DS_ORDERED_COUNT
Definition: AMDGPUISelLowering.h:501
llvm::SrcMgr
SourceMgr SrcMgr
Definition: Error.cpp:24
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::mca::InstRef::getSourceIndex
unsigned getSourceIndex() const
Definition: Instruction.h:699
llvm::mca::CustomBehaviour::SrcMgr
const mca::SourceMgr & SrcMgr
Definition: CustomBehaviour.h:59
llvm::mca::CustomBehaviour::MCII
const MCInstrInfo & MCII
Definition: CustomBehaviour.h:60
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::TargetRegistry::RegisterInstrPostProcess
static void RegisterInstrPostProcess(Target &T, Target::InstrPostProcessCtorTy Fn)
RegisterInstrPostProcess - Register an InstrPostProcess implementation for the given target.
Definition: TargetRegistry.h:1033
llvm::mca::AMDGPUInstrPostProcess::postProcessInstruction
void postProcessInstruction(std::unique_ptr< Instruction > &Inst, const MCInst &MCI) override
Definition: AMDGPUCustomBehaviour.cpp:24
llvm::mca::AMDGPUCustomBehaviour::AMDGPUCustomBehaviour
AMDGPUCustomBehaviour(const MCSubtargetInfo &STI, const mca::SourceMgr &SrcMgr, const MCInstrInfo &MCII)
Definition: AMDGPUCustomBehaviour.cpp:60
llvm::Instruction
Definition: Instruction.h:45
OpName
Definition: R600Defines.h:62
llvm::mca::AMDGPUInstrPostProcess
Definition: AMDGPUCustomBehaviour.h:27
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:945
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:57
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:746
llvm::mca::CustomBehaviour::STI
const MCSubtargetInfo & STI
Definition: CustomBehaviour.h:58
LLVMInitializeAMDGPUTargetMCA
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMCA()
Extern function to initialize the targets for the AMDGPU backend.
Definition: AMDGPUCustomBehaviour.cpp:351
llvm::TargetRegistry::RegisterCustomBehaviour
static void RegisterCustomBehaviour(Target &T, Target::CustomBehaviourCtorTy Fn)
RegisterCustomBehaviour - Register a CustomBehaviour implementation for the given target.
Definition: TargetRegistry.h:1019
llvm::mca::MCAOperand::getImm
int64_t getImm() const
Definition: Instruction.h:79
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:429
llvm::WithColor::warning
static raw_ostream & warning()
Convenience method for printing "warning: " to stderr.
Definition: WithColor.cpp:77
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
AMDGPUMCTargetDesc.h
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::mca::CustomBehaviour
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
Definition: CustomBehaviour.h:56
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::mca::SourceMgr::begin
const_iterator begin() const
Definition: SourceMgr.h:50
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
AMDGPUCustomBehaviour.h
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::mca::UNKNOWN_CYCLES
constexpr int UNKNOWN_CYCLES
Definition: Instruction.h:34
llvm::MCInst::size
size_t size() const
Definition: MCInst.h:218
llvm::mca::InstRef
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:686
llvm::MCInstrInfo::getName
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:68
SIInstrInfo.h
llvm::MCInstrDesc::mayStore
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:435
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:123
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::mca::MCAOperand::createReg
static MCAOperand createReg(unsigned Reg)
Definition: Instruction.h:98
llvm::mca::WaitCntInfo
Definition: AMDGPUCustomBehaviour.h:40
llvm::mca::InstrPostProcess
Class which can be overriden by targets to modify the mca::Instruction objects before the pipeline st...
Definition: CustomBehaviour.h:35
WithColor.h
llvm::mca::SourceMgr
Definition: SourceMgr.h:28
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
uint16_t
llvm::mca::AMDGPUCustomBehaviour
Definition: AMDGPUCustomBehaviour.h:47
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:151
llvm::mca::WaitCntInfo::LgkmCnt
bool LgkmCnt
Definition: AMDGPUCustomBehaviour.h:43
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:56
llvm::mca::WaitCntInfo::ExpCnt
bool ExpCnt
Definition: AMDGPUCustomBehaviour.h:42
createAMDGPUInstrPostProcess
static InstrPostProcess * createAMDGPUInstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)
Definition: AMDGPUCustomBehaviour.cpp:344
llvm::mca::MCAOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: Instruction.h:74
llvm::mca::MCAOperand::createImm
static MCAOperand createImm(int64_t Val)
Definition: Instruction.h:105
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:59
N
#define N
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
createAMDGPUCustomBehaviour
static CustomBehaviour * createAMDGPUCustomBehaviour(const MCSubtargetInfo &STI, const mca::SourceMgr &SrcMgr, const MCInstrInfo &MCII)
Definition: AMDGPUCustomBehaviour.cpp:337
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::mca::InstructionBase::getOpcode
unsigned getOpcode() const
Definition: Instruction.h:532
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::mca::WaitCntInfo::VsCnt
bool VsCnt
Definition: AMDGPUCustomBehaviour.h:44
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69