LLVM  14.0.0git
X86AsmParser.cpp
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1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "MCTargetDesc/X86MCExpr.h"
14 #include "X86AsmParserCommon.h"
15 #include "X86Operand.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallString.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSection.h"
31 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/MC/TargetRegistry.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/SourceMgr.h"
39 #include <algorithm>
40 #include <memory>
41 
42 using namespace llvm;
43 
45  "x86-experimental-lvi-inline-asm-hardening",
46  cl::desc("Harden inline assembly code that may be vulnerable to Load Value"
47  " Injection (LVI). This feature is experimental."), cl::Hidden);
48 
49 static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
50  if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
51  ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
52  return true;
53  }
54  return false;
55 }
56 
57 namespace {
58 
59 static const char OpPrecedence[] = {
60  0, // IC_OR
61  1, // IC_XOR
62  2, // IC_AND
63  4, // IC_LSHIFT
64  4, // IC_RSHIFT
65  5, // IC_PLUS
66  5, // IC_MINUS
67  6, // IC_MULTIPLY
68  6, // IC_DIVIDE
69  6, // IC_MOD
70  7, // IC_NOT
71  8, // IC_NEG
72  9, // IC_RPAREN
73  10, // IC_LPAREN
74  0, // IC_IMM
75  0, // IC_REGISTER
76  3, // IC_EQ
77  3, // IC_NE
78  3, // IC_LT
79  3, // IC_LE
80  3, // IC_GT
81  3 // IC_GE
82 };
83 
84 class X86AsmParser : public MCTargetAsmParser {
85  ParseInstructionInfo *InstInfo;
86  bool Code16GCC;
87  unsigned ForcedDataPrefix = 0;
88 
89  enum VEXEncoding {
90  VEXEncoding_Default,
91  VEXEncoding_VEX,
92  VEXEncoding_VEX2,
93  VEXEncoding_VEX3,
94  VEXEncoding_EVEX,
95  };
96 
97  VEXEncoding ForcedVEXEncoding = VEXEncoding_Default;
98 
99  enum DispEncoding {
100  DispEncoding_Default,
101  DispEncoding_Disp8,
102  DispEncoding_Disp32,
103  };
104 
105  DispEncoding ForcedDispEncoding = DispEncoding_Default;
106 
107 private:
108  SMLoc consumeToken() {
109  MCAsmParser &Parser = getParser();
110  SMLoc Result = Parser.getTok().getLoc();
111  Parser.Lex();
112  return Result;
113  }
114 
115  X86TargetStreamer &getTargetStreamer() {
116  assert(getParser().getStreamer().getTargetStreamer() &&
117  "do not have a target streamer");
118  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
119  return static_cast<X86TargetStreamer &>(TS);
120  }
121 
122  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
123  uint64_t &ErrorInfo, FeatureBitset &MissingFeatures,
124  bool matchingInlineAsm, unsigned VariantID = 0) {
125  // In Code16GCC mode, match as 32-bit.
126  if (Code16GCC)
127  SwitchMode(X86::Mode32Bit);
128  unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
129  MissingFeatures, matchingInlineAsm,
130  VariantID);
131  if (Code16GCC)
132  SwitchMode(X86::Mode16Bit);
133  return rv;
134  }
135 
136  enum InfixCalculatorTok {
137  IC_OR = 0,
138  IC_XOR,
139  IC_AND,
140  IC_LSHIFT,
141  IC_RSHIFT,
142  IC_PLUS,
143  IC_MINUS,
144  IC_MULTIPLY,
145  IC_DIVIDE,
146  IC_MOD,
147  IC_NOT,
148  IC_NEG,
149  IC_RPAREN,
150  IC_LPAREN,
151  IC_IMM,
152  IC_REGISTER,
153  IC_EQ,
154  IC_NE,
155  IC_LT,
156  IC_LE,
157  IC_GT,
158  IC_GE
159  };
160 
161  enum IntelOperatorKind {
162  IOK_INVALID = 0,
163  IOK_LENGTH,
164  IOK_SIZE,
165  IOK_TYPE,
166  };
167 
168  enum MasmOperatorKind {
169  MOK_INVALID = 0,
170  MOK_LENGTHOF,
171  MOK_SIZEOF,
172  MOK_TYPE,
173  };
174 
175  class InfixCalculator {
176  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
177  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
178  SmallVector<ICToken, 4> PostfixStack;
179 
180  bool isUnaryOperator(InfixCalculatorTok Op) const {
181  return Op == IC_NEG || Op == IC_NOT;
182  }
183 
184  public:
185  int64_t popOperand() {
186  assert (!PostfixStack.empty() && "Poped an empty stack!");
187  ICToken Op = PostfixStack.pop_back_val();
188  if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
189  return -1; // The invalid Scale value will be caught later by checkScale
190  return Op.second;
191  }
192  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
193  assert ((Op == IC_IMM || Op == IC_REGISTER) &&
194  "Unexpected operand!");
195  PostfixStack.push_back(std::make_pair(Op, Val));
196  }
197 
198  void popOperator() { InfixOperatorStack.pop_back(); }
199  void pushOperator(InfixCalculatorTok Op) {
200  // Push the new operator if the stack is empty.
201  if (InfixOperatorStack.empty()) {
202  InfixOperatorStack.push_back(Op);
203  return;
204  }
205 
206  // Push the new operator if it has a higher precedence than the operator
207  // on the top of the stack or the operator on the top of the stack is a
208  // left parentheses.
209  unsigned Idx = InfixOperatorStack.size() - 1;
210  InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
211  if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
212  InfixOperatorStack.push_back(Op);
213  return;
214  }
215 
216  // The operator on the top of the stack has higher precedence than the
217  // new operator.
218  unsigned ParenCount = 0;
219  while (true) {
220  // Nothing to process.
221  if (InfixOperatorStack.empty())
222  break;
223 
224  Idx = InfixOperatorStack.size() - 1;
225  StackOp = InfixOperatorStack[Idx];
226  if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
227  break;
228 
229  // If we have an even parentheses count and we see a left parentheses,
230  // then stop processing.
231  if (!ParenCount && StackOp == IC_LPAREN)
232  break;
233 
234  if (StackOp == IC_RPAREN) {
235  ++ParenCount;
236  InfixOperatorStack.pop_back();
237  } else if (StackOp == IC_LPAREN) {
238  --ParenCount;
239  InfixOperatorStack.pop_back();
240  } else {
241  InfixOperatorStack.pop_back();
242  PostfixStack.push_back(std::make_pair(StackOp, 0));
243  }
244  }
245  // Push the new operator.
246  InfixOperatorStack.push_back(Op);
247  }
248 
249  int64_t execute() {
250  // Push any remaining operators onto the postfix stack.
251  while (!InfixOperatorStack.empty()) {
252  InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
253  if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
254  PostfixStack.push_back(std::make_pair(StackOp, 0));
255  }
256 
257  if (PostfixStack.empty())
258  return 0;
259 
260  SmallVector<ICToken, 16> OperandStack;
261  for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
262  ICToken Op = PostfixStack[i];
263  if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
264  OperandStack.push_back(Op);
265  } else if (isUnaryOperator(Op.first)) {
266  assert (OperandStack.size() > 0 && "Too few operands.");
267  ICToken Operand = OperandStack.pop_back_val();
268  assert (Operand.first == IC_IMM &&
269  "Unary operation with a register!");
270  switch (Op.first) {
271  default:
272  report_fatal_error("Unexpected operator!");
273  break;
274  case IC_NEG:
275  OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
276  break;
277  case IC_NOT:
278  OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
279  break;
280  }
281  } else {
282  assert (OperandStack.size() > 1 && "Too few operands.");
283  int64_t Val;
284  ICToken Op2 = OperandStack.pop_back_val();
285  ICToken Op1 = OperandStack.pop_back_val();
286  switch (Op.first) {
287  default:
288  report_fatal_error("Unexpected operator!");
289  break;
290  case IC_PLUS:
291  Val = Op1.second + Op2.second;
292  OperandStack.push_back(std::make_pair(IC_IMM, Val));
293  break;
294  case IC_MINUS:
295  Val = Op1.second - Op2.second;
296  OperandStack.push_back(std::make_pair(IC_IMM, Val));
297  break;
298  case IC_MULTIPLY:
299  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
300  "Multiply operation with an immediate and a register!");
301  Val = Op1.second * Op2.second;
302  OperandStack.push_back(std::make_pair(IC_IMM, Val));
303  break;
304  case IC_DIVIDE:
305  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
306  "Divide operation with an immediate and a register!");
307  assert (Op2.second != 0 && "Division by zero!");
308  Val = Op1.second / Op2.second;
309  OperandStack.push_back(std::make_pair(IC_IMM, Val));
310  break;
311  case IC_MOD:
312  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
313  "Modulo operation with an immediate and a register!");
314  Val = Op1.second % Op2.second;
315  OperandStack.push_back(std::make_pair(IC_IMM, Val));
316  break;
317  case IC_OR:
318  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
319  "Or operation with an immediate and a register!");
320  Val = Op1.second | Op2.second;
321  OperandStack.push_back(std::make_pair(IC_IMM, Val));
322  break;
323  case IC_XOR:
324  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
325  "Xor operation with an immediate and a register!");
326  Val = Op1.second ^ Op2.second;
327  OperandStack.push_back(std::make_pair(IC_IMM, Val));
328  break;
329  case IC_AND:
330  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
331  "And operation with an immediate and a register!");
332  Val = Op1.second & Op2.second;
333  OperandStack.push_back(std::make_pair(IC_IMM, Val));
334  break;
335  case IC_LSHIFT:
336  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
337  "Left shift operation with an immediate and a register!");
338  Val = Op1.second << Op2.second;
339  OperandStack.push_back(std::make_pair(IC_IMM, Val));
340  break;
341  case IC_RSHIFT:
342  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
343  "Right shift operation with an immediate and a register!");
344  Val = Op1.second >> Op2.second;
345  OperandStack.push_back(std::make_pair(IC_IMM, Val));
346  break;
347  case IC_EQ:
348  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
349  "Equals operation with an immediate and a register!");
350  Val = (Op1.second == Op2.second) ? -1 : 0;
351  OperandStack.push_back(std::make_pair(IC_IMM, Val));
352  break;
353  case IC_NE:
354  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
355  "Not-equals operation with an immediate and a register!");
356  Val = (Op1.second != Op2.second) ? -1 : 0;
357  OperandStack.push_back(std::make_pair(IC_IMM, Val));
358  break;
359  case IC_LT:
360  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
361  "Less-than operation with an immediate and a register!");
362  Val = (Op1.second < Op2.second) ? -1 : 0;
363  OperandStack.push_back(std::make_pair(IC_IMM, Val));
364  break;
365  case IC_LE:
366  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
367  "Less-than-or-equal operation with an immediate and a "
368  "register!");
369  Val = (Op1.second <= Op2.second) ? -1 : 0;
370  OperandStack.push_back(std::make_pair(IC_IMM, Val));
371  break;
372  case IC_GT:
373  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
374  "Greater-than operation with an immediate and a register!");
375  Val = (Op1.second > Op2.second) ? -1 : 0;
376  OperandStack.push_back(std::make_pair(IC_IMM, Val));
377  break;
378  case IC_GE:
379  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
380  "Greater-than-or-equal operation with an immediate and a "
381  "register!");
382  Val = (Op1.second >= Op2.second) ? -1 : 0;
383  OperandStack.push_back(std::make_pair(IC_IMM, Val));
384  break;
385  }
386  }
387  }
388  assert (OperandStack.size() == 1 && "Expected a single result.");
389  return OperandStack.pop_back_val().second;
390  }
391  };
392 
393  enum IntelExprState {
394  IES_INIT,
395  IES_OR,
396  IES_XOR,
397  IES_AND,
398  IES_EQ,
399  IES_NE,
400  IES_LT,
401  IES_LE,
402  IES_GT,
403  IES_GE,
404  IES_LSHIFT,
405  IES_RSHIFT,
406  IES_PLUS,
407  IES_MINUS,
408  IES_OFFSET,
409  IES_CAST,
410  IES_NOT,
411  IES_MULTIPLY,
412  IES_DIVIDE,
413  IES_MOD,
414  IES_LBRAC,
415  IES_RBRAC,
416  IES_LPAREN,
417  IES_RPAREN,
418  IES_REGISTER,
419  IES_INTEGER,
420  IES_IDENTIFIER,
421  IES_ERROR
422  };
423 
424  class IntelExprStateMachine {
425  IntelExprState State, PrevState;
426  unsigned BaseReg, IndexReg, TmpReg, Scale;
427  int64_t Imm;
428  const MCExpr *Sym;
429  StringRef SymName;
430  InfixCalculator IC;
432  short BracCount;
433  bool MemExpr;
434  bool OffsetOperator;
435  SMLoc OffsetOperatorLoc;
436  AsmTypeInfo CurType;
437 
438  bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
439  if (Sym) {
440  ErrMsg = "cannot use more than one symbol in memory operand";
441  return true;
442  }
443  Sym = Val;
444  SymName = ID;
445  return false;
446  }
447 
448  public:
449  IntelExprStateMachine()
450  : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
451  TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
452  MemExpr(false), OffsetOperator(false) {}
453 
454  void addImm(int64_t imm) { Imm += imm; }
455  short getBracCount() const { return BracCount; }
456  bool isMemExpr() const { return MemExpr; }
457  bool isOffsetOperator() const { return OffsetOperator; }
458  SMLoc getOffsetLoc() const { return OffsetOperatorLoc; }
459  unsigned getBaseReg() const { return BaseReg; }
460  unsigned getIndexReg() const { return IndexReg; }
461  unsigned getScale() const { return Scale; }
462  const MCExpr *getSym() const { return Sym; }
463  StringRef getSymName() const { return SymName; }
464  StringRef getType() const { return CurType.Name; }
465  unsigned getSize() const { return CurType.Size; }
466  unsigned getElementSize() const { return CurType.ElementSize; }
467  unsigned getLength() const { return CurType.Length; }
468  int64_t getImm() { return Imm + IC.execute(); }
469  bool isValidEndState() const {
470  return State == IES_RBRAC || State == IES_INTEGER;
471  }
472  bool hadError() const { return State == IES_ERROR; }
473  const InlineAsmIdentifierInfo &getIdentifierInfo() const { return Info; }
474 
475  void onOr() {
476  IntelExprState CurrState = State;
477  switch (State) {
478  default:
479  State = IES_ERROR;
480  break;
481  case IES_INTEGER:
482  case IES_RPAREN:
483  case IES_REGISTER:
484  State = IES_OR;
485  IC.pushOperator(IC_OR);
486  break;
487  }
488  PrevState = CurrState;
489  }
490  void onXor() {
491  IntelExprState CurrState = State;
492  switch (State) {
493  default:
494  State = IES_ERROR;
495  break;
496  case IES_INTEGER:
497  case IES_RPAREN:
498  case IES_REGISTER:
499  State = IES_XOR;
500  IC.pushOperator(IC_XOR);
501  break;
502  }
503  PrevState = CurrState;
504  }
505  void onAnd() {
506  IntelExprState CurrState = State;
507  switch (State) {
508  default:
509  State = IES_ERROR;
510  break;
511  case IES_INTEGER:
512  case IES_RPAREN:
513  case IES_REGISTER:
514  State = IES_AND;
515  IC.pushOperator(IC_AND);
516  break;
517  }
518  PrevState = CurrState;
519  }
520  void onEq() {
521  IntelExprState CurrState = State;
522  switch (State) {
523  default:
524  State = IES_ERROR;
525  break;
526  case IES_INTEGER:
527  case IES_RPAREN:
528  case IES_REGISTER:
529  State = IES_EQ;
530  IC.pushOperator(IC_EQ);
531  break;
532  }
533  PrevState = CurrState;
534  }
535  void onNE() {
536  IntelExprState CurrState = State;
537  switch (State) {
538  default:
539  State = IES_ERROR;
540  break;
541  case IES_INTEGER:
542  case IES_RPAREN:
543  case IES_REGISTER:
544  State = IES_NE;
545  IC.pushOperator(IC_NE);
546  break;
547  }
548  PrevState = CurrState;
549  }
550  void onLT() {
551  IntelExprState CurrState = State;
552  switch (State) {
553  default:
554  State = IES_ERROR;
555  break;
556  case IES_INTEGER:
557  case IES_RPAREN:
558  case IES_REGISTER:
559  State = IES_LT;
560  IC.pushOperator(IC_LT);
561  break;
562  }
563  PrevState = CurrState;
564  }
565  void onLE() {
566  IntelExprState CurrState = State;
567  switch (State) {
568  default:
569  State = IES_ERROR;
570  break;
571  case IES_INTEGER:
572  case IES_RPAREN:
573  case IES_REGISTER:
574  State = IES_LE;
575  IC.pushOperator(IC_LE);
576  break;
577  }
578  PrevState = CurrState;
579  }
580  void onGT() {
581  IntelExprState CurrState = State;
582  switch (State) {
583  default:
584  State = IES_ERROR;
585  break;
586  case IES_INTEGER:
587  case IES_RPAREN:
588  case IES_REGISTER:
589  State = IES_GT;
590  IC.pushOperator(IC_GT);
591  break;
592  }
593  PrevState = CurrState;
594  }
595  void onGE() {
596  IntelExprState CurrState = State;
597  switch (State) {
598  default:
599  State = IES_ERROR;
600  break;
601  case IES_INTEGER:
602  case IES_RPAREN:
603  case IES_REGISTER:
604  State = IES_GE;
605  IC.pushOperator(IC_GE);
606  break;
607  }
608  PrevState = CurrState;
609  }
610  void onLShift() {
611  IntelExprState CurrState = State;
612  switch (State) {
613  default:
614  State = IES_ERROR;
615  break;
616  case IES_INTEGER:
617  case IES_RPAREN:
618  case IES_REGISTER:
619  State = IES_LSHIFT;
620  IC.pushOperator(IC_LSHIFT);
621  break;
622  }
623  PrevState = CurrState;
624  }
625  void onRShift() {
626  IntelExprState CurrState = State;
627  switch (State) {
628  default:
629  State = IES_ERROR;
630  break;
631  case IES_INTEGER:
632  case IES_RPAREN:
633  case IES_REGISTER:
634  State = IES_RSHIFT;
635  IC.pushOperator(IC_RSHIFT);
636  break;
637  }
638  PrevState = CurrState;
639  }
640  bool onPlus(StringRef &ErrMsg) {
641  IntelExprState CurrState = State;
642  switch (State) {
643  default:
644  State = IES_ERROR;
645  break;
646  case IES_INTEGER:
647  case IES_RPAREN:
648  case IES_REGISTER:
649  case IES_OFFSET:
650  State = IES_PLUS;
651  IC.pushOperator(IC_PLUS);
652  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
653  // If we already have a BaseReg, then assume this is the IndexReg with
654  // no explicit scale.
655  if (!BaseReg) {
656  BaseReg = TmpReg;
657  } else {
658  if (IndexReg) {
659  ErrMsg = "BaseReg/IndexReg already set!";
660  return true;
661  }
662  IndexReg = TmpReg;
663  Scale = 0;
664  }
665  }
666  break;
667  }
668  PrevState = CurrState;
669  return false;
670  }
671  bool onMinus(StringRef &ErrMsg) {
672  IntelExprState CurrState = State;
673  switch (State) {
674  default:
675  State = IES_ERROR;
676  break;
677  case IES_OR:
678  case IES_XOR:
679  case IES_AND:
680  case IES_EQ:
681  case IES_NE:
682  case IES_LT:
683  case IES_LE:
684  case IES_GT:
685  case IES_GE:
686  case IES_LSHIFT:
687  case IES_RSHIFT:
688  case IES_PLUS:
689  case IES_NOT:
690  case IES_MULTIPLY:
691  case IES_DIVIDE:
692  case IES_MOD:
693  case IES_LPAREN:
694  case IES_RPAREN:
695  case IES_LBRAC:
696  case IES_RBRAC:
697  case IES_INTEGER:
698  case IES_REGISTER:
699  case IES_INIT:
700  case IES_OFFSET:
701  State = IES_MINUS;
702  // push minus operator if it is not a negate operator
703  if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
704  CurrState == IES_INTEGER || CurrState == IES_RBRAC ||
705  CurrState == IES_OFFSET)
706  IC.pushOperator(IC_MINUS);
707  else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
708  // We have negate operator for Scale: it's illegal
709  ErrMsg = "Scale can't be negative";
710  return true;
711  } else
712  IC.pushOperator(IC_NEG);
713  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
714  // If we already have a BaseReg, then assume this is the IndexReg with
715  // no explicit scale.
716  if (!BaseReg) {
717  BaseReg = TmpReg;
718  } else {
719  if (IndexReg) {
720  ErrMsg = "BaseReg/IndexReg already set!";
721  return true;
722  }
723  IndexReg = TmpReg;
724  Scale = 0;
725  }
726  }
727  break;
728  }
729  PrevState = CurrState;
730  return false;
731  }
732  void onNot() {
733  IntelExprState CurrState = State;
734  switch (State) {
735  default:
736  State = IES_ERROR;
737  break;
738  case IES_OR:
739  case IES_XOR:
740  case IES_AND:
741  case IES_EQ:
742  case IES_NE:
743  case IES_LT:
744  case IES_LE:
745  case IES_GT:
746  case IES_GE:
747  case IES_LSHIFT:
748  case IES_RSHIFT:
749  case IES_PLUS:
750  case IES_MINUS:
751  case IES_NOT:
752  case IES_MULTIPLY:
753  case IES_DIVIDE:
754  case IES_MOD:
755  case IES_LPAREN:
756  case IES_LBRAC:
757  case IES_INIT:
758  State = IES_NOT;
759  IC.pushOperator(IC_NOT);
760  break;
761  }
762  PrevState = CurrState;
763  }
764  bool onRegister(unsigned Reg, StringRef &ErrMsg) {
765  IntelExprState CurrState = State;
766  switch (State) {
767  default:
768  State = IES_ERROR;
769  break;
770  case IES_PLUS:
771  case IES_LPAREN:
772  case IES_LBRAC:
773  State = IES_REGISTER;
774  TmpReg = Reg;
775  IC.pushOperand(IC_REGISTER);
776  break;
777  case IES_MULTIPLY:
778  // Index Register - Scale * Register
779  if (PrevState == IES_INTEGER) {
780  if (IndexReg) {
781  ErrMsg = "BaseReg/IndexReg already set!";
782  return true;
783  }
784  State = IES_REGISTER;
785  IndexReg = Reg;
786  // Get the scale and replace the 'Scale * Register' with '0'.
787  Scale = IC.popOperand();
788  if (checkScale(Scale, ErrMsg))
789  return true;
790  IC.pushOperand(IC_IMM);
791  IC.popOperator();
792  } else {
793  State = IES_ERROR;
794  }
795  break;
796  }
797  PrevState = CurrState;
798  return false;
799  }
800  bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
801  const InlineAsmIdentifierInfo &IDInfo,
802  const AsmTypeInfo &Type, bool ParsingMSInlineAsm,
803  StringRef &ErrMsg) {
804  // InlineAsm: Treat an enum value as an integer
805  if (ParsingMSInlineAsm)
807  return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
808  // Treat a symbolic constant like an integer
809  if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
810  return onInteger(CE->getValue(), ErrMsg);
811  PrevState = State;
812  switch (State) {
813  default:
814  State = IES_ERROR;
815  break;
816  case IES_CAST:
817  case IES_PLUS:
818  case IES_MINUS:
819  case IES_NOT:
820  case IES_INIT:
821  case IES_LBRAC:
822  case IES_LPAREN:
823  if (setSymRef(SymRef, SymRefName, ErrMsg))
824  return true;
825  MemExpr = true;
826  State = IES_INTEGER;
827  IC.pushOperand(IC_IMM);
828  if (ParsingMSInlineAsm)
829  Info = IDInfo;
830  setTypeInfo(Type);
831  break;
832  }
833  return false;
834  }
835  bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
836  IntelExprState CurrState = State;
837  switch (State) {
838  default:
839  State = IES_ERROR;
840  break;
841  case IES_PLUS:
842  case IES_MINUS:
843  case IES_NOT:
844  case IES_OR:
845  case IES_XOR:
846  case IES_AND:
847  case IES_EQ:
848  case IES_NE:
849  case IES_LT:
850  case IES_LE:
851  case IES_GT:
852  case IES_GE:
853  case IES_LSHIFT:
854  case IES_RSHIFT:
855  case IES_DIVIDE:
856  case IES_MOD:
857  case IES_MULTIPLY:
858  case IES_LPAREN:
859  case IES_INIT:
860  case IES_LBRAC:
861  State = IES_INTEGER;
862  if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
863  // Index Register - Register * Scale
864  if (IndexReg) {
865  ErrMsg = "BaseReg/IndexReg already set!";
866  return true;
867  }
868  IndexReg = TmpReg;
869  Scale = TmpInt;
870  if (checkScale(Scale, ErrMsg))
871  return true;
872  // Get the scale and replace the 'Register * Scale' with '0'.
873  IC.popOperator();
874  } else {
875  IC.pushOperand(IC_IMM, TmpInt);
876  }
877  break;
878  }
879  PrevState = CurrState;
880  return false;
881  }
882  void onStar() {
883  PrevState = State;
884  switch (State) {
885  default:
886  State = IES_ERROR;
887  break;
888  case IES_INTEGER:
889  case IES_REGISTER:
890  case IES_RPAREN:
891  State = IES_MULTIPLY;
892  IC.pushOperator(IC_MULTIPLY);
893  break;
894  }
895  }
896  void onDivide() {
897  PrevState = State;
898  switch (State) {
899  default:
900  State = IES_ERROR;
901  break;
902  case IES_INTEGER:
903  case IES_RPAREN:
904  State = IES_DIVIDE;
905  IC.pushOperator(IC_DIVIDE);
906  break;
907  }
908  }
909  void onMod() {
910  PrevState = State;
911  switch (State) {
912  default:
913  State = IES_ERROR;
914  break;
915  case IES_INTEGER:
916  case IES_RPAREN:
917  State = IES_MOD;
918  IC.pushOperator(IC_MOD);
919  break;
920  }
921  }
922  bool onLBrac() {
923  if (BracCount)
924  return true;
925  PrevState = State;
926  switch (State) {
927  default:
928  State = IES_ERROR;
929  break;
930  case IES_RBRAC:
931  case IES_INTEGER:
932  case IES_RPAREN:
933  State = IES_PLUS;
934  IC.pushOperator(IC_PLUS);
935  CurType.Length = 1;
936  CurType.Size = CurType.ElementSize;
937  break;
938  case IES_INIT:
939  case IES_CAST:
940  assert(!BracCount && "BracCount should be zero on parsing's start");
941  State = IES_LBRAC;
942  break;
943  }
944  MemExpr = true;
945  BracCount++;
946  return false;
947  }
948  bool onRBrac() {
949  IntelExprState CurrState = State;
950  switch (State) {
951  default:
952  State = IES_ERROR;
953  break;
954  case IES_INTEGER:
955  case IES_OFFSET:
956  case IES_REGISTER:
957  case IES_RPAREN:
958  if (BracCount-- != 1)
959  return true;
960  State = IES_RBRAC;
961  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
962  // If we already have a BaseReg, then assume this is the IndexReg with
963  // no explicit scale.
964  if (!BaseReg) {
965  BaseReg = TmpReg;
966  } else {
967  assert (!IndexReg && "BaseReg/IndexReg already set!");
968  IndexReg = TmpReg;
969  Scale = 0;
970  }
971  }
972  break;
973  }
974  PrevState = CurrState;
975  return false;
976  }
977  void onLParen() {
978  IntelExprState CurrState = State;
979  switch (State) {
980  default:
981  State = IES_ERROR;
982  break;
983  case IES_PLUS:
984  case IES_MINUS:
985  case IES_NOT:
986  case IES_OR:
987  case IES_XOR:
988  case IES_AND:
989  case IES_EQ:
990  case IES_NE:
991  case IES_LT:
992  case IES_LE:
993  case IES_GT:
994  case IES_GE:
995  case IES_LSHIFT:
996  case IES_RSHIFT:
997  case IES_MULTIPLY:
998  case IES_DIVIDE:
999  case IES_MOD:
1000  case IES_LPAREN:
1001  case IES_INIT:
1002  case IES_LBRAC:
1003  State = IES_LPAREN;
1004  IC.pushOperator(IC_LPAREN);
1005  break;
1006  }
1007  PrevState = CurrState;
1008  }
1009  void onRParen() {
1010  PrevState = State;
1011  switch (State) {
1012  default:
1013  State = IES_ERROR;
1014  break;
1015  case IES_INTEGER:
1016  case IES_OFFSET:
1017  case IES_REGISTER:
1018  case IES_RBRAC:
1019  case IES_RPAREN:
1020  State = IES_RPAREN;
1021  IC.pushOperator(IC_RPAREN);
1022  break;
1023  }
1024  }
1025  bool onOffset(const MCExpr *Val, SMLoc OffsetLoc, StringRef ID,
1026  const InlineAsmIdentifierInfo &IDInfo,
1027  bool ParsingMSInlineAsm, StringRef &ErrMsg) {
1028  PrevState = State;
1029  switch (State) {
1030  default:
1031  ErrMsg = "unexpected offset operator expression";
1032  return true;
1033  case IES_PLUS:
1034  case IES_INIT:
1035  case IES_LBRAC:
1036  if (setSymRef(Val, ID, ErrMsg))
1037  return true;
1038  OffsetOperator = true;
1039  OffsetOperatorLoc = OffsetLoc;
1040  State = IES_OFFSET;
1041  // As we cannot yet resolve the actual value (offset), we retain
1042  // the requested semantics by pushing a '0' to the operands stack
1043  IC.pushOperand(IC_IMM);
1044  if (ParsingMSInlineAsm) {
1045  Info = IDInfo;
1046  }
1047  break;
1048  }
1049  return false;
1050  }
1051  void onCast(AsmTypeInfo Info) {
1052  PrevState = State;
1053  switch (State) {
1054  default:
1055  State = IES_ERROR;
1056  break;
1057  case IES_LPAREN:
1058  setTypeInfo(Info);
1059  State = IES_CAST;
1060  break;
1061  }
1062  }
1063  void setTypeInfo(AsmTypeInfo Type) { CurType = Type; }
1064  };
1065 
1066  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
1067  bool MatchingInlineAsm = false) {
1068  MCAsmParser &Parser = getParser();
1069  if (MatchingInlineAsm) {
1070  if (!getLexer().isAtStartOfStatement())
1071  Parser.eatToEndOfStatement();
1072  return false;
1073  }
1074  return Parser.Error(L, Msg, Range);
1075  }
1076 
1077  bool MatchRegisterByName(unsigned &RegNo, StringRef RegName, SMLoc StartLoc,
1078  SMLoc EndLoc);
1079  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
1080  bool RestoreOnFailure);
1081 
1082  std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
1083  std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
1084  bool IsSIReg(unsigned Reg);
1085  unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1086  void
1087  AddDefaultSrcDestOperands(OperandVector &Operands,
1088  std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1089  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
1090  bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
1091  OperandVector &FinalOperands);
1092  bool ParseOperand(OperandVector &Operands);
1093  bool ParseATTOperand(OperandVector &Operands);
1094  bool ParseIntelOperand(OperandVector &Operands);
1095  bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
1097  bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
1098  unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
1099  unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
1100  unsigned IdentifyMasmOperator(StringRef Name);
1101  bool ParseMasmOperator(unsigned OpKind, int64_t &Val);
1102  bool ParseRoundingModeOp(SMLoc Start, OperandVector &Operands);
1103  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1104  bool &ParseError, SMLoc &End);
1105  bool ParseMasmNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1106  bool &ParseError, SMLoc &End);
1107  void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
1108  SMLoc End);
1109  bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
1110  bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
1112  bool IsUnevaluatedOperand, SMLoc &End,
1113  bool IsParsingOffsetOperator = false);
1114 
1115  bool ParseMemOperand(unsigned SegReg, const MCExpr *Disp, SMLoc StartLoc,
1116  SMLoc EndLoc, OperandVector &Operands);
1117 
1118  X86::CondCode ParseConditionCode(StringRef CCode);
1119 
1120  bool ParseIntelMemoryOperandSize(unsigned &Size);
1121  bool CreateMemForMSInlineAsm(unsigned SegReg, const MCExpr *Disp,
1122  unsigned BaseReg, unsigned IndexReg,
1123  unsigned Scale, SMLoc Start, SMLoc End,
1124  unsigned Size, StringRef Identifier,
1127 
1128  bool parseDirectiveArch();
1129  bool parseDirectiveNops(SMLoc L);
1130  bool parseDirectiveEven(SMLoc L);
1131  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
1132 
1133  /// CodeView FPO data directives.
1134  bool parseDirectiveFPOProc(SMLoc L);
1135  bool parseDirectiveFPOSetFrame(SMLoc L);
1136  bool parseDirectiveFPOPushReg(SMLoc L);
1137  bool parseDirectiveFPOStackAlloc(SMLoc L);
1138  bool parseDirectiveFPOStackAlign(SMLoc L);
1139  bool parseDirectiveFPOEndPrologue(SMLoc L);
1140  bool parseDirectiveFPOEndProc(SMLoc L);
1141 
1142  /// SEH directives.
1143  bool parseSEHRegisterNumber(unsigned RegClassID, unsigned &RegNo);
1144  bool parseDirectiveSEHPushReg(SMLoc);
1145  bool parseDirectiveSEHSetFrame(SMLoc);
1146  bool parseDirectiveSEHSaveReg(SMLoc);
1147  bool parseDirectiveSEHSaveXMM(SMLoc);
1148  bool parseDirectiveSEHPushFrame(SMLoc);
1149 
1150  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1151 
1152  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
1153  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
1154 
1155  // Load Value Injection (LVI) Mitigations for machine code
1156  void emitWarningForSpecialLVIInstruction(SMLoc Loc);
1157  void applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out);
1158  void applyLVILoadHardeningMitigation(MCInst &Inst, MCStreamer &Out);
1159 
1160  /// Wrapper around MCStreamer::emitInstruction(). Possibly adds
1161  /// instrumentation around Inst.
1162  void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
1163 
1164  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1167  bool MatchingInlineAsm) override;
1168 
1169  void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
1170  MCStreamer &Out, bool MatchingInlineAsm);
1171 
1172  bool ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures,
1173  bool MatchingInlineAsm);
1174 
1175  bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
1178  bool MatchingInlineAsm);
1179 
1180  bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
1183  bool MatchingInlineAsm);
1184 
1185  bool OmitRegisterFromClobberLists(unsigned RegNo) override;
1186 
1187  /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
1188  /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
1189  /// return false if no parsing errors occurred, true otherwise.
1190  bool HandleAVX512Operand(OperandVector &Operands);
1191 
1192  bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
1193 
1194  bool is64BitMode() const {
1195  // FIXME: Can tablegen auto-generate this?
1196  return getSTI().getFeatureBits()[X86::Mode64Bit];
1197  }
1198  bool is32BitMode() const {
1199  // FIXME: Can tablegen auto-generate this?
1200  return getSTI().getFeatureBits()[X86::Mode32Bit];
1201  }
1202  bool is16BitMode() const {
1203  // FIXME: Can tablegen auto-generate this?
1204  return getSTI().getFeatureBits()[X86::Mode16Bit];
1205  }
1206  void SwitchMode(unsigned mode) {
1207  MCSubtargetInfo &STI = copySTI();
1208  FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
1209  FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
1210  FeatureBitset FB = ComputeAvailableFeatures(
1211  STI.ToggleFeature(OldMode.flip(mode)));
1212  setAvailableFeatures(FB);
1213 
1214  assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
1215  }
1216 
1217  unsigned getPointerWidth() {
1218  if (is16BitMode()) return 16;
1219  if (is32BitMode()) return 32;
1220  if (is64BitMode()) return 64;
1221  llvm_unreachable("invalid mode");
1222  }
1223 
1224  bool isParsingIntelSyntax() {
1225  return getParser().getAssemblerDialect();
1226  }
1227 
1228  /// @name Auto-generated Matcher Functions
1229  /// {
1230 
1231 #define GET_ASSEMBLER_HEADER
1232 #include "X86GenAsmMatcher.inc"
1233 
1234  /// }
1235 
1236 public:
1237  enum X86MatchResultTy {
1238  Match_Unsupported = FIRST_TARGET_MATCH_RESULT_TY,
1239 #define GET_OPERAND_DIAGNOSTIC_TYPES
1240 #include "X86GenAsmMatcher.inc"
1241  };
1242 
1243  X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
1244  const MCInstrInfo &mii, const MCTargetOptions &Options)
1245  : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
1246  Code16GCC(false) {
1247 
1248  Parser.addAliasForDirective(".word", ".2byte");
1249 
1250  // Initialize the set of available features.
1251  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
1252  }
1253 
1254  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
1255  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1256  SMLoc &EndLoc) override;
1257 
1258  bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
1259 
1260  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1261  SMLoc NameLoc, OperandVector &Operands) override;
1262 
1263  bool ParseDirective(AsmToken DirectiveID) override;
1264 };
1265 } // end anonymous namespace
1266 
1267 /// @name Auto-generated Match Functions
1268 /// {
1269 
1270 static unsigned MatchRegisterName(StringRef Name);
1271 
1272 /// }
1273 
1274 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
1275  unsigned Scale, bool Is64BitMode,
1276  StringRef &ErrMsg) {
1277  // If we have both a base register and an index register make sure they are
1278  // both 64-bit or 32-bit registers.
1279  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1280 
1281  if (BaseReg != 0 &&
1282  !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
1283  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||
1284  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||
1285  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {
1286  ErrMsg = "invalid base+index expression";
1287  return true;
1288  }
1289 
1290  if (IndexReg != 0 &&
1291  !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1292  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1293  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1294  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1295  X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1296  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1297  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
1298  ErrMsg = "invalid base+index expression";
1299  return true;
1300  }
1301 
1302  if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1303  IndexReg == X86::EIP || IndexReg == X86::RIP ||
1304  IndexReg == X86::ESP || IndexReg == X86::RSP) {
1305  ErrMsg = "invalid base+index expression";
1306  return true;
1307  }
1308 
1309  // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1310  // and then only in non-64-bit modes.
1311  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1312  (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1313  BaseReg != X86::SI && BaseReg != X86::DI))) {
1314  ErrMsg = "invalid 16-bit base register";
1315  return true;
1316  }
1317 
1318  if (BaseReg == 0 &&
1319  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1320  ErrMsg = "16-bit memory operand may not include only index register";
1321  return true;
1322  }
1323 
1324  if (BaseReg != 0 && IndexReg != 0) {
1325  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1326  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1327  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1328  IndexReg == X86::EIZ)) {
1329  ErrMsg = "base register is 64-bit, but index register is not";
1330  return true;
1331  }
1332  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1333  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1334  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1335  IndexReg == X86::RIZ)) {
1336  ErrMsg = "base register is 32-bit, but index register is not";
1337  return true;
1338  }
1339  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
1340  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1341  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1342  ErrMsg = "base register is 16-bit, but index register is not";
1343  return true;
1344  }
1345  if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1346  (IndexReg != X86::SI && IndexReg != X86::DI)) {
1347  ErrMsg = "invalid 16-bit base/index register combination";
1348  return true;
1349  }
1350  }
1351  }
1352 
1353  // RIP/EIP-relative addressing is only supported in 64-bit mode.
1354  if (!Is64BitMode && BaseReg != 0 &&
1355  (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1356  ErrMsg = "IP-relative addressing requires 64-bit mode";
1357  return true;
1358  }
1359 
1360  return checkScale(Scale, ErrMsg);
1361 }
1362 
1363 bool X86AsmParser::MatchRegisterByName(unsigned &RegNo, StringRef RegName,
1364  SMLoc StartLoc, SMLoc EndLoc) {
1365  // If we encounter a %, ignore it. This code handles registers with and
1366  // without the prefix, unprefixed registers can occur in cfi directives.
1367  RegName.consume_front("%");
1368 
1369  RegNo = MatchRegisterName(RegName);
1370 
1371  // If the match failed, try the register name as lowercase.
1372  if (RegNo == 0)
1373  RegNo = MatchRegisterName(RegName.lower());
1374 
1375  // The "flags" and "mxcsr" registers cannot be referenced directly.
1376  // Treat it as an identifier instead.
1377  if (isParsingMSInlineAsm() && isParsingIntelSyntax() &&
1378  (RegNo == X86::EFLAGS || RegNo == X86::MXCSR))
1379  RegNo = 0;
1380 
1381  if (!is64BitMode()) {
1382  // FIXME: This should be done using Requires<Not64BitMode> and
1383  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1384  // checked.
1385  if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1386  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1388  X86II::isX86_64ExtendedReg(RegNo)) {
1389  return Error(StartLoc,
1390  "register %" + RegName + " is only available in 64-bit mode",
1391  SMRange(StartLoc, EndLoc));
1392  }
1393  }
1394 
1395  // If this is "db[0-15]", match it as an alias
1396  // for dr[0-15].
1397  if (RegNo == 0 && RegName.startswith("db")) {
1398  if (RegName.size() == 3) {
1399  switch (RegName[2]) {
1400  case '0':
1401  RegNo = X86::DR0;
1402  break;
1403  case '1':
1404  RegNo = X86::DR1;
1405  break;
1406  case '2':
1407  RegNo = X86::DR2;
1408  break;
1409  case '3':
1410  RegNo = X86::DR3;
1411  break;
1412  case '4':
1413  RegNo = X86::DR4;
1414  break;
1415  case '5':
1416  RegNo = X86::DR5;
1417  break;
1418  case '6':
1419  RegNo = X86::DR6;
1420  break;
1421  case '7':
1422  RegNo = X86::DR7;
1423  break;
1424  case '8':
1425  RegNo = X86::DR8;
1426  break;
1427  case '9':
1428  RegNo = X86::DR9;
1429  break;
1430  }
1431  } else if (RegName.size() == 4 && RegName[2] == '1') {
1432  switch (RegName[3]) {
1433  case '0':
1434  RegNo = X86::DR10;
1435  break;
1436  case '1':
1437  RegNo = X86::DR11;
1438  break;
1439  case '2':
1440  RegNo = X86::DR12;
1441  break;
1442  case '3':
1443  RegNo = X86::DR13;
1444  break;
1445  case '4':
1446  RegNo = X86::DR14;
1447  break;
1448  case '5':
1449  RegNo = X86::DR15;
1450  break;
1451  }
1452  }
1453  }
1454 
1455  if (RegNo == 0) {
1456  if (isParsingIntelSyntax())
1457  return true;
1458  return Error(StartLoc, "invalid register name", SMRange(StartLoc, EndLoc));
1459  }
1460  return false;
1461 }
1462 
1463 bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1464  SMLoc &EndLoc, bool RestoreOnFailure) {
1465  MCAsmParser &Parser = getParser();
1466  MCAsmLexer &Lexer = getLexer();
1467  RegNo = 0;
1468 
1469  SmallVector<AsmToken, 5> Tokens;
1470  auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() {
1471  if (RestoreOnFailure) {
1472  while (!Tokens.empty()) {
1473  Lexer.UnLex(Tokens.pop_back_val());
1474  }
1475  }
1476  };
1477 
1478  const AsmToken &PercentTok = Parser.getTok();
1479  StartLoc = PercentTok.getLoc();
1480 
1481  // If we encounter a %, ignore it. This code handles registers with and
1482  // without the prefix, unprefixed registers can occur in cfi directives.
1483  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent)) {
1484  Tokens.push_back(PercentTok);
1485  Parser.Lex(); // Eat percent token.
1486  }
1487 
1488  const AsmToken &Tok = Parser.getTok();
1489  EndLoc = Tok.getEndLoc();
1490 
1491  if (Tok.isNot(AsmToken::Identifier)) {
1492  OnFailure();
1493  if (isParsingIntelSyntax()) return true;
1494  return Error(StartLoc, "invalid register name",
1495  SMRange(StartLoc, EndLoc));
1496  }
1497 
1498  if (MatchRegisterByName(RegNo, Tok.getString(), StartLoc, EndLoc)) {
1499  OnFailure();
1500  return true;
1501  }
1502 
1503  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1504  if (RegNo == X86::ST0) {
1505  Tokens.push_back(Tok);
1506  Parser.Lex(); // Eat 'st'
1507 
1508  // Check to see if we have '(4)' after %st.
1509  if (Lexer.isNot(AsmToken::LParen))
1510  return false;
1511  // Lex the paren.
1512  Tokens.push_back(Parser.getTok());
1513  Parser.Lex();
1514 
1515  const AsmToken &IntTok = Parser.getTok();
1516  if (IntTok.isNot(AsmToken::Integer)) {
1517  OnFailure();
1518  return Error(IntTok.getLoc(), "expected stack index");
1519  }
1520  switch (IntTok.getIntVal()) {
1521  case 0: RegNo = X86::ST0; break;
1522  case 1: RegNo = X86::ST1; break;
1523  case 2: RegNo = X86::ST2; break;
1524  case 3: RegNo = X86::ST3; break;
1525  case 4: RegNo = X86::ST4; break;
1526  case 5: RegNo = X86::ST5; break;
1527  case 6: RegNo = X86::ST6; break;
1528  case 7: RegNo = X86::ST7; break;
1529  default:
1530  OnFailure();
1531  return Error(IntTok.getLoc(), "invalid stack index");
1532  }
1533 
1534  // Lex IntTok
1535  Tokens.push_back(IntTok);
1536  Parser.Lex();
1537  if (Lexer.isNot(AsmToken::RParen)) {
1538  OnFailure();
1539  return Error(Parser.getTok().getLoc(), "expected ')'");
1540  }
1541 
1542  EndLoc = Parser.getTok().getEndLoc();
1543  Parser.Lex(); // Eat ')'
1544  return false;
1545  }
1546 
1547  EndLoc = Parser.getTok().getEndLoc();
1548 
1549  if (RegNo == 0) {
1550  OnFailure();
1551  if (isParsingIntelSyntax()) return true;
1552  return Error(StartLoc, "invalid register name",
1553  SMRange(StartLoc, EndLoc));
1554  }
1555 
1556  Parser.Lex(); // Eat identifier token.
1557  return false;
1558 }
1559 
1560 bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1561  SMLoc &EndLoc) {
1562  return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1563 }
1564 
1565 OperandMatchResultTy X86AsmParser::tryParseRegister(unsigned &RegNo,
1566  SMLoc &StartLoc,
1567  SMLoc &EndLoc) {
1568  bool Result =
1569  ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1570  bool PendingErrors = getParser().hasPendingError();
1571  getParser().clearPendingErrors();
1572  if (PendingErrors)
1573  return MatchOperand_ParseFail;
1574  if (Result)
1575  return MatchOperand_NoMatch;
1576  return MatchOperand_Success;
1577 }
1578 
1579 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1580  bool Parse32 = is32BitMode() || Code16GCC;
1581  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1582  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1583  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1584  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1585  Loc, Loc, 0);
1586 }
1587 
1588 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1589  bool Parse32 = is32BitMode() || Code16GCC;
1590  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1591  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1592  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1593  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1594  Loc, Loc, 0);
1595 }
1596 
1597 bool X86AsmParser::IsSIReg(unsigned Reg) {
1598  switch (Reg) {
1599  default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1600  case X86::RSI:
1601  case X86::ESI:
1602  case X86::SI:
1603  return true;
1604  case X86::RDI:
1605  case X86::EDI:
1606  case X86::DI:
1607  return false;
1608  }
1609 }
1610 
1611 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1612  bool IsSIReg) {
1613  switch (RegClassID) {
1614  default: llvm_unreachable("Unexpected register class");
1615  case X86::GR64RegClassID:
1616  return IsSIReg ? X86::RSI : X86::RDI;
1617  case X86::GR32RegClassID:
1618  return IsSIReg ? X86::ESI : X86::EDI;
1619  case X86::GR16RegClassID:
1620  return IsSIReg ? X86::SI : X86::DI;
1621  }
1622 }
1623 
1624 void X86AsmParser::AddDefaultSrcDestOperands(
1625  OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1626  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1627  if (isParsingIntelSyntax()) {
1628  Operands.push_back(std::move(Dst));
1629  Operands.push_back(std::move(Src));
1630  }
1631  else {
1632  Operands.push_back(std::move(Src));
1633  Operands.push_back(std::move(Dst));
1634  }
1635 }
1636 
1637 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1638  OperandVector &FinalOperands) {
1639 
1640  if (OrigOperands.size() > 1) {
1641  // Check if sizes match, OrigOperands also contains the instruction name
1642  assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1643  "Operand size mismatch");
1644 
1646  // Verify types match
1647  int RegClassID = -1;
1648  for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1649  X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1650  X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1651 
1652  if (FinalOp.isReg() &&
1653  (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1654  // Return false and let a normal complaint about bogus operands happen
1655  return false;
1656 
1657  if (FinalOp.isMem()) {
1658 
1659  if (!OrigOp.isMem())
1660  // Return false and let a normal complaint about bogus operands happen
1661  return false;
1662 
1663  unsigned OrigReg = OrigOp.Mem.BaseReg;
1664  unsigned FinalReg = FinalOp.Mem.BaseReg;
1665 
1666  // If we've already encounterd a register class, make sure all register
1667  // bases are of the same register class
1668  if (RegClassID != -1 &&
1669  !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1670  return Error(OrigOp.getStartLoc(),
1671  "mismatching source and destination index registers");
1672  }
1673 
1674  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1675  RegClassID = X86::GR64RegClassID;
1676  else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1677  RegClassID = X86::GR32RegClassID;
1678  else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1679  RegClassID = X86::GR16RegClassID;
1680  else
1681  // Unexpected register class type
1682  // Return false and let a normal complaint about bogus operands happen
1683  return false;
1684 
1685  bool IsSI = IsSIReg(FinalReg);
1686  FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1687 
1688  if (FinalReg != OrigReg) {
1689  std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1690  Warnings.push_back(std::make_pair(
1691  OrigOp.getStartLoc(),
1692  "memory operand is only for determining the size, " + RegName +
1693  " will be used for the location"));
1694  }
1695 
1696  FinalOp.Mem.Size = OrigOp.Mem.Size;
1697  FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1698  FinalOp.Mem.BaseReg = FinalReg;
1699  }
1700  }
1701 
1702  // Produce warnings only if all the operands passed the adjustment - prevent
1703  // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1704  for (auto &WarningMsg : Warnings) {
1705  Warning(WarningMsg.first, WarningMsg.second);
1706  }
1707 
1708  // Remove old operands
1709  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1710  OrigOperands.pop_back();
1711  }
1712  // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1713  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1714  OrigOperands.push_back(std::move(FinalOperands[i]));
1715 
1716  return false;
1717 }
1718 
1719 bool X86AsmParser::ParseOperand(OperandVector &Operands) {
1720  if (isParsingIntelSyntax())
1721  return ParseIntelOperand(Operands);
1722 
1723  return ParseATTOperand(Operands);
1724 }
1725 
1726 bool X86AsmParser::CreateMemForMSInlineAsm(
1727  unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1728  unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
1730  // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1731  // some other label reference.
1733  // Insert an explicit size if the user didn't have one.
1734  if (!Size) {
1735  Size = getPointerWidth();
1736  InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1737  /*Len=*/0, Size);
1738  }
1739  // Create an absolute memory reference in order to match against
1740  // instructions taking a PC relative operand.
1741  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
1742  End, Size, Identifier,
1743  Info.Label.Decl));
1744  return false;
1745  }
1746  // We either have a direct symbol reference, or an offset from a symbol. The
1747  // parser always puts the symbol on the LHS, so look there for size
1748  // calculation purposes.
1749  unsigned FrontendSize = 0;
1750  void *Decl = nullptr;
1751  bool IsGlobalLV = false;
1752  if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
1753  // Size is in terms of bits in this context.
1754  FrontendSize = Info.Var.Type * 8;
1755  Decl = Info.Var.Decl;
1756  IsGlobalLV = Info.Var.IsGlobalLV;
1757  }
1758  // It is widely common for MS InlineAsm to use a global variable and one/two
1759  // registers in a mmory expression, and though unaccessible via rip/eip.
1760  if (IsGlobalLV && (BaseReg || IndexReg)) {
1761  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
1762  End, Size, Identifier, Decl,
1763  FrontendSize));
1764  return false;
1765  }
1766  // Otherwise, we set the base register to a non-zero value
1767  // if we don't know the actual value at this time. This is necessary to
1768  // get the matching correct in some cases.
1769  BaseReg = BaseReg ? BaseReg : 1;
1770  Operands.push_back(X86Operand::CreateMem(
1771  getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
1772  Size,
1773  /*DefaultBaseReg=*/X86::RIP, Identifier, Decl, FrontendSize));
1774  return false;
1775 }
1776 
1777 // Some binary bitwise operators have a named synonymous
1778 // Query a candidate string for being such a named operator
1779 // and if so - invoke the appropriate handler
1780 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
1781  IntelExprStateMachine &SM,
1782  bool &ParseError, SMLoc &End) {
1783  // A named operator should be either lower or upper case, but not a mix...
1784  // except in MASM, which uses full case-insensitivity.
1785  if (Name.compare(Name.lower()) && Name.compare(Name.upper()) &&
1786  !getParser().isParsingMasm())
1787  return false;
1788  if (Name.equals_insensitive("not")) {
1789  SM.onNot();
1790  } else if (Name.equals_insensitive("or")) {
1791  SM.onOr();
1792  } else if (Name.equals_insensitive("shl")) {
1793  SM.onLShift();
1794  } else if (Name.equals_insensitive("shr")) {
1795  SM.onRShift();
1796  } else if (Name.equals_insensitive("xor")) {
1797  SM.onXor();
1798  } else if (Name.equals_insensitive("and")) {
1799  SM.onAnd();
1800  } else if (Name.equals_insensitive("mod")) {
1801  SM.onMod();
1802  } else if (Name.equals_insensitive("offset")) {
1803  SMLoc OffsetLoc = getTok().getLoc();
1804  const MCExpr *Val = nullptr;
1805  StringRef ID;
1807  ParseError = ParseIntelOffsetOperator(Val, ID, Info, End);
1808  if (ParseError)
1809  return true;
1810  StringRef ErrMsg;
1811  ParseError =
1812  SM.onOffset(Val, OffsetLoc, ID, Info, isParsingMSInlineAsm(), ErrMsg);
1813  if (ParseError)
1814  return Error(SMLoc::getFromPointer(Name.data()), ErrMsg);
1815  } else {
1816  return false;
1817  }
1818  if (!Name.equals_insensitive("offset"))
1819  End = consumeToken();
1820  return true;
1821 }
1822 bool X86AsmParser::ParseMasmNamedOperator(StringRef Name,
1823  IntelExprStateMachine &SM,
1824  bool &ParseError, SMLoc &End) {
1825  if (Name.equals_insensitive("eq")) {
1826  SM.onEq();
1827  } else if (Name.equals_insensitive("ne")) {
1828  SM.onNE();
1829  } else if (Name.equals_insensitive("lt")) {
1830  SM.onLT();
1831  } else if (Name.equals_insensitive("le")) {
1832  SM.onLE();
1833  } else if (Name.equals_insensitive("gt")) {
1834  SM.onGT();
1835  } else if (Name.equals_insensitive("ge")) {
1836  SM.onGE();
1837  } else {
1838  return false;
1839  }
1840  End = consumeToken();
1841  return true;
1842 }
1843 
1844 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1845  MCAsmParser &Parser = getParser();
1846  StringRef ErrMsg;
1847 
1849  bool Done = false;
1850  while (!Done) {
1851  // Get a fresh reference on each loop iteration in case the previous
1852  // iteration moved the token storage during UnLex().
1853  const AsmToken &Tok = Parser.getTok();
1854 
1855  bool UpdateLocLex = true;
1856  AsmToken::TokenKind TK = getLexer().getKind();
1857 
1858  switch (TK) {
1859  default:
1860  if ((Done = SM.isValidEndState()))
1861  break;
1862  return Error(Tok.getLoc(), "unknown token in expression");
1863  case AsmToken::Error:
1864  return Error(getLexer().getErrLoc(), getLexer().getErr());
1865  break;
1867  Done = true;
1868  break;
1869  case AsmToken::Real:
1870  // DotOperator: [ebx].0
1871  UpdateLocLex = false;
1872  if (ParseIntelDotOperator(SM, End))
1873  return true;
1874  break;
1875  case AsmToken::Dot:
1876  if (!Parser.isParsingMasm()) {
1877  if ((Done = SM.isValidEndState()))
1878  break;
1879  return Error(Tok.getLoc(), "unknown token in expression");
1880  }
1881  // MASM allows spaces around the dot operator (e.g., "var . x")
1882  Lex();
1883  UpdateLocLex = false;
1884  if (ParseIntelDotOperator(SM, End))
1885  return true;
1886  break;
1887  case AsmToken::Dollar:
1888  if (!Parser.isParsingMasm()) {
1889  if ((Done = SM.isValidEndState()))
1890  break;
1891  return Error(Tok.getLoc(), "unknown token in expression");
1892  }
1894  case AsmToken::String: {
1895  if (Parser.isParsingMasm()) {
1896  // MASM parsers handle strings in expressions as constants.
1897  SMLoc ValueLoc = Tok.getLoc();
1898  int64_t Res;
1899  const MCExpr *Val;
1900  if (Parser.parsePrimaryExpr(Val, End, nullptr))
1901  return true;
1902  UpdateLocLex = false;
1903  if (!Val->evaluateAsAbsolute(Res, getStreamer().getAssemblerPtr()))
1904  return Error(ValueLoc, "expected absolute value");
1905  if (SM.onInteger(Res, ErrMsg))
1906  return Error(ValueLoc, ErrMsg);
1907  break;
1908  }
1910  }
1911  case AsmToken::At:
1912  case AsmToken::Identifier: {
1913  SMLoc IdentLoc = Tok.getLoc();
1914  StringRef Identifier = Tok.getString();
1915  UpdateLocLex = false;
1916  if (Parser.isParsingMasm()) {
1917  size_t DotOffset = Identifier.find_first_of('.');
1918  if (DotOffset != StringRef::npos) {
1919  consumeToken();
1920  StringRef LHS = Identifier.slice(0, DotOffset);
1921  StringRef Dot = Identifier.slice(DotOffset, DotOffset + 1);
1922  StringRef RHS = Identifier.slice(DotOffset + 1, StringRef::npos);
1923  if (!RHS.empty()) {
1924  getLexer().UnLex(AsmToken(AsmToken::Identifier, RHS));
1925  }
1926  getLexer().UnLex(AsmToken(AsmToken::Dot, Dot));
1927  if (!LHS.empty()) {
1928  getLexer().UnLex(AsmToken(AsmToken::Identifier, LHS));
1929  }
1930  break;
1931  }
1932  }
1933  // (MASM only) <TYPE> PTR operator
1934  if (Parser.isParsingMasm()) {
1935  const AsmToken &NextTok = getLexer().peekTok();
1936  if (NextTok.is(AsmToken::Identifier) &&
1937  NextTok.getIdentifier().equals_insensitive("ptr")) {
1938  AsmTypeInfo Info;
1939  if (Parser.lookUpType(Identifier, Info))
1940  return Error(Tok.getLoc(), "unknown type");
1941  SM.onCast(Info);
1942  // Eat type and PTR.
1943  consumeToken();
1944  End = consumeToken();
1945  break;
1946  }
1947  }
1948  // Register, or (MASM only) <register>.<field>
1949  unsigned Reg;
1950  if (Tok.is(AsmToken::Identifier)) {
1951  if (!ParseRegister(Reg, IdentLoc, End, /*RestoreOnFailure=*/true)) {
1952  if (SM.onRegister(Reg, ErrMsg))
1953  return Error(IdentLoc, ErrMsg);
1954  break;
1955  }
1956  if (Parser.isParsingMasm()) {
1957  const std::pair<StringRef, StringRef> IDField =
1958  Tok.getString().split('.');
1959  const StringRef ID = IDField.first, Field = IDField.second;
1960  SMLoc IDEndLoc = SMLoc::getFromPointer(ID.data() + ID.size());
1961  if (!Field.empty() &&
1962  !MatchRegisterByName(Reg, ID, IdentLoc, IDEndLoc)) {
1963  if (SM.onRegister(Reg, ErrMsg))
1964  return Error(IdentLoc, ErrMsg);
1965 
1967  SMLoc FieldStartLoc = SMLoc::getFromPointer(Field.data());
1968  if (Parser.lookUpField(Field, Info))
1969  return Error(FieldStartLoc, "unknown offset");
1970  else if (SM.onPlus(ErrMsg))
1971  return Error(getTok().getLoc(), ErrMsg);
1972  else if (SM.onInteger(Info.Offset, ErrMsg))
1973  return Error(IdentLoc, ErrMsg);
1974  SM.setTypeInfo(Info.Type);
1975 
1976  End = consumeToken();
1977  break;
1978  }
1979  }
1980  }
1981  // Operator synonymous ("not", "or" etc.)
1982  bool ParseError = false;
1983  if (ParseIntelNamedOperator(Identifier, SM, ParseError, End)) {
1984  if (ParseError)
1985  return true;
1986  break;
1987  }
1988  if (Parser.isParsingMasm() &&
1989  ParseMasmNamedOperator(Identifier, SM, ParseError, End)) {
1990  if (ParseError)
1991  return true;
1992  break;
1993  }
1994  // Symbol reference, when parsing assembly content
1996  AsmFieldInfo FieldInfo;
1997  const MCExpr *Val;
1998  if (isParsingMSInlineAsm() || Parser.isParsingMasm()) {
1999  // MS Dot Operator expression
2000  if (Identifier.count('.') &&
2001  (PrevTK == AsmToken::RBrac || PrevTK == AsmToken::RParen)) {
2002  if (ParseIntelDotOperator(SM, End))
2003  return true;
2004  break;
2005  }
2006  }
2007  if (isParsingMSInlineAsm()) {
2008  // MS InlineAsm operators (TYPE/LENGTH/SIZE)
2009  if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
2010  if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
2011  if (SM.onInteger(Val, ErrMsg))
2012  return Error(IdentLoc, ErrMsg);
2013  } else {
2014  return true;
2015  }
2016  break;
2017  }
2018  // MS InlineAsm identifier
2019  // Call parseIdentifier() to combine @ with the identifier behind it.
2020  if (TK == AsmToken::At && Parser.parseIdentifier(Identifier))
2021  return Error(IdentLoc, "expected identifier");
2022  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
2023  return true;
2024  else if (SM.onIdentifierExpr(Val, Identifier, Info, FieldInfo.Type,
2025  true, ErrMsg))
2026  return Error(IdentLoc, ErrMsg);
2027  break;
2028  }
2029  if (Parser.isParsingMasm()) {
2030  if (unsigned OpKind = IdentifyMasmOperator(Identifier)) {
2031  int64_t Val;
2032  if (ParseMasmOperator(OpKind, Val))
2033  return true;
2034  if (SM.onInteger(Val, ErrMsg))
2035  return Error(IdentLoc, ErrMsg);
2036  break;
2037  }
2038  if (!getParser().lookUpType(Identifier, FieldInfo.Type)) {
2039  // Field offset immediate; <TYPE>.<field specification>
2040  Lex(); // eat type
2041  bool EndDot = parseOptionalToken(AsmToken::Dot);
2042  while (EndDot || (getTok().is(AsmToken::Identifier) &&
2043  getTok().getString().startswith("."))) {
2044  getParser().parseIdentifier(Identifier);
2045  if (!EndDot)
2046  Identifier.consume_front(".");
2047  EndDot = Identifier.consume_back(".");
2048  if (getParser().lookUpField(FieldInfo.Type.Name, Identifier,
2049  FieldInfo)) {
2050  SMLoc IDEnd =
2051  SMLoc::getFromPointer(Identifier.data() + Identifier.size());
2052  return Error(IdentLoc, "Unable to lookup field reference!",
2053  SMRange(IdentLoc, IDEnd));
2054  }
2055  if (!EndDot)
2056  EndDot = parseOptionalToken(AsmToken::Dot);
2057  }
2058  if (SM.onInteger(FieldInfo.Offset, ErrMsg))
2059  return Error(IdentLoc, ErrMsg);
2060  break;
2061  }
2062  }
2063  if (getParser().parsePrimaryExpr(Val, End, &FieldInfo.Type)) {
2064  return Error(Tok.getLoc(), "Unexpected identifier!");
2065  } else if (SM.onIdentifierExpr(Val, Identifier, Info, FieldInfo.Type,
2066  false, ErrMsg)) {
2067  return Error(IdentLoc, ErrMsg);
2068  }
2069  break;
2070  }
2071  case AsmToken::Integer: {
2072  // Look for 'b' or 'f' following an Integer as a directional label
2073  SMLoc Loc = getTok().getLoc();
2074  int64_t IntVal = getTok().getIntVal();
2075  End = consumeToken();
2076  UpdateLocLex = false;
2077  if (getLexer().getKind() == AsmToken::Identifier) {
2078  StringRef IDVal = getTok().getString();
2079  if (IDVal == "f" || IDVal == "b") {
2080  MCSymbol *Sym =
2081  getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
2083  const MCExpr *Val =
2084  MCSymbolRefExpr::create(Sym, Variant, getContext());
2085  if (IDVal == "b" && Sym->isUndefined())
2086  return Error(Loc, "invalid reference to undefined symbol");
2087  StringRef Identifier = Sym->getName();
2089  AsmTypeInfo Type;
2090  if (SM.onIdentifierExpr(Val, Identifier, Info, Type,
2091  isParsingMSInlineAsm(), ErrMsg))
2092  return Error(Loc, ErrMsg);
2093  End = consumeToken();
2094  } else {
2095  if (SM.onInteger(IntVal, ErrMsg))
2096  return Error(Loc, ErrMsg);
2097  }
2098  } else {
2099  if (SM.onInteger(IntVal, ErrMsg))
2100  return Error(Loc, ErrMsg);
2101  }
2102  break;
2103  }
2104  case AsmToken::Plus:
2105  if (SM.onPlus(ErrMsg))
2106  return Error(getTok().getLoc(), ErrMsg);
2107  break;
2108  case AsmToken::Minus:
2109  if (SM.onMinus(ErrMsg))
2110  return Error(getTok().getLoc(), ErrMsg);
2111  break;
2112  case AsmToken::Tilde: SM.onNot(); break;
2113  case AsmToken::Star: SM.onStar(); break;
2114  case AsmToken::Slash: SM.onDivide(); break;
2115  case AsmToken::Percent: SM.onMod(); break;
2116  case AsmToken::Pipe: SM.onOr(); break;
2117  case AsmToken::Caret: SM.onXor(); break;
2118  case AsmToken::Amp: SM.onAnd(); break;
2119  case AsmToken::LessLess:
2120  SM.onLShift(); break;
2122  SM.onRShift(); break;
2123  case AsmToken::LBrac:
2124  if (SM.onLBrac())
2125  return Error(Tok.getLoc(), "unexpected bracket encountered");
2126  break;
2127  case AsmToken::RBrac:
2128  if (SM.onRBrac())
2129  return Error(Tok.getLoc(), "unexpected bracket encountered");
2130  break;
2131  case AsmToken::LParen: SM.onLParen(); break;
2132  case AsmToken::RParen: SM.onRParen(); break;
2133  }
2134  if (SM.hadError())
2135  return Error(Tok.getLoc(), "unknown token in expression");
2136 
2137  if (!Done && UpdateLocLex)
2138  End = consumeToken();
2139 
2140  PrevTK = TK;
2141  }
2142  return false;
2143 }
2144 
2145 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
2146  SMLoc Start, SMLoc End) {
2147  SMLoc Loc = Start;
2148  unsigned ExprLen = End.getPointer() - Start.getPointer();
2149  // Skip everything before a symbol displacement (if we have one)
2150  if (SM.getSym() && !SM.isOffsetOperator()) {
2151  StringRef SymName = SM.getSymName();
2152  if (unsigned Len = SymName.data() - Start.getPointer())
2153  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
2154  Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
2155  ExprLen = End.getPointer() - (SymName.data() + SymName.size());
2156  // If we have only a symbol than there's no need for complex rewrite,
2157  // simply skip everything after it
2158  if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
2159  if (ExprLen)
2160  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
2161  return;
2162  }
2163  }
2164  // Build an Intel Expression rewrite
2165  StringRef BaseRegStr;
2166  StringRef IndexRegStr;
2167  StringRef OffsetNameStr;
2168  if (SM.getBaseReg())
2169  BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
2170  if (SM.getIndexReg())
2171  IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
2172  if (SM.isOffsetOperator())
2173  OffsetNameStr = SM.getSymName();
2174  // Emit it
2175  IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), OffsetNameStr,
2176  SM.getImm(), SM.isMemExpr());
2177  InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
2178 }
2179 
2180 // Inline assembly may use variable names with namespace alias qualifiers.
2181 bool X86AsmParser::ParseIntelInlineAsmIdentifier(
2182  const MCExpr *&Val, StringRef &Identifier, InlineAsmIdentifierInfo &Info,
2183  bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator) {
2184  MCAsmParser &Parser = getParser();
2185  assert(isParsingMSInlineAsm() && "Expected to be parsing inline assembly.");
2186  Val = nullptr;
2187 
2188  StringRef LineBuf(Identifier.data());
2189  SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
2190 
2191  const AsmToken &Tok = Parser.getTok();
2192  SMLoc Loc = Tok.getLoc();
2193 
2194  // Advance the token stream until the end of the current token is
2195  // after the end of what the frontend claimed.
2196  const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
2197  do {
2198  End = Tok.getEndLoc();
2199  getLexer().Lex();
2200  } while (End.getPointer() < EndPtr);
2201  Identifier = LineBuf;
2202 
2203  // The frontend should end parsing on an assembler token boundary, unless it
2204  // failed parsing.
2205  assert((End.getPointer() == EndPtr ||
2207  "frontend claimed part of a token?");
2208 
2209  // If the identifier lookup was unsuccessful, assume that we are dealing with
2210  // a label.
2212  StringRef InternalName =
2213  SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
2214  Loc, false);
2215  assert(InternalName.size() && "We should have an internal name here.");
2216  // Push a rewrite for replacing the identifier name with the internal name,
2217  // unless we are parsing the operand of an offset operator
2218  if (!IsParsingOffsetOperator)
2219  InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
2220  InternalName);
2221  else
2222  Identifier = InternalName;
2223  } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
2224  return false;
2225  // Create the symbol reference.
2226  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
2228  Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
2229  return false;
2230 }
2231 
2232 //ParseRoundingModeOp - Parse AVX-512 rounding mode operand
2233 bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
2234  MCAsmParser &Parser = getParser();
2235  const AsmToken &Tok = Parser.getTok();
2236  // Eat "{" and mark the current place.
2237  const SMLoc consumedToken = consumeToken();
2238  if (Tok.isNot(AsmToken::Identifier))
2239  return Error(Tok.getLoc(), "Expected an identifier after {");
2240  if (Tok.getIdentifier().startswith("r")){
2241  int rndMode = StringSwitch<int>(Tok.getIdentifier())
2246  .Default(-1);
2247  if (-1 == rndMode)
2248  return Error(Tok.getLoc(), "Invalid rounding mode.");
2249  Parser.Lex(); // Eat "r*" of r*-sae
2250  if (!getLexer().is(AsmToken::Minus))
2251  return Error(Tok.getLoc(), "Expected - at this point");
2252  Parser.Lex(); // Eat "-"
2253  Parser.Lex(); // Eat the sae
2254  if (!getLexer().is(AsmToken::RCurly))
2255  return Error(Tok.getLoc(), "Expected } at this point");
2256  SMLoc End = Tok.getEndLoc();
2257  Parser.Lex(); // Eat "}"
2258  const MCExpr *RndModeOp =
2259  MCConstantExpr::create(rndMode, Parser.getContext());
2260  Operands.push_back(X86Operand::CreateImm(RndModeOp, Start, End));
2261  return false;
2262  }
2263  if(Tok.getIdentifier().equals("sae")){
2264  Parser.Lex(); // Eat the sae
2265  if (!getLexer().is(AsmToken::RCurly))
2266  return Error(Tok.getLoc(), "Expected } at this point");
2267  Parser.Lex(); // Eat "}"
2268  Operands.push_back(X86Operand::CreateToken("{sae}", consumedToken));
2269  return false;
2270  }
2271  return Error(Tok.getLoc(), "unknown token in expression");
2272 }
2273 
2274 /// Parse the '.' operator.
2275 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
2276  SMLoc &End) {
2277  const AsmToken &Tok = getTok();
2279 
2280  // Drop the optional '.'.
2281  StringRef DotDispStr = Tok.getString();
2282  if (DotDispStr.startswith("."))
2283  DotDispStr = DotDispStr.drop_front(1);
2284  StringRef TrailingDot;
2285 
2286  // .Imm gets lexed as a real.
2287  if (Tok.is(AsmToken::Real)) {
2288  APInt DotDisp;
2289  DotDispStr.getAsInteger(10, DotDisp);
2290  Info.Offset = DotDisp.getZExtValue();
2291  } else if ((isParsingMSInlineAsm() || getParser().isParsingMasm()) &&
2292  Tok.is(AsmToken::Identifier)) {
2293  if (DotDispStr.endswith(".")) {
2294  TrailingDot = DotDispStr.substr(DotDispStr.size() - 1);
2295  DotDispStr = DotDispStr.drop_back(1);
2296  }
2297  const std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
2298  const StringRef Base = BaseMember.first, Member = BaseMember.second;
2299  if (getParser().lookUpField(SM.getType(), DotDispStr, Info) &&
2300  getParser().lookUpField(SM.getSymName(), DotDispStr, Info) &&
2301  getParser().lookUpField(DotDispStr, Info) &&
2302  (!SemaCallback ||
2303  SemaCallback->LookupInlineAsmField(Base, Member, Info.Offset)))
2304  return Error(Tok.getLoc(), "Unable to lookup field reference!");
2305  } else {
2306  return Error(Tok.getLoc(), "Unexpected token type!");
2307  }
2308 
2309  // Eat the DotExpression and update End
2310  End = SMLoc::getFromPointer(DotDispStr.data());
2311  const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
2312  while (Tok.getLoc().getPointer() < DotExprEndLoc)
2313  Lex();
2314  if (!TrailingDot.empty())
2315  getLexer().UnLex(AsmToken(AsmToken::Dot, TrailingDot));
2316  SM.addImm(Info.Offset);
2317  SM.setTypeInfo(Info.Type);
2318  return false;
2319 }
2320 
2321 /// Parse the 'offset' operator.
2322 /// This operator is used to specify the location of a given operand
2323 bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
2325  SMLoc &End) {
2326  // Eat offset, mark start of identifier.
2327  SMLoc Start = Lex().getLoc();
2328  ID = getTok().getString();
2329  if (!isParsingMSInlineAsm()) {
2330  if ((getTok().isNot(AsmToken::Identifier) &&
2331  getTok().isNot(AsmToken::String)) ||
2332  getParser().parsePrimaryExpr(Val, End, nullptr))
2333  return Error(Start, "unexpected token!");
2334  } else if (ParseIntelInlineAsmIdentifier(Val, ID, Info, false, End, true)) {
2335  return Error(Start, "unable to lookup expression");
2336  } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) {
2337  return Error(Start, "offset operator cannot yet handle constants");
2338  }
2339  return false;
2340 }
2341 
2342 // Query a candidate string for being an Intel assembly operator
2343 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
2344 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
2346  .Cases("TYPE","type",IOK_TYPE)
2347  .Cases("SIZE","size",IOK_SIZE)
2348  .Cases("LENGTH","length",IOK_LENGTH)
2349  .Default(IOK_INVALID);
2350 }
2351 
2352 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
2353 /// returns the number of elements in an array. It returns the value 1 for
2354 /// non-array variables. The SIZE operator returns the size of a C or C++
2355 /// variable. A variable's size is the product of its LENGTH and TYPE. The
2356 /// TYPE operator returns the size of a C or C++ type or variable. If the
2357 /// variable is an array, TYPE returns the size of a single element.
2358 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
2359  MCAsmParser &Parser = getParser();
2360  const AsmToken &Tok = Parser.getTok();
2361  Parser.Lex(); // Eat operator.
2362 
2363  const MCExpr *Val = nullptr;
2365  SMLoc Start = Tok.getLoc(), End;
2366  StringRef Identifier = Tok.getString();
2367  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
2368  /*IsUnevaluatedOperand=*/true, End))
2369  return 0;
2370 
2371  if (!Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
2372  Error(Start, "unable to lookup expression");
2373  return 0;
2374  }
2375 
2376  unsigned CVal = 0;
2377  switch(OpKind) {
2378  default: llvm_unreachable("Unexpected operand kind!");
2379  case IOK_LENGTH: CVal = Info.Var.Length; break;
2380  case IOK_SIZE: CVal = Info.Var.Size; break;
2381  case IOK_TYPE: CVal = Info.Var.Type; break;
2382  }
2383 
2384  return CVal;
2385 }
2386 
2387 // Query a candidate string for being an Intel assembly operator
2388 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
2389 unsigned X86AsmParser::IdentifyMasmOperator(StringRef Name) {
2390  return StringSwitch<unsigned>(Name.lower())
2391  .Case("type", MOK_TYPE)
2392  .Cases("size", "sizeof", MOK_SIZEOF)
2393  .Cases("length", "lengthof", MOK_LENGTHOF)
2394  .Default(MOK_INVALID);
2395 }
2396 
2397 /// Parse the 'LENGTHOF', 'SIZEOF', and 'TYPE' operators. The LENGTHOF operator
2398 /// returns the number of elements in an array. It returns the value 1 for
2399 /// non-array variables. The SIZEOF operator returns the size of a type or
2400 /// variable in bytes. A variable's size is the product of its LENGTH and TYPE.
2401 /// The TYPE operator returns the size of a variable. If the variable is an
2402 /// array, TYPE returns the size of a single element.
2403 bool X86AsmParser::ParseMasmOperator(unsigned OpKind, int64_t &Val) {
2404  MCAsmParser &Parser = getParser();
2405  SMLoc OpLoc = Parser.getTok().getLoc();
2406  Parser.Lex(); // Eat operator.
2407 
2408  Val = 0;
2409  if (OpKind == MOK_SIZEOF || OpKind == MOK_TYPE) {
2410  // Check for SIZEOF(<type>) and TYPE(<type>).
2411  bool InParens = Parser.getTok().is(AsmToken::LParen);
2412  const AsmToken &IDTok = InParens ? getLexer().peekTok() : Parser.getTok();
2413  AsmTypeInfo Type;
2414  if (IDTok.is(AsmToken::Identifier) &&
2415  !Parser.lookUpType(IDTok.getIdentifier(), Type)) {
2416  Val = Type.Size;
2417 
2418  // Eat tokens.
2419  if (InParens)
2420  parseToken(AsmToken::LParen);
2421  parseToken(AsmToken::Identifier);
2422  if (InParens)
2423  parseToken(AsmToken::RParen);
2424  }
2425  }
2426 
2427  if (!Val) {
2428  IntelExprStateMachine SM;
2429  SMLoc End, Start = Parser.getTok().getLoc();
2430  if (ParseIntelExpression(SM, End))
2431  return true;
2432 
2433  switch (OpKind) {
2434  default:
2435  llvm_unreachable("Unexpected operand kind!");
2436  case MOK_SIZEOF:
2437  Val = SM.getSize();
2438  break;
2439  case MOK_LENGTHOF:
2440  Val = SM.getLength();
2441  break;
2442  case MOK_TYPE:
2443  Val = SM.getElementSize();
2444  break;
2445  }
2446 
2447  if (!Val)
2448  return Error(OpLoc, "expression has unknown type", SMRange(Start, End));
2449  }
2450 
2451  return false;
2452 }
2453 
2454 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
2455  Size = StringSwitch<unsigned>(getTok().getString())
2456  .Cases("BYTE", "byte", 8)
2457  .Cases("WORD", "word", 16)
2458  .Cases("DWORD", "dword", 32)
2459  .Cases("FLOAT", "float", 32)
2460  .Cases("LONG", "long", 32)
2461  .Cases("FWORD", "fword", 48)
2462  .Cases("DOUBLE", "double", 64)
2463  .Cases("QWORD", "qword", 64)
2464  .Cases("MMWORD","mmword", 64)
2465  .Cases("XWORD", "xword", 80)
2466  .Cases("TBYTE", "tbyte", 80)
2467  .Cases("XMMWORD", "xmmword", 128)
2468  .Cases("YMMWORD", "ymmword", 256)
2469  .Cases("ZMMWORD", "zmmword", 512)
2470  .Default(0);
2471  if (Size) {
2472  const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
2473  if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
2474  return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
2475  Lex(); // Eat ptr.
2476  }
2477  return false;
2478 }
2479 
2480 bool X86AsmParser::ParseIntelOperand(OperandVector &Operands) {
2481  MCAsmParser &Parser = getParser();
2482  const AsmToken &Tok = Parser.getTok();
2483  SMLoc Start, End;
2484 
2485  // Parse optional Size directive.
2486  unsigned Size;
2487  if (ParseIntelMemoryOperandSize(Size))
2488  return true;
2489  bool PtrInOperand = bool(Size);
2490 
2491  Start = Tok.getLoc();
2492 
2493  // Rounding mode operand.
2494  if (getLexer().is(AsmToken::LCurly))
2495  return ParseRoundingModeOp(Start, Operands);
2496 
2497  // Register operand.
2498  unsigned RegNo = 0;
2499  if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
2500  if (RegNo == X86::RIP)
2501  return Error(Start, "rip can only be used as a base register");
2502  // A Register followed by ':' is considered a segment override
2503  if (Tok.isNot(AsmToken::Colon)) {
2504  if (PtrInOperand)
2505  return Error(Start, "expected memory operand after 'ptr', "
2506  "found register operand instead");
2507  Operands.push_back(X86Operand::CreateReg(RegNo, Start, End));
2508  return false;
2509  }
2510  // An alleged segment override. check if we have a valid segment register
2511  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
2512  return Error(Start, "invalid segment register");
2513  // Eat ':' and update Start location
2514  Start = Lex().getLoc();
2515  }
2516 
2517  // Immediates and Memory
2518  IntelExprStateMachine SM;
2519  if (ParseIntelExpression(SM, End))
2520  return true;
2521 
2522  if (isParsingMSInlineAsm())
2523  RewriteIntelExpression(SM, Start, Tok.getLoc());
2524 
2525  int64_t Imm = SM.getImm();
2526  const MCExpr *Disp = SM.getSym();
2527  const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
2528  if (Disp && Imm)
2529  Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
2530  if (!Disp)
2531  Disp = ImmDisp;
2532 
2533  // RegNo != 0 specifies a valid segment register,
2534  // and we are parsing a segment override
2535  if (!SM.isMemExpr() && !RegNo) {
2536  if (isParsingMSInlineAsm() && SM.isOffsetOperator()) {
2537  const InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
2538  if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
2539  // Disp includes the address of a variable; make sure this is recorded
2540  // for later handling.
2541  Operands.push_back(X86Operand::CreateImm(Disp, Start, End,
2542  SM.getSymName(), Info.Var.Decl,
2543  Info.Var.IsGlobalLV));
2544  return false;
2545  }
2546  }
2547 
2548  Operands.push_back(X86Operand::CreateImm(Disp, Start, End));
2549  return false;
2550  }
2551 
2552  StringRef ErrMsg;
2553  unsigned BaseReg = SM.getBaseReg();
2554  unsigned IndexReg = SM.getIndexReg();
2555  unsigned Scale = SM.getScale();
2556  if (!PtrInOperand)
2557  Size = SM.getElementSize() << 3;
2558 
2559  if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
2560  (IndexReg == X86::ESP || IndexReg == X86::RSP))
2561  std::swap(BaseReg, IndexReg);
2562 
2563  // If BaseReg is a vector register and IndexReg is not, swap them unless
2564  // Scale was specified in which case it would be an error.
2565  if (Scale == 0 &&
2566  !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
2567  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
2568  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
2569  (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
2570  X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
2571  X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
2572  std::swap(BaseReg, IndexReg);
2573 
2574  if (Scale != 0 &&
2575  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
2576  return Error(Start, "16-bit addresses cannot have a scale");
2577 
2578  // If there was no explicit scale specified, change it to 1.
2579  if (Scale == 0)
2580  Scale = 1;
2581 
2582  // If this is a 16-bit addressing mode with the base and index in the wrong
2583  // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
2584  // shared with att syntax where order matters.
2585  if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
2586  (IndexReg == X86::BX || IndexReg == X86::BP))
2587  std::swap(BaseReg, IndexReg);
2588 
2589  if ((BaseReg || IndexReg) &&
2590  CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2591  ErrMsg))
2592  return Error(Start, ErrMsg);
2593  if (isParsingMSInlineAsm())
2594  return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale, Start,
2595  End, Size, SM.getSymName(),
2596  SM.getIdentifierInfo(), Operands);
2597 
2598  // When parsing x64 MS-style assembly, all non-absolute references to a named
2599  // variable default to RIP-relative.
2600  if (Parser.isParsingMasm() && is64BitMode() && SM.getElementSize() > 0) {
2601  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
2602  BaseReg, IndexReg, Scale, Start,
2603  End, Size,
2604  /*DefaultBaseReg=*/X86::RIP));
2605  return false;
2606  }
2607 
2608  if ((BaseReg || IndexReg || RegNo))
2609  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
2610  BaseReg, IndexReg, Scale, Start,
2611  End, Size));
2612  else
2613  Operands.push_back(
2614  X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
2615  return false;
2616 }
2617 
2618 bool X86AsmParser::ParseATTOperand(OperandVector &Operands) {
2619  MCAsmParser &Parser = getParser();
2620  switch (getLexer().getKind()) {
2621  case AsmToken::Dollar: {
2622  // $42 or $ID -> immediate.
2623  SMLoc Start = Parser.getTok().getLoc(), End;
2624  Parser.Lex();
2625  const MCExpr *Val;
2626  // This is an immediate, so we should not parse a register. Do a precheck
2627  // for '%' to supercede intra-register parse errors.
2628  SMLoc L = Parser.getTok().getLoc();
2629  if (check(getLexer().is(AsmToken::Percent), L,
2630  "expected immediate expression") ||
2631  getParser().parseExpression(Val, End) ||
2632  check(isa<X86MCExpr>(Val), L, "expected immediate expression"))
2633  return true;
2634  Operands.push_back(X86Operand::CreateImm(Val, Start, End));
2635  return false;
2636  }
2637  case AsmToken::LCurly: {
2638  SMLoc Start = Parser.getTok().getLoc();
2639  return ParseRoundingModeOp(Start, Operands);
2640  }
2641  default: {
2642  // This a memory operand or a register. We have some parsing complications
2643  // as a '(' may be part of an immediate expression or the addressing mode
2644  // block. This is complicated by the fact that an assembler-level variable
2645  // may refer either to a register or an immediate expression.
2646 
2647  SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
2648  const MCExpr *Expr = nullptr;
2649  unsigned Reg = 0;
2650  if (getLexer().isNot(AsmToken::LParen)) {
2651  // No '(' so this is either a displacement expression or a register.
2652  if (Parser.parseExpression(Expr, EndLoc))
2653  return true;
2654  if (auto *RE = dyn_cast<X86MCExpr>(Expr)) {
2655  // Segment Register. Reset Expr and copy value to register.
2656  Expr = nullptr;
2657  Reg = RE->getRegNo();
2658 
2659  // Check the register.
2660  if (Reg == X86::EIZ || Reg == X86::RIZ)
2661  return Error(
2662  Loc, "%eiz and %riz can only be used as index registers",
2663  SMRange(Loc, EndLoc));
2664  if (Reg == X86::RIP)
2665  return Error(Loc, "%rip can only be used as a base register",
2666  SMRange(Loc, EndLoc));
2667  // Return register that are not segment prefixes immediately.
2668  if (!Parser.parseOptionalToken(AsmToken::Colon)) {
2669  Operands.push_back(X86Operand::CreateReg(Reg, Loc, EndLoc));
2670  return false;
2671  }
2672  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
2673  return Error(Loc, "invalid segment register");
2674  // Accept a '*' absolute memory reference after the segment. Place it
2675  // before the full memory operand.
2676  if (getLexer().is(AsmToken::Star))
2677  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2678  }
2679  }
2680  // This is a Memory operand.
2681  return ParseMemOperand(Reg, Expr, Loc, EndLoc, Operands);
2682  }
2683  }
2684 }
2685 
2686 // X86::COND_INVALID if not a recognized condition code or alternate mnemonic,
2687 // otherwise the EFLAGS Condition Code enumerator.
2688 X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
2689  return StringSwitch<X86::CondCode>(CC)
2690  .Case("o", X86::COND_O) // Overflow
2691  .Case("no", X86::COND_NO) // No Overflow
2692  .Cases("b", "nae", X86::COND_B) // Below/Neither Above nor Equal
2693  .Cases("ae", "nb", X86::COND_AE) // Above or Equal/Not Below
2694  .Cases("e", "z", X86::COND_E) // Equal/Zero
2695  .Cases("ne", "nz", X86::COND_NE) // Not Equal/Not Zero
2696  .Cases("be", "na", X86::COND_BE) // Below or Equal/Not Above
2697  .Cases("a", "nbe", X86::COND_A) // Above/Neither Below nor Equal
2698  .Case("s", X86::COND_S) // Sign
2699  .Case("ns", X86::COND_NS) // No Sign
2700  .Cases("p", "pe", X86::COND_P) // Parity/Parity Even
2701  .Cases("np", "po", X86::COND_NP) // No Parity/Parity Odd
2702  .Cases("l", "nge", X86::COND_L) // Less/Neither Greater nor Equal
2703  .Cases("ge", "nl", X86::COND_GE) // Greater or Equal/Not Less
2704  .Cases("le", "ng", X86::COND_LE) // Less or Equal/Not Greater
2705  .Cases("g", "nle", X86::COND_G) // Greater/Neither Less nor Equal
2707 }
2708 
2709 // true on failure, false otherwise
2710 // If no {z} mark was found - Parser doesn't advance
2711 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2712  const SMLoc &StartLoc) {
2713  MCAsmParser &Parser = getParser();
2714  // Assuming we are just pass the '{' mark, quering the next token
2715  // Searched for {z}, but none was found. Return false, as no parsing error was
2716  // encountered
2717  if (!(getLexer().is(AsmToken::Identifier) &&
2718  (getLexer().getTok().getIdentifier() == "z")))
2719  return false;
2720  Parser.Lex(); // Eat z
2721  // Query and eat the '}' mark
2722  if (!getLexer().is(AsmToken::RCurly))
2723  return Error(getLexer().getLoc(), "Expected } at this point");
2724  Parser.Lex(); // Eat '}'
2725  // Assign Z with the {z} mark opernad
2726  Z = X86Operand::CreateToken("{z}", StartLoc);
2727  return false;
2728 }
2729 
2730 // true on failure, false otherwise
2731 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
2732  MCAsmParser &Parser = getParser();
2733  if (getLexer().is(AsmToken::LCurly)) {
2734  // Eat "{" and mark the current place.
2735  const SMLoc consumedToken = consumeToken();
2736  // Distinguish {1to<NUM>} from {%k<NUM>}.
2737  if(getLexer().is(AsmToken::Integer)) {
2738  // Parse memory broadcasting ({1to<NUM>}).
2739  if (getLexer().getTok().getIntVal() != 1)
2740  return TokError("Expected 1to<NUM> at this point");
2741  StringRef Prefix = getLexer().getTok().getString();
2742  Parser.Lex(); // Eat first token of 1to8
2743  if (!getLexer().is(AsmToken::Identifier))
2744  return TokError("Expected 1to<NUM> at this point");
2745  // Recognize only reasonable suffixes.
2746  SmallVector<char, 5> BroadcastVector;
2747  StringRef BroadcastString = (Prefix + getLexer().getTok().getIdentifier())
2748  .toStringRef(BroadcastVector);
2749  if (!BroadcastString.startswith("1to"))
2750  return TokError("Expected 1to<NUM> at this point");
2751  const char *BroadcastPrimitive =
2752  StringSwitch<const char *>(BroadcastString)
2753  .Case("1to2", "{1to2}")
2754  .Case("1to4", "{1to4}")
2755  .Case("1to8", "{1to8}")
2756  .Case("1to16", "{1to16}")
2757  .Case("1to32", "{1to32}")
2758  .Default(nullptr);
2759  if (!BroadcastPrimitive)
2760  return TokError("Invalid memory broadcast primitive.");
2761  Parser.Lex(); // Eat trailing token of 1toN
2762  if (!getLexer().is(AsmToken::RCurly))
2763  return TokError("Expected } at this point");
2764  Parser.Lex(); // Eat "}"
2765  Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
2766  consumedToken));
2767  // No AVX512 specific primitives can pass
2768  // after memory broadcasting, so return.
2769  return false;
2770  } else {
2771  // Parse either {k}{z}, {z}{k}, {k} or {z}
2772  // last one have no meaning, but GCC accepts it
2773  // Currently, we're just pass a '{' mark
2774  std::unique_ptr<X86Operand> Z;
2775  if (ParseZ(Z, consumedToken))
2776  return true;
2777  // Reaching here means that parsing of the allegadly '{z}' mark yielded
2778  // no errors.
2779  // Query for the need of further parsing for a {%k<NUM>} mark
2780  if (!Z || getLexer().is(AsmToken::LCurly)) {
2781  SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2782  // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2783  // expected
2784  unsigned RegNo;
2785  SMLoc RegLoc;
2786  if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
2787  X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
2788  if (RegNo == X86::K0)
2789  return Error(RegLoc, "Register k0 can't be used as write mask");
2790  if (!getLexer().is(AsmToken::RCurly))
2791  return Error(getLexer().getLoc(), "Expected } at this point");
2792  Operands.push_back(X86Operand::CreateToken("{", StartLoc));
2793  Operands.push_back(
2794  X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
2795  Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2796  } else
2797  return Error(getLexer().getLoc(),
2798  "Expected an op-mask register at this point");
2799  // {%k<NUM>} mark is found, inquire for {z}
2800  if (getLexer().is(AsmToken::LCurly) && !Z) {
2801  // Have we've found a parsing error, or found no (expected) {z} mark
2802  // - report an error
2803  if (ParseZ(Z, consumeToken()) || !Z)
2804  return Error(getLexer().getLoc(),
2805  "Expected a {z} mark at this point");
2806 
2807  }
2808  // '{z}' on its own is meaningless, hence should be ignored.
2809  // on the contrary - have it been accompanied by a K register,
2810  // allow it.
2811  if (Z)
2812  Operands.push_back(std::move(Z));
2813  }
2814  }
2815  }
2816  return false;
2817 }
2818 
2819 /// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
2820 /// has already been parsed if present. disp may be provided as well.
2821 bool X86AsmParser::ParseMemOperand(unsigned SegReg, const MCExpr *Disp,
2822  SMLoc StartLoc, SMLoc EndLoc,
2824  MCAsmParser &Parser = getParser();
2825  SMLoc Loc;
2826  // Based on the initial passed values, we may be in any of these cases, we are
2827  // in one of these cases (with current position (*)):
2828 
2829  // 1. seg : * disp (base-index-scale-expr)
2830  // 2. seg : *(disp) (base-index-scale-expr)
2831  // 3. seg : *(base-index-scale-expr)
2832  // 4. disp *(base-index-scale-expr)
2833  // 5. *(disp) (base-index-scale-expr)
2834  // 6. *(base-index-scale-expr)
2835  // 7. disp *
2836  // 8. *(disp)
2837 
2838  // If we do not have an displacement yet, check if we're in cases 4 or 6 by
2839  // checking if the first object after the parenthesis is a register (or an
2840  // identifier referring to a register) and parse the displacement or default
2841  // to 0 as appropriate.
2842  auto isAtMemOperand = [this]() {
2843  if (this->getLexer().isNot(AsmToken::LParen))
2844  return false;
2845  AsmToken Buf[2];
2846  StringRef Id;
2847  auto TokCount = this->getLexer().peekTokens(Buf, true);
2848  if (TokCount == 0)
2849  return false;
2850  switch (Buf[0].getKind()) {
2851  case AsmToken::Percent:
2852  case AsmToken::Comma:
2853  return true;
2854  // These lower cases are doing a peekIdentifier.
2855  case AsmToken::At:
2856  case AsmToken::Dollar:
2857  if ((TokCount > 1) &&
2858  (Buf[1].is(AsmToken::Identifier) || Buf[1].is(AsmToken::String)) &&
2859  (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
2860  Id = StringRef(Buf[0].getLoc().getPointer(),
2861  Buf[1].getIdentifier().size() + 1);
2862  break;
2863  case AsmToken::Identifier:
2864  case AsmToken::String:
2865  Id = Buf[0].getIdentifier();
2866  break;
2867  default:
2868  return false;
2869  }
2870  // We have an ID. Check if it is bound to a register.
2871  if (!Id.empty()) {
2872  MCSymbol *Sym = this->getContext().getOrCreateSymbol(Id);
2873  if (Sym->isVariable()) {
2874  auto V = Sym->getVariableValue(/*SetUsed*/ false);
2875  return isa<X86MCExpr>(V);
2876  }
2877  }
2878  return false;
2879  };
2880 
2881  if (!Disp) {
2882  // Parse immediate if we're not at a mem operand yet.
2883  if (!isAtMemOperand()) {
2884  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Disp, EndLoc))
2885  return true;
2886  assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
2887  } else {
2888  // Disp is implicitly zero if we haven't parsed it yet.
2889  Disp = MCConstantExpr::create(0, Parser.getContext());
2890  }
2891  }
2892 
2893  // We are now either at the end of the operand or at the '(' at the start of a
2894  // base-index-scale-expr.
2895 
2896  if (!parseOptionalToken(AsmToken::LParen)) {
2897  if (SegReg == 0)
2898  Operands.push_back(
2899  X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
2900  else
2901  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
2902  0, 0, 1, StartLoc, EndLoc));
2903  return false;
2904  }
2905 
2906  // If we reached here, then eat the '(' and Process
2907  // the rest of the memory operand.
2908  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2909  SMLoc BaseLoc = getLexer().getLoc();
2910  const MCExpr *E;
2911  StringRef ErrMsg;
2912 
2913  // Parse BaseReg if one is provided.
2914  if (getLexer().isNot(AsmToken::Comma) && getLexer().isNot(AsmToken::RParen)) {
2915  if (Parser.parseExpression(E, EndLoc) ||
2916  check(!isa<X86MCExpr>(E), BaseLoc, "expected register here"))
2917  return true;
2918 
2919  // Check the register.
2920  BaseReg = cast<X86MCExpr>(E)->getRegNo();
2921  if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
2922  return Error(BaseLoc, "eiz and riz can only be used as index registers",
2923  SMRange(BaseLoc, EndLoc));
2924  }
2925 
2926  if (parseOptionalToken(AsmToken::Comma)) {
2927  // Following the comma we should have either an index register, or a scale
2928  // value. We don't support the later form, but we want to parse it
2929  // correctly.
2930  //
2931  // Even though it would be completely consistent to support syntax like
2932  // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2933  if (getLexer().isNot(AsmToken::RParen)) {
2934  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(E, EndLoc))
2935  return true;
2936 
2937  if (!isa<X86MCExpr>(E)) {
2938  // We've parsed an unexpected Scale Value instead of an index
2939  // register. Interpret it as an absolute.
2940  int64_t ScaleVal;
2941  if (!E->evaluateAsAbsolute(ScaleVal, getStreamer().getAssemblerPtr()))
2942  return Error(Loc, "expected absolute expression");
2943  if (ScaleVal != 1)
2944  Warning(Loc, "scale factor without index register is ignored");
2945  Scale = 1;
2946  } else { // IndexReg Found.
2947  IndexReg = cast<X86MCExpr>(E)->getRegNo();
2948 
2949  if (BaseReg == X86::RIP)
2950  return Error(Loc,
2951  "%rip as base register can not have an index register");
2952  if (IndexReg == X86::RIP)
2953  return Error(Loc, "%rip is not allowed as an index register");
2954 
2955  if (parseOptionalToken(AsmToken::Comma)) {
2956  // Parse the scale amount:
2957  // ::= ',' [scale-expression]
2958 
2959  // A scale amount without an index is ignored.
2960  if (getLexer().isNot(AsmToken::RParen)) {
2961  int64_t ScaleVal;
2962  if (Parser.parseTokenLoc(Loc) ||
2963  Parser.parseAbsoluteExpression(ScaleVal))
2964  return Error(Loc, "expected scale expression");
2965  Scale = (unsigned)ScaleVal;
2966  // Validate the scale amount.
2967  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2968  Scale != 1)
2969  return Error(Loc, "scale factor in 16-bit address must be 1");
2970  if (checkScale(Scale, ErrMsg))
2971  return Error(Loc, ErrMsg);
2972  }
2973  }
2974  }
2975  }
2976  }
2977 
2978  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2979  if (parseToken(AsmToken::RParen, "unexpected token in memory operand"))
2980  return true;
2981 
2982  // This is to support otherwise illegal operand (%dx) found in various
2983  // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
2984  // be supported. Mark such DX variants separately fix only in special cases.
2985  if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
2986  isa<MCConstantExpr>(Disp) &&
2987  cast<MCConstantExpr>(Disp)->getValue() == 0) {
2988  Operands.push_back(X86Operand::CreateDXReg(BaseLoc, BaseLoc));
2989  return false;
2990  }
2991 
2992  if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2993  ErrMsg))
2994  return Error(BaseLoc, ErrMsg);
2995 
2996  if (SegReg || BaseReg || IndexReg)
2997  Operands.push_back(X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
2998  BaseReg, IndexReg, Scale, StartLoc,
2999  EndLoc));
3000  else
3001  Operands.push_back(
3002  X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
3003  return false;
3004 }
3005 
3006 // Parse either a standard primary expression or a register.
3007 bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
3008  MCAsmParser &Parser = getParser();
3009  // See if this is a register first.
3010  if (getTok().is(AsmToken::Percent) ||
3011  (isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
3012  MatchRegisterName(Parser.getTok().getString()))) {
3013  SMLoc StartLoc = Parser.getTok().getLoc();
3014  unsigned RegNo;
3015  if (ParseRegister(RegNo, StartLoc, EndLoc))
3016  return true;
3017  Res = X86MCExpr::create(RegNo, Parser.getContext());
3018  return false;
3019  }
3020  return Parser.parsePrimaryExpr(Res, EndLoc, nullptr);
3021 }
3022 
3023 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
3024  SMLoc NameLoc, OperandVector &Operands) {
3025  MCAsmParser &Parser = getParser();
3026  InstInfo = &Info;
3027 
3028  // Reset the forced VEX encoding.
3029  ForcedVEXEncoding = VEXEncoding_Default;
3030  ForcedDispEncoding = DispEncoding_Default;
3031 
3032  // Parse pseudo prefixes.
3033  while (true) {
3034  if (Name == "{") {
3035  if (getLexer().isNot(AsmToken::Identifier))
3036  return Error(Parser.getTok().getLoc(), "Unexpected token after '{'");
3037  std::string Prefix = Parser.getTok().getString().lower();
3038  Parser.Lex(); // Eat identifier.
3039  if (getLexer().isNot(AsmToken::RCurly))
3040  return Error(Parser.getTok().getLoc(), "Expected '}'");
3041  Parser.Lex(); // Eat curly.
3042 
3043  if (Prefix == "vex")
3044  ForcedVEXEncoding = VEXEncoding_VEX;
3045  else if (Prefix == "vex2")
3046  ForcedVEXEncoding = VEXEncoding_VEX2;
3047  else if (Prefix == "vex3")
3048  ForcedVEXEncoding = VEXEncoding_VEX3;
3049  else if (Prefix == "evex")
3050  ForcedVEXEncoding = VEXEncoding_EVEX;
3051  else if (Prefix == "disp8")
3052  ForcedDispEncoding = DispEncoding_Disp8;
3053  else if (Prefix == "disp32")
3054  ForcedDispEncoding = DispEncoding_Disp32;
3055  else
3056  return Error(NameLoc, "unknown prefix");
3057 
3058  NameLoc = Parser.getTok().getLoc();
3059  if (getLexer().is(AsmToken::LCurly)) {
3060  Parser.Lex();
3061  Name = "{";
3062  } else {
3063  if (getLexer().isNot(AsmToken::Identifier))
3064  return Error(Parser.getTok().getLoc(), "Expected identifier");
3065  // FIXME: The mnemonic won't match correctly if its not in lower case.
3066  Name = Parser.getTok().getString();
3067  Parser.Lex();
3068  }
3069  continue;
3070  }
3071  // Parse MASM style pseudo prefixes.
3072  if (isParsingMSInlineAsm()) {
3073  if (Name.equals_insensitive("vex"))
3074  ForcedVEXEncoding = VEXEncoding_VEX;
3075  else if (Name.equals_insensitive("vex2"))
3076  ForcedVEXEncoding = VEXEncoding_VEX2;
3077  else if (Name.equals_insensitive("vex3"))
3078  ForcedVEXEncoding = VEXEncoding_VEX3;
3079  else if (Name.equals_insensitive("evex"))
3080  ForcedVEXEncoding = VEXEncoding_EVEX;
3081 
3082  if (ForcedVEXEncoding != VEXEncoding_Default) {
3083  if (getLexer().isNot(AsmToken::Identifier))
3084  return Error(Parser.getTok().getLoc(), "Expected identifier");
3085  // FIXME: The mnemonic won't match correctly if its not in lower case.
3086  Name = Parser.getTok().getString();
3087  NameLoc = Parser.getTok().getLoc();
3088  Parser.Lex();
3089  }
3090  }
3091  break;
3092  }
3093 
3094  // Support the suffix syntax for overriding displacement size as well.
3095  if (Name.consume_back(".d32")) {
3096  ForcedDispEncoding = DispEncoding_Disp32;
3097  } else if (Name.consume_back(".d8")) {
3098  ForcedDispEncoding = DispEncoding_Disp8;
3099  }
3100 
3101  StringRef PatchedName = Name;
3102 
3103  // Hack to skip "short" following Jcc.
3104  if (isParsingIntelSyntax() &&
3105  (PatchedName == "jmp" || PatchedName == "jc" || PatchedName == "jnc" ||
3106  PatchedName == "jcxz" || PatchedName == "jecxz" ||
3107  (PatchedName.startswith("j") &&
3108  ParseConditionCode(PatchedName.substr(1)) != X86::COND_INVALID))) {
3109  StringRef NextTok = Parser.getTok().getString();
3110  if (Parser.isParsingMasm() ? NextTok.equals_insensitive("short")
3111  : NextTok == "short") {
3112  SMLoc NameEndLoc =
3113  NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
3114  // Eat the short keyword.
3115  Parser.Lex();
3116  // MS and GAS ignore the short keyword; they both determine the jmp type
3117  // based on the distance of the label. (NASM does emit different code with
3118  // and without "short," though.)
3119  InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
3120  NextTok.size() + 1);
3121  }
3122  }
3123 
3124  // FIXME: Hack to recognize setneb as setne.
3125  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
3126  PatchedName != "setb" && PatchedName != "setnb")
3127  PatchedName = PatchedName.substr(0, Name.size()-1);
3128 
3129  unsigned ComparisonPredicate = ~0U;
3130 
3131  // FIXME: Hack to recognize cmp<comparison code>{sh,ss,sd,ph,ps,pd}.
3132  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
3133  (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
3134  PatchedName.endswith("sh") || PatchedName.endswith("ph") ||
3135  PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
3136  bool IsVCMP = PatchedName[0] == 'v';
3137  unsigned CCIdx = IsVCMP ? 4 : 3;
3138  unsigned CC = StringSwitch<unsigned>(
3139  PatchedName.slice(CCIdx, PatchedName.size() - 2))
3140  .Case("eq", 0x00)
3141  .Case("eq_oq", 0x00)
3142  .Case("lt", 0x01)
3143  .Case("lt_os", 0x01)
3144  .Case("le", 0x02)
3145  .Case("le_os", 0x02)
3146  .Case("unord", 0x03)
3147  .Case("unord_q", 0x03)
3148  .Case("neq", 0x04)
3149  .Case("neq_uq", 0x04)
3150  .Case("nlt", 0x05)
3151  .Case("nlt_us", 0x05)
3152  .Case("nle", 0x06)
3153  .Case("nle_us", 0x06)
3154  .Case("ord", 0x07)
3155  .Case("ord_q", 0x07)
3156  /* AVX only from here */
3157  .Case("eq_uq", 0x08)
3158  .Case("nge", 0x09)
3159  .Case("nge_us", 0x09)
3160  .Case("ngt", 0x0A)
3161  .Case("ngt_us", 0x0A)
3162  .Case("false", 0x0B)
3163  .Case("false_oq", 0x0B)
3164  .Case("neq_oq", 0x0C)
3165  .Case("ge", 0x0D)
3166  .Case("ge_os", 0x0D)
3167  .Case("gt", 0x0E)
3168  .Case("gt_os", 0x0E)
3169  .Case("true", 0x0F)
3170  .Case("true_uq", 0x0F)
3171  .Case("eq_os", 0x10)
3172  .Case("lt_oq", 0x11)
3173  .Case("le_oq", 0x12)
3174  .Case("unord_s", 0x13)
3175  .Case("neq_us", 0x14)
3176  .Case("nlt_uq", 0x15)
3177  .Case("nle_uq", 0x16)
3178  .Case("ord_s", 0x17)
3179  .Case("eq_us", 0x18)
3180  .Case("nge_uq", 0x19)
3181  .Case("ngt_uq", 0x1A)
3182  .Case("false_os", 0x1B)
3183  .Case("neq_os", 0x1C)
3184  .Case("ge_oq", 0x1D)
3185  .Case("gt_oq", 0x1E)
3186  .Case("true_us", 0x1F)
3187  .Default(~0U);
3188  if (CC != ~0U && (IsVCMP || CC < 8) &&
3189  (IsVCMP || PatchedName.back() != 'h')) {
3190  if (PatchedName.endswith("ss"))
3191  PatchedName = IsVCMP ? "vcmpss" : "cmpss";
3192  else if (PatchedName.endswith("sd"))
3193  PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
3194  else if (PatchedName.endswith("ps"))
3195  PatchedName = IsVCMP ? "vcmpps" : "cmpps";
3196  else if (PatchedName.endswith("pd"))
3197  PatchedName = IsVCMP ? "vcmppd" : "cmppd";
3198  else if (PatchedName.endswith("sh"))
3199  PatchedName = "vcmpsh";
3200  else if (PatchedName.endswith("ph"))
3201  PatchedName = "vcmpph";
3202  else
3203  llvm_unreachable("Unexpected suffix!");
3204 
3205  ComparisonPredicate = CC;
3206  }
3207  }
3208 
3209  // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3210  if (PatchedName.startswith("vpcmp") &&
3211  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3212  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3213  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3214  unsigned CC = StringSwitch<unsigned>(
3215  PatchedName.slice(5, PatchedName.size() - SuffixSize))
3216  .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
3217  .Case("lt", 0x1)
3218  .Case("le", 0x2)
3219  //.Case("false", 0x3) // Not a documented alias.
3220  .Case("neq", 0x4)
3221  .Case("nlt", 0x5)
3222  .Case("nle", 0x6)
3223  //.Case("true", 0x7) // Not a documented alias.
3224  .Default(~0U);
3225  if (CC != ~0U && (CC != 0 || SuffixSize == 2)) {
3226  switch (PatchedName.back()) {
3227  default: llvm_unreachable("Unexpected character!");
3228  case 'b': PatchedName = SuffixSize == 2 ? "vpcmpub" : "vpcmpb"; break;
3229  case 'w': PatchedName = SuffixSize == 2 ? "vpcmpuw" : "vpcmpw"; break;
3230  case 'd': PatchedName = SuffixSize == 2 ? "vpcmpud" : "vpcmpd"; break;
3231  case 'q': PatchedName = SuffixSize == 2 ? "vpcmpuq" : "vpcmpq"; break;
3232  }
3233  // Set up the immediate to push into the operands later.
3234  ComparisonPredicate = CC;
3235  }
3236  }
3237 
3238  // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3239  if (PatchedName.startswith("vpcom") &&
3240  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3241  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3242  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3243  unsigned CC = StringSwitch<unsigned>(
3244  PatchedName.slice(5, PatchedName.size() - SuffixSize))
3245  .Case("lt", 0x0)
3246  .Case("le", 0x1)
3247  .Case("gt", 0x2)
3248  .Case("ge", 0x3)
3249  .Case("eq", 0x4)
3250  .Case("neq", 0x5)
3251  .Case("false", 0x6)
3252  .Case("true", 0x7)
3253  .Default(~0U);
3254  if (CC != ~0U) {
3255  switch (PatchedName.back()) {
3256  default: llvm_unreachable("Unexpected character!");
3257  case 'b': PatchedName = SuffixSize == 2 ? "vpcomub" : "vpcomb"; break;
3258  case 'w': PatchedName = SuffixSize == 2 ? "vpcomuw" : "vpcomw"; break;
3259  case 'd': PatchedName = SuffixSize == 2 ? "vpcomud" : "vpcomd"; break;
3260  case 'q': PatchedName = SuffixSize == 2 ? "vpcomuq" : "vpcomq"; break;
3261  }
3262  // Set up the immediate to push into the operands later.
3263  ComparisonPredicate = CC;
3264  }
3265  }
3266 
3267 
3268  // Determine whether this is an instruction prefix.
3269  // FIXME:
3270  // Enhance prefixes integrity robustness. for example, following forms
3271  // are currently tolerated:
3272  // repz repnz <insn> ; GAS errors for the use of two similar prefixes
3273  // lock addq %rax, %rbx ; Destination operand must be of memory type
3274  // xacquire <insn> ; xacquire must be accompanied by 'lock'
3275  bool IsPrefix =
3277  .Cases("cs", "ds", "es", "fs", "gs", "ss", true)
3278  .Cases("rex64", "data32", "data16", "addr32", "addr16", true)
3279  .Cases("xacquire", "xrelease", true)
3280  .Cases("acquire", "release", isParsingIntelSyntax())
3281  .Default(false);
3282 
3283  auto isLockRepeatNtPrefix = [](StringRef N) {
3284  return StringSwitch<bool>(N)
3285  .Cases("lock", "rep", "repe", "repz", "repne", "repnz", "notrack", true)
3286  .Default(false);
3287  };
3288 
3289  bool CurlyAsEndOfStatement = false;
3290 
3291  unsigned Flags = X86::IP_NO_PREFIX;
3292  while (isLockRepeatNtPrefix(Name.lower())) {
3293  unsigned Prefix =
3295  .Cases("lock", "lock", X86::IP_HAS_LOCK)
3296  .Cases("rep", "repe", "repz", X86::IP_HAS_REPEAT)
3297  .Cases("repne", "repnz", X86::IP_HAS_REPEAT_NE)
3298  .Cases("notrack", "notrack", X86::IP_HAS_NOTRACK)
3299  .Default(X86::IP_NO_PREFIX); // Invalid prefix (impossible)
3300  Flags |= Prefix;
3301  if (getLexer().is(AsmToken::EndOfStatement)) {
3302  // We don't have real instr with the given prefix
3303  // let's use the prefix as the instr.
3304  // TODO: there could be several prefixes one after another
3305  Flags = X86::IP_NO_PREFIX;
3306  break;
3307  }
3308  // FIXME: The mnemonic won't match correctly if its not in lower case.
3309  Name = Parser.getTok().getString();
3310  Parser.Lex(); // eat the prefix
3311  // Hack: we could have something like "rep # some comment" or
3312  // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
3313  while (Name.startswith(";") || Name.startswith("\n") ||
3314  Name.startswith("#") || Name.startswith("\t") ||
3315  Name.startswith("/")) {
3316  // FIXME: The mnemonic won't match correctly if its not in lower case.
3317  Name = Parser.getTok().getString();
3318  Parser.Lex(); // go to next prefix or instr
3319  }
3320  }
3321 
3322  if (Flags)
3323  PatchedName = Name;
3324 
3325  // Hacks to handle 'data16' and 'data32'
3326  if (PatchedName == "data16" && is16BitMode()) {
3327  return Error(NameLoc, "redundant data16 prefix");
3328  }
3329  if (PatchedName == "data32") {
3330  if (is32BitMode())
3331  return Error(NameLoc, "redundant data32 prefix");
3332  if (is64BitMode())
3333  return Error(NameLoc, "'data32' is not supported in 64-bit mode");
3334  // Hack to 'data16' for the table lookup.
3335  PatchedName = "data16";
3336 
3337  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3338  StringRef Next = Parser.getTok().getString();
3339  getLexer().Lex();
3340  // data32 effectively changes the instruction suffix.
3341  // TODO Generalize.
3342  if (Next == "callw")
3343  Next = "calll";
3344  if (Next == "ljmpw")
3345  Next = "ljmpl";
3346 
3347  Name = Next;
3348  PatchedName = Name;
3349  ForcedDataPrefix = X86::Mode32Bit;
3350  IsPrefix = false;
3351  }
3352  }
3353 
3354  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
3355 
3356  // Push the immediate if we extracted one from the mnemonic.
3357  if (ComparisonPredicate != ~0U && !isParsingIntelSyntax()) {
3358  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
3359  getParser().getContext());
3360  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
3361  }
3362 
3363  // This does the actual operand parsing. Don't parse any more if we have a
3364  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
3365  // just want to parse the "lock" as the first instruction and the "incl" as
3366  // the next one.
3367  if (getLexer().isNot(AsmToken::EndOfStatement) && !IsPrefix) {
3368  // Parse '*' modifier.
3369  if (getLexer().is(AsmToken::Star))
3370  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
3371 
3372  // Read the operands.
3373  while (true) {
3374  if (ParseOperand(Operands))
3375  return true;
3376  if (HandleAVX512Operand(Operands))
3377  return true;
3378 
3379  // check for comma and eat it
3380  if (getLexer().is(AsmToken::Comma))
3381  Parser.Lex();
3382  else
3383  break;
3384  }
3385 
3386  // In MS inline asm curly braces mark the beginning/end of a block,
3387  // therefore they should be interepreted as end of statement
3388  CurlyAsEndOfStatement =
3389  isParsingIntelSyntax() && isParsingMSInlineAsm() &&
3390  (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
3391  if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
3392  return TokError("unexpected token in argument list");
3393  }
3394 
3395  // Push the immediate if we extracted one from the mnemonic.
3396  if (ComparisonPredicate != ~0U && isParsingIntelSyntax()) {
3397  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
3398  getParser().getContext());
3399  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
3400  }
3401 
3402  // Consume the EndOfStatement or the prefix separator Slash
3403  if (getLexer().is(AsmToken::EndOfStatement) ||
3404  (IsPrefix && getLexer().is(AsmToken::Slash)))
3405  Parser.Lex();
3406  else if (CurlyAsEndOfStatement)
3407  // Add an actual EndOfStatement before the curly brace
3408  Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
3409  getLexer().getTok().getLoc(), 0);
3410 
3411  // This is for gas compatibility and cannot be done in td.
3412  // Adding "p" for some floating point with no argument.
3413  // For example: fsub --> fsubp
3414  bool IsFp =
3415  Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
3416  if (IsFp && Operands.size() == 1) {
3417  const char *Repl = StringSwitch<const char *>(Name)
3418  .Case("fsub", "fsubp")
3419  .Case("fdiv", "fdivp")
3420  .Case("fsubr", "fsubrp")
3421  .Case("fdivr", "fdivrp");
3422  static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
3423  }
3424 
3425  if ((Name == "mov" || Name == "movw" || Name == "movl") &&
3426  (Operands.size() == 3)) {
3427  X86Operand &Op1 = (X86Operand &)*Operands[1];
3428  X86Operand &Op2 = (X86Operand &)*Operands[2];
3429  SMLoc Loc = Op1.getEndLoc();
3430  // Moving a 32 or 16 bit value into a segment register has the same
3431  // behavior. Modify such instructions to always take shorter form.
3432  if (Op1.isReg() && Op2.isReg() &&
3433  X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
3434  Op2.getReg()) &&
3435  (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
3436  X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
3437  // Change instruction name to match new instruction.
3438  if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
3439  Name = is16BitMode() ? "movw" : "movl";
3440  Operands[0] = X86Operand::CreateToken(Name, NameLoc);
3441  }
3442  // Select the correct equivalent 16-/32-bit source register.
3443  unsigned Reg =
3444  getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
3445  Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
3446  }
3447  }
3448 
3449  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
3450  // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
3451  // documented form in various unofficial manuals, so a lot of code uses it.
3452  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
3453  Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
3454  Operands.size() == 3) {
3455  X86Operand &Op = (X86Operand &)*Operands.back();
3456  if (Op.isDXReg())
3457  Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3458  Op.getEndLoc());
3459  }
3460  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
3461  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
3462  Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
3463  Operands.size() == 3) {
3464  X86Operand &Op = (X86Operand &)*Operands[1];
3465  if (Op.isDXReg())
3466  Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
3467  Op.getEndLoc());
3468  }
3469 
3471  bool HadVerifyError = false;
3472 
3473  // Append default arguments to "ins[bwld]"
3474  if (Name.startswith("ins") &&
3475  (Operands.size() == 1 || Operands.size() == 3) &&
3476  (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
3477  Name == "ins")) {
3478 
3479  AddDefaultSrcDestOperands(TmpOperands,
3480  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
3481  DefaultMemDIOperand(NameLoc));
3482  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3483  }
3484 
3485  // Append default arguments to "outs[bwld]"
3486  if (Name.startswith("outs") &&
3487  (Operands.size() == 1 || Operands.size() == 3) &&
3488  (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
3489  Name == "outsd" || Name == "outs")) {
3490  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
3491  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
3492  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3493  }
3494 
3495  // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
3496  // values of $SIREG according to the mode. It would be nice if this
3497  // could be achieved with InstAlias in the tables.
3498  if (Name.startswith("lods") &&
3499  (Operands.size() == 1 || Operands.size() == 2) &&
3500  (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
3501  Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
3502  TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
3503  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3504  }
3505 
3506  // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
3507  // values of $DIREG according to the mode. It would be nice if this
3508  // could be achieved with InstAlias in the tables.
3509  if (Name.startswith("stos") &&
3510  (Operands.size() == 1 || Operands.size() == 2) &&
3511  (Name == "stos" || Name == "stosb" || Name == "stosw" ||
3512  Name == "stosl" || Name == "stosd" || Name == "stosq")) {
3513  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
3514  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3515  }
3516 
3517  // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
3518  // values of $DIREG according to the mode. It would be nice if this
3519  // could be achieved with InstAlias in the tables.
3520  if (Name.startswith("scas") &&
3521  (Operands.size() == 1 || Operands.size() == 2) &&
3522  (Name == "scas" || Name == "scasb" || Name == "scasw" ||
3523  Name == "scasl" || Name == "scasd" || Name == "scasq")) {
3524  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
3525  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3526  }
3527 
3528  // Add default SI and DI operands to "cmps[bwlq]".
3529  if (Name.startswith("cmps") &&
3530  (Operands.size() == 1 || Operands.size() == 3) &&
3531  (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
3532  Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
3533  AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
3534  DefaultMemSIOperand(NameLoc));
3535  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3536  }
3537 
3538  // Add default SI and DI operands to "movs[bwlq]".
3539  if (((Name.startswith("movs") &&
3540  (Name == "movs" || Name == "movsb" || Name == "movsw" ||
3541  Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
3542  (Name.startswith("smov") &&
3543  (Name == "smov" || Name == "smovb" || Name == "smovw" ||
3544  Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
3545  (Operands.size() == 1 || Operands.size() == 3)) {
3546  if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
3547  Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
3548  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
3549  DefaultMemDIOperand(NameLoc));
3550  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
3551  }
3552 
3553  // Check if we encountered an error for one the string insturctions
3554  if (HadVerifyError) {
3555  return HadVerifyError;
3556  }
3557 
3558  // Transforms "xlat mem8" into "xlatb"
3559  if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
3560  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
3561  if (Op1.isMem8()) {
3562  Warning(Op1.getStartLoc(), "memory operand is only for determining the "
3563  "size, (R|E)BX will be used for the location");
3564  Operands.pop_back();
3565  static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
3566  }
3567  }
3568 
3569  if (Flags)
3570  Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
3571  return false;
3572 }
3573 
3574 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
3575  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3576 
3577  switch (Inst.getOpcode()) {
3578  default: return false;
3579  case X86::JMP_1:
3580  // {disp32} forces a larger displacement as if the instruction was relaxed.
3581  // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3582  // This matches GNU assembler.
3583  if (ForcedDispEncoding == DispEncoding_Disp32) {
3584  Inst.setOpcode(is16BitMode() ? X86::JMP_2 : X86::JMP_4);
3585  return true;
3586  }
3587 
3588  return false;
3589  case X86::JCC_1:
3590  // {disp32} forces a larger displacement as if the instruction was relaxed.
3591  // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
3592  // This matches GNU assembler.
3593  if (ForcedDispEncoding == DispEncoding_Disp32) {
3594  Inst.setOpcode(is16BitMode() ? X86::JCC_2 : X86::JCC_4);
3595  return true;
3596  }
3597 
3598  return false;
3599  case X86::VMOVZPQILo2PQIrr:
3600  case X86::VMOVAPDrr:
3601  case X86::VMOVAPDYrr:
3602  case X86::VMOVAPSrr:
3603  case X86::VMOVAPSYrr:
3604  case X86::VMOVDQArr:
3605  case X86::VMOVDQAYrr:
3606  case X86::VMOVDQUrr:
3607  case X86::VMOVDQUYrr:
3608  case X86::VMOVUPDrr:
3609  case X86::VMOVUPDYrr:
3610  case X86::VMOVUPSrr:
3611  case X86::VMOVUPSYrr: {
3612  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3613  // the registers is extended, but other isn't.
3614  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
3615  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
3616  MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8)
3617  return false;
3618 
3619  unsigned NewOpc;
3620  switch (Inst.getOpcode()) {
3621  default: llvm_unreachable("Invalid opcode");
3622  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
3623  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
3624  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
3625  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
3626  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
3627  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
3628  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
3629  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
3630  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
3631  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
3632  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
3633  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
3634  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
3635  }
3636  Inst.setOpcode(NewOpc);
3637  return true;
3638  }
3639  case X86::VMOVSDrr:
3640  case X86::VMOVSSrr: {
3641  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3642  // the registers is extended, but other isn't.
3643  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
3644  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
3645  MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8)
3646  return false;
3647 
3648  unsigned NewOpc;
3649  switch (Inst.getOpcode()) {
3650  default: llvm_unreachable("Invalid opcode");
3651  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
3652  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
3653  }
3654  Inst.setOpcode(NewOpc);
3655  return true;
3656  }
3657  case X86::RCR8ri: case X86::RCR16ri: case X86::RCR32ri: case X86::RCR64ri:
3658  case X86::RCL8ri: case X86::RCL16ri: case X86::RCL32ri: case X86::RCL64ri:
3659  case X86::ROR8ri: case X86::ROR16ri: case X86::ROR32ri: case X86::ROR64ri:
3660  case X86::ROL8ri: case X86::ROL16ri: case X86::ROL32ri: case X86::ROL64ri:
3661  case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri: case X86::SAR64ri:
3662  case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri: case X86::SHR64ri:
3663  case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri: case X86::SHL64ri: {
3664  // Optimize s{hr,ar,hl} $1, <op> to "shift <op>". Similar for rotate.
3665  // FIXME: It would be great if we could just do this with an InstAlias.
3666  if (!Inst.getOperand(2).isImm() || Inst.getOperand(2).getImm() != 1)
3667  return false;
3668 
3669  unsigned NewOpc;
3670  switch (Inst.getOpcode()) {
3671  default: llvm_unreachable("Invalid opcode");
3672  case X86::RCR8ri: NewOpc = X86::RCR8r1; break;
3673  case X86::RCR16ri: NewOpc = X86::RCR16r1; break;
3674  case X86::RCR32ri: NewOpc = X86::RCR32r1; break;
3675  case X86::RCR64ri: NewOpc = X86::RCR64r1; break;
3676  case X86::RCL8ri: NewOpc = X86::RCL8r1; break;
3677  case X86::RCL16ri: NewOpc = X86::RCL16r1; break;
3678  case X86::RCL32ri: NewOpc = X86::RCL32r1; break;
3679  case X86::RCL64ri: NewOpc = X86::RCL64r1; break;
3680  case X86::ROR8ri: NewOpc = X86::ROR8r1; break;
3681  case X86::ROR16ri: NewOpc = X86::ROR16r1; break;
3682  case X86::ROR32ri: NewOpc = X86::ROR32r1; break;
3683  case X86::ROR64ri: NewOpc = X86::ROR64r1; break;
3684  case X86::ROL8ri: NewOpc = X86::ROL8r1; break;
3685  case X86::ROL16ri: NewOpc = X86::ROL16r1; break;
3686  case X86::ROL32ri: NewOpc = X86::ROL32r1; break;
3687  case X86::ROL64ri: NewOpc = X86::ROL64r1; break;
3688  case X86::SAR8ri: NewOpc = X86::SAR8r1; break;
3689  case X86::SAR16ri: NewOpc = X86::SAR16r1; break;
3690  case X86::SAR32ri: NewOpc = X86::SAR32r1; break;
3691  case X86::SAR64ri: NewOpc = X86::SAR64r1; break;
3692  case X86::SHR8ri: NewOpc = X86::SHR8r1; break;
3693  case X86::SHR16ri: NewOpc = X86::SHR16r1; break;
3694  case X86::SHR32ri: NewOpc = X86::SHR32r1; break;
3695  case X86::SHR64ri: NewOpc = X86::SHR64r1; break;
3696  case X86::SHL8ri: NewOpc = X86::SHL8r1; break;
3697  case X86::SHL16ri: NewOpc = X86::SHL16r1; break;
3698  case X86::SHL32ri: NewOpc = X86::SHL32r1; break;
3699  case X86::SHL64ri: NewOpc = X86::SHL64r1; break;
3700  }
3701 
3702  MCInst TmpInst;
3703  TmpInst.setOpcode(NewOpc);
3704  TmpInst.addOperand(Inst.getOperand(0));
3705  TmpInst.addOperand(Inst.getOperand(1));
3706  Inst = TmpInst;
3707  return true;
3708  }
3709  case X86::RCR8mi: case X86::RCR16mi: case X86::RCR32mi: case X86::RCR64mi:
3710  case X86::RCL8mi: case X86::RCL16mi: case X86::RCL32mi: case X86::RCL64mi:
3711  case X86::ROR8mi: case X86::ROR16mi: case X86::ROR32mi: case X86::ROR64mi:
3712  case X86::ROL8mi: case X86::ROL16mi: case X86::ROL32mi: case X86::ROL64mi:
3713  case X86::SAR8mi: case X86::SAR16mi: case X86::SAR32mi: case X86::SAR64mi:
3714  case X86::SHR8mi: case X86::SHR16mi: case X86::SHR32mi: case X86::SHR64mi:
3715  case X86::SHL8mi: case X86::SHL16mi: case X86::SHL32mi: case X86::SHL64mi: {
3716  // Optimize s{hr,ar,hl} $1, <op> to "shift <op>". Similar for rotate.
3717  // FIXME: It would be great if we could just do this with an InstAlias.
3718  if (!Inst.getOperand(X86::AddrNumOperands).isImm() ||
3719  Inst.getOperand(X86::AddrNumOperands).getImm() != 1)
3720  return false;
3721 
3722  unsigned NewOpc;
3723  switch (Inst.getOpcode()) {
3724  default: llvm_unreachable("Invalid opcode");
3725  case X86::RCR8mi: NewOpc = X86::RCR8m1; break;
3726  case X86::RCR16mi: NewOpc = X86::RCR16m1; break;
3727  case X86::RCR32mi: NewOpc = X86::RCR32m1; break;
3728  case X86::RCR64mi: NewOpc = X86::RCR64m1; break;
3729  case X86::RCL8mi: NewOpc = X86::RCL8m1; break;
3730  case X86::RCL16mi: NewOpc = X86::RCL16m1; break;
3731  case X86::RCL32mi: NewOpc = X86::RCL32m1; break;
3732  case X86::RCL64mi: NewOpc = X86::RCL64m1; break;
3733  case X86::ROR8mi: NewOpc = X86::ROR8m1; break;
3734  case X86::ROR16mi: NewOpc = X86::ROR16m1; break;
3735  case X86::ROR32mi: NewOpc = X86::ROR32m1; break;
3736  case X86::ROR64mi: NewOpc = X86::ROR64m1; break;
3737  case X86::ROL8mi: NewOpc = X86::ROL8m1; break;
3738  case X86::ROL16mi: NewOpc = X86::ROL16m1; break;
3739  case X86::ROL32mi: NewOpc = X86::ROL32m1; break;
3740  case X86::ROL64mi: NewOpc = X86::ROL64m1; break;
3741  case X86::SAR8mi: NewOpc = X86::SAR8m1; break;
3742  case X86::SAR16mi: NewOpc = X86::SAR16m1; break;
3743  case X86::SAR32mi: NewOpc = X86::SAR32m1; break;
3744  case X86::SAR64mi: NewOpc = X86::SAR64m1; break;
3745  case X86::SHR8mi: NewOpc = X86::SHR8m1; break;
3746  case X86::SHR16mi: NewOpc = X86::SHR16m1; break;
3747  case X86::SHR32mi: NewOpc = X86::SHR32m1; break;
3748  case X86::SHR64mi: NewOpc = X86::SHR64m1; break;
3749  case X86::SHL8mi: NewOpc = X86::SHL8m1; break;
3750  case X86::SHL16mi: NewOpc = X86::SHL16m1; break;
3751  case X86::SHL32mi: NewOpc = X86::SHL32m1; break;
3752  case X86::SHL64mi: NewOpc = X86::SHL64m1; break;
3753  }
3754 
3755  MCInst TmpInst;
3756  TmpInst.setOpcode(NewOpc);
3757  for (int i = 0; i != X86::AddrNumOperands; ++i)
3758  TmpInst.addOperand(Inst.getOperand(i));
3759  Inst = TmpInst;
3760  return true;
3761  }
3762  case X86::INT: {
3763  // Transforms "int $3" into "int3" as a size optimization. We can't write an
3764  // instalias with an immediate operand yet.
3765  if (!Inst.getOperand(0).isImm() || Inst.getOperand(0).getImm() != 3)
3766  return false;
3767 
3768  MCInst TmpInst;
3769  TmpInst.setOpcode(X86::INT3);
3770  Inst = TmpInst;
3771  return true;
3772  }
3773  }
3774 }
3775 
3776 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
3777  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
3778 
3779  switch (Inst.getOpcode()) {
3780  case X86::VGATHERDPDYrm:
3781  case X86::VGATHERDPDrm:
3782  case X86::VGATHERDPSYrm:
3783  case X86::VGATHERDPSrm:
3784  case X86::VGATHERQPDYrm:
3785  case X86::VGATHERQPDrm:
3786  case X86::VGATHERQPSYrm:
3787  case X86::VGATHERQPSrm:
3788  case X86::VPGATHERDDYrm:
3789  case X86::VPGATHERDDrm:
3790  case X86::VPGATHERDQYrm:
3791  case X86::VPGATHERDQrm:
3792  case X86::VPGATHERQDYrm:
3793  case X86::VPGATHERQDrm:
3794  case X86::VPGATHERQQYrm:
3795  case X86::VPGATHERQQrm: {
3796  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
3797  unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
3798  unsigned Index =
3799  MRI->getEncodingValue(Inst.getOperand(3 + X86::AddrIndexReg).getReg());
3800  if (Dest == Mask || Dest == Index || Mask == Index)
3801  return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
3802  "registers should be distinct");
3803  break;
3804  }
3805  case X86::VGATHERDPDZ128rm:
3806  case X86::VGATHERDPDZ256rm:
3807  case X86::VGATHERDPDZrm:
3808  case X86::VGATHERDPSZ128rm:
3809  case X86::VGATHERDPSZ256rm:
3810  case X86::VGATHERDPSZrm:
3811  case X86::VGATHERQPDZ128rm:
3812  case X86::VGATHERQPDZ256rm:
3813  case X86::VGATHERQPDZrm:
3814  case X86::VGATHERQPSZ128rm:
3815  case X86::VGATHERQPSZ256rm:
3816  case X86::VGATHERQPSZrm:
3817  case X86::VPGATHERDDZ128rm:
3818  case X86::VPGATHERDDZ256rm:
3819  case X86::VPGATHERDDZrm:
3820  case X86::VPGATHERDQZ128rm:
3821  case X86::VPGATHERDQZ256rm:
3822  case X86::VPGATHERDQZrm:
3823  case X86::VPGATHERQDZ128rm:
3824  case X86::VPGATHERQDZ256rm:
3825  case X86::VPGATHERQDZrm:
3826  case X86::VPGATHERQQZ128rm:
3827  case X86::VPGATHERQQZ256rm:
3828  case X86::VPGATHERQQZrm: {
3829  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
3830  unsigned Index =
3831  MRI->getEncodingValue(Inst.getOperand(4 + X86::AddrIndexReg).getReg());
3832  if (Dest == Index)
3833  return Warning(Ops[0]->getStartLoc(), "index and destination registers "
3834  "should be distinct");
3835  break;
3836  }
3837  case X86::V4FMADDPSrm:
3838  case X86::V4FMADDPSrmk:
3839  case X86::V4FMADDPSrmkz:
3840  case X86::V4FMADDSSrm:
3841  case X86::V4FMADDSSrmk:
3842  case X86::V4FMADDSSrmkz:
3843  case X86::V4FNMADDPSrm:
3844  case X86::V4FNMADDPSrmk:
3845  case X86::V4FNMADDPSrmkz:
3846  case X86::V4FNMADDSSrm:
3847  case X86::V4FNMADDSSrmk:
3848  case X86::V4FNMADDSSrmkz:
3849  case X86::VP4DPWSSDSrm:
3850  case X86::VP4DPWSSDSrmk:
3851  case X86::VP4DPWSSDSrmkz:
3852  case X86::VP4DPWSSDrm:
3853  case X86::VP4DPWSSDrmk:
3854  case X86::VP4DPWSSDrmkz: {
3855  unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
3857  unsigned Src2Enc = MRI->getEncodingValue(Src2);
3858  if (Src2Enc % 4 != 0) {
3860  unsigned GroupStart = (Src2Enc / 4) * 4;
3861  unsigned GroupEnd = GroupStart + 3;
3862  return Warning(Ops[0]->getStartLoc(),
3863  "source register '" + RegName + "' implicitly denotes '" +
3864  RegName.take_front(3) + Twine(GroupStart) + "' to '" +
3865  RegName.take_front(3) + Twine(GroupEnd) +
3866  "' source group");
3867  }
3868  break;
3869  }
3870  case X86::VFCMADDCPHZ128m:
3871  case X86::VFCMADDCPHZ256m:
3872  case X86::VFCMADDCPHZm:
3873  case X86::VFCMADDCPHZ128mb:
3874  case X86::VFCMADDCPHZ256mb:
3875  case X86::VFCMADDCPHZmb:
3876  case X86::VFCMADDCPHZ128mbk:
3877  case X86::VFCMADDCPHZ256mbk:
3878  case X86::VFCMADDCPHZmbk:
3879  case X86::VFCMADDCPHZ128mbkz:
3880  case X86::VFCMADDCPHZ256mbkz:
3881  case X86::VFCMADDCPHZmbkz:
3882  case X86::VFCMADDCPHZ128mk:
3883  case X86::VFCMADDCPHZ256mk:
3884  case X86::VFCMADDCPHZmk:
3885  case X86::VFCMADDCPHZ128mkz:
3886  case X86::VFCMADDCPHZ256mkz:
3887  case X86::VFCMADDCPHZmkz:
3888  case X86::VFCMADDCPHZ128r:
3889  case X86::VFCMADDCPHZ256r:
3890  case X86::VFCMADDCPHZr:
3891  case X86::VFCMADDCPHZ128rk:
3892  case X86::VFCMADDCPHZ256rk:
3893  case X86::VFCMADDCPHZrk:
3894  case X86::VFCMADDCPHZ128rkz:
3895  case X86::VFCMADDCPHZ256rkz:
3896  case X86::VFCMADDCPHZrkz:
3897  case X86::VFCMADDCPHZrb:
3898  case X86::VFCMADDCPHZrbk:
3899  case X86::VFCMADDCPHZrbkz:
3900  case X86::VFCMADDCSHZm:
3901  case X86::VFCMADDCSHZmk:
3902  case X86::VFCMADDCSHZmkz:
3903  case X86::VFCMADDCSHZr:
3904  case X86::VFCMADDCSHZrb:
3905  case X86::VFCMADDCSHZrbk:
3906  case X86::VFCMADDCSHZrbkz:
3907  case X86::VFCMADDCSHZrk:
3908  case X86::VFCMADDCSHZrkz:
3909  case X86::VFMADDCPHZ128m:
3910  case X86::VFMADDCPHZ256m:
3911  case X86::VFMADDCPHZm:
3912  case X86::VFMADDCPHZ128mb:
3913  case X86::VFMADDCPHZ256mb:
3914  case X86::VFMADDCPHZmb:
3915  case X86::VFMADDCPHZ128mbk:
3916  case X86::VFMADDCPHZ256mbk:
3917  case X86::VFMADDCPHZmbk:
3918  case X86::VFMADDCPHZ128mbkz:
3919  case X86::VFMADDCPHZ256mbkz:
3920  case X86::VFMADDCPHZmbkz:
3921  case X86::VFMADDCPHZ128mk:
3922  case X86::VFMADDCPHZ256mk:
3923  case X86::VFMADDCPHZmk:
3924  case X86::VFMADDCPHZ128mkz:
3925  case X86::VFMADDCPHZ256mkz:
3926  case X86::VFMADDCPHZmkz:
3927  case X86::VFMADDCPHZ128r:
3928  case X86::VFMADDCPHZ256r:
3929  case X86::VFMADDCPHZr:
3930  case X86::VFMADDCPHZ128rk:
3931  case X86::VFMADDCPHZ256rk:
3932  case X86::VFMADDCPHZrk:
3933  case X86::VFMADDCPHZ128rkz:
3934  case X86::VFMADDCPHZ256rkz:
3935  case X86::VFMADDCPHZrkz:
3936  case X86::VFMADDCPHZrb:
3937  case X86::VFMADDCPHZrbk:
3938  case X86::VFMADDCPHZrbkz:
3939  case X86::VFMADDCSHZm:
3940  case X86::VFMADDCSHZmk:
3941  case X86::VFMADDCSHZmkz:
3942  case X86::VFMADDCSHZr:
3943  case X86::VFMADDCSHZrb:
3944  case X86::VFMADDCSHZrbk:
3945  case X86::VFMADDCSHZrbkz:
3946  case X86::VFMADDCSHZrk:
3947  case X86::VFMADDCSHZrkz: {
3948  unsigned Dest = Inst.getOperand(0).getReg();
3949  for (unsigned i = 2; i < Inst.getNumOperands(); i++)
3950  if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
3951  return Warning(Ops[0]->getStartLoc(), "Destination register should be "
3952  "distinct from source registers");
3953  break;
3954  }
3955  case X86::VFCMULCPHZ128rm:
3956  case X86::VFCMULCPHZ256rm:
3957  case X86::VFCMULCPHZrm:
3958  case X86::VFCMULCPHZ128rmb:
3959  case X86::VFCMULCPHZ256rmb:
3960  case X86::VFCMULCPHZrmb:
3961  case X86::VFCMULCPHZ128rmbk:
3962  case X86::VFCMULCPHZ256rmbk:
3963  case X86::VFCMULCPHZrmbk:
3964  case X86::VFCMULCPHZ128rmbkz:
3965  case X86::VFCMULCPHZ256rmbkz:
3966  case X86::VFCMULCPHZrmbkz:
3967  case X86::VFCMULCPHZ128rmk:
3968  case X86::VFCMULCPHZ256rmk:
3969  case X86::VFCMULCPHZrmk:
3970  case X86::VFCMULCPHZ128rmkz:
3971  case X86::VFCMULCPHZ256rmkz:
3972  case X86::VFCMULCPHZrmkz:
3973  case X86::VFCMULCPHZ128rr:
3974  case X86::VFCMULCPHZ256rr:
3975  case X86::VFCMULCPHZrr:
3976  case X86::VFCMULCPHZ128rrk:
3977  case X86::VFCMULCPHZ256rrk:
3978  case X86::VFCMULCPHZrrk:
3979  case X86::VFCMULCPHZ128rrkz:
3980  case X86::VFCMULCPHZ256rrkz:
3981  case X86::VFCMULCPHZrrkz:
3982  case X86::VFCMULCPHZrrb:
3983  case X86::VFCMULCPHZrrbk:
3984  case X86::VFCMULCPHZrrbkz:
3985  case X86::VFCMULCSHZrm:
3986  case X86::VFCMULCSHZrmk:
3987  case X86::VFCMULCSHZrmkz:
3988  case X86::VFCMULCSHZrr:
3989  case X86::VFCMULCSHZrrb:
3990  case X86::VFCMULCSHZrrbk:
3991  case X86::VFCMULCSHZrrbkz:
3992  case X86::VFCMULCSHZrrk:
3993  case X86::VFCMULCSHZrrkz:
3994  case X86::VFMULCPHZ128rm:
3995  case X86::VFMULCPHZ256rm:
3996  case X86::VFMULCPHZrm:
3997  case X86::VFMULCPHZ128rmb:
3998  case X86::VFMULCPHZ256rmb:
3999  case X86::VFMULCPHZrmb:
4000  case X86::VFMULCPHZ128rmbk:
4001  case X86::VFMULCPHZ256rmbk:
4002  case X86::VFMULCPHZrmbk:
4003  case X86::VFMULCPHZ128rmbkz:
4004  case X86::VFMULCPHZ256rmbkz:
4005  case X86::VFMULCPHZrmbkz:
4006  case X86::VFMULCPHZ128rmk:
4007  case X86::VFMULCPHZ256rmk:
4008  case X86::VFMULCPHZrmk:
4009  case X86::VFMULCPHZ128rmkz:
4010  case X86::VFMULCPHZ256rmkz:
4011  case X86::VFMULCPHZrmkz:
4012  case X86::VFMULCPHZ128rr:
4013  case X86::VFMULCPHZ256rr:
4014  case X86::VFMULCPHZrr:
4015  case X86::VFMULCPHZ128rrk:
4016  case X86::VFMULCPHZ256rrk:
4017  case X86::VFMULCPHZrrk:
4018  case X86::VFMULCPHZ128rrkz:
4019  case X86::VFMULCPHZ256rrkz:
4020  case X86::VFMULCPHZrrkz:
4021  case X86::VFMULCPHZrrb:
4022  case X86::VFMULCPHZrrbk:
4023  case X86::VFMULCPHZrrbkz:
4024  case X86::VFMULCSHZrm:
4025  case X86::VFMULCSHZrmk:
4026  case X86::VFMULCSHZrmkz:
4027  case X86::VFMULCSHZrr:
4028  case X86::VFMULCSHZrrb:
4029  case X86::VFMULCSHZrrbk:
4030  case X86::VFMULCSHZrrbkz:
4031  case X86::VFMULCSHZrrk:
4032  case X86::VFMULCSHZrrkz: {
4033  unsigned Dest = Inst.getOperand(0).getReg();
4034  for (unsigned i = 1; i < Inst.getNumOperands(); i++)
4035  if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
4036  return Warning(Ops[0]->getStartLoc(), "Destination register should be "
4037  "distinct from source registers");
4038  break;
4039  }
4040  }
4041 
4042  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
4043  // Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to
4044  // check this with the legacy encoding, VEX/EVEX/XOP don't use REX.
4045  if ((MCID.TSFlags & X86II::EncodingMask) == 0) {
4046  MCPhysReg HReg = X86::NoRegister;
4047  bool UsesRex = MCID.TSFlags & X86II::REX_W;
4048  unsigned NumOps = Inst.getNumOperands();
4049  for (unsigned i = 0; i != NumOps; ++i) {
4050  const MCOperand &MO = Inst.getOperand(i);
4051  if (!MO.isReg())
4052  continue;
4053  unsigned Reg = MO.getReg();
4054  if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
4055  HReg = Reg;
4058  UsesRex = true;
4059  }
4060 
4061  if (UsesRex && HReg != X86::NoRegister) {
4063  return Error(Ops[0]->getStartLoc(),
4064  "can't encode '" + RegName + "' in an instruction requiring "
4065  "REX prefix");
4066  }
4067  }
4068 
4069  return false;
4070 }
4071 
4072 static const char *getSubtargetFeatureName(uint64_t Val);
4073 
4074 void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) {
4075  Warning(Loc, "Instruction may be vulnerable to LVI and "
4076  "requires manual mitigation");
4077  Note(SMLoc(), "See https://software.intel.com/"
4078  "security-software-guidance/insights/"
4079  "deep-dive-load-value-injection#specialinstructions"
4080  " for more information");
4081 }
4082 
4083 /// RET instructions and also instructions that indirect calls/jumps from memory
4084 /// combine a load and a branch within a single instruction. To mitigate these
4085 /// instructions against LVI, they must be decomposed into separate load and
4086 /// branch instructions, with an LFENCE in between. For more details, see:
4087 /// - X86LoadValueInjectionRetHardening.cpp
4088 /// - X86LoadValueInjectionIndirectThunks.cpp
4089 /// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4090 ///
4091 /// Returns `true` if a mitigation was applied or warning was emitted.
4092 void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
4093  // Information on control-flow instructions that require manual mitigation can
4094  // be found here:
4095  // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4096  switch (Inst.getOpcode()) {
4097  case X86::RET16:
4098  case X86::RET32:
4099  case X86::RET64:
4100  case X86::RETI16:
4101  case X86::RETI32:
4102  case X86::RETI64: {
4103  MCInst ShlInst, FenceInst;
4104  bool Parse32 = is32BitMode() || Code16GCC;
4105  unsigned Basereg =
4106  is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP);
4107  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
4108  auto ShlMemOp = X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
4109  /*BaseReg=*/Basereg, /*IndexReg=*/0,
4110  /*Scale=*/1, SMLoc{}, SMLoc{}, 0);
4111  ShlInst.setOpcode(X86::SHL64mi);
4112  ShlMemOp->addMemOperands(ShlInst, 5);
4113  ShlInst.addOperand(MCOperand::createImm(0));
4114  FenceInst.setOpcode(X86::LFENCE);
4115  Out.emitInstruction(ShlInst, getSTI());
4116  Out.emitInstruction(FenceInst, getSTI());
4117  return;
4118  }
4119  case X86::JMP16m:
4120  case X86::JMP32m:
4121  case X86::JMP64m:
4122  case X86::CALL16m:
4123  case X86::CALL32m:
4124  case X86::CALL64m:
4125  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4126  return;
4127  }
4128 }
4129 
4130 /// To mitigate LVI, every instruction that performs a load can be followed by
4131 /// an LFENCE instruction to squash any potential mis-speculation. There are
4132 /// some instructions that require additional considerations, and may requre
4133 /// manual mitigation. For more details, see:
4134 /// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4135 ///
4136 /// Returns `true` if a mitigation was applied or warning was emitted.
4137 void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
4138  MCStreamer &Out) {
4139  auto Opcode = Inst.getOpcode();
4140  auto Flags = Inst.getFlags();
4141  if ((Flags & X86::IP_HAS_REPEAT) || (Flags & X86::IP_HAS_REPEAT_NE)) {
4142  // Information on REP string instructions that require manual mitigation can
4143  // be found here:
4144  // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4145  switch (Opcode) {
4146  case X86::CMPSB:
4147  case X86::CMPSW:
4148  case X86::CMPSL:
4149  case X86::CMPSQ:
4150  case X86::SCASB:
4151  case X86::SCASW:
4152  case X86::SCASL:
4153  case X86::SCASQ:
4154  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4155  return;
4156  }
4157  } else if (Opcode == X86::REP_PREFIX || Opcode == X86::REPNE_PREFIX) {
4158  // If a REP instruction is found on its own line, it may or may not be
4159  // followed by a vulnerable instruction. Emit a warning just in case.
4160  emitWarningForSpecialLVIInstruction(Inst.getLoc());
4161  return;
4162  }
4163 
4164  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
4165 
4166  // Can't mitigate after terminators or calls. A control flow change may have
4167  // already occurred.
4168  if (MCID.isTerminator() || MCID.isCall())
4169  return;
4170 
4171  // LFENCE has the mayLoad property, don't double fence.
4172  if (MCID.mayLoad() && Inst.getOpcode() != X86::LFENCE) {
4173  MCInst FenceInst;
4174  FenceInst.setOpcode(X86::LFENCE);
4175  Out.emitInstruction(FenceInst, getSTI());
4176  }
4177 }
4178 
4179 void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
4180  MCStreamer &Out) {
4181  if (LVIInlineAsmHardening &&
4182  getSTI().getFeatureBits()[X86::FeatureLVIControlFlowIntegrity])
4183  applyLVICFIMitigation(Inst, Out);
4184 
4185  Out.emitInstruction(Inst, getSTI());
4186 
4187  if (LVIInlineAsmHardening &&
4188  getSTI().getFeatureBits()[X86::FeatureLVILoadHardening])
4189  applyLVILoadHardeningMitigation(Inst, Out);
4190 }
4191 
4192 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4194  MCStreamer &Out, uint64_t &ErrorInfo,
4195  bool MatchingInlineAsm) {
4196  if (isParsingIntelSyntax())
4197  return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
4198  MatchingInlineAsm);
4199  return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
4200  MatchingInlineAsm);
4201 }
4202 
4203 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
4205  bool MatchingInlineAsm) {
4206  // FIXME: This should be replaced with a real .td file alias mechanism.
4207  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
4208  // call.
4209  const char *Repl = StringSwitch<const char *>(Op.getToken())
4210  .Case("finit", "fninit")
4211  .Case("fsave", "fnsave")
4212  .Case("fstcw", "fnstcw")
4213  .Case("fstcww", "fnstcw")
4214  .Case("fstenv", "fnstenv")
4215  .Case("fstsw", "fnstsw")
4216  .Case("fstsww", "fnstsw")
4217  .Case("fclex", "fnclex")
4218  .Default(nullptr);
4219  if (Repl) {
4220  MCInst Inst;
4221  Inst.setOpcode(X86::WAIT);
4222  Inst.setLoc(IDLoc);
4223  if (!MatchingInlineAsm)
4224  emitInstruction(Inst, Operands, Out);
4225  Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
4226  }
4227 }
4228 
4229 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
4230  const FeatureBitset &MissingFeatures,
4231  bool MatchingInlineAsm) {
4232  assert(MissingFeatures.any() && "Unknown missing feature!");
4233  SmallString<126> Msg;
4234  raw_svector_ostream OS(Msg);
4235  OS << "instruction requires:";
4236  for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
4237  if (MissingFeatures[i])
4238  OS << ' ' << getSubtargetFeatureName(i);
4239  }
4240  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
4241 }
4242 
4244  unsigned Result = 0;
4245  X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
4246  if (Prefix.isPrefix()) {
4247  Result = Prefix.getPrefix();
4248  Operands.pop_back();
4249  }
4250  return Result;
4251 }
4252 
4253 unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4254  unsigned Opc = Inst.getOpcode();
4255  const MCInstrDesc &MCID = MII.get(Opc);
4256 
4257  if (ForcedVEXEncoding == VEXEncoding_EVEX &&
4259  return Match_Unsupported;
4260 
4261  if ((ForcedVEXEncoding == VEXEncoding_VEX ||
4262  ForcedVEXEncoding == VEXEncoding_VEX2 ||
4263  ForcedVEXEncoding == VEXEncoding_VEX3) &&
4265  return Match_Unsupported;
4266 
4267  // These instructions are only available with {vex}, {vex2} or {vex3} prefix
4268  if (MCID.TSFlags & X86II::ExplicitVEXPrefix &&
4269  (ForcedVEXEncoding != VEXEncoding_VEX &&
4270  ForcedVEXEncoding != VEXEncoding_VEX2 &&
4271  ForcedVEXEncoding != VEXEncoding_VEX3))
4272  return Match_Unsupported;
4273 
4274  return Match_Success;
4275 }
4276 
4277 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
4279  MCStreamer &Out,
4281  bool MatchingInlineAsm) {
4282  assert(!Operands.empty() && "Unexpect empty operand list!");
4283  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4284  SMRange EmptyRange = None;
4285 
4286  // First, handle aliases that expand to multiple instructions.
4287  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands,
4288  Out, MatchingInlineAsm);
4289  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4290  unsigned Prefixes = getPrefixes(Operands);
4291 
4292  MCInst Inst;
4293 
4294  // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
4295  // encoder and printer.
4296  if (ForcedVEXEncoding == VEXEncoding_VEX)
4297  Prefixes |= X86::IP_USE_VEX;
4298  else if (ForcedVEXEncoding == VEXEncoding_VEX2)
4299  Prefixes |= X86::IP_USE_VEX2;
4300  else if (ForcedVEXEncoding == VEXEncoding_VEX3)
4301  Prefixes |= X86::IP_USE_VEX3;
4302  else if (ForcedVEXEncoding == VEXEncoding_EVEX)
4303  Prefixes |= X86::IP_USE_EVEX;
4304 
4305  // Set encoded flags for {disp8} and {disp32}.
4306  if (ForcedDispEncoding == DispEncoding_Disp8)
4307  Prefixes |= X86::IP_USE_DISP8;
4308  else if (ForcedDispEncoding == DispEncoding_Disp32)
4309  Prefixes |= X86::IP_USE_DISP32;
4310 
4311  if (Prefixes)
4312  Inst.setFlags(Prefixes);
4313 
4314  // In 16-bit mode, if data32 is specified, temporarily switch to 32-bit mode
4315  // when matching the instruction.
4316  if (ForcedDataPrefix == X86::Mode32Bit)
4317  SwitchMode(X86::Mode32Bit);
4318  // First, try a direct match.
4319  FeatureBitset MissingFeatures;
4320  unsigned OriginalError = MatchInstruction(Operands, Inst, ErrorInfo,
4321  MissingFeatures, MatchingInlineAsm,
4322  isParsingIntelSyntax());
4323  if (ForcedDataPrefix == X86::Mode32Bit) {
4324  SwitchMode(X86::Mode16Bit);
4325  ForcedDataPrefix = 0;
4326  }
4327  switch (OriginalError) {
4328  default: llvm_unreachable("Unexpected match result!");
4329  case Match_Success:
4330  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4331  return true;
4332  // Some instructions need post-processing to, for example, tweak which
4333  // encoding is selected. Loop on it while changes happen so the
4334  // individual transformations can chain off each other.
4335  if (!MatchingInlineAsm)
4336  while (processInstruction(Inst, Operands))
4337  ;
4338 
4339  Inst.setLoc(IDLoc);
4340  if (!MatchingInlineAsm)
4341  emitInstruction(Inst, Operands, Out);
4342  Opcode = Inst.getOpcode();
4343  return false;
4344  case Match_InvalidImmUnsignedi4: {
4345  SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4346  if (ErrorLoc == SMLoc())
4347  ErrorLoc = IDLoc;
4348  return Error(ErrorLoc, "immediate must be an integer in range [0, 15]",
4349  EmptyRange, MatchingInlineAsm);
4350  }
4351  case Match_MissingFeature:
4352  return ErrorMissingFeature(IDLoc, MissingFeatures, MatchingInlineAsm);
4353  case Match_InvalidOperand:
4354  case Match_MnemonicFail:
4355  case Match_Unsupported:
4356  break;
4357  }
4358  if (Op.getToken().empty()) {
4359  Error(IDLoc, "instruction must have size higher than 0", EmptyRange,
4360  MatchingInlineAsm);
4361  return true;
4362  }
4363 
4364  // FIXME: Ideally, we would only attempt suffix matches for things which are
4365  // valid prefixes, and we could just infer the right unambiguous
4366  // type. However, that requires substantially more matcher support than the
4367  // following hack.
4368 
4369  // Change the operand to point to a temporary token.
4370  StringRef Base = Op.getToken();
4371  SmallString<16> Tmp;
4372  Tmp += Base;
4373  Tmp += ' ';
4374  Op.setTokenValue(Tmp);
4375 
4376  // If this instruction starts with an 'f', then it is a floating point stack
4377  // instruction. These come in up to three forms for 32-bit, 64-bit, and
4378  // 80-bit floating point, which use the suffixes s,l,t respectively.
4379  //
4380  // Otherwise, we assume that this may be an integer instruction, which comes
4381  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
4382  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
4383  // MemSize corresponding to Suffixes. { 8, 16, 32, 64 } { 32, 64, 80, 0 }
4384  const char *MemSize = Base[0] != 'f' ? "\x08\x10\x20\x40" : "\x20\x40\x50\0";
4385 
4386  // Check for the various suffix matches.
4387  uint64_t ErrorInfoIgnore;
4388  FeatureBitset ErrorInfoMissingFeatures; // Init suppresses compiler warnings.
4389  unsigned Match[4];
4390 
4391  // Some instruction like VPMULDQ is NOT the variant of VPMULD but a new one.
4392  // So we should make sure the suffix matcher only works for memory variant
4393  // that has the same size with the suffix.
4394  // FIXME: This flag is a workaround for legacy instructions that didn't
4395  // declare non suffix variant assembly.
4396  bool HasVectorReg = false;
4397  X86Operand *MemOp = nullptr;
4398  for (const auto &Op : Operands) {
4399  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4400  if (X86Op->isVectorReg())
4401  HasVectorReg = true;
4402  else if (X86Op->isMem()) {
4403  MemOp = X86Op;
4404  assert(MemOp->Mem.Size == 0 && "Memory size always 0 under ATT syntax");
4405  // Have we found an unqualified memory operand,
4406  // break. IA allows only one memory operand.
4407  break;
4408  }
4409  }
4410 
4411  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
4412  Tmp.back() = Suffixes[I];
4413  if (MemOp && HasVectorReg)
4414  MemOp->Mem.Size = MemSize[I];
4415  Match[I] = Match_MnemonicFail;
4416  if (MemOp || !HasVectorReg) {
4417  Match[I] =
4418  MatchInstruction(Operands, Inst, ErrorInfoIgnore, MissingFeatures,
4419  MatchingInlineAsm, isParsingIntelSyntax());
4420  // If this returned as a missing feature failure, remember that.
4421  if (Match[I] == Match_MissingFeature)
4422  ErrorInfoMissingFeatures = MissingFeatures;
4423  }
4424  }
4425 
4426  // Restore the old token.
4427  Op.setTokenValue(Base);
4428 
4429  // If exactly one matched, then we treat that as a successful match (and the
4430  // instruction will already have been filled in correctly, since the failing
4431  // matches won't have modified it).
4432  unsigned NumSuccessfulMatches = llvm::count(Match, Match_Success);
4433  if (NumSuccessfulMatches == 1) {
4434  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4435  return true;
4436  // Some instructions need post-processing to, for example, tweak which
4437  // encoding is selected. Loop on it while changes happen so the
4438  // individual transformations can chain off each other.
4439  if (!MatchingInlineAsm)
4440  while (processInstruction(Inst, Operands))
4441  ;
4442 
4443  Inst.setLoc(IDLoc);
4444  if (!MatchingInlineAsm)
4445  emitInstruction(Inst, Operands, Out);
4446  Opcode = Inst.getOpcode();
4447  return false;
4448  }
4449 
4450  // Otherwise, the match failed, try to produce a decent error message.
4451 
4452  // If we had multiple suffix matches, then identify this as an ambiguous
4453  // match.
4454  if (NumSuccessfulMatches > 1) {
4455  char MatchChars[4];
4456  unsigned NumMatches = 0;
4457  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
4458  if (Match[I] == Match_Success)
4459  MatchChars[NumMatches++] = Suffixes[I];
4460 
4461  SmallString<126> Msg;
4462  raw_svector_ostream OS(Msg);
4463  OS << "ambiguous instructions require an explicit suffix (could be ";
4464  for (unsigned i = 0; i != NumMatches; ++i) {
4465  if (i != 0)
4466  OS << ", ";
4467  if (i + 1 == NumMatches)
4468  OS << "or ";
4469  OS << "'" << Base << MatchChars[i] << "'";
4470  }
4471  OS << ")";
4472  Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
4473  return true;
4474  }
4475 
4476  // Okay, we know that none of the variants matched successfully.
4477 
4478  // If all of the instructions reported an invalid mnemonic, then the original
4479  // mnemonic was invalid.
4480  if (llvm::count(Match, Match_MnemonicFail) == 4) {
4481  if (OriginalError == Match_MnemonicFail)
4482  return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
4483  Op.getLocRange(), MatchingInlineAsm);
4484 
4485  if (OriginalError == Match_Unsupported)
4486  return Error(IDLoc, "unsupported instruction", EmptyRange,
4487  MatchingInlineAsm);
4488 
4489  assert(OriginalError == Match_InvalidOperand && "Unexpected error");
4490  // Recover location info for the operand if we know which was the problem.
4491  if (ErrorInfo != ~0ULL) {
4492  if (ErrorInfo >= Operands.size())
4493  return Error(IDLoc, "too few operands for instruction", EmptyRange,
4494  MatchingInlineAsm);
4495 
4496  X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
4497  if (Operand.getStartLoc().isValid()) {
4498  SMRange OperandRange = Operand.getLocRange();
4499  return Error(Operand.getStartLoc(), "invalid operand for instruction",
4500  OperandRange, MatchingInlineAsm);
4501  }
4502  }
4503 
4504  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4505  MatchingInlineAsm);
4506  }
4507 
4508  // If one instruction matched as unsupported, report this as unsupported.
4509  if (llvm::count(Match, Match_Unsupported) == 1) {
4510  return Error(IDLoc, "unsupported instruction", EmptyRange,
4511  MatchingInlineAsm);
4512  }
4513 
4514  // If one instruction matched with a missing feature, report this as a
4515  // missing feature.
4516  if (llvm::count(Match, Match_MissingFeature) == 1) {
4517  ErrorInfo = Match_MissingFeature;
4518  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
4519  MatchingInlineAsm);
4520  }
4521 
4522  // If one instruction matched with an invalid operand, report this as an
4523  // operand failure.
4524  if (llvm::count(Match, Match_InvalidOperand) == 1) {
4525  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4526  MatchingInlineAsm);
4527  }
4528 
4529  // If all of these were an outright failure, report it in a useless way.
4530  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
4531  EmptyRange, MatchingInlineAsm);
4532  return true;
4533 }
4534 
4535 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
4537  MCStreamer &Out,
4539  bool MatchingInlineAsm) {
4540  assert(!Operands.empty() && "Unexpect empty operand list!");
4541  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4542  StringRef Mnemonic = (static_cast<X86Operand &>(*Operands[0])).getToken();
4543  SMRange EmptyRange = None;
4544  StringRef Base = (static_cast<X86Operand &>(*Operands[0])).getToken();
4545  unsigned Prefixes = getPrefixes(Operands);
4546 
4547  // First, handle aliases that expand to multiple instructions.
4548  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands, Out, MatchingInlineAsm);
4549  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4550 
4551  MCInst Inst;
4552 
4553  // If VEX/EVEX encoding is forced, we need to pass the USE_* flag to the
4554  // encoder and printer.
4555  if (ForcedVEXEncoding == VEXEncoding_VEX)
4556  Prefixes |= X86::IP_USE_VEX;
4557  else if (ForcedVEXEncoding == VEXEncoding_VEX2)
4558  Prefixes |= X86::IP_USE_VEX2;
4559  else if (ForcedVEXEncoding == VEXEncoding_VEX3)
4560  Prefixes |= X86::IP_USE_VEX3;
4561  else if (ForcedVEXEncoding == VEXEncoding_EVEX)
4562  Prefixes |= X86::IP_USE_EVEX;
4563 
4564  // Set encoded flags for {disp8} and {disp32}.
4565  if (ForcedDispEncoding == DispEncoding_Disp8)
4566  Prefixes |= X86::IP_USE_DISP8;
4567  else if (ForcedDispEncoding == DispEncoding_Disp32)
4568  Prefixes |= X86::IP_USE_DISP32;
4569 
4570  if (Prefixes)
4571  Inst.setFlags(Prefixes);
4572 
4573  // Find one unsized memory operand, if present.
4574  X86Operand *UnsizedMemOp = nullptr;
4575  for (const auto &Op : Operands) {
4576  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4577  if (X86Op->isMemUnsized()) {
4578  UnsizedMemOp = X86Op;
4579  // Have we found an unqualified memory operand,
4580  // break. IA allows only one memory operand.
4581  break;
4582  }
4583  }
4584 
4585  // Allow some instructions to have implicitly pointer-sized operands. This is
4586  // compatible with gas.
4587  if (UnsizedMemOp) {
4588  static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
4589  for (const char *Instr : PtrSizedInstrs) {
4590  if (Mnemonic == Instr) {
4591  UnsizedMemOp->Mem.Size = getPointerWidth();
4592  break;
4593  }
4594  }
4595  }
4596 
4598  FeatureBitset ErrorInfoMissingFeatures;
4599  FeatureBitset MissingFeatures;
4600 
4601  // If unsized push has immediate operand we should default the default pointer
4602  // size for the size.
4603  if (Mnemonic == "push" && Operands.size() == 2) {
4604  auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
4605  if (X86Op->isImm()) {
4606  // If it's not a constant fall through and let remainder take care of it.
4607  const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
4608  unsigned Size = getPointerWidth();
4609  if (CE &&
4610  (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
4611  SmallString<16> Tmp;
4612  Tmp += Base;
4613  Tmp += (is64BitMode())
4614  ? "q"
4615  : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
4616  Op.setTokenValue(Tmp);
4617  // Do match in ATT mode to allow explicit suffix usage.
4618  Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
4619  MissingFeatures, MatchingInlineAsm,
4620  false /*isParsingIntelSyntax()*/));
4621  Op.setTokenValue(Base);
4622  }
4623  }
4624  }
4625 
4626  // If an unsized memory operand is present, try to match with each memory
4627  // operand size. In Intel assembly, the size is not part of the instruction
4628  // mnemonic.
4629  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
4630  static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
4631  for (unsigned Size : MopSizes) {
4632  UnsizedMemOp->Mem.Size = Size;
4633  uint64_t ErrorInfoIgnore;
4634  unsigned LastOpcode = Inst.getOpcode();
4635  unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
4636  MissingFeatures, MatchingInlineAsm,
4637  isParsingIntelSyntax());
4638  if (Match.empty() || LastOpcode != Inst.getOpcode())
4639  Match.push_back(M);
4640 
4641  // If this returned as a missing feature failure, remember that.
4642  if (Match.back() == Match_MissingFeature)
4643  ErrorInfoMissingFeatures = MissingFeatures;
4644  }
4645 
4646  // Restore the size of the unsized memory operand if we modified it.
4647  UnsizedMemOp->Mem.Size = 0;
4648  }
4649 
4650  // If we haven't matched anything yet, this is not a basic integer or FPU
4651  // operation. There shouldn't be any ambiguity in our mnemonic table, so try
4652  // matching with the unsized operand.
4653  if (Match.empty()) {
4654  Match.push_back(MatchInstruction(
4655  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
4656  isParsingIntelSyntax()));
4657  // If this returned as a missing feature failure, remember that.
4658  if (Match.back() == Match_MissingFeature)
4659  ErrorInfoMissingFeatures = MissingFeatures;
4660  }
4661 
4662  // Restore the size of the unsized memory operand if we modified it.
4663  if (UnsizedMemOp)
4664  UnsizedMemOp->Mem.Size = 0;
4665 
4666  // If it's a bad mnemonic, all results will be the same.
4667  if (Match.back() == Match_MnemonicFail) {
4668  return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
4669  Op.getLocRange(), MatchingInlineAsm);
4670  }
4671 
4672  unsigned NumSuccessfulMatches = llvm::count(Match, Match_Success);
4673 
4674  // If matching was ambiguous and we had size information from the frontend,
4675  // try again with that. This handles cases like "movxz eax, m8/m16".
4676  if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
4677  UnsizedMemOp->getMemFrontendSize()) {
4678  UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
4679  unsigned M = MatchInstruction(
4680  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
4681  isParsingIntelSyntax());
4682  if (M == Match_Success)
4683  NumSuccessfulMatches = 1;
4684 
4685  // Add a rewrite that encodes the size information we used from the
4686  // frontend.
4687  InstInfo->AsmRewrites->emplace_back(
4688  AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
4689  /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
4690  }
4691 
4692  // If exactly one matched, then we treat that as a successful match (and the
4693  // instruction will already have been filled in correctly, since the failing
4694  // matches won't have modified it).
4695  if (NumSuccessfulMatches == 1) {
4696  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
4697  return true;
4698  // Some instructions need post-processing to, for example, tweak which
4699  // encoding is selected. Loop on it while changes happen so the individual
4700  // transformations can chain off each other.
4701  if (!MatchingInlineAsm)
4702  while (processInstruction(Inst, Operands))
4703  ;
4704  Inst.setLoc(IDLoc);
4705  if (!MatchingInlineAsm)
4706  emitInstruction(Inst, Operands, Out);
4707  Opcode = Inst.getOpcode();
4708  return false;
4709  } else if (NumSuccessfulMatches > 1) {
4710  assert(UnsizedMemOp &&
4711  "multiple matches only possible with unsized memory operands");
4712  return Error(UnsizedMemOp->getStartLoc(),
4713  "ambiguous operand size for instruction '" + Mnemonic + "\'",
4714  UnsizedMemOp->getLocRange());
4715  }
4716 
4717  // If one instruction matched as unsupported, report this as unsupported.
4718  if (llvm::count(Match, Match_Unsupported) == 1) {
4719  return Error(IDLoc, "unsupported instruction", EmptyRange,
4720  MatchingInlineAsm);
4721  }
4722 
4723  // If one instruction matched with a missing feature, report this as a
4724  // missing feature.
4725  if (llvm::count(Match, Match_MissingFeature) == 1) {
4726  ErrorInfo = Match_MissingFeature;
4727  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
4728  MatchingInlineAsm);
4729  }
4730 
4731  // If one instruction matched with an invalid operand, report this as an
4732  // operand failure.
4733  if (llvm::count(Match, Match_InvalidOperand) == 1) {
4734  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
4735  MatchingInlineAsm);
4736  }
4737 
4738  if (llvm::count(Match, Match_InvalidImmUnsignedi4) == 1) {
4739  SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4740  if (ErrorLoc == SMLoc())
4741  ErrorLoc = IDLoc;
4742  return Error(ErrorLoc, "immediate must be an integer in range [0, 15]",
4743  EmptyRange, MatchingInlineAsm);
4744  }
4745 
4746  // If all of these were an outright failure, report it in a useless way.
4747  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
4748  MatchingInlineAsm);
4749 }
4750 
4751 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
4752  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
4753 }
4754 
4755 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
4756  MCAsmParser &Parser = getParser();
4757  StringRef IDVal = DirectiveID.getIdentifier();
4758  if (IDVal.startswith(".arch"))
4759  return parseDirectiveArch();
4760  if (IDVal.startswith(".code"))
4761  return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
4762  else if (IDVal.startswith(".att_syntax")) {
4763  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4764  if (Parser.getTok().getString() == "prefix")
4765  Parser.Lex();
4766  else if (Parser.getTok().getString() == "noprefix")
4767  return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
4768  "supported: registers must have a "
4769  "'%' prefix in .att_syntax");
4770  }
4771  getParser().setAssemblerDialect(0);
4772  return false;
4773  } else if (IDVal.startswith(".intel_syntax")) {
4774  getParser().setAssemblerDialect(1);
4775  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4776  if (Parser.getTok().getString() == "noprefix")
4777  Parser.Lex();
4778  else if (Parser.getTok().getString() == "prefix")
4779  return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
4780  "supported: registers must not have "
4781  "a '%' prefix in .intel_syntax");
4782  }
4783  return false;
4784  } else if (IDVal == ".nops")
4785  return parseDirectiveNops(DirectiveID.getLoc());
4786  else if (IDVal == ".even")
4787  return parseDirectiveEven(DirectiveID.getLoc());
4788  else if (IDVal == ".cv_fpo_proc")
4789  return parseDirectiveFPOProc(DirectiveID.getLoc());
4790  else if (IDVal == ".cv_fpo_setframe")
4791  return parseDirectiveFPOSetFrame(DirectiveID.getLoc());
4792  else if (IDVal == ".cv_fpo_pushreg")
4793  return parseDirectiveFPOPushReg(DirectiveID.getLoc());
4794  else if (IDVal == ".cv_fpo_stackalloc")
4795  return parseDirectiveFPOStackAlloc(DirectiveID.getLoc());
4796  else if (IDVal == ".cv_fpo_stackalign")
4797  return parseDirectiveFPOStackAlign(DirectiveID.getLoc());
4798  else if (IDVal == ".cv_fpo_endprologue")
4799  return parseDirectiveFPOEndPrologue(DirectiveID.getLoc());
4800  else if (IDVal == ".cv_fpo_endproc")
4801  return parseDirectiveFPOEndProc(DirectiveID.getLoc());
4802  else if (IDVal == ".seh_pushreg" ||
4803  (Parser.isParsingMasm() && IDVal.equals_insensitive(".pushreg")))
4804  return parseDirectiveSEHPushReg(DirectiveID.getLoc());
4805  else if (IDVal == ".seh_setframe" ||
4806  (Parser.isParsingMasm() && IDVal.equals_insensitive(".setframe")))
4807  return parseDirectiveSEHSetFrame(DirectiveID.getLoc());
4808  else if (IDVal == ".seh_savereg" ||
4809  (Parser.isParsingMasm() && IDVal.equals_insensitive(".savereg")))
4810  return parseDirectiveSEHSaveReg(DirectiveID.getLoc());
4811  else if (IDVal == ".seh_savexmm" ||
4812  (Parser.isParsingMasm() && IDVal.equals_insensitive(".savexmm128")))
4813  return parseDirectiveSEHSaveXMM(DirectiveID.getLoc());
4814  else if (IDVal == ".seh_pushframe" ||
4815  (Parser.isParsingMasm() && IDVal.equals_insensitive(".pushframe")))
4816  return parseDirectiveSEHPushFrame(DirectiveID.getLoc());
4817 
4818  return true;
4819 }
4820 
4821 bool X86AsmParser::parseDirectiveArch() {
4822  // Ignore .arch for now.
4823  getParser().parseStringToEndOfStatement();
4824  return false;
4825 }
4826 
4827 /// parseDirectiveNops
4828 /// ::= .nops size[, control]
4829 bool X86AsmParser::parseDirectiveNops(SMLoc L) {
4830  int64_t NumBytes = 0, Control = 0;
4831  SMLoc NumBytesLoc, ControlLoc;
4832  const MCSubtargetInfo& STI = getSTI();
4833  NumBytesLoc = getTok().getLoc();
4834  if (getParser().checkForValidSection() ||
4835  getParser().parseAbsoluteExpression(NumBytes))
4836  return true;
4837 
4838  if (parseOptionalToken(AsmToken::Comma)) {
4839  ControlLoc = getTok().getLoc();
4840  if (getParser().parseAbsoluteExpression(Control))
4841  return true;
4842  }
4843  if (getParser().parseToken(AsmToken::EndOfStatement,
4844  "unexpected token in '.nops' directive"))
4845  return true;
4846 
4847  if (NumBytes <= 0) {
4848  Error(NumBytesLoc, "'.nops' directive with non-positive size");
4849  return false;
4850  }
4851 
4852  if (Control < 0) {
4853  Error(ControlLoc, "'.nops' directive with negative NOP size");
4854  return false;
4855  }
4856 
4857  /// Emit nops
4858  getParser().getStreamer().emitNops(NumBytes, Control, L, STI);
4859 
4860  return false;
4861 }
4862 
4863 /// parseDirectiveEven
4864 /// ::= .even
4865 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
4866  if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
4867  return false;
4868 
4869  const MCSection *Section = getStreamer().getCurrentSectionOnly();
4870  if (!Section) {
4871  getStreamer().initSections(false, getSTI());
4872  Section = getStreamer().getCurrentSectionOnly();
4873  }
4874  if (Section->UseCodeAlign())
4875  getStreamer().emitCodeAlignment(2, &getSTI(), 0);
4876  else
4877  getStreamer().emitValueToAlignment(2, 0, 1, 0);
4878  return false;
4879 }
4880 
4881 /// ParseDirectiveCode
4882 /// ::= .code16 | .code32 | .code64
4883 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
4884  MCAsmParser &Parser = getParser();
4885  Code16GCC = false;
4886  if (IDVal == ".code16") {
4887  Parser.Lex();
4888  if (!is16BitMode()) {
4889  SwitchMode(X86::Mode16Bit);
4890  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
4891  }
4892  } else if (IDVal == ".code16gcc") {
4893  // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
4894  Parser.Lex();
4895  Code16GCC = true;
4896  if (!is16BitMode()) {
4897  SwitchMode(X86::Mode16Bit);
4898  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
4899  }
4900  } else if (IDVal == ".code32") {
4901  Parser.Lex();
4902  if (!is32BitMode()) {
4903  SwitchMode(X86::Mode32Bit);
4904  getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
4905  }
4906  } else if (IDVal == ".code64") {
4907  Parser.Lex();
4908  if (!is64BitMode()) {
4909  SwitchMode(X86::Mode64Bit);
4910  getParser().getStreamer().emitAssemblerFlag(MCAF_Code64);
4911  }
4912  } else {
4913  Error(L, "unknown directive " + IDVal);
4914  return false;
4915  }
4916 
4917  return false;
4918 }
4919 
4920 // .cv_fpo_proc foo
4921 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
4922  MCAsmParser &Parser = getParser();
4923  StringRef ProcName;
4924  int64_t ParamsSize;
4925  if (Parser.parseIdentifier(ProcName))
4926  return Parser.TokError("expected symbol name");
4927  if (Parser.parseIntToken(ParamsSize, "expected parameter byte count"))
4928  return true;
4929  if (!isUIntN(32, ParamsSize))
4930  return Parser.TokError("parameters size out of range");
4931  if (parseEOL())
4932  return true;
4933  MCSymbol *ProcSym = getContext().getOrCreateSymbol(ProcName);
4934  return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
4935 }
4936 
4937 // .cv_fpo_setframe ebp
4938 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
4939  unsigned Reg;
4940  SMLoc DummyLoc;
4941  if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
4942  return true;
4943  return getTargetStreamer().emitFPOSetFrame(Reg, L);
4944 }
4945 
4946 // .cv_fpo_pushreg ebx
4947 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
4948  unsigned Reg;
4949  SMLoc DummyLoc;
4950  if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
4951  return true;
4952  return getTargetStreamer().emitFPOPushReg(Reg, L);
4953 }
4954 
4955 // .cv_fpo_stackalloc 20
4956 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
4957  MCAsmParser &Parser = getParser();
4958  int64_t Offset;
4959  if (Parser.parseIntToken(Offset, "expected offset") || parseEOL())
4960  return true;
4961  return getTargetStreamer().emitFPOStackAlloc(Offset, L);
4962 }
4963 
4964 // .cv_fpo_stackalign 8
4965 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
4966  MCAsmParser &Parser = getParser();
4967  int64_t Offset;
4968  if (Parser.parseIntToken(Offset, "expected offset") || parseEOL())
4969  return true;
4970  return getTargetStreamer().emitFPOStackAlign(Offset, L);
4971 }
4972 
4973 // .cv_fpo_endprologue
4974 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
4975  MCAsmParser &Parser = getParser();
4976  if (Parser.parseEOL())
4977  return true;
4978  return getTargetStreamer().emitFPOEndPrologue(L);
4979 }
4980 
4981 // .cv_fpo_endproc
4982 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
4983  MCAsmParser &Parser = getParser();
4984  if (Parser.parseEOL())
4985  return true;
4986  return getTargetStreamer().emitFPOEndProc(L);
4987 }
4988 
4989 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
4990  unsigned &RegNo) {
4991  SMLoc startLoc = getLexer().getLoc();
4992  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
4993 
4994  // Try parsing the argument as a register first.
4995  if (getLexer().getTok().isNot(AsmToken::Integer)) {
4996  SMLoc endLoc;
4997  if (ParseRegister(RegNo, startLoc, endLoc))
4998  return true;
4999 
5000  if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) {
5001  return Error(startLoc,
5002  "register is not supported for use with this directive");
5003  }
5004  } else {
5005  // Otherwise, an integer number matching the encoding of the desired
5006  // register may appear.
5007  int64_t EncodedReg;
5008  if (getParser().parseAbsoluteExpression(EncodedReg))
5009  return true;
5010 
5011  // The SEH register number is the same as the encoding register number. Map
5012  // from the encoding back to the LLVM register number.
5013  RegNo = 0;
5014  for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
5015  if (MRI->getEncodingValue(Reg) == EncodedReg) {
5016  RegNo = Reg;
5017  break;
5018  }
5019  }
5020  if (RegNo == 0) {
5021  return Error(startLoc,
5022  "incorrect register number for use with this directive");
5023  }
5024  }
5025 
5026  return false;
5027 }
5028 
5029 bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
5030  unsigned Reg = 0;
5031  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5032  return true;
5033 
5034  if (getLexer().isNot(AsmToken::EndOfStatement))
5035  return TokError("unexpected token in directive");
5036 
5037  getParser().Lex();
5038  getStreamer().EmitWinCFIPushReg(Reg, Loc);
5039  return false;
5040 }
5041 
5042 bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
5043  unsigned Reg = 0;
5044  int64_t Off;
5045  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5046  return true;
5047  if (getLexer().isNot(AsmToken::Comma))
5048  return TokError("you must specify a stack pointer offset");
5049 
5050  getParser().Lex();
5051  if (getParser().parseAbsoluteExpression(Off))
5052  return true;
5053 
5054  if (getLexer().isNot(AsmToken::EndOfStatement))
5055  return TokError("unexpected token in directive");
5056 
5057  getParser().Lex();
5058  getStreamer().EmitWinCFISetFrame(Reg, Off, Loc);
5059  return false;
5060 }
5061 
5062 bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
5063  unsigned Reg = 0;
5064  int64_t Off;
5065  if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
5066  return true;
5067  if (getLexer().isNot(AsmToken::Comma))
5068  return TokError("you must specify an offset on the stack");
5069 
5070  getParser().Lex();
5071  if (getParser().parseAbsoluteExpression(Off))
5072  return true;
5073 
5074  if (getLexer().isNot(AsmToken::EndOfStatement))
5075  return TokError("unexpected token in directive");
5076 
5077  getParser().Lex();
5078  getStreamer().EmitWinCFISaveReg(Reg, Off, Loc);
5079  return false;
5080 }
5081 
5082 bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) {
5083  unsigned Reg = 0;
5084  int64_t Off;
5085  if (parseSEHRegisterNumber(X86::VR128XRegClassID, Reg))
5086  return true;
5087  if (getLexer().isNot(AsmToken::Comma))
5088  return TokError("you must specify an offset on the stack");
5089 
5090  getParser().Lex();
5091  if (getParser().parseAbsoluteExpression(Off))
5092  return true;
5093 
5094  if (getLexer().isNot(AsmToken::EndOfStatement))
5095  return TokError("unexpected token in directive");
5096 
5097  getParser().Lex();
5098  getStreamer().EmitWinCFISaveXMM(Reg, Off, Loc);
5099  return false;
5100 }
5101 
5102 bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) {
5103  bool Code = false;
5104  StringRef CodeID;
5105  if (getLexer().is(AsmToken::At)) {
5106  SMLoc startLoc = getLexer().getLoc();
5107  getParser().Lex();
5108  if (!getParser().parseIdentifier(CodeID)) {
5109  if (CodeID != "code")
5110  return Error(startLoc, "expected @code");
5111  Code = true;
5112  }
5113  }
5114 
5115  if (getLexer().isNot(AsmToken::EndOfStatement))
5116  return TokError("unexpected token in directive");
5117 
5118  getParser().Lex();
5119  getStreamer().EmitWinCFIPushFrame(Code, Loc);
5120  return false;
5121 }
5122 
5123 // Force static initialization.
5127 }
5128 
5129 #define GET_REGISTER_MATCHER
5130 #define GET_MATCHER_IMPLEMENTATION
5131 #define GET_SUBTARGET_FEATURE_NAME
5132 #include "X86GenAsmMatcher.inc"
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::MCTargetStreamer::getStreamer
MCStreamer & getStreamer()
Definition: MCStreamer.h:98
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
checkScale
static bool checkScale(unsigned Scale, StringRef &ErrMsg)
Definition: X86AsmParser.cpp:49
i
i
Definition: README.txt:29
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
llvm::StringRef::back
LLVM_NODISCARD char back() const
back - Get the last character in the string.
Definition: StringRef.h:167
llvm::AsmFieldInfo::Offset
unsigned Offset
Definition: MCAsmParser.h:105
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:285
llvm::MCAsmParser::Error
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:99
getSubtargetFeatureName
static const char * getSubtargetFeatureName(uint64_t Val)
llvm::X86Operand::getEndLoc
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:90
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::AsmToken::is
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
llvm::X86Operand::Mem
struct MemOp Mem
Definition: X86Operand.h:75
llvm::MCAsmLexer
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:39
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:164
llvm::pdb::PDB_DataKind::Member
@ Member
llvm::StringRef::endswith
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:296
llvm::X86::TO_POS_INF
@ TO_POS_INF
Definition: X86BaseInfo.h:49
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::AsmToken::LBrac
@ LBrac
Definition: MCAsmMacro.h:48
Note
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles Note
Definition: README.txt:239
llvm::AsmToken::Dot
@ Dot
Definition: MCAsmMacro.h:49
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
llvm::AsmToken::EndOfStatement
@ EndOfStatement
Definition: MCAsmMacro.h:42
llvm::X86Operand::isMem8
bool isMem8() const
Definition: X86Operand.h:300
llvm::MCAsmParser::parseEOL
bool parseEOL()
Definition: MCAsmParser.cpp:47
llvm::AsmToken::getIntVal
int64_t getIntVal() const
Definition: MCAsmMacro.h:115
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:59
llvm::X86::COND_BE
@ COND_BE
Definition: X86BaseInfo.h:87
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::tgtok::Code
@ Code
Definition: TGLexer.h:50
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
MCParsedAsmOperand.h
llvm::MCAsmParser::parseIdentifier
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents.
CH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference CH
Definition: README-X86-64.txt:44
llvm::X86::COND_P
@ COND_P
Definition: X86BaseInfo.h:91
llvm::X86::COND_GE
@ COND_GE
Definition: X86BaseInfo.h:94
llvm::MCSymbol::isUndefined
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:252
llvm::pdb::PDB_BuiltinType::Variant
@ Variant
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MemOp
Definition: TargetLowering.h:111
llvm::X86::COND_L
@ COND_L
Definition: X86BaseInfo.h:93
llvm::X86::IP_HAS_LOCK
@ IP_HAS_LOCK
Definition: X86BaseInfo.h:62
startswith
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:30
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::X86::IP_USE_DISP8
@ IP_USE_DISP8
Definition: X86BaseInfo.h:68
llvm::AsmToken::Integer
@ Integer
Definition: MCAsmMacro.h:32
llvm::MCAsmParser::parseOptionalToken
bool parseOptionalToken(AsmToken::TokenKind T)
Attempt to parse and consume token, returning true on success.
Definition: MCAsmParser.cpp:78
llvm::AsmTypeInfo::Name
StringRef Name
Definition: MCAsmParser.h:97
llvm::FenceInst
An instruction for ordering other memory operations.
Definition: Instructions.h:449
llvm::X86Operand::isMem
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:296
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::InlineAsmIdentifierInfo
Definition: MCAsmParser.h:37
STLExtras.h
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:644
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
llvm::X86::CondCode
CondCode
Definition: X86BaseInfo.h:80
llvm::InlineAsmIdentifierInfo::IK_EnumVal
@ IK_EnumVal
Definition: MCAsmParser.h:41
llvm::StringRef::slice
LLVM_NODISCARD StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:731
llvm::X86::COND_INVALID
@ COND_INVALID
Definition: X86BaseInfo.h:107
llvm::getX86SubSuperRegisterOrZero
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:640
getSym
static ModuleSymbolTable::Symbol getSym(DataRefImpl &Symb)
Definition: IRObjectFile.cpp:37
MCAsmParser.h
llvm::X86::COND_S
@ COND_S
Definition: X86BaseInfo.h:89
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
MCTargetAsmParser.h
llvm::X86::IP_HAS_NOTRACK
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:63
llvm::X86Operand::isReg
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:466
llvm::MCAsmParser::parseAbsoluteExpression
virtual bool parseAbsoluteExpression(int64_t &Res)=0
Parse an expression which must evaluate to an absolute value.
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
llvm::HighlightColor::Warning
@ Warning
llvm::X86::COND_O
@ COND_O
Definition: X86BaseInfo.h:81
llvm::X86Operand::CreatePrefix
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:648
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::AsmToken::Minus
@ Minus
Definition: MCAsmMacro.h:45
llvm::ARMBuildAttrs::Section
@ Section
Legacy Tags.
Definition: ARMBuildAttributes.h:82
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:610
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
CommandLine.h
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:198
LHS
Value * LHS
Definition: X86PartialReduction.cpp:73
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::AsmToken::Dollar
@ Dollar
Definition: MCAsmMacro.h:49
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1355
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::MCAsmParser::parseExpression
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1317
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:122
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::N86::ESP
@ ESP
Definition: X86MCTargetDesc.h:51
SmallString.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:748
getPrefixes
static unsigned getPrefixes(OperandVector &Operands)
Definition: X86AsmParser.cpp:4243
llvm::AsmToken::GreaterGreater
@ GreaterGreater
Definition: MCAsmMacro.h:54
llvm::AsmTypeInfo::Size
unsigned Size
Definition: MCAsmParser.h:98
Twine.h
llvm::MCAsmParser::parseIntToken
bool parseIntToken(int64_t &V, const Twine &ErrMsg)
Definition: MCAsmParser.cpp:70
llvm::X86::IP_USE_EVEX
@ IP_USE_EVEX
Definition: X86BaseInfo.h:67
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::AsmTypeInfo
Definition: MCAsmParser.h:96
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::X86II::isX86_64ExtendedReg
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1185
llvm::MCAF_Code16
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:53
MCInst.h
false
Definition: StackSlotColoring.cpp:142
llvm::MCInstrDesc::isTerminator
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:292
check
#define check(cond)
llvm::MCSymbol::getVariableValue
const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
Definition: MCSymbol.h:298
llvm::dwarf::toStringRef
StringRef toStringRef(const Optional< DWARFFormValue > &V, StringRef Default={})
Take an optional DWARFFormValue and try to extract a string value from it.
Definition: DWARFFormValue.h:191
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::isUIntN
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:455
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::AsmToken::Star
@ Star
Definition: MCAsmMacro.h:49
llvm::MCAsmParser::getContext
virtual MCContext & getContext()=0
llvm::ParseInstructionInfo::AsmRewrites
SmallVectorImpl< AsmRewrite > * AsmRewrites
Definition: MCTargetAsmParser.h:114
llvm::MCAsmParser::isParsingMasm
virtual bool isParsingMasm() const
Definition: MCAsmParser.h:188
llvm::X86::COND_A
@ COND_A
Definition: X86BaseInfo.h:88
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1467
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::X86Operand::isImm
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:209
llvm::MCAsmParser::addAliasForDirective
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
llvm::X86Operand::CreateMem
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0)
Create an absolute memory operand.
Definition: X86Operand.h:670
llvm::MCInst::setFlags
void setFlags(unsigned F)
Definition: MCInst.h:200
llvm::AsmToken::getKind
TokenKind getKind() const
Definition: MCAsmMacro.h:81
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:90
llvm::InlineAsmIdentifierInfo::IK_Label
@ IK_Label
Definition: MCAsmParser.h:40
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::X86::TO_NEG_INF
@ TO_NEG_INF
Definition: X86BaseInfo.h:48
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
X86Operand.h
isNot
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
Definition: AMDGPULegalizerInfo.cpp:2823