LLVM  14.0.0git
SystemZDisassembler.cpp
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1 //===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "SystemZ.h"
14 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/TargetRegistry.h"
18 #include <cassert>
19 #include <cstdint>
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "systemz-disassembler"
24 
26 
27 namespace {
28 
29 class SystemZDisassembler : public MCDisassembler {
30 public:
31  SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
32  : MCDisassembler(STI, Ctx) {}
33  ~SystemZDisassembler() override = default;
34 
35  DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
37  raw_ostream &CStream) const override;
38 };
39 
40 } // end anonymous namespace
41 
43  const MCSubtargetInfo &STI,
44  MCContext &Ctx) {
45  return new SystemZDisassembler(STI, Ctx);
46 }
47 
49  // Register the disassembler.
52 }
53 
54 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
55 /// immediate Value in the MCInst.
56 ///
57 /// @param Value - The immediate Value, has had any PC adjustment made by
58 /// the caller.
59 /// @param isBranch - If the instruction is a branch instruction
60 /// @param Address - The starting address of the instruction
61 /// @param Offset - The byte offset to this immediate in the instruction
62 /// @param Width - The byte width of this immediate in the instruction
63 ///
64 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
65 /// called then that function is called to get any symbolic information for the
66 /// immediate in the instruction using the Address, Offset and Width. If that
67 /// returns non-zero then the symbolic information it returns is used to create
68 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
69 /// returns zero and isBranch is true then a symbol look up for immediate Value
70 /// is done and if a symbol is found an MCExpr is created with that, else
71 /// an MCExpr with the immediate Value is created. This function returns true
72 /// if it adds an operand to the MCInst and false otherwise.
73 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
74  uint64_t Address, uint64_t Offset,
76  const void *Decoder) {
77  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
79  Offset, Width);
80 }
81 
83  const unsigned *Regs, unsigned Size) {
84  assert(RegNo < Size && "Invalid register");
85  RegNo = Regs[RegNo];
86  if (RegNo == 0)
87  return MCDisassembler::Fail;
88  Inst.addOperand(MCOperand::createReg(RegNo));
90 }
91 
93  uint64_t Address,
94  const void *Decoder) {
95  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
96 }
97 
99  uint64_t Address,
100  const void *Decoder) {
101  return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
102 }
103 
105  uint64_t Address,
106  const void *Decoder) {
107  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
108 }
109 
111  uint64_t Address,
112  const void *Decoder) {
113  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
114 }
115 
117  uint64_t Address,
118  const void *Decoder) {
119  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
120 }
121 
123  uint64_t Address,
124  const void *Decoder) {
125  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
126 }
127 
129  uint64_t Address,
130  const void *Decoder) {
131  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
132 }
133 
135  uint64_t Address,
136  const void *Decoder) {
137  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
138 }
139 
141  uint64_t Address,
142  const void *Decoder) {
143  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
144 }
145 
147  uint64_t Address,
148  const void *Decoder) {
149  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
150 }
151 
153  uint64_t Address,
154  const void *Decoder) {
155  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
156 }
157 
159  uint64_t Address,
160  const void *Decoder) {
161  return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
162 }
163 
165  uint64_t Address,
166  const void *Decoder) {
167  return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
168 }
169 
170 template<unsigned N>
172  if (!isUInt<N>(Imm))
173  return MCDisassembler::Fail;
174  Inst.addOperand(MCOperand::createImm(Imm));
176 }
177 
178 template<unsigned N>
180  if (!isUInt<N>(Imm))
181  return MCDisassembler::Fail;
182  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
184 }
185 
187  uint64_t Address, const void *Decoder) {
188  return decodeUImmOperand<1>(Inst, Imm);
189 }
190 
192  uint64_t Address, const void *Decoder) {
193  return decodeUImmOperand<2>(Inst, Imm);
194 }
195 
197  uint64_t Address, const void *Decoder) {
198  return decodeUImmOperand<3>(Inst, Imm);
199 }
200 
202  uint64_t Address, const void *Decoder) {
203  return decodeUImmOperand<4>(Inst, Imm);
204 }
205 
207  uint64_t Address, const void *Decoder) {
208  return decodeUImmOperand<6>(Inst, Imm);
209 }
210 
212  uint64_t Address, const void *Decoder) {
213  return decodeUImmOperand<8>(Inst, Imm);
214 }
215 
217  uint64_t Address, const void *Decoder) {
218  return decodeUImmOperand<12>(Inst, Imm);
219 }
220 
222  uint64_t Address, const void *Decoder) {
223  return decodeUImmOperand<16>(Inst, Imm);
224 }
225 
227  uint64_t Address, const void *Decoder) {
228  return decodeUImmOperand<32>(Inst, Imm);
229 }
230 
232  uint64_t Address, const void *Decoder) {
233  return decodeSImmOperand<8>(Inst, Imm);
234 }
235 
237  uint64_t Address, const void *Decoder) {
238  return decodeSImmOperand<16>(Inst, Imm);
239 }
240 
242  uint64_t Address, const void *Decoder) {
243  return decodeSImmOperand<32>(Inst, Imm);
244 }
245 
246 template<unsigned N>
248  uint64_t Address,
249  bool isBranch,
250  const void *Decoder) {
251  assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
252  uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
253 
255  Inst, Decoder))
257 
259 }
260 
262  uint64_t Address,
263  const void *Decoder) {
264  return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
265 }
266 
268  uint64_t Address,
269  const void *Decoder) {
270  return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
271 }
272 
274  uint64_t Address,
275  const void *Decoder) {
276  return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
277 }
278 
280  uint64_t Address,
281  const void *Decoder) {
282  return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
283 }
284 
286  uint64_t Address,
287  const void *Decoder) {
288  return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
289 }
290 
292  const unsigned *Regs) {
293  uint64_t Base = Field >> 12;
294  uint64_t Disp = Field & 0xfff;
295  assert(Base < 16 && "Invalid BDAddr12");
296  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
297  Inst.addOperand(MCOperand::createImm(Disp));
299 }
300 
302  const unsigned *Regs) {
303  uint64_t Base = Field >> 20;
304  uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
305  assert(Base < 16 && "Invalid BDAddr20");
306  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
307  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
309 }
310 
312  const unsigned *Regs) {
313  uint64_t Index = Field >> 16;
314  uint64_t Base = (Field >> 12) & 0xf;
315  uint64_t Disp = Field & 0xfff;
316  assert(Index < 16 && "Invalid BDXAddr12");
317  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
318  Inst.addOperand(MCOperand::createImm(Disp));
319  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
321 }
322 
324  const unsigned *Regs) {
325  uint64_t Index = Field >> 24;
326  uint64_t Base = (Field >> 20) & 0xf;
327  uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
328  assert(Index < 16 && "Invalid BDXAddr20");
329  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
330  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
331  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
333 }
334 
336  const unsigned *Regs) {
337  uint64_t Length = Field >> 16;
338  uint64_t Base = (Field >> 12) & 0xf;
339  uint64_t Disp = Field & 0xfff;
340  assert(Length < 16 && "Invalid BDLAddr12Len4");
341  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
342  Inst.addOperand(MCOperand::createImm(Disp));
343  Inst.addOperand(MCOperand::createImm(Length + 1));
345 }
346 
348  const unsigned *Regs) {
349  uint64_t Length = Field >> 16;
350  uint64_t Base = (Field >> 12) & 0xf;
351  uint64_t Disp = Field & 0xfff;
352  assert(Length < 256 && "Invalid BDLAddr12Len8");
353  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
354  Inst.addOperand(MCOperand::createImm(Disp));
355  Inst.addOperand(MCOperand::createImm(Length + 1));
357 }
358 
360  const unsigned *Regs) {
361  uint64_t Length = Field >> 16;
362  uint64_t Base = (Field >> 12) & 0xf;
363  uint64_t Disp = Field & 0xfff;
364  assert(Length < 16 && "Invalid BDRAddr12");
365  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
366  Inst.addOperand(MCOperand::createImm(Disp));
367  Inst.addOperand(MCOperand::createReg(Regs[Length]));
369 }
370 
372  const unsigned *Regs) {
373  uint64_t Index = Field >> 16;
374  uint64_t Base = (Field >> 12) & 0xf;
375  uint64_t Disp = Field & 0xfff;
376  assert(Index < 32 && "Invalid BDVAddr12");
377  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
378  Inst.addOperand(MCOperand::createImm(Disp));
381 }
382 
384  uint64_t Address,
385  const void *Decoder) {
387 }
388 
390  uint64_t Address,
391  const void *Decoder) {
393 }
394 
396  uint64_t Address,
397  const void *Decoder) {
399 }
400 
402  uint64_t Address,
403  const void *Decoder) {
405 }
406 
408  uint64_t Address,
409  const void *Decoder) {
411 }
412 
414  uint64_t Address,
415  const void *Decoder) {
417 }
418 
420  uint64_t Field,
421  uint64_t Address,
422  const void *Decoder) {
424 }
425 
427  uint64_t Field,
428  uint64_t Address,
429  const void *Decoder) {
431 }
432 
434  uint64_t Field,
435  uint64_t Address,
436  const void *Decoder) {
438 }
439 
441  uint64_t Address,
442  const void *Decoder) {
444 }
445 
446 #include "SystemZGenDisassemblerTables.inc"
447 
448 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
449  ArrayRef<uint8_t> Bytes,
450  uint64_t Address,
451  raw_ostream &CS) const {
452  // Get the first two bytes of the instruction.
453  Size = 0;
454  if (Bytes.size() < 2)
455  return MCDisassembler::Fail;
456 
457  // The top 2 bits of the first byte specify the size.
458  const uint8_t *Table;
459  if (Bytes[0] < 0x40) {
460  Size = 2;
461  Table = DecoderTable16;
462  } else if (Bytes[0] < 0xc0) {
463  Size = 4;
464  Table = DecoderTable32;
465  } else {
466  Size = 6;
467  Table = DecoderTable48;
468  }
469 
470  // Read any remaining bytes.
471  if (Bytes.size() < Size) {
472  Size = Bytes.size();
473  return MCDisassembler::Fail;
474  }
475 
476  // Construct the instruction.
477  uint64_t Inst = 0;
478  for (uint64_t I = 0; I < Size; ++I)
479  Inst = (Inst << 8) | Bytes[I];
480 
481  return decodeInstruction(Table, MI, Inst, Address, this, STI);
482 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
decodeU1ImmOperand
static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:186
MCFixedLenDisassembler.h
llvm::SystemZMC::GR128Regs
const unsigned GR128Regs[16]
Definition: SystemZMCTargetDesc.cpp:54
decodeS16ImmOperand
static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:236
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MathExtras.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
MCDisassembler.h
decodeBDLAddr64Disp12Len8Operand
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:426
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
decodeU8ImmOperand
static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:211
llvm::SystemZMC::VR128Regs
const unsigned VR128Regs[32]
Definition: SystemZMCTargetDesc.cpp:104
llvm::SystemZMC::FP32Regs
const unsigned FP32Regs[16]
Definition: SystemZMCTargetDesc.cpp:61
decodeU6ImmOperand
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:206
decodeBDVAddr12Operand
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:371
decodeU12ImmOperand
static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:216
decodePC16DBLBranchOperand
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:267
llvm::SystemZMC::GR64Regs
const unsigned GR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:47
decodeBDXAddr64Disp20Operand
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:413
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: SystemZDisassembler.cpp:25
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
tryAddingSymbolicOperand
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
Definition: SystemZDisassembler.cpp:73
SystemZMCTargetDesc.h
Offset
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Definition: ELFObjHandler.cpp:81
DecodeVR128BitRegisterClass
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:152
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const unsigned FP128Regs[16]
Definition: SystemZMCTargetDesc.cpp:75
DecodeGRH32BitRegisterClass
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:98
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::SystemZMC::AR32Regs
const unsigned AR32Regs[16]
Definition: SystemZMCTargetDesc.cpp:115
decodePC24DBLBranchOperand
static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:273
decodeBDAddr32Disp12Operand
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:383
SystemZTargetInfo.h
decodeU3ImmOperand
static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:196
DecodeCR64BitRegisterClass
static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:164
DecodeAR32BitRegisterClass
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:158
llvm::SystemZMC::CR64Regs
const unsigned CR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:122
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static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:301
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static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:407
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Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14
decodeBDRAddr12Operand
static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:359
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
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const unsigned GR32Regs[16]
Definition: SystemZMCTargetDesc.cpp:33
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static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:104
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This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
DecodeGR128BitRegisterClass
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:110
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Definition: SystemZDisassembler.cpp:171
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Definition: SystemZDisassembler.cpp:179
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DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
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Definition: MCInst.h:210
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Definition: SystemZDisassembler.cpp:226
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LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZDisassembler()
Definition: SystemZDisassembler.cpp:48
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Definition: SystemZDisassembler.cpp:122
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Definition: ELFObjHandler.cpp:84
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Definition: SystemZDisassembler.cpp:389
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#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
DecodeGR32BitRegisterClass
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:92
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static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:395
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Superclass for all disassemblers.
Definition: MCDisassembler.h:76
I
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Definition: MD5.cpp:59
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Definition: SystemZDisassembler.cpp:116
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Definition: SystemZDisassembler.cpp:261
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Definition: R600InstrInfo.cpp:647
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Definition: SystemZMCTargetDesc.cpp:68
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Definition: MCDisassembler.cpp:26
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static MCDisassembler * createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: SystemZDisassembler.cpp:42
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const unsigned GRH32Regs[16]
Definition: SystemZMCTargetDesc.cpp:40
decodeS32ImmOperand
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:241
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Definition: SystemZDisassembler.cpp:419
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decodeBDRAddr64Disp12Operand
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Definition: SystemZDisassembler.cpp:433
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Definition: SystemZDisassembler.cpp:191
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Definition: MCInst.h:134
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Definition: SystemZDisassembler.cpp:323
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
decodeBDXAddr12Operand
static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:311
decodeU16ImmOperand
static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:221
decodeBDLAddr12Len4Operand
static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:335
DecodeFP64BitRegisterClass
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:128
DecodeVR64BitRegisterClass
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:146
llvm::SystemZMC::VR64Regs
const unsigned VR64Regs[32]
Definition: SystemZMCTargetDesc.cpp:93
decodeRegisterClass
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size)
Definition: SystemZDisassembler.cpp:82
decodeBDVAddr64Disp12Operand
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:440
decodePC32DBLBranchOperand
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:279
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:413
DecodeFP128BitRegisterClass
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:134
decodeBDAddr64Disp20Operand
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:401
N
#define N
decodeBDLAddr12Len8Operand
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:347
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
decodeS8ImmOperand
static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:231
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
decodePCDBLOperand
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, bool isBranch, const void *Decoder)
Definition: SystemZDisassembler.cpp:247
DecodeVR32BitRegisterClass
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:140
decodeU4ImmOperand
static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:201
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::SystemZMC::VR32Regs
const unsigned VR32Regs[32]
Definition: SystemZMCTargetDesc.cpp:82
decodeBDAddr12Operand
static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Definition: SystemZDisassembler.cpp:291
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
decodePC32DBLOperand
static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: SystemZDisassembler.cpp:285