LLVM 17.0.0git
SystemZDisassembler.cpp
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1//===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "SystemZ.h"
14#include "llvm/MC/MCInst.h"
18#include <cassert>
19#include <cstdint>
20
21using namespace llvm;
22
23#define DEBUG_TYPE "systemz-disassembler"
24
26
27namespace {
28
29class SystemZDisassembler : public MCDisassembler {
30public:
31 SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
32 : MCDisassembler(STI, Ctx) {}
33 ~SystemZDisassembler() override = default;
34
36 ArrayRef<uint8_t> Bytes, uint64_t Address,
37 raw_ostream &CStream) const override;
38};
39
40} // end anonymous namespace
41
43 const MCSubtargetInfo &STI,
44 MCContext &Ctx) {
45 return new SystemZDisassembler(STI, Ctx);
46}
47
49 // Register the disassembler.
52}
53
54/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
55/// immediate Value in the MCInst.
56///
57/// @param Value - The immediate Value, has had any PC adjustment made by
58/// the caller.
59/// @param isBranch - If the instruction is a branch instruction
60/// @param Address - The starting address of the instruction
61/// @param Offset - The byte offset to this immediate in the instruction
62/// @param Width - The byte width of this immediate in the instruction
63///
64/// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
65/// called then that function is called to get any symbolic information for the
66/// immediate in the instruction using the Address, Offset and Width. If that
67/// returns non-zero then the symbolic information it returns is used to create
68/// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
69/// returns zero and isBranch is true then a symbol look up for immediate Value
70/// is done and if a symbol is found an MCExpr is created with that, else
71/// an MCExpr with the immediate Value is created. This function returns true
72/// if it adds an operand to the MCInst and false otherwise.
73static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
74 uint64_t Address, uint64_t Offset,
75 uint64_t Width, MCInst &MI,
76 const MCDisassembler *Decoder) {
77 return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
78 Width, /*InstSize=*/0);
79}
80
82 const unsigned *Regs, unsigned Size) {
83 assert(RegNo < Size && "Invalid register");
84 RegNo = Regs[RegNo];
85 if (RegNo == 0)
89}
90
92 uint64_t Address,
93 const MCDisassembler *Decoder) {
94 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
95}
96
98 uint64_t Address,
99 const MCDisassembler *Decoder) {
100 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
101}
102
104 uint64_t Address,
105 const MCDisassembler *Decoder) {
106 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
107}
108
110 uint64_t Address,
111 const MCDisassembler *Decoder) {
112 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
113}
114
115static DecodeStatus
117 const MCDisassembler *Decoder) {
118 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
119}
120
122 uint64_t Address,
123 const MCDisassembler *Decoder) {
124 return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
125}
126
128 uint64_t Address,
129 const MCDisassembler *Decoder) {
130 return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
131}
132
134 uint64_t Address,
135 const MCDisassembler *Decoder) {
136 return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
137}
138
140 uint64_t Address,
141 const MCDisassembler *Decoder) {
142 return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
143}
144
146 uint64_t Address,
147 const MCDisassembler *Decoder) {
148 return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
149}
150
152 uint64_t Address,
153 const MCDisassembler *Decoder) {
154 return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
155}
156
158 uint64_t Address,
159 const MCDisassembler *Decoder) {
160 return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
161}
162
164 uint64_t Address,
165 const MCDisassembler *Decoder) {
166 return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
167}
168
169template<unsigned N>
171 if (!isUInt<N>(Imm))
175}
176
177template<unsigned N>
179 if (!isUInt<N>(Imm))
181 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
183}
184
186 uint64_t Address,
187 const MCDisassembler *Decoder) {
188 return decodeUImmOperand<1>(Inst, Imm);
189}
190
192 uint64_t Address,
193 const MCDisassembler *Decoder) {
194 return decodeUImmOperand<2>(Inst, Imm);
195}
196
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 return decodeUImmOperand<3>(Inst, Imm);
201}
202
204 uint64_t Address,
205 const MCDisassembler *Decoder) {
206 return decodeUImmOperand<4>(Inst, Imm);
207}
208
210 uint64_t Address,
211 const MCDisassembler *Decoder) {
212 return decodeUImmOperand<6>(Inst, Imm);
213}
214
216 uint64_t Address,
217 const MCDisassembler *Decoder) {
218 return decodeUImmOperand<8>(Inst, Imm);
219}
220
222 uint64_t Address,
223 const MCDisassembler *Decoder) {
224 return decodeUImmOperand<12>(Inst, Imm);
225}
226
228 uint64_t Address,
229 const MCDisassembler *Decoder) {
230 return decodeUImmOperand<16>(Inst, Imm);
231}
232
234 uint64_t Address,
235 const MCDisassembler *Decoder) {
236 return decodeUImmOperand<32>(Inst, Imm);
237}
238
240 uint64_t Address,
241 const MCDisassembler *Decoder) {
242 return decodeSImmOperand<8>(Inst, Imm);
243}
244
246 uint64_t Address,
247 const MCDisassembler *Decoder) {
248 return decodeSImmOperand<16>(Inst, Imm);
249}
250
252 uint64_t Address,
253 const MCDisassembler *Decoder) {
254 return decodeSImmOperand<32>(Inst, Imm);
255}
256
257template <unsigned N>
259 uint64_t Address, bool isBranch,
260 const MCDisassembler *Decoder) {
261 assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
262 uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
263
264 if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
265 Inst, Decoder))
267
269}
270
272 uint64_t Address,
273 const MCDisassembler *Decoder) {
274 return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
275}
276
278 uint64_t Address,
279 const MCDisassembler *Decoder) {
280 return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
281}
282
284 uint64_t Address,
285 const MCDisassembler *Decoder) {
286 return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
287}
288
290 uint64_t Address,
291 const MCDisassembler *Decoder) {
292 return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
293}
294
296 uint64_t Address,
297 const MCDisassembler *Decoder) {
298 return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
299}
300
302 const unsigned *Regs) {
303 uint64_t Base = Field >> 12;
304 uint64_t Disp = Field & 0xfff;
305 assert(Base < 16 && "Invalid BDAddr12");
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
309}
310
312 const unsigned *Regs) {
313 uint64_t Base = Field >> 20;
314 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
315 assert(Base < 16 && "Invalid BDAddr20");
316 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
317 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
319}
320
322 const unsigned *Regs) {
323 uint64_t Index = Field >> 16;
324 uint64_t Base = (Field >> 12) & 0xf;
325 uint64_t Disp = Field & 0xfff;
326 assert(Index < 16 && "Invalid BDXAddr12");
327 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
329 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
331}
332
334 const unsigned *Regs) {
335 uint64_t Index = Field >> 24;
336 uint64_t Base = (Field >> 20) & 0xf;
337 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
338 assert(Index < 16 && "Invalid BDXAddr20");
339 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
340 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
341 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
343}
344
346 const unsigned *Regs) {
347 uint64_t Length = Field >> 16;
348 uint64_t Base = (Field >> 12) & 0xf;
349 uint64_t Disp = Field & 0xfff;
350 assert(Length < 16 && "Invalid BDLAddr12Len4");
351 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
355}
356
358 const unsigned *Regs) {
359 uint64_t Length = Field >> 16;
360 uint64_t Base = (Field >> 12) & 0xf;
361 uint64_t Disp = Field & 0xfff;
362 assert(Length < 256 && "Invalid BDLAddr12Len8");
363 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
367}
368
370 const unsigned *Regs) {
371 uint64_t Length = Field >> 16;
372 uint64_t Base = (Field >> 12) & 0xf;
373 uint64_t Disp = Field & 0xfff;
374 assert(Length < 16 && "Invalid BDRAddr12");
375 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
379}
380
382 const unsigned *Regs) {
383 uint64_t Index = Field >> 16;
384 uint64_t Base = (Field >> 12) & 0xf;
385 uint64_t Disp = Field & 0xfff;
386 assert(Index < 32 && "Invalid BDVAddr12");
387 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
391}
392
394 uint64_t Address,
395 const MCDisassembler *Decoder) {
397}
398
400 uint64_t Address,
401 const MCDisassembler *Decoder) {
403}
404
406 uint64_t Address,
407 const MCDisassembler *Decoder) {
409}
410
412 uint64_t Address,
413 const MCDisassembler *Decoder) {
415}
416
417static DecodeStatus
419 const MCDisassembler *Decoder) {
421}
422
423static DecodeStatus
425 const MCDisassembler *Decoder) {
427}
428
429static DecodeStatus
431 const MCDisassembler *Decoder) {
433}
434
435static DecodeStatus
437 const MCDisassembler *Decoder) {
439}
440
441static DecodeStatus
443 const MCDisassembler *Decoder) {
445}
446
447static DecodeStatus
449 const MCDisassembler *Decoder) {
451}
452
453#include "SystemZGenDisassemblerTables.inc"
454
455DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
456 ArrayRef<uint8_t> Bytes,
457 uint64_t Address,
458 raw_ostream &CS) const {
459 // Get the first two bytes of the instruction.
460 Size = 0;
461 if (Bytes.size() < 2)
463
464 // The top 2 bits of the first byte specify the size.
465 const uint8_t *Table;
466 if (Bytes[0] < 0x40) {
467 Size = 2;
468 Table = DecoderTable16;
469 } else if (Bytes[0] < 0xc0) {
470 Size = 4;
471 Table = DecoderTable32;
472 } else {
473 Size = 6;
474 Table = DecoderTable48;
475 }
476
477 // Read any remaining bytes.
478 if (Bytes.size() < Size) {
479 Size = Bytes.size();
481 }
482
483 // Construct the instruction.
484 uint64_t Inst = 0;
485 for (uint64_t I = 0; I < Size; ++I)
486 Inst = (Inst << 8) | Bytes[I];
487
488 return decodeInstruction(Table, MI, Inst, Address, this, STI);
489}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm)
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZDisassembler()
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, bool isBranch, const MCDisassembler *Decoder)
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size)
static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static MCDisassembler * createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm)
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
const unsigned GR64Regs[16]
const unsigned VR128Regs[32]
const unsigned GR128Regs[16]
const unsigned GRH32Regs[16]
const unsigned FP32Regs[16]
const unsigned GR32Regs[16]
const unsigned FP64Regs[16]
const unsigned VR64Regs[32]
const unsigned FP128Regs[16]
const unsigned AR32Regs[16]
const unsigned VR32Regs[32]
const unsigned CR64Regs[16]
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSystemZTarget()
@ Offset
Definition: DWP.cpp:406
@ Length
Definition: DWP.cpp:406
#define N
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.