28#define DEBUG_TYPE "riscv-disassembler"
34 std::unique_ptr<MCInstrInfo const>
const MCII;
50 return new RISCVDisassembler(STI, Ctx,
T.createMCInstrInfo());
66 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
68 if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
165 if (RegNo >= 32 || RegNo & 1)
193 const RISCVDisassembler *Dis =
194 static_cast<const RISCVDisassembler *
>(Decoder);
198 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
213 const RISCVDisassembler *Dis =
214 static_cast<const RISCVDisassembler *
>(Decoder);
218 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
233 const RISCVDisassembler *Dis =
234 static_cast<const RISCVDisassembler *
>(Decoder);
238 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
274 if (Inst.
getOpcode() == RISCV::C_ADDI16SP) {
284 assert(isUInt<N>(Imm) &&
"Invalid immediate");
296 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
303 assert(isUInt<N>(Imm) &&
"Invalid immediate");
316 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
323 assert(isUInt<N>(Imm) &&
"Invalid immediate");
334 assert(isUInt<6>(Imm) &&
"Invalid immediate");
336 Imm = (SignExtend64<6>(Imm) & 0xfffff);
344 assert(isUInt<3>(Imm) &&
"Invalid immediate");
372#include "RISCVGenDisassemblerTables.inc"
378 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
379 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
390 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
391 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
403 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
404 DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
413 unsigned Rd = fieldFromInstruction(
Insn, 7, 5);
414 unsigned Rs2 = fieldFromInstruction(
Insn, 2, 5);
423 unsigned Rd = fieldFromInstruction(
Insn, 7, 5);
424 unsigned Rs2 = fieldFromInstruction(
Insn, 2, 5);
441 if ((Bytes[0] & 0x3) == 0x3) {
442 if (Bytes.
size() < 4) {
447 if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] &&
448 !STI.getFeatureBits()[RISCV::Feature64Bit]) {
449 LLVM_DEBUG(
dbgs() <<
"Trying RV32Zdinx table (Double in Integer and"
451 Result = decodeInstruction(DecoderTableRV32Zdinx32,
MI,
Insn, Address,
459 if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) {
460 LLVM_DEBUG(
dbgs() <<
"Trying RVZfinx table (Float in Integer):\n");
461 Result = decodeInstruction(DecoderTableRVZfinx32,
MI,
Insn, Address,
this,
468 if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) {
470 Result = decodeInstruction(DecoderTableVentana32,
MI,
Insn, Address,
this,
477 if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) {
480 decodeInstruction(DecoderTableTHeadV32,
MI,
Insn, Address,
this, STI);
488 Result = decodeInstruction(DecoderTable32,
MI,
Insn, Address,
this, STI);
491 if (Bytes.
size() < 2) {
497 if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
499 dbgs() <<
"Trying RISCV32Only_16 table (16-bit Instruction):\n");
501 Result = decodeInstruction(DecoderTableRISCV32Only_16,
MI,
Insn, Address,
509 LLVM_DEBUG(
dbgs() <<
"Trying RISCV_C table (16-bit Instruction):\n");
511 Result = decodeInstruction(DecoderTable16,
MI,
Insn, Address,
this, STI);
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static void addImplySP(MCInst &Inst, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Container class for subtarget features.
Context object for machine code objects.
Superclass for all disassemblers.
const MCSubtargetInfo & getSubtargetInfo() const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Interface to description of machine instruction set.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
static bool isValidRoundingMode(unsigned Mode)
uint16_t read16le(const void *P)
uint32_t read32le(const void *P)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheRISCV32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Target & getTheRISCV64Target()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.