28#define DEBUG_TYPE "riscv-disassembler"
34 std::unique_ptr<MCInstrInfo const>
const MCII;
46 void addSPOperands(
MCInst &
MI)
const;
53 return new RISCVDisassembler(STI, Ctx,
T.createMCInstrInfo());
69 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
166 if (RegNo >= 32 || RegNo & 1)
176 const void *Decoder) {
180 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
199 if (RegNo >= 32 || RegNo % 2)
202 const RISCVDisassembler *Dis =
203 static_cast<const RISCVDisassembler *
>(Decoder);
207 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
216 if (RegNo >= 32 || RegNo % 4)
219 const RISCVDisassembler *Dis =
220 static_cast<const RISCVDisassembler *
>(Decoder);
224 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
233 if (RegNo >= 32 || RegNo % 8)
236 const RISCVDisassembler *Dis =
237 static_cast<const RISCVDisassembler *
>(Decoder);
241 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
253 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
263 assert(isUInt<N>(Imm) &&
"Invalid immediate");
274 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
281 assert(isUInt<N>(Imm) &&
"Invalid immediate");
293 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
300 assert(isUInt<N>(Imm) &&
"Invalid immediate");
311 assert(isUInt<6>(Imm) &&
"Invalid immediate");
313 Imm = (SignExtend64<6>(Imm) & 0xfffff);
321 assert(isUInt<3>(Imm) &&
"Invalid immediate");
354 uint64_t Address,
const void *Decoder);
360 uint64_t Address,
const void *Decoder);
362#include "RISCVGenDisassemblerTables.inc"
381 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
382 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
394 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
395 DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
432 DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
438 bool IsWordOp = (
Opcode == RISCV::TH_LWD ||
Opcode == RISCV::TH_LWUD ||
449 uint64_t Address,
const void *Decoder) {
467 uint64_t Address,
const void *Decoder) {
475void RISCVDisassembler::addSPOperands(
MCInst &
MI)
const {
478 if (MCID.
operands()[i].RegClass == RISCV::SPRegClassID)
491#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
492 DESC, ADDITIONAL_OPERATION) \
494 if (FEATURE_CHECKS) { \
495 LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
496 Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
497 if (Result != MCDisassembler::Fail) { \
498 ADDITIONAL_OPERATION; \
503#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC) \
504 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
506#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC) \
507 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
509#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
510 TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
513 if ((Bytes[0] & 0x3) == 0x3) {
514 if (Bytes.
size() < 4) {
523 !STI.hasFeature(RISCV::Feature64Bit),
524 DecoderTableRV32Zdinx32,
525 "RV32Zdinx table (Double in Integer and rv32)");
527 "RVZfinx table (Float in Integer)");
529 DecoderTableXVentana32,
"Ventana custom opcode table");
531 "XTHeadBa custom opcode table");
533 "XTHeadBb custom opcode table");
535 "XTHeadBs custom opcode table");
537 DecoderTableXTHeadCondMov32,
538 "XTHeadCondMov custom opcode table");
540 "XTHeadCmo custom opcode table");
542 DecoderTableXTHeadFMemIdx32,
543 "XTHeadFMemIdx custom opcode table");
545 "XTHeadMac custom opcode table");
547 DecoderTableXTHeadMemIdx32,
548 "XTHeadMemIdx custom opcode table");
550 DecoderTableXTHeadMemPair32,
551 "XTHeadMemPair custom opcode table");
553 DecoderTableXTHeadSync32,
554 "XTHeadSync custom opcode table");
556 "XTHeadVdot custom opcode table");
558 "SiFive VCIX custom opcode table");
560 RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
561 "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
563 RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
564 "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
566 RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
567 "SiFive Matrix Multiplication Instruction opcode table");
569 RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
570 "SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
572 "Sifive CIE custom opcode table");
574 DecoderTableXCVbitmanip32,
575 "CORE-V Bit Manipulation custom opcode table");
577 "CORE-V Event load custom opcode table");
579 "CORE-V MAC custom opcode table");
581 "CORE-V MEM custom opcode table");
583 "CORE-V ALU custom opcode table");
585 "CORE-V SIMD extensions custom opcode table");
587 "CORE-V Immediate Branching custom opcode table");
593 if (Bytes.
size() < 2) {
601 DecoderTableRISCV32Only_16,
602 "RISCV32Only_16 table (16-bit Instruction)");
604 "Zcmt table (16-bit Table Jump Instructions)");
606 RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
607 "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
609 "RISCV_C table (16-bit Instruction)");
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC)
static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC)
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static constexpr uint32_t Opcode
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
const MCSubtargetInfo & getSubtargetInfo() const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
Interface to description of machine instruction set.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
static bool isValidRoundingMode(unsigned Mode)
uint16_t read16le(const void *P)
uint32_t read32le(const void *P)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheRISCV32Target()
Target & getTheRISCV64Target()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.