LLVM 19.0.0git
RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
16#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "riscv-disassembler"
29
31
32namespace {
33class RISCVDisassembler : public MCDisassembler {
34 std::unique_ptr<MCInstrInfo const> const MCII;
35
36public:
37 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
38 MCInstrInfo const *MCII)
39 : MCDisassembler(STI, Ctx), MCII(MCII) {}
40
42 ArrayRef<uint8_t> Bytes, uint64_t Address,
43 raw_ostream &CStream) const override;
44
45private:
46 void addSPOperands(MCInst &MI) const;
47};
48} // end anonymous namespace
49
51 const MCSubtargetInfo &STI,
52 MCContext &Ctx) {
53 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
54}
55
57 // Register the disassembler for each target.
62}
63
65 uint64_t Address,
66 const MCDisassembler *Decoder) {
67 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
68
69 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
71
72 MCRegister Reg = RISCV::X0 + RegNo;
75}
76
78 uint64_t Address,
79 const MCDisassembler *Decoder) {
80 MCRegister Reg = RISCV::X0 + RegNo;
81 if (Reg != RISCV::X1 && Reg != RISCV::X5)
83
86}
87
89 uint64_t Address,
90 const MCDisassembler *Decoder) {
91 if (RegNo >= 32)
93
94 MCRegister Reg = RISCV::F0_H + RegNo;
97}
98
100 uint64_t Address,
101 const MCDisassembler *Decoder) {
102 if (RegNo >= 32)
104
105 MCRegister Reg = RISCV::F0_F + RegNo;
108}
109
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 if (RegNo >= 8) {
115 }
116 MCRegister Reg = RISCV::F8_F + RegNo;
119}
120
122 uint64_t Address,
123 const MCDisassembler *Decoder) {
124 if (RegNo >= 32)
126
127 MCRegister Reg = RISCV::F0_D + RegNo;
130}
131
133 uint64_t Address,
134 const MCDisassembler *Decoder) {
135 if (RegNo >= 8) {
137 }
138 MCRegister Reg = RISCV::F8_D + RegNo;
141}
142
144 uint64_t Address,
145 const MCDisassembler *Decoder) {
146 if (RegNo == 0) {
148 }
149
150 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
151}
152
153static DecodeStatus
155 const MCDisassembler *Decoder) {
156 if (RegNo == 2) {
158 }
159
160 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
161}
162
164 uint64_t Address,
165 const MCDisassembler *Decoder) {
166 if (RegNo >= 8)
168
169 MCRegister Reg = RISCV::X8 + RegNo;
172}
173
175 uint64_t Address,
176 const MCDisassembler *Decoder) {
177 if (RegNo >= 32 || RegNo & 1)
179
180 MCRegister Reg = RISCV::X0 + RegNo;
183}
184
186 uint64_t Address,
187 const void *Decoder) {
188 if (RegNo >= 8)
190
191 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
194}
195
197 uint64_t Address,
198 const MCDisassembler *Decoder) {
199 if (RegNo >= 32)
201
202 MCRegister Reg = RISCV::V0 + RegNo;
205}
206
208 uint64_t Address,
209 const MCDisassembler *Decoder) {
210 if (RegNo >= 32 || RegNo % 2)
212
213 const RISCVDisassembler *Dis =
214 static_cast<const RISCVDisassembler *>(Decoder);
215 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
216 MCRegister Reg =
217 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
218 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
219
222}
223
225 uint64_t Address,
226 const MCDisassembler *Decoder) {
227 if (RegNo >= 32 || RegNo % 4)
229
230 const RISCVDisassembler *Dis =
231 static_cast<const RISCVDisassembler *>(Decoder);
232 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
233 MCRegister Reg =
234 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
235 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
236
239}
240
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
244 if (RegNo >= 32 || RegNo % 8)
246
247 const RISCVDisassembler *Dis =
248 static_cast<const RISCVDisassembler *>(Decoder);
249 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
250 MCRegister Reg =
251 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
252 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
253
256}
257
259 uint64_t Address,
260 const MCDisassembler *Decoder) {
261 if (RegNo > 2) {
263 }
264 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
265
268}
269
270template <unsigned N>
272 int64_t Address,
273 const MCDisassembler *Decoder) {
274 assert(isUInt<N>(Imm) && "Invalid immediate");
277}
278
279template <unsigned N>
281 int64_t Address,
282 const MCDisassembler *Decoder) {
283 if (Imm == 0)
285 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
286}
287
288template <unsigned N>
290 int64_t Address,
291 const MCDisassembler *Decoder) {
292 assert(isUInt<N>(Imm) && "Invalid immediate");
293 // Sign-extend the number in the bottom N bits of Imm
294 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
296}
297
298template <unsigned N>
300 int64_t Address,
301 const MCDisassembler *Decoder) {
302 if (Imm == 0)
304 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
305}
306
307template <unsigned N>
309 int64_t Address,
310 const MCDisassembler *Decoder) {
311 assert(isUInt<N>(Imm) && "Invalid immediate");
312 // Sign-extend the number in the bottom N bits of Imm after accounting for
313 // the fact that the N bit immediate is stored in N-1 bits (the LSB is
314 // always zero)
315 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
317}
318
320 int64_t Address,
321 const MCDisassembler *Decoder) {
322 assert(isUInt<6>(Imm) && "Invalid immediate");
323 if (Imm > 31) {
324 Imm = (SignExtend64<6>(Imm) & 0xfffff);
325 }
328}
329
330static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
331 const MCDisassembler *Decoder) {
332 assert(isUInt<3>(Imm) && "Invalid immediate");
335
338}
339
341 uint64_t Address,
342 const MCDisassembler *Decoder);
343
345 uint64_t Address,
346 const MCDisassembler *Decoder);
347
349 uint64_t Address,
350 const MCDisassembler *Decoder);
351
353 uint64_t Address,
354 const MCDisassembler *Decoder);
355
357 uint64_t Address,
358 const MCDisassembler *Decoder);
359
361 uint64_t Address,
362 const MCDisassembler *Decoder);
363
364static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
365 uint64_t Address, const void *Decoder);
366
368 const MCDisassembler *Decoder);
369
370static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
371 uint64_t Address, const void *Decoder);
372
374 uint64_t Address,
375 const MCDisassembler *Decoder);
376
377#include "RISCVGenDisassemblerTables.inc"
378
380 uint64_t Address,
381 const MCDisassembler *Decoder) {
382 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
383 [[maybe_unused]] DecodeStatus Result =
384 DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
385 assert(Result == MCDisassembler::Success && "Invalid register");
386 Inst.addOperand(Inst.getOperand(0));
389}
390
392 uint64_t Address,
393 const MCDisassembler *Decoder) {
394 uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
395 [[maybe_unused]] DecodeStatus Result =
396 DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
397 assert(Result == MCDisassembler::Success && "Invalid register");
399}
400
402 uint64_t Address,
403 const MCDisassembler *Decoder) {
404 Inst.addOperand(MCOperand::createReg(RISCV::X0));
405 uint32_t SImm6 =
406 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
407 [[maybe_unused]] DecodeStatus Result =
408 decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
409 assert(Result == MCDisassembler::Success && "Invalid immediate");
411}
412
414 uint64_t Address,
415 const MCDisassembler *Decoder) {
416 Inst.addOperand(MCOperand::createReg(RISCV::X0));
417 Inst.addOperand(Inst.getOperand(0));
418 uint32_t UImm6 =
419 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
420 [[maybe_unused]] DecodeStatus Result =
421 decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
422 assert(Result == MCDisassembler::Success && "Invalid immediate");
424}
425
427 uint64_t Address,
428 const MCDisassembler *Decoder) {
429 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
430 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
431 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
432 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
434}
435
437 uint64_t Address,
438 const MCDisassembler *Decoder) {
439 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
440 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
441 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
442 Inst.addOperand(Inst.getOperand(0));
443 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
445}
446
448 uint64_t Address,
449 const MCDisassembler *Decoder) {
450 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
451 uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
452 uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
453 uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
454 DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
455 DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
456 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
457 [[maybe_unused]] DecodeStatus Result =
458 decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
459 assert(Result == MCDisassembler::Success && "Invalid immediate");
460
461 // Disassemble the final operand which is implicit.
462 unsigned Opcode = Inst.getOpcode();
463 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
464 Opcode == RISCV::TH_SWD);
465 if (IsWordOp)
467 else
469
471}
472
473static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
474 uint64_t Address, const void *Decoder) {
475 if (Imm <= 3)
479}
480
482 const MCDisassembler *Decoder) {
483 uint32_t Rs1 = fieldFromInstruction(Insn, 0, 5);
484 uint32_t Rs2 = fieldFromInstruction(Insn, 5, 5);
485 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
486 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
488}
489
490static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
491 uint64_t Address, const void *Decoder) {
494}
495
496// Add implied SP operand for C.*SP compressed instructions. The SP operand
497// isn't explicitly encoded in the instruction.
498void RISCVDisassembler::addSPOperands(MCInst &MI) const {
499 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
500 for (unsigned i = 0; i < MCID.getNumOperands(); i++)
501 if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
502 MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
503}
504
505DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
506 ArrayRef<uint8_t> Bytes,
507 uint64_t Address,
508 raw_ostream &CS) const {
509 // TODO: This will need modification when supporting instruction set
510 // extensions with instructions > 32-bits (up to 176 bits wide).
513
514#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
515 DESC, ADDITIONAL_OPERATION) \
516 do { \
517 if (FEATURE_CHECKS) { \
518 LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
519 Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
520 if (Result != MCDisassembler::Fail) { \
521 ADDITIONAL_OPERATION; \
522 return Result; \
523 } \
524 } \
525 } while (false)
526#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC) \
527 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
528 addSPOperands(MI))
529#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC) \
530 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
531 (void)nullptr)
532#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
533 TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
534
535 // It's a 32 bit instruction if bit 0 and 1 are 1.
536 if ((Bytes[0] & 0x3) == 0x3) {
537 if (Bytes.size() < 4) {
538 Size = 0;
540 }
541 Size = 4;
542
544
545 TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
546 !STI.hasFeature(RISCV::Feature64Bit),
547 DecoderTableRV32Zdinx32,
548 "RV32Zdinx table (Double in Integer and rv32)");
549 TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
550 !STI.hasFeature(RISCV::Feature64Bit),
551 DecoderTableRV32Zacas32,
552 "RV32Zacas table (Compare-And-Swap and rv32)");
553 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
554 "RVZfinx table (Float in Integer)");
555 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
556 DecoderTableXVentana32, "Ventana custom opcode table");
557 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
558 "XTHeadBa custom opcode table");
559 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
560 "XTHeadBb custom opcode table");
561 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
562 "XTHeadBs custom opcode table");
563 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
564 DecoderTableXTHeadCondMov32,
565 "XTHeadCondMov custom opcode table");
566 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
567 "XTHeadCmo custom opcode table");
568 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
569 DecoderTableXTHeadFMemIdx32,
570 "XTHeadFMemIdx custom opcode table");
571 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
572 "XTHeadMac custom opcode table");
573 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
574 DecoderTableXTHeadMemIdx32,
575 "XTHeadMemIdx custom opcode table");
576 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
577 DecoderTableXTHeadMemPair32,
578 "XTHeadMemPair custom opcode table");
579 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
580 DecoderTableXTHeadSync32,
581 "XTHeadSync custom opcode table");
582 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
583 "XTHeadVdot custom opcode table");
584 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
585 "SiFive VCIX custom opcode table");
587 RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
588 "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
590 RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
591 "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
593 RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
594 "SiFive Matrix Multiplication Instruction opcode table");
596 RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
597 "SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
598 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
599 DecoderTableXSiFivecdiscarddlone32,
600 "SiFive sf.cdiscard.d.l1 custom opcode table");
601 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
602 DecoderTableXSiFivecflushdlone32,
603 "SiFive sf.cflush.d.l1 custom opcode table");
604 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
605 "SiFive sf.cease custom opcode table");
606 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
607 DecoderTableXCVbitmanip32,
608 "CORE-V Bit Manipulation custom opcode table");
609 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
610 "CORE-V Event load custom opcode table");
611 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
612 "CORE-V MAC custom opcode table");
613 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
614 "CORE-V MEM custom opcode table");
615 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
616 "CORE-V ALU custom opcode table");
617 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
618 "CORE-V SIMD extensions custom opcode table");
619 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
620 "CORE-V Immediate Branching custom opcode table");
621 TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
622
624 }
625
626 if (Bytes.size() < 2) {
627 Size = 0;
629 }
630 Size = 2;
631
633 TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
634 DecoderTableRISCV32Only_16,
635 "RISCV32Only_16 table (16-bit Instruction)");
636 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16,
637 "RVZicfiss table (Shadow Stack)");
638 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
639 "Zcmt table (16-bit Table Jump Instructions)");
641 RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
642 "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
643 TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
644 "RISCV_C table (16-bit Instruction)");
645
647}
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
uint64_t Size
IRTranslator LLVM IR MI
#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC)
static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC)
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
const T * data() const
Definition: ArrayRef.h:162
Context object for machine code objects.
Definition: MCContext.h:81
Superclass for all disassemblers.
const MCSubtargetInfo & getSubtargetInfo() const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
static bool isValidRoundingMode(unsigned Mode)
uint16_t read16le(const void *P)
Definition: Endian.h:406
uint32_t read32le(const void *P)
Definition: Endian.h:409
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheRISCV32Target()
Target & getTheRISCV64Target()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.