LLVM  16.0.0git
PPCAsmParser.cpp
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1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/MC/TargetRegistry.h"
27 #include "llvm/Support/SourceMgr.h"
29 
30 using namespace llvm;
31 
33 
34 // Evaluate an expression containing condition register
35 // or condition register field symbols. Returns positive
36 // value on success, or -1 on error.
37 static int64_t
39  switch (E->getKind()) {
40  case MCExpr::Target:
41  return -1;
42 
43  case MCExpr::Constant: {
44  int64_t Res = cast<MCConstantExpr>(E)->getValue();
45  return Res < 0 ? -1 : Res;
46  }
47 
48  case MCExpr::SymbolRef: {
49  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
50  StringRef Name = SRE->getSymbol().getName();
51 
52  if (Name == "lt") return 0;
53  if (Name == "gt") return 1;
54  if (Name == "eq") return 2;
55  if (Name == "so") return 3;
56  if (Name == "un") return 3;
57 
58  if (Name == "cr0") return 0;
59  if (Name == "cr1") return 1;
60  if (Name == "cr2") return 2;
61  if (Name == "cr3") return 3;
62  if (Name == "cr4") return 4;
63  if (Name == "cr5") return 5;
64  if (Name == "cr6") return 6;
65  if (Name == "cr7") return 7;
66 
67  return -1;
68  }
69 
70  case MCExpr::Unary:
71  return -1;
72 
73  case MCExpr::Binary: {
74  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
75  int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
76  int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
77  int64_t Res;
78 
79  if (LHSVal < 0 || RHSVal < 0)
80  return -1;
81 
82  switch (BE->getOpcode()) {
83  default: return -1;
84  case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
85  case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
86  }
87 
88  return Res < 0 ? -1 : Res;
89  }
90  }
91 
92  llvm_unreachable("Invalid expression kind!");
93 }
94 
95 namespace {
96 
97 struct PPCOperand;
98 
99 class PPCAsmParser : public MCTargetAsmParser {
100  bool IsPPC64;
101 
102  void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
103 
104  bool isPPC64() const { return IsPPC64; }
105 
106  bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
107 
108  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
109  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
110  SMLoc &EndLoc) override;
111 
112  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
113  PPCMCExpr::VariantKind &Variant);
114  const MCExpr *FixupVariantKind(const MCExpr *E);
115  bool ParseExpression(const MCExpr *&EVal);
116 
117  bool ParseOperand(OperandVector &Operands);
118 
119  bool ParseDirectiveWord(unsigned Size, AsmToken ID);
120  bool ParseDirectiveTC(unsigned Size, AsmToken ID);
121  bool ParseDirectiveMachine(SMLoc L);
122  bool ParseDirectiveAbiVersion(SMLoc L);
123  bool ParseDirectiveLocalEntry(SMLoc L);
124  bool ParseGNUAttribute(SMLoc L);
125 
126  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
129  bool MatchingInlineAsm) override;
130 
131  void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
132 
133  /// @name Auto-generated Match Functions
134  /// {
135 
136 #define GET_ASSEMBLER_HEADER
137 #include "PPCGenAsmMatcher.inc"
138 
139  /// }
140 
141 
142 public:
143  PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
144  const MCInstrInfo &MII, const MCTargetOptions &Options)
145  : MCTargetAsmParser(Options, STI, MII) {
146  // Check for 64-bit vs. 32-bit pointer mode.
147  const Triple &TheTriple = STI.getTargetTriple();
148  IsPPC64 = TheTriple.isPPC64();
149  // Initialize the set of available features.
150  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
151  }
152 
153  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
154  SMLoc NameLoc, OperandVector &Operands) override;
155 
156  bool ParseDirective(AsmToken DirectiveID) override;
157 
158  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
159  unsigned Kind) override;
160 
161  const MCExpr *applyModifierToExpr(const MCExpr *E,
163  MCContext &Ctx) override;
164 };
165 
166 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
167 /// instruction.
168 struct PPCOperand : public MCParsedAsmOperand {
169  enum KindTy {
170  Token,
171  Immediate,
172  ContextImmediate,
173  Expression,
174  TLSRegister
175  } Kind;
176 
177  SMLoc StartLoc, EndLoc;
178  bool IsPPC64;
179 
180  struct TokOp {
181  const char *Data;
182  unsigned Length;
183  };
184 
185  struct ImmOp {
186  int64_t Val;
187  };
188 
189  struct ExprOp {
190  const MCExpr *Val;
191  int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
192  };
193 
194  struct TLSRegOp {
195  const MCSymbolRefExpr *Sym;
196  };
197 
198  union {
199  struct TokOp Tok;
200  struct ImmOp Imm;
201  struct ExprOp Expr;
202  struct TLSRegOp TLSReg;
203  };
204 
205  PPCOperand(KindTy K) : Kind(K) {}
206 
207 public:
208  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
209  Kind = o.Kind;
210  StartLoc = o.StartLoc;
211  EndLoc = o.EndLoc;
212  IsPPC64 = o.IsPPC64;
213  switch (Kind) {
214  case Token:
215  Tok = o.Tok;
216  break;
217  case Immediate:
218  case ContextImmediate:
219  Imm = o.Imm;
220  break;
221  case Expression:
222  Expr = o.Expr;
223  break;
224  case TLSRegister:
225  TLSReg = o.TLSReg;
226  break;
227  }
228  }
229 
230  // Disable use of sized deallocation due to overallocation of PPCOperand
231  // objects in CreateTokenWithStringCopy.
232  void operator delete(void *p) { ::operator delete(p); }
233 
234  /// getStartLoc - Get the location of the first token of this operand.
235  SMLoc getStartLoc() const override { return StartLoc; }
236 
237  /// getEndLoc - Get the location of the last token of this operand.
238  SMLoc getEndLoc() const override { return EndLoc; }
239 
240  /// getLocRange - Get the range between the first and last token of this
241  /// operand.
242  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
243 
244  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
245  bool isPPC64() const { return IsPPC64; }
246 
247  int64_t getImm() const {
248  assert(Kind == Immediate && "Invalid access!");
249  return Imm.Val;
250  }
251  int64_t getImmS16Context() const {
252  assert((Kind == Immediate || Kind == ContextImmediate) &&
253  "Invalid access!");
254  if (Kind == Immediate)
255  return Imm.Val;
256  return static_cast<int16_t>(Imm.Val);
257  }
258  int64_t getImmU16Context() const {
259  assert((Kind == Immediate || Kind == ContextImmediate) &&
260  "Invalid access!");
261  return Imm.Val;
262  }
263 
264  const MCExpr *getExpr() const {
265  assert(Kind == Expression && "Invalid access!");
266  return Expr.Val;
267  }
268 
269  int64_t getExprCRVal() const {
270  assert(Kind == Expression && "Invalid access!");
271  return Expr.CRVal;
272  }
273 
274  const MCExpr *getTLSReg() const {
275  assert(Kind == TLSRegister && "Invalid access!");
276  return TLSReg.Sym;
277  }
278 
279  unsigned getReg() const override {
280  assert(isRegNumber() && "Invalid access!");
281  return (unsigned) Imm.Val;
282  }
283 
284  unsigned getVSReg() const {
285  assert(isVSRegNumber() && "Invalid access!");
286  return (unsigned) Imm.Val;
287  }
288 
289  unsigned getACCReg() const {
290  assert(isACCRegNumber() && "Invalid access!");
291  return (unsigned) Imm.Val;
292  }
293 
294  unsigned getDMRROWReg() const {
295  assert(isDMRROWRegNumber() && "Invalid access!");
296  return (unsigned)Imm.Val;
297  }
298 
299  unsigned getDMRROWpReg() const {
300  assert(isDMRROWpRegNumber() && "Invalid access!");
301  return (unsigned)Imm.Val;
302  }
303 
304  unsigned getDMRReg() const {
305  assert(isDMRRegNumber() && "Invalid access!");
306  return (unsigned)Imm.Val;
307  }
308 
309  unsigned getDMRpReg() const {
310  assert(isDMRpRegNumber() && "Invalid access!");
311  return (unsigned)Imm.Val;
312  }
313 
314  unsigned getVSRpEvenReg() const {
315  assert(isVSRpEvenRegNumber() && "Invalid access!");
316  return (unsigned) Imm.Val >> 1;
317  }
318 
319  unsigned getG8pReg() const {
320  assert(isEvenRegNumber() && "Invalid access!");
321  return (unsigned)Imm.Val;
322  }
323 
324  unsigned getCCReg() const {
325  assert(isCCRegNumber() && "Invalid access!");
326  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
327  }
328 
329  unsigned getCRBit() const {
330  assert(isCRBitNumber() && "Invalid access!");
331  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
332  }
333 
334  unsigned getCRBitMask() const {
335  assert(isCRBitMask() && "Invalid access!");
336  return 7 - countTrailingZeros<uint64_t>(Imm.Val);
337  }
338 
339  bool isToken() const override { return Kind == Token; }
340  bool isImm() const override {
341  return Kind == Immediate || Kind == Expression;
342  }
343  bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
344  bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
345  bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
346  bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
347  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
348  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
349  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
350  bool isU6ImmX2() const { return Kind == Immediate &&
351  isUInt<6>(getImm()) &&
352  (getImm() & 1) == 0; }
353  bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
354  bool isU7ImmX4() const { return Kind == Immediate &&
355  isUInt<7>(getImm()) &&
356  (getImm() & 3) == 0; }
357  bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
358  bool isU8ImmX8() const { return Kind == Immediate &&
359  isUInt<8>(getImm()) &&
360  (getImm() & 7) == 0; }
361 
362  bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
363  bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
364  bool isU16Imm() const { return isExtImm<16>(/*Signed*/ false, 1); }
365  bool isS16Imm() const { return isExtImm<16>(/*Signed*/ true, 1); }
366  bool isS16ImmX4() const { return isExtImm<16>(/*Signed*/ true, 4); }
367  bool isS16ImmX16() const { return isExtImm<16>(/*Signed*/ true, 16); }
368  bool isS17Imm() const { return isExtImm<17>(/*Signed*/ true, 1); }
369 
370  bool isHashImmX8() const {
371  // The Hash Imm form is used for instructions that check or store a hash.
372  // These instructions have a small immediate range that spans between
373  // -8 and -512.
374  return (Kind == Immediate && getImm() <= -8 && getImm() >= -512 &&
375  (getImm() & 7) == 0);
376  }
377 
378  bool isS34ImmX16() const {
379  return Kind == Expression ||
380  (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
381  }
382  bool isS34Imm() const {
383  // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
384  // ContextImmediate is needed.
385  return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()));
386  }
387 
388  bool isTLSReg() const { return Kind == TLSRegister; }
389  bool isDirectBr() const {
390  if (Kind == Expression)
391  return true;
392  if (Kind != Immediate)
393  return false;
394  // Operand must be 64-bit aligned, signed 27-bit immediate.
395  if ((getImm() & 3) != 0)
396  return false;
397  if (isInt<26>(getImm()))
398  return true;
399  if (!IsPPC64) {
400  // In 32-bit mode, large 32-bit quantities wrap around.
401  if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
402  return true;
403  }
404  return false;
405  }
406  bool isCondBr() const { return Kind == Expression ||
407  (Kind == Immediate && isInt<16>(getImm()) &&
408  (getImm() & 3) == 0); }
409  bool isImmZero() const { return Kind == Immediate && getImm() == 0; }
410  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
411  bool isACCRegNumber() const {
412  return Kind == Immediate && isUInt<3>(getImm());
413  }
414  bool isDMRROWRegNumber() const {
415  return Kind == Immediate && isUInt<6>(getImm());
416  }
417  bool isDMRROWpRegNumber() const {
418  return Kind == Immediate && isUInt<5>(getImm());
419  }
420  bool isDMRRegNumber() const {
421  return Kind == Immediate && isUInt<3>(getImm());
422  }
423  bool isDMRpRegNumber() const {
424  return Kind == Immediate && isUInt<2>(getImm());
425  }
426  bool isVSRpEvenRegNumber() const {
427  return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0);
428  }
429  bool isVSRegNumber() const {
430  return Kind == Immediate && isUInt<6>(getImm());
431  }
432  bool isCCRegNumber() const { return (Kind == Expression
433  && isUInt<3>(getExprCRVal())) ||
434  (Kind == Immediate
435  && isUInt<3>(getImm())); }
436  bool isCRBitNumber() const { return (Kind == Expression
437  && isUInt<5>(getExprCRVal())) ||
438  (Kind == Immediate
439  && isUInt<5>(getImm())); }
440 
441  bool isEvenRegNumber() const { return isRegNumber() && (getImm() & 1) == 0; }
442 
443  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
444  isPowerOf2_32(getImm()); }
445  bool isATBitsAsHint() const { return false; }
446  bool isMem() const override { return false; }
447  bool isReg() const override { return false; }
448 
449  void addRegOperands(MCInst &Inst, unsigned N) const {
450  llvm_unreachable("addRegOperands");
451  }
452 
453  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
454  assert(N == 1 && "Invalid number of operands!");
455  Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
456  }
457 
458  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
459  assert(N == 1 && "Invalid number of operands!");
460  Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
461  }
462 
463  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
464  assert(N == 1 && "Invalid number of operands!");
465  Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
466  }
467 
468  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
469  assert(N == 1 && "Invalid number of operands!");
470  Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
471  }
472 
473  void addRegG8pRCOperands(MCInst &Inst, unsigned N) const {
474  assert(N == 1 && "Invalid number of operands!");
475  Inst.addOperand(MCOperand::createReg(XRegs[getG8pReg()]));
476  }
477 
478  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
479  if (isPPC64())
480  addRegG8RCOperands(Inst, N);
481  else
482  addRegGPRCOperands(Inst, N);
483  }
484 
485  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
486  if (isPPC64())
487  addRegG8RCNoX0Operands(Inst, N);
488  else
489  addRegGPRCNoR0Operands(Inst, N);
490  }
491 
492  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
493  assert(N == 1 && "Invalid number of operands!");
494  Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
495  }
496 
497  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
498  assert(N == 1 && "Invalid number of operands!");
499  Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
500  }
501 
502  void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
503  assert(N == 1 && "Invalid number of operands!");
504  Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
505  }
506 
507  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
508  assert(N == 1 && "Invalid number of operands!");
509  Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
510  }
511 
512  void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
513  assert(N == 1 && "Invalid number of operands!");
514  Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
515  }
516 
517  void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
518  assert(N == 1 && "Invalid number of operands!");
519  Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
520  }
521 
522  void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
523  assert(N == 1 && "Invalid number of operands!");
524  Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
525  }
526 
527  void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
528  assert(N == 1 && "Invalid number of operands!");
529  Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
530  }
531 
532  void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
533  assert(N == 1 && "Invalid number of operands!");
534  Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
535  }
536 
537  void addRegACCRCOperands(MCInst &Inst, unsigned N) const {
538  assert(N == 1 && "Invalid number of operands!");
539  Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()]));
540  }
541 
542  void addRegDMRROWRCOperands(MCInst &Inst, unsigned N) const {
543  assert(N == 1 && "Invalid number of operands!");
544  Inst.addOperand(MCOperand::createReg(DMRROWRegs[getDMRROWReg()]));
545  }
546 
547  void addRegDMRROWpRCOperands(MCInst &Inst, unsigned N) const {
548  assert(N == 1 && "Invalid number of operands!");
549  Inst.addOperand(MCOperand::createReg(DMRROWpRegs[getDMRROWpReg()]));
550  }
551 
552  void addRegDMRRCOperands(MCInst &Inst, unsigned N) const {
553  assert(N == 1 && "Invalid number of operands!");
554  Inst.addOperand(MCOperand::createReg(DMRRegs[getDMRReg()]));
555  }
556 
557  void addRegDMRpRCOperands(MCInst &Inst, unsigned N) const {
558  assert(N == 1 && "Invalid number of operands!");
559  Inst.addOperand(MCOperand::createReg(DMRpRegs[getDMRpReg()]));
560  }
561 
562  void addRegWACCRCOperands(MCInst &Inst, unsigned N) const {
563  assert(N == 1 && "Invalid number of operands!");
564  Inst.addOperand(MCOperand::createReg(WACCRegs[getACCReg()]));
565  }
566 
567  void addRegWACC_HIRCOperands(MCInst &Inst, unsigned N) const {
568  assert(N == 1 && "Invalid number of operands!");
569  Inst.addOperand(MCOperand::createReg(WACC_HIRegs[getACCReg()]));
570  }
571 
572  void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const {
573  assert(N == 1 && "Invalid number of operands!");
574  Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
575  }
576 
577  void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const {
578  assert(N == 1 && "Invalid number of operands!");
579  Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
580  }
581 
582  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
583  assert(N == 1 && "Invalid number of operands!");
584  Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
585  }
586 
587  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
588  assert(N == 1 && "Invalid number of operands!");
589  Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
590  }
591 
592  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
593  assert(N == 1 && "Invalid number of operands!");
594  Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
595  }
596 
597  void addImmOperands(MCInst &Inst, unsigned N) const {
598  assert(N == 1 && "Invalid number of operands!");
599  if (Kind == Immediate)
600  Inst.addOperand(MCOperand::createImm(getImm()));
601  else
603  }
604 
605  void addS16ImmOperands(MCInst &Inst, unsigned N) const {
606  assert(N == 1 && "Invalid number of operands!");
607  switch (Kind) {
608  case Immediate:
609  Inst.addOperand(MCOperand::createImm(getImm()));
610  break;
611  case ContextImmediate:
612  Inst.addOperand(MCOperand::createImm(getImmS16Context()));
613  break;
614  default:
616  break;
617  }
618  }
619 
620  void addU16ImmOperands(MCInst &Inst, unsigned N) const {
621  assert(N == 1 && "Invalid number of operands!");
622  switch (Kind) {
623  case Immediate:
624  Inst.addOperand(MCOperand::createImm(getImm()));
625  break;
626  case ContextImmediate:
627  Inst.addOperand(MCOperand::createImm(getImmU16Context()));
628  break;
629  default:
631  break;
632  }
633  }
634 
635  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
636  assert(N == 1 && "Invalid number of operands!");
637  if (Kind == Immediate)
638  Inst.addOperand(MCOperand::createImm(getImm() / 4));
639  else
641  }
642 
643  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
644  assert(N == 1 && "Invalid number of operands!");
645  Inst.addOperand(MCOperand::createExpr(getTLSReg()));
646  }
647 
648  StringRef getToken() const {
649  assert(Kind == Token && "Invalid access!");
650  return StringRef(Tok.Data, Tok.Length);
651  }
652 
653  void print(raw_ostream &OS) const override;
654 
655  static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
656  bool IsPPC64) {
657  auto Op = std::make_unique<PPCOperand>(Token);
658  Op->Tok.Data = Str.data();
659  Op->Tok.Length = Str.size();
660  Op->StartLoc = S;
661  Op->EndLoc = S;
662  Op->IsPPC64 = IsPPC64;
663  return Op;
664  }
665 
666  static std::unique_ptr<PPCOperand>
667  CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
668  // Allocate extra memory for the string and copy it.
669  // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
670  // deleter which will destroy them by simply using "delete", not correctly
671  // calling operator delete on this extra memory after calling the dtor
672  // explicitly.
673  void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
674  std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
675  Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
676  Op->Tok.Length = Str.size();
677  std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
678  Op->StartLoc = S;
679  Op->EndLoc = S;
680  Op->IsPPC64 = IsPPC64;
681  return Op;
682  }
683 
684  static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
685  bool IsPPC64) {
686  auto Op = std::make_unique<PPCOperand>(Immediate);
687  Op->Imm.Val = Val;
688  Op->StartLoc = S;
689  Op->EndLoc = E;
690  Op->IsPPC64 = IsPPC64;
691  return Op;
692  }
693 
694  static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
695  SMLoc E, bool IsPPC64) {
696  auto Op = std::make_unique<PPCOperand>(Expression);
697  Op->Expr.Val = Val;
698  Op->Expr.CRVal = EvaluateCRExpr(Val);
699  Op->StartLoc = S;
700  Op->EndLoc = E;
701  Op->IsPPC64 = IsPPC64;
702  return Op;
703  }
704 
705  static std::unique_ptr<PPCOperand>
706  CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
707  auto Op = std::make_unique<PPCOperand>(TLSRegister);
708  Op->TLSReg.Sym = Sym;
709  Op->StartLoc = S;
710  Op->EndLoc = E;
711  Op->IsPPC64 = IsPPC64;
712  return Op;
713  }
714 
715  static std::unique_ptr<PPCOperand>
716  CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
717  auto Op = std::make_unique<PPCOperand>(ContextImmediate);
718  Op->Imm.Val = Val;
719  Op->StartLoc = S;
720  Op->EndLoc = E;
721  Op->IsPPC64 = IsPPC64;
722  return Op;
723  }
724 
725  static std::unique_ptr<PPCOperand>
726  CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
727  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
728  return CreateImm(CE->getValue(), S, E, IsPPC64);
729 
730  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
731  if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS ||
732  SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL)
733  return CreateTLSReg(SRE, S, E, IsPPC64);
734 
735  if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
736  int64_t Res;
737  if (TE->evaluateAsConstant(Res))
738  return CreateContextImm(Res, S, E, IsPPC64);
739  }
740 
741  return CreateExpr(Val, S, E, IsPPC64);
742  }
743 
744 private:
745  template <unsigned Width>
746  bool isExtImm(bool Signed, unsigned Multiple) const {
747  switch (Kind) {
748  default:
749  return false;
750  case Expression:
751  return true;
752  case Immediate:
753  case ContextImmediate:
754  if (Signed)
755  return isInt<Width>(getImmS16Context()) &&
756  (getImmS16Context() & (Multiple - 1)) == 0;
757  else
758  return isUInt<Width>(getImmU16Context()) &&
759  (getImmU16Context() & (Multiple - 1)) == 0;
760  }
761  }
762 };
763 
764 } // end anonymous namespace.
765 
766 void PPCOperand::print(raw_ostream &OS) const {
767  switch (Kind) {
768  case Token:
769  OS << "'" << getToken() << "'";
770  break;
771  case Immediate:
772  case ContextImmediate:
773  OS << getImm();
774  break;
775  case Expression:
776  OS << *getExpr();
777  break;
778  case TLSRegister:
779  OS << *getTLSReg();
780  break;
781  }
782 }
783 
784 static void
786  if (Op.isImm()) {
787  Inst.addOperand(MCOperand::createImm(-Op.getImm()));
788  return;
789  }
790  const MCExpr *Expr = Op.getExpr();
791  if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
792  if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
793  Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
794  return;
795  }
796  } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
797  if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
798  const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
799  BinExpr->getLHS(), Ctx);
801  return;
802  }
803  }
805 }
806 
807 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
808  const OperandVector &Operands) {
809  int Opcode = Inst.getOpcode();
810  switch (Opcode) {
811  case PPC::DCBTx:
812  case PPC::DCBTT:
813  case PPC::DCBTSTx:
814  case PPC::DCBTSTT: {
815  MCInst TmpInst;
816  TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
817  PPC::DCBT : PPC::DCBTST);
819  (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
820  TmpInst.addOperand(Inst.getOperand(0));
821  TmpInst.addOperand(Inst.getOperand(1));
822  Inst = TmpInst;
823  break;
824  }
825  case PPC::DCBTCT:
826  case PPC::DCBTDS: {
827  MCInst TmpInst;
828  TmpInst.setOpcode(PPC::DCBT);
829  TmpInst.addOperand(Inst.getOperand(2));
830  TmpInst.addOperand(Inst.getOperand(0));
831  TmpInst.addOperand(Inst.getOperand(1));
832  Inst = TmpInst;
833  break;
834  }
835  case PPC::DCBTSTCT:
836  case PPC::DCBTSTDS: {
837  MCInst TmpInst;
838  TmpInst.setOpcode(PPC::DCBTST);
839  TmpInst.addOperand(Inst.getOperand(2));
840  TmpInst.addOperand(Inst.getOperand(0));
841  TmpInst.addOperand(Inst.getOperand(1));
842  Inst = TmpInst;
843  break;
844  }
845  case PPC::DCBFx:
846  case PPC::DCBFL:
847  case PPC::DCBFLP:
848  case PPC::DCBFPS:
849  case PPC::DCBSTPS: {
850  int L = 0;
851  if (Opcode == PPC::DCBFL)
852  L = 1;
853  else if (Opcode == PPC::DCBFLP)
854  L = 3;
855  else if (Opcode == PPC::DCBFPS)
856  L = 4;
857  else if (Opcode == PPC::DCBSTPS)
858  L = 6;
859 
860  MCInst TmpInst;
861  TmpInst.setOpcode(PPC::DCBF);
862  TmpInst.addOperand(MCOperand::createImm(L));
863  TmpInst.addOperand(Inst.getOperand(0));
864  TmpInst.addOperand(Inst.getOperand(1));
865  Inst = TmpInst;
866  break;
867  }
868  case PPC::LAx: {
869  MCInst TmpInst;
870  TmpInst.setOpcode(PPC::LA);
871  TmpInst.addOperand(Inst.getOperand(0));
872  TmpInst.addOperand(Inst.getOperand(2));
873  TmpInst.addOperand(Inst.getOperand(1));
874  Inst = TmpInst;
875  break;
876  }
877  case PPC::SUBI: {
878  MCInst TmpInst;
879  TmpInst.setOpcode(PPC::ADDI);
880  TmpInst.addOperand(Inst.getOperand(0));
881  TmpInst.addOperand(Inst.getOperand(1));
882  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
883  Inst = TmpInst;
884  break;
885  }
886  case PPC::SUBIS: {
887  MCInst TmpInst;
888  TmpInst.setOpcode(PPC::ADDIS);
889  TmpInst.addOperand(Inst.getOperand(0));
890  TmpInst.addOperand(Inst.getOperand(1));
891  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
892  Inst = TmpInst;
893  break;
894  }
895  case PPC::SUBIC: {
896  MCInst TmpInst;
897  TmpInst.setOpcode(PPC::ADDIC);
898  TmpInst.addOperand(Inst.getOperand(0));
899  TmpInst.addOperand(Inst.getOperand(1));
900  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
901  Inst = TmpInst;
902  break;
903  }
904  case PPC::SUBIC_rec: {
905  MCInst TmpInst;
906  TmpInst.setOpcode(PPC::ADDIC_rec);
907  TmpInst.addOperand(Inst.getOperand(0));
908  TmpInst.addOperand(Inst.getOperand(1));
909  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
910  Inst = TmpInst;
911  break;
912  }
913  case PPC::EXTLWI:
914  case PPC::EXTLWI_rec: {
915  MCInst TmpInst;
916  int64_t N = Inst.getOperand(2).getImm();
917  int64_t B = Inst.getOperand(3).getImm();
918  TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec);
919  TmpInst.addOperand(Inst.getOperand(0));
920  TmpInst.addOperand(Inst.getOperand(1));
922  TmpInst.addOperand(MCOperand::createImm(0));
923  TmpInst.addOperand(MCOperand::createImm(N - 1));
924  Inst = TmpInst;
925  break;
926  }
927  case PPC::EXTRWI:
928  case PPC::EXTRWI_rec: {
929  MCInst TmpInst;
930  int64_t N = Inst.getOperand(2).getImm();
931  int64_t B = Inst.getOperand(3).getImm();
932  TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
933  TmpInst.addOperand(Inst.getOperand(0));
934  TmpInst.addOperand(Inst.getOperand(1));
935  TmpInst.addOperand(MCOperand::createImm(B + N));
936  TmpInst.addOperand(MCOperand::createImm(32 - N));
937  TmpInst.addOperand(MCOperand::createImm(31));
938  Inst = TmpInst;
939  break;
940  }
941  case PPC::INSLWI:
942  case PPC::INSLWI_rec: {
943  MCInst TmpInst;
944  int64_t N = Inst.getOperand(2).getImm();
945  int64_t B = Inst.getOperand(3).getImm();
946  TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
947  TmpInst.addOperand(Inst.getOperand(0));
948  TmpInst.addOperand(Inst.getOperand(0));
949  TmpInst.addOperand(Inst.getOperand(1));
950  TmpInst.addOperand(MCOperand::createImm(32 - B));
952  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
953  Inst = TmpInst;
954  break;
955  }
956  case PPC::INSRWI:
957  case PPC::INSRWI_rec: {
958  MCInst TmpInst;
959  int64_t N = Inst.getOperand(2).getImm();
960  int64_t B = Inst.getOperand(3).getImm();
961  TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
962  TmpInst.addOperand(Inst.getOperand(0));
963  TmpInst.addOperand(Inst.getOperand(0));
964  TmpInst.addOperand(Inst.getOperand(1));
965  TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
967  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
968  Inst = TmpInst;
969  break;
970  }
971  case PPC::ROTRWI:
972  case PPC::ROTRWI_rec: {
973  MCInst TmpInst;
974  int64_t N = Inst.getOperand(2).getImm();
975  TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
976  TmpInst.addOperand(Inst.getOperand(0));
977  TmpInst.addOperand(Inst.getOperand(1));
978  TmpInst.addOperand(MCOperand::createImm(32 - N));
979  TmpInst.addOperand(MCOperand::createImm(0));
980  TmpInst.addOperand(MCOperand::createImm(31));
981  Inst = TmpInst;
982  break;
983  }
984  case PPC::SLWI:
985  case PPC::SLWI_rec: {
986  MCInst TmpInst;
987  int64_t N = Inst.getOperand(2).getImm();
988  TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec);
989  TmpInst.addOperand(Inst.getOperand(0));
990  TmpInst.addOperand(Inst.getOperand(1));
992  TmpInst.addOperand(MCOperand::createImm(0));
993  TmpInst.addOperand(MCOperand::createImm(31 - N));
994  Inst = TmpInst;
995  break;
996  }
997  case PPC::SRWI:
998  case PPC::SRWI_rec: {
999  MCInst TmpInst;
1000  int64_t N = Inst.getOperand(2).getImm();
1001  TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1002  TmpInst.addOperand(Inst.getOperand(0));
1003  TmpInst.addOperand(Inst.getOperand(1));
1004  TmpInst.addOperand(MCOperand::createImm(32 - N));
1005  TmpInst.addOperand(MCOperand::createImm(N));
1006  TmpInst.addOperand(MCOperand::createImm(31));
1007  Inst = TmpInst;
1008  break;
1009  }
1010  case PPC::CLRRWI:
1011  case PPC::CLRRWI_rec: {
1012  MCInst TmpInst;
1013  int64_t N = Inst.getOperand(2).getImm();
1014  TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1015  TmpInst.addOperand(Inst.getOperand(0));
1016  TmpInst.addOperand(Inst.getOperand(1));
1017  TmpInst.addOperand(MCOperand::createImm(0));
1018  TmpInst.addOperand(MCOperand::createImm(0));
1019  TmpInst.addOperand(MCOperand::createImm(31 - N));
1020  Inst = TmpInst;
1021  break;
1022  }
1023  case PPC::CLRLSLWI:
1024  case PPC::CLRLSLWI_rec: {
1025  MCInst TmpInst;
1026  int64_t B = Inst.getOperand(2).getImm();
1027  int64_t N = Inst.getOperand(3).getImm();
1028  TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec);
1029  TmpInst.addOperand(Inst.getOperand(0));
1030  TmpInst.addOperand(Inst.getOperand(1));
1031  TmpInst.addOperand(MCOperand::createImm(N));
1032  TmpInst.addOperand(MCOperand::createImm(B - N));
1033  TmpInst.addOperand(MCOperand::createImm(31 - N));
1034  Inst = TmpInst;
1035  break;
1036  }
1037  case PPC::EXTLDI:
1038  case PPC::EXTLDI_rec: {
1039  MCInst TmpInst;
1040  int64_t N = Inst.getOperand(2).getImm();
1041  int64_t B = Inst.getOperand(3).getImm();
1042  TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1043  TmpInst.addOperand(Inst.getOperand(0));
1044  TmpInst.addOperand(Inst.getOperand(1));
1045  TmpInst.addOperand(MCOperand::createImm(B));
1046  TmpInst.addOperand(MCOperand::createImm(N - 1));
1047  Inst = TmpInst;
1048  break;
1049  }
1050  case PPC::EXTRDI:
1051  case PPC::EXTRDI_rec: {
1052  MCInst TmpInst;
1053  int64_t N = Inst.getOperand(2).getImm();
1054  int64_t B = Inst.getOperand(3).getImm();
1055  TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1056  TmpInst.addOperand(Inst.getOperand(0));
1057  TmpInst.addOperand(Inst.getOperand(1));
1058  TmpInst.addOperand(MCOperand::createImm(B + N));
1059  TmpInst.addOperand(MCOperand::createImm(64 - N));
1060  Inst = TmpInst;
1061  break;
1062  }
1063  case PPC::INSRDI:
1064  case PPC::INSRDI_rec: {
1065  MCInst TmpInst;
1066  int64_t N = Inst.getOperand(2).getImm();
1067  int64_t B = Inst.getOperand(3).getImm();
1068  TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec);
1069  TmpInst.addOperand(Inst.getOperand(0));
1070  TmpInst.addOperand(Inst.getOperand(0));
1071  TmpInst.addOperand(Inst.getOperand(1));
1072  TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1073  TmpInst.addOperand(MCOperand::createImm(B));
1074  Inst = TmpInst;
1075  break;
1076  }
1077  case PPC::ROTRDI:
1078  case PPC::ROTRDI_rec: {
1079  MCInst TmpInst;
1080  int64_t N = Inst.getOperand(2).getImm();
1081  TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1082  TmpInst.addOperand(Inst.getOperand(0));
1083  TmpInst.addOperand(Inst.getOperand(1));
1084  TmpInst.addOperand(MCOperand::createImm(64 - N));
1085  TmpInst.addOperand(MCOperand::createImm(0));
1086  Inst = TmpInst;
1087  break;
1088  }
1089  case PPC::SLDI:
1090  case PPC::SLDI_rec: {
1091  MCInst TmpInst;
1092  int64_t N = Inst.getOperand(2).getImm();
1093  TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1094  TmpInst.addOperand(Inst.getOperand(0));
1095  TmpInst.addOperand(Inst.getOperand(1));
1096  TmpInst.addOperand(MCOperand::createImm(N));
1097  TmpInst.addOperand(MCOperand::createImm(63 - N));
1098  Inst = TmpInst;
1099  break;
1100  }
1101  case PPC::SUBPCIS: {
1102  MCInst TmpInst;
1103  int64_t N = Inst.getOperand(1).getImm();
1104  TmpInst.setOpcode(PPC::ADDPCIS);
1105  TmpInst.addOperand(Inst.getOperand(0));
1106  TmpInst.addOperand(MCOperand::createImm(-N));
1107  Inst = TmpInst;
1108  break;
1109  }
1110  case PPC::SRDI:
1111  case PPC::SRDI_rec: {
1112  MCInst TmpInst;
1113  int64_t N = Inst.getOperand(2).getImm();
1114  TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1115  TmpInst.addOperand(Inst.getOperand(0));
1116  TmpInst.addOperand(Inst.getOperand(1));
1117  TmpInst.addOperand(MCOperand::createImm(64 - N));
1118  TmpInst.addOperand(MCOperand::createImm(N));
1119  Inst = TmpInst;
1120  break;
1121  }
1122  case PPC::CLRRDI:
1123  case PPC::CLRRDI_rec: {
1124  MCInst TmpInst;
1125  int64_t N = Inst.getOperand(2).getImm();
1126  TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec);
1127  TmpInst.addOperand(Inst.getOperand(0));
1128  TmpInst.addOperand(Inst.getOperand(1));
1129  TmpInst.addOperand(MCOperand::createImm(0));
1130  TmpInst.addOperand(MCOperand::createImm(63 - N));
1131  Inst = TmpInst;
1132  break;
1133  }
1134  case PPC::CLRLSLDI:
1135  case PPC::CLRLSLDI_rec: {
1136  MCInst TmpInst;
1137  int64_t B = Inst.getOperand(2).getImm();
1138  int64_t N = Inst.getOperand(3).getImm();
1139  TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec);
1140  TmpInst.addOperand(Inst.getOperand(0));
1141  TmpInst.addOperand(Inst.getOperand(1));
1142  TmpInst.addOperand(MCOperand::createImm(N));
1143  TmpInst.addOperand(MCOperand::createImm(B - N));
1144  Inst = TmpInst;
1145  break;
1146  }
1147  case PPC::RLWINMbm:
1148  case PPC::RLWINMbm_rec: {
1149  unsigned MB, ME;
1150  int64_t BM = Inst.getOperand(3).getImm();
1151  if (!isRunOfOnes(BM, MB, ME))
1152  break;
1153 
1154  MCInst TmpInst;
1155  TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec);
1156  TmpInst.addOperand(Inst.getOperand(0));
1157  TmpInst.addOperand(Inst.getOperand(1));
1158  TmpInst.addOperand(Inst.getOperand(2));
1159  TmpInst.addOperand(MCOperand::createImm(MB));
1160  TmpInst.addOperand(MCOperand::createImm(ME));
1161  Inst = TmpInst;
1162  break;
1163  }
1164  case PPC::RLWIMIbm:
1165  case PPC::RLWIMIbm_rec: {
1166  unsigned MB, ME;
1167  int64_t BM = Inst.getOperand(3).getImm();
1168  if (!isRunOfOnes(BM, MB, ME))
1169  break;
1170 
1171  MCInst TmpInst;
1172  TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec);
1173  TmpInst.addOperand(Inst.getOperand(0));
1174  TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1175  TmpInst.addOperand(Inst.getOperand(1));
1176  TmpInst.addOperand(Inst.getOperand(2));
1177  TmpInst.addOperand(MCOperand::createImm(MB));
1178  TmpInst.addOperand(MCOperand::createImm(ME));
1179  Inst = TmpInst;
1180  break;
1181  }
1182  case PPC::RLWNMbm:
1183  case PPC::RLWNMbm_rec: {
1184  unsigned MB, ME;
1185  int64_t BM = Inst.getOperand(3).getImm();
1186  if (!isRunOfOnes(BM, MB, ME))
1187  break;
1188 
1189  MCInst TmpInst;
1190  TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec);
1191  TmpInst.addOperand(Inst.getOperand(0));
1192  TmpInst.addOperand(Inst.getOperand(1));
1193  TmpInst.addOperand(Inst.getOperand(2));
1194  TmpInst.addOperand(MCOperand::createImm(MB));
1195  TmpInst.addOperand(MCOperand::createImm(ME));
1196  Inst = TmpInst;
1197  break;
1198  }
1199  case PPC::MFTB: {
1200  if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1201  assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1202  Inst.setOpcode(PPC::MFSPR);
1203  }
1204  break;
1205  }
1206  }
1207 }
1208 
1209 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
1210  unsigned VariantID = 0);
1211 
1212 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1214  MCStreamer &Out, uint64_t &ErrorInfo,
1215  bool MatchingInlineAsm) {
1216  MCInst Inst;
1217 
1218  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1219  case Match_Success:
1220  // Post-process instructions (typically extended mnemonics)
1221  ProcessInstruction(Inst, Operands);
1222  Inst.setLoc(IDLoc);
1223  Out.emitInstruction(Inst, getSTI());
1224  return false;
1225  case Match_MissingFeature:
1226  return Error(IDLoc, "instruction use requires an option to be enabled");
1227  case Match_MnemonicFail: {
1228  FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1229  std::string Suggestion = PPCMnemonicSpellCheck(
1230  ((PPCOperand &)*Operands[0]).getToken(), FBS);
1231  return Error(IDLoc, "invalid instruction" + Suggestion,
1232  ((PPCOperand &)*Operands[0]).getLocRange());
1233  }
1234  case Match_InvalidOperand: {
1235  SMLoc ErrorLoc = IDLoc;
1236  if (ErrorInfo != ~0ULL) {
1237  if (ErrorInfo >= Operands.size())
1238  return Error(IDLoc, "too few operands for instruction");
1239 
1240  ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1241  if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1242  }
1243 
1244  return Error(ErrorLoc, "invalid operand for instruction");
1245  }
1246  }
1247 
1248  llvm_unreachable("Implement any new match types added!");
1249 }
1250 
1251 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1252  if (getParser().getTok().is(AsmToken::Percent))
1253  getParser().Lex(); // Eat the '%'.
1254 
1255  if (!getParser().getTok().is(AsmToken::Identifier))
1256  return true;
1257 
1258  StringRef Name = getParser().getTok().getString();
1259  if (Name.equals_insensitive("lr")) {
1260  RegNo = isPPC64() ? PPC::LR8 : PPC::LR;
1261  IntVal = 8;
1262  } else if (Name.equals_insensitive("ctr")) {
1263  RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR;
1264  IntVal = 9;
1265  } else if (Name.equals_insensitive("vrsave")) {
1266  RegNo = PPC::VRSAVE;
1267  IntVal = 256;
1268  } else if (Name.startswith_insensitive("r") &&
1269  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1270  RegNo = isPPC64() ? XRegs[IntVal] : RRegs[IntVal];
1271  } else if (Name.startswith_insensitive("f") &&
1272  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1273  RegNo = FRegs[IntVal];
1274  } else if (Name.startswith_insensitive("vs") &&
1275  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1276  RegNo = VSRegs[IntVal];
1277  } else if (Name.startswith_insensitive("v") &&
1278  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1279  RegNo = VRegs[IntVal];
1280  } else if (Name.startswith_insensitive("cr") &&
1281  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1282  RegNo = CRRegs[IntVal];
1283  } else if (Name.startswith_insensitive("acc") &&
1284  !Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
1285  RegNo = ACCRegs[IntVal];
1286  } else if (Name.startswith_insensitive("wacc_hi") &&
1287  !Name.substr(7).getAsInteger(10, IntVal) && IntVal < 8) {
1288  RegNo = ACCRegs[IntVal];
1289  } else if (Name.startswith_insensitive("wacc") &&
1290  !Name.substr(4).getAsInteger(10, IntVal) && IntVal < 8) {
1291  RegNo = WACCRegs[IntVal];
1292  } else if (Name.startswith_insensitive("dmrrowp") &&
1293  !Name.substr(7).getAsInteger(10, IntVal) && IntVal < 32) {
1294  RegNo = DMRROWpRegs[IntVal];
1295  } else if (Name.startswith_insensitive("dmrrow") &&
1296  !Name.substr(6).getAsInteger(10, IntVal) && IntVal < 64) {
1297  RegNo = DMRROWRegs[IntVal];
1298  } else if (Name.startswith_insensitive("dmrp") &&
1299  !Name.substr(4).getAsInteger(10, IntVal) && IntVal < 4) {
1300  RegNo = DMRROWpRegs[IntVal];
1301  } else if (Name.startswith_insensitive("dmr") &&
1302  !Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
1303  RegNo = DMRRegs[IntVal];
1304  } else
1305  return true;
1306  getParser().Lex();
1307  return false;
1308 }
1309 
1310 bool PPCAsmParser::
1311 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1312  if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
1313  return TokError("invalid register name");
1314  return false;
1315 }
1316 
1317 OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo,
1318  SMLoc &StartLoc,
1319  SMLoc &EndLoc) {
1320  const AsmToken &Tok = getParser().getTok();
1321  StartLoc = Tok.getLoc();
1322  EndLoc = Tok.getEndLoc();
1323  RegNo = 0;
1324  int64_t IntVal;
1325  if (MatchRegisterName(RegNo, IntVal))
1326  return MatchOperand_NoMatch;
1327  return MatchOperand_Success;
1328 }
1329 
1330 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1331 /// the expression and check for VK_PPC_LO/HI/HA
1332 /// symbol variants. If all symbols with modifier use the same
1333 /// variant, return the corresponding PPCMCExpr::VariantKind,
1334 /// and a modified expression using the default symbol variant.
1335 /// Otherwise, return NULL.
1336 const MCExpr *PPCAsmParser::
1337 ExtractModifierFromExpr(const MCExpr *E,
1338  PPCMCExpr::VariantKind &Variant) {
1339  MCContext &Context = getParser().getContext();
1341 
1342  switch (E->getKind()) {
1343  case MCExpr::Target:
1344  case MCExpr::Constant:
1345  return nullptr;
1346 
1347  case MCExpr::SymbolRef: {
1348  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1349 
1350  switch (SRE->getKind()) {
1353  break;
1356  break;
1359  break;
1362  break;
1365  break;
1368  break;
1371  break;
1374  break;
1377  break;
1378  default:
1379  return nullptr;
1380  }
1381 
1382  return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1383  }
1384 
1385  case MCExpr::Unary: {
1386  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1387  const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1388  if (!Sub)
1389  return nullptr;
1390  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1391  }
1392 
1393  case MCExpr::Binary: {
1394  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1395  PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1396  const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1397  const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1398 
1399  if (!LHS && !RHS)
1400  return nullptr;
1401 
1402  if (!LHS) LHS = BE->getLHS();
1403  if (!RHS) RHS = BE->getRHS();
1404 
1405  if (LHSVariant == PPCMCExpr::VK_PPC_None)
1406  Variant = RHSVariant;
1407  else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1408  Variant = LHSVariant;
1409  else if (LHSVariant == RHSVariant)
1410  Variant = LHSVariant;
1411  else
1412  return nullptr;
1413 
1414  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1415  }
1416  }
1417 
1418  llvm_unreachable("Invalid expression kind!");
1419 }
1420 
1421 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1422 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1423 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1424 /// FIXME: This is a hack.
1425 const MCExpr *PPCAsmParser::
1426 FixupVariantKind(const MCExpr *E) {
1427  MCContext &Context = getParser().getContext();
1428 
1429  switch (E->getKind()) {
1430  case MCExpr::Target:
1431  case MCExpr::Constant:
1432  return E;
1433 
1434  case MCExpr::SymbolRef: {
1435  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1437 
1438  switch (SRE->getKind()) {
1441  break;
1444  break;
1445  default:
1446  return E;
1447  }
1448  return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1449  }
1450 
1451  case MCExpr::Unary: {
1452  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1453  const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1454  if (Sub == UE->getSubExpr())
1455  return E;
1456  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1457  }
1458 
1459  case MCExpr::Binary: {
1460  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1461  const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1462  const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1463  if (LHS == BE->getLHS() && RHS == BE->getRHS())
1464  return E;
1465  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1466  }
1467  }
1468 
1469  llvm_unreachable("Invalid expression kind!");
1470 }
1471 
1472 /// ParseExpression. This differs from the default "parseExpression" in that
1473 /// it handles modifiers.
1474 bool PPCAsmParser::
1475 ParseExpression(const MCExpr *&EVal) {
1476  // (ELF Platforms)
1477  // Handle \code @l/@ha \endcode
1478  if (getParser().parseExpression(EVal))
1479  return true;
1480 
1481  EVal = FixupVariantKind(EVal);
1482 
1484  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1485  if (E)
1486  EVal = PPCMCExpr::create(Variant, E, getParser().getContext());
1487 
1488  return false;
1489 }
1490 
1491 /// ParseOperand
1492 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1493 /// rNN for MachO.
1494 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1495  MCAsmParser &Parser = getParser();
1496  SMLoc S = Parser.getTok().getLoc();
1497  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1498  const MCExpr *EVal;
1499 
1500  // Attempt to parse the next token as an immediate
1501  switch (getLexer().getKind()) {
1502  // Special handling for register names. These are interpreted
1503  // as immediates corresponding to the register number.
1504  case AsmToken::Percent: {
1505  unsigned RegNo;
1506  int64_t IntVal;
1507  if (MatchRegisterName(RegNo, IntVal))
1508  return Error(S, "invalid register name");
1509 
1510  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1511  return false;
1512  }
1513  case AsmToken::Identifier:
1514  case AsmToken::LParen:
1515  case AsmToken::Plus:
1516  case AsmToken::Minus:
1517  case AsmToken::Integer:
1518  case AsmToken::Dot:
1519  case AsmToken::Dollar:
1520  case AsmToken::Exclaim:
1521  case AsmToken::Tilde:
1522  if (!ParseExpression(EVal))
1523  break;
1524  // Fall-through
1525  [[fallthrough]];
1526  default:
1527  return Error(S, "unknown operand");
1528  }
1529 
1530  // Push the parsed operand into the list of operands
1531  Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1532 
1533  // Check whether this is a TLS call expression
1534  bool TLSCall = false;
1535  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1536  TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1537 
1538  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1539  const MCExpr *TLSSym;
1540 
1541  Parser.Lex(); // Eat the '('.
1542  S = Parser.getTok().getLoc();
1543  if (ParseExpression(TLSSym))
1544  return Error(S, "invalid TLS call expression");
1545  if (getLexer().isNot(AsmToken::RParen))
1546  return Error(Parser.getTok().getLoc(), "missing ')'");
1547  E = Parser.getTok().getLoc();
1548  Parser.Lex(); // Eat the ')'.
1549 
1550  Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1551  }
1552 
1553  // Otherwise, check for D-form memory operands
1554  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1555  Parser.Lex(); // Eat the '('.
1556  S = Parser.getTok().getLoc();
1557 
1558  int64_t IntVal;
1559  switch (getLexer().getKind()) {
1560  case AsmToken::Percent: {
1561  unsigned RegNo;
1562  if (MatchRegisterName(RegNo, IntVal))
1563  return Error(S, "invalid register name");
1564  break;
1565  }
1566  case AsmToken::Integer:
1567  if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1568  IntVal > 31)
1569  return Error(S, "invalid register number");
1570  break;
1571  case AsmToken::Identifier:
1572  default:
1573  return Error(S, "invalid memory operand");
1574  }
1575 
1576  E = Parser.getTok().getLoc();
1577  if (parseToken(AsmToken::RParen, "missing ')'"))
1578  return true;
1579  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1580  }
1581 
1582  return false;
1583 }
1584 
1585 /// Parse an instruction mnemonic followed by its operands.
1586 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1587  SMLoc NameLoc, OperandVector &Operands) {
1588  // The first operand is the token for the instruction name.
1589  // If the next character is a '+' or '-', we need to add it to the
1590  // instruction name, to match what TableGen is doing.
1591  std::string NewOpcode;
1592  if (parseOptionalToken(AsmToken::Plus)) {
1593  NewOpcode = std::string(Name);
1594  NewOpcode += '+';
1595  Name = NewOpcode;
1596  }
1597  if (parseOptionalToken(AsmToken::Minus)) {
1598  NewOpcode = std::string(Name);
1599  NewOpcode += '-';
1600  Name = NewOpcode;
1601  }
1602  // If the instruction ends in a '.', we need to create a separate
1603  // token for it, to match what TableGen is doing.
1604  size_t Dot = Name.find('.');
1605  StringRef Mnemonic = Name.slice(0, Dot);
1606  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1607  Operands.push_back(
1608  PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1609  else
1610  Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1611  if (Dot != StringRef::npos) {
1612  SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1613  StringRef DotStr = Name.slice(Dot, StringRef::npos);
1614  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1615  Operands.push_back(
1616  PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1617  else
1618  Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1619  }
1620 
1621  // If there are no more operands then finish
1622  if (parseOptionalToken(AsmToken::EndOfStatement))
1623  return false;
1624 
1625  // Parse the first operand
1626  if (ParseOperand(Operands))
1627  return true;
1628 
1629  while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1630  if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1631  return true;
1632  }
1633 
1634  // We'll now deal with an unfortunate special case: the syntax for the dcbt
1635  // and dcbtst instructions differs for server vs. embedded cores.
1636  // The syntax for dcbt is:
1637  // dcbt ra, rb, th [server]
1638  // dcbt th, ra, rb [embedded]
1639  // where th can be omitted when it is 0. dcbtst is the same. We take the
1640  // server form to be the default, so swap the operands if we're parsing for
1641  // an embedded core (they'll be swapped again upon printing).
1642  if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1643  Operands.size() == 4 &&
1644  (Name == "dcbt" || Name == "dcbtst")) {
1645  std::swap(Operands[1], Operands[3]);
1646  std::swap(Operands[2], Operands[1]);
1647  }
1648 
1649  // Handle base mnemonic for atomic loads where the EH bit is zero.
1650  if (Name == "lqarx" || Name == "ldarx" || Name == "lwarx" ||
1651  Name == "lharx" || Name == "lbarx") {
1652  if (Operands.size() != 5)
1653  return false;
1654  PPCOperand &EHOp = (PPCOperand &)*Operands[4];
1655  if (EHOp.isU1Imm() && EHOp.getImm() == 0)
1656  Operands.pop_back();
1657  }
1658 
1659  return false;
1660 }
1661 
1662 /// ParseDirective parses the PPC specific directives
1663 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1664  StringRef IDVal = DirectiveID.getIdentifier();
1665  if (IDVal == ".word")
1666  ParseDirectiveWord(2, DirectiveID);
1667  else if (IDVal == ".llong")
1668  ParseDirectiveWord(8, DirectiveID);
1669  else if (IDVal == ".tc")
1670  ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1671  else if (IDVal == ".machine")
1672  ParseDirectiveMachine(DirectiveID.getLoc());
1673  else if (IDVal == ".abiversion")
1674  ParseDirectiveAbiVersion(DirectiveID.getLoc());
1675  else if (IDVal == ".localentry")
1676  ParseDirectiveLocalEntry(DirectiveID.getLoc());
1677  else if (IDVal.startswith(".gnu_attribute"))
1678  ParseGNUAttribute(DirectiveID.getLoc());
1679  else
1680  return true;
1681  return false;
1682 }
1683 
1684 /// ParseDirectiveWord
1685 /// ::= .word [ expression (, expression)* ]
1686 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1687  auto parseOp = [&]() -> bool {
1688  const MCExpr *Value;
1689  SMLoc ExprLoc = getParser().getTok().getLoc();
1690  if (getParser().parseExpression(Value))
1691  return true;
1692  if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1693  assert(Size <= 8 && "Invalid size");
1694  uint64_t IntValue = MCE->getValue();
1695  if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1696  return Error(ExprLoc, "literal value out of range for '" +
1697  ID.getIdentifier() + "' directive");
1698  getStreamer().emitIntValue(IntValue, Size);
1699  } else
1700  getStreamer().emitValue(Value, Size, ExprLoc);
1701  return false;
1702  };
1703 
1704  if (parseMany(parseOp))
1705  return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1706  return false;
1707 }
1708 
1709 /// ParseDirectiveTC
1710 /// ::= .tc [ symbol (, expression)* ]
1711 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1712  MCAsmParser &Parser = getParser();
1713  // Skip TC symbol, which is only used with XCOFF.
1714  while (getLexer().isNot(AsmToken::EndOfStatement)
1715  && getLexer().isNot(AsmToken::Comma))
1716  Parser.Lex();
1717  if (parseToken(AsmToken::Comma))
1718  return addErrorSuffix(" in '.tc' directive");
1719 
1720  // Align to word size.
1721  getParser().getStreamer().emitValueToAlignment(Align(Size));
1722 
1723  // Emit expressions.
1724  return ParseDirectiveWord(Size, ID);
1725 }
1726 
1727 /// ParseDirectiveMachine (ELF platforms)
1728 /// ::= .machine [ cpu | "push" | "pop" ]
1729 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1730  MCAsmParser &Parser = getParser();
1731  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1732  Parser.getTok().isNot(AsmToken::String))
1733  return Error(L, "unexpected token in '.machine' directive");
1734 
1735  StringRef CPU = Parser.getTok().getIdentifier();
1736 
1737  // FIXME: Right now, the parser always allows any available
1738  // instruction, so the .machine directive is not useful.
1739  // In the wild, any/push/pop/ppc64/altivec/power[4-9] are seen.
1740 
1741  Parser.Lex();
1742 
1743  if (parseToken(AsmToken::EndOfStatement))
1744  return addErrorSuffix(" in '.machine' directive");
1745 
1746  PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1747  getParser().getStreamer().getTargetStreamer());
1748  if (TStreamer != nullptr)
1749  TStreamer->emitMachine(CPU);
1750 
1751  return false;
1752 }
1753 
1754 /// ParseDirectiveAbiVersion
1755 /// ::= .abiversion constant-expression
1756 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1757  int64_t AbiVersion;
1758  if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1759  "expected constant expression") ||
1760  parseToken(AsmToken::EndOfStatement))
1761  return addErrorSuffix(" in '.abiversion' directive");
1762 
1763  PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1764  getParser().getStreamer().getTargetStreamer());
1765  if (TStreamer != nullptr)
1766  TStreamer->emitAbiVersion(AbiVersion);
1767 
1768  return false;
1769 }
1770 
1771 /// ParseDirectiveLocalEntry
1772 /// ::= .localentry symbol, expression
1773 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1774  StringRef Name;
1775  if (getParser().parseIdentifier(Name))
1776  return Error(L, "expected identifier in '.localentry' directive");
1777 
1778  MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1779  const MCExpr *Expr;
1780 
1781  if (parseToken(AsmToken::Comma) ||
1782  check(getParser().parseExpression(Expr), L, "expected expression") ||
1783  parseToken(AsmToken::EndOfStatement))
1784  return addErrorSuffix(" in '.localentry' directive");
1785 
1786  PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1787  getParser().getStreamer().getTargetStreamer());
1788  if (TStreamer != nullptr)
1789  TStreamer->emitLocalEntry(Sym, Expr);
1790 
1791  return false;
1792 }
1793 
1794 bool PPCAsmParser::ParseGNUAttribute(SMLoc L) {
1795  int64_t Tag;
1796  int64_t IntegerValue;
1797  if (!getParser().parseGNUAttribute(L, Tag, IntegerValue))
1798  return false;
1799 
1800  getParser().getStreamer().emitGNUAttribute(Tag, IntegerValue);
1801 
1802  return true;
1803 }
1804 
1805 /// Force static initialization.
1811 }
1812 
1813 #define GET_REGISTER_MATCHER
1814 #define GET_MATCHER_IMPLEMENTATION
1815 #define GET_MNEMONIC_SPELL_CHECKER
1816 #include "PPCGenAsmMatcher.inc"
1817 
1818 // Define this matcher function after the auto-generated include so we
1819 // have the match class enum definitions.
1820 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1821  unsigned Kind) {
1822  // If the kind is a token for a literal immediate, check if our asm
1823  // operand matches. This is for InstAliases which have a fixed-value
1824  // immediate in the syntax.
1825  int64_t ImmVal;
1826  switch (Kind) {
1827  case MCK_0: ImmVal = 0; break;
1828  case MCK_1: ImmVal = 1; break;
1829  case MCK_2: ImmVal = 2; break;
1830  case MCK_3: ImmVal = 3; break;
1831  case MCK_4: ImmVal = 4; break;
1832  case MCK_5: ImmVal = 5; break;
1833  case MCK_6: ImmVal = 6; break;
1834  case MCK_7: ImmVal = 7; break;
1835  default: return Match_InvalidOperand;
1836  }
1837 
1838  PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1839  if (Op.isU3Imm() && Op.getImm() == ImmVal)
1840  return Match_Success;
1841 
1842  return Match_InvalidOperand;
1843 }
1844 
1845 const MCExpr *
1846 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1848  MCContext &Ctx) {
1849  switch (Variant) {
1868  default:
1869  return nullptr;
1870  }
1871 }
llvm::MCSymbolRefExpr::getKind
VariantKind getKind() const
Definition: MCExpr.h:401
llvm::PPCMCExpr::VK_PPC_HA
@ VK_PPC_HA
Definition: PPCMCExpr.h:24
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4715
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MCSymbolRefExpr::VK_PPC_HIGHESTA
@ VK_PPC_HIGHESTA
Definition: MCExpr.h:256
llvm::lltok::Error
@ Error
Definition: LLToken.h:21
llvm::AArch64CC::NE
@ NE
Definition: AArch64BaseInfo.h:256
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MCUnaryExpr::getOpcode
Opcode getOpcode() const
Get the kind of this unary expression.
Definition: MCExpr.h:468
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:189
llvm::MCParsedAsmOperand
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Definition: MCParsedAsmOperand.h:24
llvm::MCSymbolRefExpr::VK_PPC_TLSGD
@ VK_PPC_TLSGD
Definition: MCExpr.h:299
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::AsmToken::Dot
@ Dot
Definition: MCAsmMacro.h:49
llvm::AsmToken::EndOfStatement
@ EndOfStatement
Definition: MCAsmMacro.h:42
llvm::MCSymbolRefExpr::VK_PPC_HIGHA
@ VK_PPC_HIGHA
Definition: MCExpr.h:252
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:52
MCParsedAsmOperand.h
llvm::MCUnaryExpr::createMinus
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:451
llvm::pdb::PDB_BuiltinType::Variant
@ Variant
llvm::MCBinaryExpr::Add
@ Add
Addition.
Definition: MCExpr.h:484
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
addNegOperand
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Definition: PPCAsmParser.cpp:785
llvm::MCBinaryExpr::Mul
@ Mul
Multiplication.
Definition: MCExpr.h:499
llvm::PPCMCExpr::VK_PPC_LO
@ VK_PPC_LO
Definition: PPCMCExpr.h:22
llvm::AsmToken::Integer
@ Integer
Definition: MCAsmMacro.h:32
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::PPCMCExpr::VK_PPC_HIGHA
@ VK_PPC_HIGHA
Definition: PPCMCExpr.h:26
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::ARM::PredBlockMask::TE
@ TE
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::dwarf::Tag
Tag
Definition: Dwarf.h:105
llvm::MCBinaryExpr
Binary assembler expressions.
Definition: MCExpr.h:481
PPCMCTargetDesc.h
MCAsmParser.h
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
llvm::MCUnaryExpr
Unary assembler expressions.
Definition: MCExpr.h:425
MCTargetAsmParser.h
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
p
the resulting code requires compare and branches when and if * p
Definition: README.txt:396
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:1218
llvm::PPCMCExpr
Definition: PPCMCExpr.h:18
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::MCSymbolELF
Definition: MCSymbolELF.h:14
llvm::AsmToken::Minus
@ Minus
Definition: MCAsmMacro.h:45
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MCSymbolRefExpr::VK_PPC_TLS
@ VK_PPC_TLS
Definition: MCExpr.h:294
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::getThePPC64LETarget
Target & getThePPC64LETarget()
Definition: PowerPCTargetInfo.cpp:25
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::AsmToken::Dollar
@ Dollar
Definition: MCAsmMacro.h:49
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1399
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:127
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::StringRef::startswith
bool startswith(StringRef Prefix) const
Definition: StringRef.h:260
llvm::ModRefInfo::Ref
@ Ref
The access may reference the value stored in memory.
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition: MCExpr.h:42
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Twine.h
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:109
MCSymbolELF.h
MCContext.h
llvm::PPCMCExpr::VK_PPC_HIGHEST
@ VK_PPC_HIGHEST
Definition: PPCMCExpr.h:29
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCInst.h
llvm::MCBinaryExpr::getRHS
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:631
check
#define check(cond)
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::isUIntN
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:422
llvm::MCUnaryExpr::create
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.cpp:189
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:113
llvm::PPCMCExpr::VK_PPC_HI
@ VK_PPC_HI
Definition: PPCMCExpr.h:23
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCSymbolRefExpr::getSymbol
const MCSymbol & getSymbol() const
Definition: MCExpr.h:399
llvm::MCSymbolRefExpr::VK_TLSLD
@ VK_TLSLD
Definition: MCExpr.h:210
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
isNot
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
Definition: AMDGPULegalizerInfo.cpp:3196
llvm::AsmToken::Percent
@ Percent
Definition: MCAsmMacro.h:52
llvm::PPCMCExpr::VK_PPC_HIGHERA
@ VK_PPC_HIGHERA
Definition: PPCMCExpr.h:28
llvm::MCSymbolRefExpr::VK_PPC_HA
@ VK_PPC_HA
Definition: MCExpr.h:250
llvm::isIntN
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:427
llvm::MCUnaryExpr::Minus
@ Minus
Unary minus.
Definition: MCExpr.h:429
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
SourceMgr.h
llvm::MCExpr::Binary
@ Binary
Binary expressions.
Definition: MCExpr.h:38
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::MCSymbolRefExpr::VK_PPC_HI
@ VK_PPC_HI
Definition: MCExpr.h:249
llvm::MCConstantExpr
Definition: MCExpr.h:144
LLVMInitializePowerPCAsmParser
LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser()
Force static initialization.
Definition: PPCAsmParser.cpp:1806
llvm::PPCMCExpr::VK_PPC_None
@ VK_PPC_None
Definition: PPCMCExpr.h:21
llvm::MCSymbolRefExpr::VK_PPC_TLSLD
@ VK_PPC_TLSLD
Definition: MCExpr.h:311
MCAsmLexer.h
llvm::ParseInstructionInfo
Definition: MCTargetAsmParser.h:118
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
PPCMCExpr.h
uint64_t
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::MCSymbolRefExpr::VK_PPC_TLS_PCREL
@ VK_PPC_TLS_PCREL
Definition: MCExpr.h:310
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1096
PowerPCTargetInfo.h
llvm::MCBinaryExpr::create
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.cpp:183
llvm::AsmToken::Exclaim
@ Exclaim
Definition: MCAsmMacro.h:52
llvm::MCSymbolRefExpr::VK_PPC_HIGHEST
@ VK_PPC_HIGHEST
Definition: MCExpr.h:255
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
memcpy
<%struct.s * > cast struct s *S to sbyte *< sbyte * > sbyte uint cast struct s *agg result to sbyte *< sbyte * > sbyte uint cast struct s *memtmp to sbyte *< sbyte * > sbyte uint ret void llc ends up issuing two memcpy or custom lower memcpy(of small size) to be ldmia/stmia. I think option 2 is better but the current register allocator cannot allocate a chunk of registers at a time. A feasible temporary solution is to use specific physical registers at the lowering time for small(<
EvaluateCRExpr
static DEFINE_PPC_REGCLASSES int64_t EvaluateCRExpr(const MCExpr *E)
Definition: PPCAsmParser.cpp:38
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::PPCTargetStreamer::emitLocalEntry
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)=0
MatchRegisterName
static unsigned MatchRegisterName(StringRef Name)
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:347
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::AsmToken::Comma
@ Comma
Definition: MCAsmMacro.h:49
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition: GCNRegPressure.cpp:138
llvm::Expression
Class representing an expression and its matching format.
Definition: FileCheckImpl.h:237
llvm::isRunOfOnes
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side.
Definition: PPCMCTargetDesc.h:57
llvm::MCUnaryExpr::getSubExpr
const MCExpr * getSubExpr() const
Get the child of this unary expression.
Definition: MCExpr.h:471
llvm::MatchOperand_NoMatch
@ MatchOperand_NoMatch
Definition: MCTargetAsmParser.h:128
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MCAsmParser::getTok
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:40
llvm::AsmToken::Plus
@ Plus
Definition: MCAsmMacro.h:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
A
* A
Definition: README_ALTIVEC.txt:89
llvm::PPCTargetStreamer::emitAbiVersion
virtual void emitAbiVersion(int AbiVersion)=0
llvm::PPCMCExpr::create
static const PPCMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: PPCMCExpr.cpp:20
llvm::objcopy::SymbolFlag::Warning
@ Warning
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AsmToken::RParen
@ RParen
Definition: MCAsmMacro.h:48
llvm::MCSymbolRefExpr::VK_PPC_HIGH
@ VK_PPC_HIGH
Definition: MCExpr.h:251
llvm::RISCVISD::LA
@ LA
Definition: RISCVISelLowering.h:330
llvm::PPCMCExpr::VK_PPC_HIGHESTA
@ VK_PPC_HIGHESTA
Definition: PPCMCExpr.h:30
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::OperandMatchResultTy
OperandMatchResultTy
Definition: MCTargetAsmParser.h:126
llvm::getThePPC64Target
Target & getThePPC64Target()
Definition: PowerPCTargetInfo.cpp:21
llvm::tgtok::IntVal
@ IntVal
Definition: TGLexer.h:65
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::MCBinaryExpr::getOpcode
Opcode getOpcode() const
Get the kind of this binary expression.
Definition: MCExpr.h:625
llvm::AsmToken::Tilde
@ Tilde
Definition: MCAsmMacro.h:45
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:203
llvm::AsmToken::Identifier
@ Identifier
Definition: MCAsmMacro.h:28
llvm::AsmToken::isNot
bool isNot(TokenKind K) const
Definition: MCAsmMacro.h:83
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:34
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::MCBinaryExpr::Sub
@ Sub
Subtraction.
Definition: MCExpr.h:506
DEFINE_PPC_REGCLASSES
#define DEFINE_PPC_REGCLASSES
Definition: PPCMCTargetDesc.h:181
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCTargetAsmParser
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:314
PPCTargetStreamer.h
llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:209
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
llvm::MCSymbolRefExpr::VK_PPC_HIGHER
@ VK_PPC_HIGHER
Definition: MCExpr.h:253
llvm::getThePPC32LETarget
Target & getThePPC32LETarget()
Definition: PowerPCTargetInfo.cpp:17
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::MCExpr::Unary
@ Unary
Unary expressions.
Definition: MCExpr.h:41
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::AsmToken::getIdentifier
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
llvm::MCSymbolRefExpr::VK_PPC_LO
@ VK_PPC_LO
Definition: MCExpr.h:248
llvm::PPCTargetStreamer::emitMachine
virtual void emitMachine(StringRef CPU)=0
N
#define N
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::HexagonMCInstrInfo::getExpr
const MCExpr & getExpr(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:310
llvm::PPCMCExpr::VariantKind
VariantKind
Definition: PPCMCExpr.h:20
llvm::MCExpr::Constant
@ Constant
Constant expressions.
Definition: MCExpr.h:39
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:131
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SMLoc::getFromPointer
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
llvm::PPCMCExpr::VK_PPC_HIGHER
@ VK_PPC_HIGHER
Definition: PPCMCExpr.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::PPCMCExpr::VK_PPC_HIGH
@ VK_PPC_HIGH
Definition: PPCMCExpr.h:25
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::AsmToken::String
@ String
Definition: MCAsmMacro.h:29
InlinePriorityMode::Size
@ Size
llvm::MCSymbolRefExpr::VK_PPC_HIGHERA
@ VK_PPC_HIGHERA
Definition: MCExpr.h:254
raw_ostream.h
llvm::AsmToken::getLoc
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
llvm::AsmToken::getEndLoc
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
TargetRegistry.h
MCExpr.h
llvm::PPCTargetStreamer
Definition: PPCTargetStreamer.h:22
llvm::Triple::isPPC64
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Definition: Triple.h:880
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MCBinaryExpr::getLHS
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:628
PPCMnemonicSpellCheck
static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
llvm::getThePPC32Target
Target & getThePPC32Target()
Definition: PowerPCTargetInfo.cpp:13