39 switch (
E->getKind()) {
44 int64_t Res = cast<MCConstantExpr>(
E)->getValue();
45 return Res < 0 ? -1 : Res;
52 if (
Name ==
"lt")
return 0;
53 if (
Name ==
"gt")
return 1;
54 if (
Name ==
"eq")
return 2;
55 if (
Name ==
"so")
return 3;
56 if (
Name ==
"un")
return 3;
58 if (
Name ==
"cr0")
return 0;
59 if (
Name ==
"cr1")
return 1;
60 if (
Name ==
"cr2")
return 2;
61 if (
Name ==
"cr3")
return 3;
62 if (
Name ==
"cr4")
return 4;
63 if (
Name ==
"cr5")
return 5;
64 if (
Name ==
"cr6")
return 6;
65 if (
Name ==
"cr7")
return 7;
79 if (LHSVal < 0 || RHSVal < 0)
88 return Res < 0 ? -1 : Res;
104 bool isPPC64()
const {
return IsPPC64; }
108 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
110 SMLoc &EndLoc)
override;
115 bool ParseExpression(
const MCExpr *&EVal);
119 bool ParseDirectiveWord(
unsigned Size,
AsmToken ID);
120 bool ParseDirectiveTC(
unsigned Size,
AsmToken ID);
121 bool ParseDirectiveMachine(
SMLoc L);
122 bool ParseDirectiveAbiVersion(
SMLoc L);
123 bool ParseDirectiveLocalEntry(
SMLoc L);
124 bool ParseGNUAttribute(
SMLoc L);
126 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
129 bool MatchingInlineAsm)
override;
136 #define GET_ASSEMBLER_HEADER
137 #include "PPCGenAsmMatcher.inc"
150 setAvailableFeatures(ComputeAvailableFeatures(STI.
getFeatureBits()));
156 bool ParseDirective(
AsmToken DirectiveID)
override;
159 unsigned Kind)
override;
177 SMLoc StartLoc, EndLoc;
202 struct TLSRegOp TLSReg;
205 PPCOperand(KindTy K) :
Kind(K) {}
210 StartLoc = o.StartLoc;
218 case ContextImmediate:
232 void operator delete(
void *
p) { ::operator
delete(
p); }
235 SMLoc getStartLoc()
const override {
return StartLoc; }
238 SMLoc getEndLoc()
const override {
return EndLoc; }
245 bool isPPC64()
const {
return IsPPC64; }
247 int64_t getImm()
const {
248 assert(
Kind == Immediate &&
"Invalid access!");
251 int64_t getImmS16Context()
const {
254 if (
Kind == Immediate)
256 return static_cast<int16_t
>(Imm.Val);
258 int64_t getImmU16Context()
const {
269 int64_t getExprCRVal()
const {
274 const MCExpr *getTLSReg()
const {
275 assert(
Kind == TLSRegister &&
"Invalid access!");
279 unsigned getReg()
const override {
280 assert(isRegNumber() &&
"Invalid access!");
281 return (
unsigned) Imm.Val;
284 unsigned getVSReg()
const {
285 assert(isVSRegNumber() &&
"Invalid access!");
286 return (
unsigned) Imm.Val;
289 unsigned getACCReg()
const {
290 assert(isACCRegNumber() &&
"Invalid access!");
291 return (
unsigned) Imm.Val;
294 unsigned getVSRpEvenReg()
const {
295 assert(isVSRpEvenRegNumber() &&
"Invalid access!");
296 return (
unsigned) Imm.Val >> 1;
299 unsigned getG8pReg()
const {
300 assert(isEvenRegNumber() &&
"Invalid access!");
301 return (
unsigned)Imm.Val;
304 unsigned getCCReg()
const {
305 assert(isCCRegNumber() &&
"Invalid access!");
306 return (
unsigned) (
Kind == Immediate ? Imm.Val : Expr.CRVal);
309 unsigned getCRBit()
const {
310 assert(isCRBitNumber() &&
"Invalid access!");
311 return (
unsigned) (
Kind == Immediate ? Imm.Val : Expr.CRVal);
314 unsigned getCRBitMask()
const {
315 assert(isCRBitMask() &&
"Invalid access!");
316 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
319 bool isToken()
const override {
return Kind == Token; }
320 bool isImm()
const override {
323 bool isU1Imm()
const {
return Kind == Immediate && isUInt<1>(getImm()); }
324 bool isU2Imm()
const {
return Kind == Immediate && isUInt<2>(getImm()); }
325 bool isU3Imm()
const {
return Kind == Immediate && isUInt<3>(getImm()); }
326 bool isU4Imm()
const {
return Kind == Immediate && isUInt<4>(getImm()); }
327 bool isU5Imm()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
328 bool isS5Imm()
const {
return Kind == Immediate && isInt<5>(getImm()); }
329 bool isU6Imm()
const {
return Kind == Immediate && isUInt<6>(getImm()); }
330 bool isU6ImmX2()
const {
return Kind == Immediate &&
331 isUInt<6>(getImm()) &&
332 (getImm() & 1) == 0; }
333 bool isU7Imm()
const {
return Kind == Immediate && isUInt<7>(getImm()); }
334 bool isU7ImmX4()
const {
return Kind == Immediate &&
335 isUInt<7>(getImm()) &&
336 (getImm() & 3) == 0; }
337 bool isU8Imm()
const {
return Kind == Immediate &&
isUInt<8>(getImm()); }
338 bool isU8ImmX8()
const {
return Kind == Immediate &&
340 (getImm() & 7) == 0; }
342 bool isU10Imm()
const {
return Kind == Immediate && isUInt<10>(getImm()); }
343 bool isU12Imm()
const {
return Kind == Immediate && isUInt<12>(getImm()); }
344 bool isU16Imm()
const {
return isExtImm<16>(
false, 1); }
345 bool isS16Imm()
const {
return isExtImm<16>(
true, 1); }
346 bool isS16ImmX4()
const {
return isExtImm<16>(
true, 4); }
347 bool isS16ImmX16()
const {
return isExtImm<16>(
true, 16); }
348 bool isS17Imm()
const {
return isExtImm<17>(
true, 1); }
350 bool isHashImmX8()
const {
354 return (
Kind == Immediate && getImm() <= -8 && getImm() >= -512 &&
355 (getImm() & 7) == 0);
358 bool isS34ImmX16()
const {
360 (
Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
362 bool isS34Imm()
const {
368 bool isTLSReg()
const {
return Kind == TLSRegister; }
369 bool isDirectBr()
const {
372 if (
Kind != Immediate)
375 if ((getImm() & 3) != 0)
377 if (isInt<26>(getImm()))
381 if (
isUInt<32>(getImm()) && isInt<26>(
static_cast<int32_t
>(getImm())))
388 (getImm() & 3) == 0); }
389 bool isImmZero()
const {
return Kind == Immediate && getImm() == 0; }
390 bool isRegNumber()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
391 bool isACCRegNumber()
const {
392 return Kind == Immediate && isUInt<3>(getImm());
394 bool isVSRpEvenRegNumber()
const {
395 return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0);
397 bool isVSRegNumber()
const {
398 return Kind == Immediate && isUInt<6>(getImm());
401 && isUInt<3>(getExprCRVal())) ||
403 && isUInt<3>(getImm())); }
405 && isUInt<5>(getExprCRVal())) ||
407 && isUInt<5>(getImm())); }
409 bool isEvenRegNumber()
const {
return isRegNumber() && (getImm() & 1) == 0; }
411 bool isCRBitMask()
const {
return Kind == Immediate &&
isUInt<8>(getImm()) &&
413 bool isATBitsAsHint()
const {
return false; }
414 bool isMem()
const override {
return false; }
415 bool isReg()
const override {
return false; }
417 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
421 void addRegGPRCOperands(
MCInst &Inst,
unsigned N)
const {
422 assert(
N == 1 &&
"Invalid number of operands!");
426 void addRegGPRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
427 assert(
N == 1 &&
"Invalid number of operands!");
431 void addRegG8RCOperands(
MCInst &Inst,
unsigned N)
const {
432 assert(
N == 1 &&
"Invalid number of operands!");
436 void addRegG8RCNoX0Operands(
MCInst &Inst,
unsigned N)
const {
437 assert(
N == 1 &&
"Invalid number of operands!");
441 void addRegG8pRCOperands(
MCInst &Inst,
unsigned N)
const {
442 assert(
N == 1 &&
"Invalid number of operands!");
446 void addRegGxRCOperands(
MCInst &Inst,
unsigned N)
const {
448 addRegG8RCOperands(Inst,
N);
450 addRegGPRCOperands(Inst,
N);
453 void addRegGxRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
455 addRegG8RCNoX0Operands(Inst,
N);
457 addRegGPRCNoR0Operands(Inst,
N);
460 void addRegF4RCOperands(
MCInst &Inst,
unsigned N)
const {
461 assert(
N == 1 &&
"Invalid number of operands!");
465 void addRegF8RCOperands(
MCInst &Inst,
unsigned N)
const {
466 assert(
N == 1 &&
"Invalid number of operands!");
470 void addRegVFRCOperands(
MCInst &Inst,
unsigned N)
const {
471 assert(
N == 1 &&
"Invalid number of operands!");
475 void addRegVRRCOperands(
MCInst &Inst,
unsigned N)
const {
476 assert(
N == 1 &&
"Invalid number of operands!");
480 void addRegVSRCOperands(
MCInst &Inst,
unsigned N)
const {
481 assert(
N == 1 &&
"Invalid number of operands!");
485 void addRegVSFRCOperands(
MCInst &Inst,
unsigned N)
const {
486 assert(
N == 1 &&
"Invalid number of operands!");
490 void addRegVSSRCOperands(
MCInst &Inst,
unsigned N)
const {
491 assert(
N == 1 &&
"Invalid number of operands!");
495 void addRegSPE4RCOperands(
MCInst &Inst,
unsigned N)
const {
496 assert(
N == 1 &&
"Invalid number of operands!");
500 void addRegSPERCOperands(
MCInst &Inst,
unsigned N)
const {
501 assert(
N == 1 &&
"Invalid number of operands!");
505 void addRegACCRCOperands(
MCInst &Inst,
unsigned N)
const {
506 assert(
N == 1 &&
"Invalid number of operands!");
510 void addRegVSRpRCOperands(
MCInst &Inst,
unsigned N)
const {
511 assert(
N == 1 &&
"Invalid number of operands!");
515 void addRegVSRpEvenRCOperands(
MCInst &Inst,
unsigned N)
const {
516 assert(
N == 1 &&
"Invalid number of operands!");
520 void addRegCRBITRCOperands(
MCInst &Inst,
unsigned N)
const {
521 assert(
N == 1 &&
"Invalid number of operands!");
525 void addRegCRRCOperands(
MCInst &Inst,
unsigned N)
const {
526 assert(
N == 1 &&
"Invalid number of operands!");
530 void addCRBitMaskOperands(
MCInst &Inst,
unsigned N)
const {
531 assert(
N == 1 &&
"Invalid number of operands!");
535 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
536 assert(
N == 1 &&
"Invalid number of operands!");
537 if (
Kind == Immediate)
543 void addS16ImmOperands(
MCInst &Inst,
unsigned N)
const {
544 assert(
N == 1 &&
"Invalid number of operands!");
549 case ContextImmediate:
558 void addU16ImmOperands(
MCInst &Inst,
unsigned N)
const {
559 assert(
N == 1 &&
"Invalid number of operands!");
564 case ContextImmediate:
573 void addBranchTargetOperands(
MCInst &Inst,
unsigned N)
const {
574 assert(
N == 1 &&
"Invalid number of operands!");
575 if (
Kind == Immediate)
581 void addTLSRegOperands(
MCInst &Inst,
unsigned N)
const {
582 assert(
N == 1 &&
"Invalid number of operands!");
595 auto Op = std::make_unique<PPCOperand>(Token);
596 Op->Tok.Data = Str.data();
597 Op->Tok.Length = Str.size();
600 Op->IsPPC64 = IsPPC64;
604 static std::unique_ptr<PPCOperand>
611 void *Mem = ::operator
new(
sizeof(PPCOperand) + Str.size());
612 std::unique_ptr<PPCOperand>
Op(
new (Mem) PPCOperand(Token));
613 Op->Tok.Data =
reinterpret_cast<const char *
>(
Op.get() + 1);
614 Op->Tok.Length = Str.size();
615 std::memcpy(
const_cast<char *
>(
Op->Tok.Data), Str.data(), Str.size());
618 Op->IsPPC64 = IsPPC64;
622 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val,
SMLoc S,
SMLoc E,
624 auto Op = std::make_unique<PPCOperand>(Immediate);
628 Op->IsPPC64 = IsPPC64;
632 static std::unique_ptr<PPCOperand> CreateExpr(
const MCExpr *Val,
SMLoc S,
639 Op->IsPPC64 = IsPPC64;
643 static std::unique_ptr<PPCOperand>
645 auto Op = std::make_unique<PPCOperand>(TLSRegister);
646 Op->TLSReg.Sym = Sym;
649 Op->IsPPC64 = IsPPC64;
653 static std::unique_ptr<PPCOperand>
654 CreateContextImm(int64_t Val,
SMLoc S,
SMLoc E,
bool IsPPC64) {
655 auto Op = std::make_unique<PPCOperand>(ContextImmediate);
659 Op->IsPPC64 = IsPPC64;
663 static std::unique_ptr<PPCOperand>
666 return CreateImm(
CE->getValue(),
S,
E, IsPPC64);
671 return CreateTLSReg(SRE,
S,
E, IsPPC64);
673 if (
const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
675 if (
TE->evaluateAsConstant(Res))
676 return CreateContextImm(Res,
S,
E, IsPPC64);
679 return CreateExpr(Val,
S,
E, IsPPC64);
683 template <
unsigned W
idth>
684 bool isExtImm(
bool Signed,
unsigned Multiple)
const {
691 case ContextImmediate:
693 return isInt<Width>(getImmS16Context()) &&
694 (getImmS16Context() & (Multiple - 1)) == 0;
696 return isUInt<Width>(getImmU16Context()) &&
697 (getImmU16Context() & (Multiple - 1)) == 0;
707 OS <<
"'" << getToken() <<
"'";
710 case ContextImmediate:
729 if (
const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
734 }
else if (
const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
737 BinExpr->getLHS(), Ctx);
745 void PPCAsmParser::ProcessInstruction(
MCInst &Inst,
754 TmpInst.
setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
755 PPC::DCBT : PPC::DCBTST);
757 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
774 case PPC::DCBTSTDS: {
789 if (Opcode == PPC::DCBFL)
791 else if (Opcode == PPC::DCBFLP)
793 else if (Opcode == PPC::DCBFPS)
795 else if (Opcode == PPC::DCBSTPS)
842 case PPC::SUBIC_rec: {
852 case PPC::EXTLWI_rec: {
856 TmpInst.
setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec);
866 case PPC::EXTRWI_rec: {
870 TmpInst.
setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
880 case PPC::INSLWI_rec: {
884 TmpInst.
setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
895 case PPC::INSRWI_rec: {
899 TmpInst.
setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
910 case PPC::ROTRWI_rec: {
913 TmpInst.
setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
923 case PPC::SLWI_rec: {
926 TmpInst.
setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec);
936 case PPC::SRWI_rec: {
939 TmpInst.
setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec);
949 case PPC::CLRRWI_rec: {
952 TmpInst.
setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec);
962 case PPC::CLRLSLWI_rec: {
966 TmpInst.
setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec);
976 case PPC::EXTLDI_rec: {
980 TmpInst.
setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec);
989 case PPC::EXTRDI_rec: {
993 TmpInst.
setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1002 case PPC::INSRDI_rec: {
1006 TmpInst.
setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec);
1016 case PPC::ROTRDI_rec: {
1019 TmpInst.
setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1028 case PPC::SLDI_rec: {
1031 TmpInst.
setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1039 case PPC::SUBPCIS: {
1049 case PPC::SRDI_rec: {
1052 TmpInst.
setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1061 case PPC::CLRRDI_rec: {
1064 TmpInst.
setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec);
1073 case PPC::CLRLSLDI_rec: {
1077 TmpInst.
setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec);
1086 case PPC::RLWINMbm_rec: {
1093 TmpInst.
setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec);
1103 case PPC::RLWIMIbm_rec: {
1110 TmpInst.
setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec);
1121 case PPC::RLWNMbm_rec: {
1128 TmpInst.
setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec);
1138 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1148 unsigned VariantID = 0);
1150 bool PPCAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
1153 bool MatchingInlineAsm) {
1159 ProcessInstruction(Inst,
Operands);
1163 case Match_MissingFeature:
1164 return Error(IDLoc,
"instruction use requires an option to be enabled");
1165 case Match_MnemonicFail: {
1166 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1168 ((PPCOperand &)*
Operands[0]).getToken(), FBS);
1169 return Error(IDLoc,
"invalid instruction" + Suggestion,
1170 ((PPCOperand &)*
Operands[0]).getLocRange());
1172 case Match_InvalidOperand: {
1173 SMLoc ErrorLoc = IDLoc;
1176 return Error(IDLoc,
"too few operands for instruction");
1179 if (ErrorLoc ==
SMLoc()) ErrorLoc = IDLoc;
1182 return Error(ErrorLoc,
"invalid operand for instruction");
1197 if (
Name.equals_insensitive(
"lr")) {
1198 RegNo = isPPC64() ? PPC::LR8 : PPC::LR;
1200 }
else if (
Name.equals_insensitive(
"ctr")) {
1201 RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR;
1203 }
else if (
Name.equals_insensitive(
"vrsave")) {
1204 RegNo = PPC::VRSAVE;
1206 }
else if (
Name.startswith_insensitive(
"r") &&
1209 }
else if (
Name.startswith_insensitive(
"f") &&
1212 }
else if (
Name.startswith_insensitive(
"vs") &&
1215 }
else if (
Name.startswith_insensitive(
"v") &&
1218 }
else if (
Name.startswith_insensitive(
"cr") &&
1228 ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
1230 return TokError(
"invalid register name");
1237 const AsmToken &Tok = getParser().getTok();
1253 const MCExpr *PPCAsmParser::
1254 ExtractModifierFromExpr(
const MCExpr *
E,
1259 switch (
E->getKind()) {
1313 const MCExpr *
LHS = ExtractModifierFromExpr(BE->
getLHS(), LHSVariant);
1314 const MCExpr *
RHS = ExtractModifierFromExpr(BE->
getRHS(), RHSVariant);
1326 else if (LHSVariant == RHSVariant)
1342 const MCExpr *PPCAsmParser::
1343 FixupVariantKind(
const MCExpr *
E) {
1346 switch (
E->getKind()) {
1392 ParseExpression(
const MCExpr *&EVal) {
1395 if (getParser().parseExpression(EVal))
1398 EVal = FixupVariantKind(EVal);
1401 const MCExpr *
E = ExtractModifierFromExpr(EVal, Variant);
1418 switch (getLexer().getKind()) {
1425 return Error(
S,
"invalid register name");
1439 if (!ParseExpression(EVal))
1444 return Error(
S,
"unknown operand");
1448 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal,
S,
E, isPPC64()));
1451 bool TLSCall =
false;
1453 TLSCall =
Ref->getSymbol().getName() ==
"__tls_get_addr";
1460 if (ParseExpression(TLSSym))
1461 return Error(
S,
"invalid TLS call expression");
1467 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym,
S,
E, isPPC64()));
1476 switch (getLexer().getKind()) {
1480 return Error(
S,
"invalid register name");
1484 if (getParser().parseAbsoluteExpression(
IntVal) ||
IntVal < 0 ||
1486 return Error(
S,
"invalid register number");
1490 return Error(
S,
"invalid memory operand");
1508 std::string NewOpcode;
1510 NewOpcode = std::string(
Name);
1515 NewOpcode = std::string(
Name);
1521 size_t Dot =
Name.find(
'.');
1523 if (!NewOpcode.empty())
1525 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1527 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1531 if (!NewOpcode.empty())
1533 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1535 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1559 if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1561 (
Name ==
"dcbt" ||
Name ==
"dcbtst")) {
1567 if (
Name ==
"lqarx" ||
Name ==
"ldarx" ||
Name ==
"lwarx" ||
1568 Name ==
"lharx" ||
Name ==
"lbarx") {
1571 PPCOperand &EHOp = (PPCOperand &)*
Operands[4];
1572 if (EHOp.isU1Imm() && EHOp.getImm() == 0)
1580 bool PPCAsmParser::ParseDirective(
AsmToken DirectiveID) {
1582 if (IDVal ==
".word")
1583 ParseDirectiveWord(2, DirectiveID);
1584 else if (IDVal ==
".llong")
1585 ParseDirectiveWord(8, DirectiveID);
1586 else if (IDVal ==
".tc")
1587 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1588 else if (IDVal ==
".machine")
1589 ParseDirectiveMachine(DirectiveID.
getLoc());
1590 else if (IDVal ==
".abiversion")
1591 ParseDirectiveAbiVersion(DirectiveID.
getLoc());
1592 else if (IDVal ==
".localentry")
1593 ParseDirectiveLocalEntry(DirectiveID.
getLoc());
1595 ParseGNUAttribute(DirectiveID.
getLoc());
1603 bool PPCAsmParser::ParseDirectiveWord(
unsigned Size,
AsmToken ID) {
1604 auto parseOp = [&]() ->
bool {
1606 SMLoc ExprLoc = getParser().getTok().getLoc();
1607 if (getParser().parseExpression(
Value))
1609 if (
const auto *MCE = dyn_cast<MCConstantExpr>(
Value)) {
1611 uint64_t IntValue = MCE->getValue();
1613 return Error(ExprLoc,
"literal value out of range for '" +
1614 ID.getIdentifier() +
"' directive");
1615 getStreamer().emitIntValue(IntValue,
Size);
1617 getStreamer().emitValue(
Value,
Size, ExprLoc);
1621 if (parseMany(parseOp))
1622 return addErrorSuffix(
" in '" +
ID.getIdentifier() +
"' directive");
1628 bool PPCAsmParser::ParseDirectiveTC(
unsigned Size,
AsmToken ID) {
1635 return addErrorSuffix(
" in '.tc' directive");
1638 getParser().getStreamer().emitValueToAlignment(
Size);
1641 return ParseDirectiveWord(
Size,
ID);
1646 bool PPCAsmParser::ParseDirectiveMachine(
SMLoc L) {
1650 return Error(L,
"unexpected token in '.machine' directive");
1661 return addErrorSuffix(
" in '.machine' directive");
1664 getParser().getStreamer().getTargetStreamer());
1665 if (TStreamer !=
nullptr)
1673 bool PPCAsmParser::ParseDirectiveAbiVersion(
SMLoc L) {
1675 if (
check(getParser().parseAbsoluteExpression(AbiVersion), L,
1676 "expected constant expression") ||
1678 return addErrorSuffix(
" in '.abiversion' directive");
1681 getParser().getStreamer().getTargetStreamer());
1682 if (TStreamer !=
nullptr)
1690 bool PPCAsmParser::ParseDirectiveLocalEntry(
SMLoc L) {
1692 if (getParser().parseIdentifier(
Name))
1693 return Error(L,
"expected identifier in '.localentry' directive");
1695 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(
Name));
1699 check(getParser().parseExpression(Expr), L,
"expected expression") ||
1701 return addErrorSuffix(
" in '.localentry' directive");
1704 getParser().getStreamer().getTargetStreamer());
1705 if (TStreamer !=
nullptr)
1711 bool PPCAsmParser::ParseGNUAttribute(
SMLoc L) {
1713 int64_t IntegerValue;
1714 if (!getParser().parseGNUAttribute(L,
Tag, IntegerValue))
1717 getParser().getStreamer().emitGNUAttribute(
Tag, IntegerValue);
1730 #define GET_REGISTER_MATCHER
1731 #define GET_MATCHER_IMPLEMENTATION
1732 #define GET_MNEMONIC_SPELL_CHECKER
1733 #include "PPCGenAsmMatcher.inc"
1744 case MCK_0: ImmVal = 0;
break;
1745 case MCK_1: ImmVal = 1;
break;
1746 case MCK_2: ImmVal = 2;
break;
1747 case MCK_3: ImmVal = 3;
break;
1748 case MCK_4: ImmVal = 4;
break;
1749 case MCK_5: ImmVal = 5;
break;
1750 case MCK_6: ImmVal = 6;
break;
1751 case MCK_7: ImmVal = 7;
break;
1752 default:
return Match_InvalidOperand;
1755 PPCOperand &
Op =
static_cast<PPCOperand &
>(AsmOp);
1756 if (
Op.isU3Imm() &&
Op.getImm() == ImmVal)
1757 return Match_Success;
1759 return Match_InvalidOperand;
1763 PPCAsmParser::applyModifierToExpr(
const MCExpr *
E,