29#define DEBUG_TYPE "csky-disassembler"
35 std::unique_ptr<MCInstrInfo const>
const MCII;
57 return new CSKYDisassembler(STI, Ctx,
T.createMCInstrInfo());
66 CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3, CSKY::R4, CSKY::R5, CSKY::R6,
67 CSKY::R7, CSKY::R8, CSKY::R9, CSKY::R10, CSKY::R11, CSKY::R12, CSKY::R13,
68 CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
69 CSKY::R21, CSKY::R22, CSKY::R23, CSKY::R24, CSKY::R25, CSKY::R26, CSKY::R27,
70 CSKY::R28, CSKY::R29, CSKY::R30, CSKY::R31};
73 CSKY::R0_R1, CSKY::R1_R2, CSKY::R2_R3, CSKY::R3_R4, CSKY::R4_R5,
74 CSKY::R5_R6, CSKY::R6_R7, CSKY::R7_R8, CSKY::R8_R9, CSKY::R9_R10,
75 CSKY::R10_R11, CSKY::R11_R12, CSKY::R12_R13, CSKY::R13_R14, CSKY::R14_R15,
76 CSKY::R15_R16, CSKY::R16_R17, CSKY::R17_R18, CSKY::R18_R19, CSKY::R19_R20,
77 CSKY::R20_R21, CSKY::R21_R22, CSKY::R22_R23, CSKY::R23_R24, CSKY::R24_R25,
78 CSKY::R25_R26, CSKY::R26_R27, CSKY::R27_R28, CSKY::R28_R29, CSKY::R29_R30,
79 CSKY::R30_R31, CSKY::R31_R32};
82 CSKY::F0_32, CSKY::F1_32, CSKY::F2_32, CSKY::F3_32, CSKY::F4_32,
83 CSKY::F5_32, CSKY::F6_32, CSKY::F7_32, CSKY::F8_32, CSKY::F9_32,
84 CSKY::F10_32, CSKY::F11_32, CSKY::F12_32, CSKY::F13_32, CSKY::F14_32,
85 CSKY::F15_32, CSKY::F16_32, CSKY::F17_32, CSKY::F18_32, CSKY::F19_32,
86 CSKY::F20_32, CSKY::F21_32, CSKY::F22_32, CSKY::F23_32, CSKY::F24_32,
87 CSKY::F25_32, CSKY::F26_32, CSKY::F27_32, CSKY::F28_32, CSKY::F29_32,
88 CSKY::F30_32, CSKY::F31_32};
91 CSKY::F0_64, CSKY::F1_64, CSKY::F2_64, CSKY::F3_64, CSKY::F4_64,
92 CSKY::F5_64, CSKY::F6_64, CSKY::F7_64, CSKY::F8_64, CSKY::F9_64,
93 CSKY::F10_64, CSKY::F11_64, CSKY::F12_64, CSKY::F13_64, CSKY::F14_64,
94 CSKY::F15_64, CSKY::F16_64, CSKY::F17_64, CSKY::F18_64, CSKY::F19_64,
95 CSKY::F20_64, CSKY::F21_64, CSKY::F22_64, CSKY::F23_64, CSKY::F24_64,
96 CSKY::F25_64, CSKY::F26_64, CSKY::F27_64, CSKY::F28_64, CSKY::F29_64,
97 CSKY::F30_64, CSKY::F31_64};
100 CSKY::F0_128, CSKY::F1_128, CSKY::F2_128, CSKY::F3_128, CSKY::F4_128,
101 CSKY::F5_128, CSKY::F6_128, CSKY::F7_128, CSKY::F8_128, CSKY::F9_128,
102 CSKY::F10_128, CSKY::F11_128, CSKY::F12_128, CSKY::F13_128, CSKY::F14_128,
103 CSKY::F15_128, CSKY::F16_128, CSKY::F17_128, CSKY::F18_128, CSKY::F19_128,
104 CSKY::F20_128, CSKY::F21_128, CSKY::F22_128, CSKY::F23_128, CSKY::F24_128,
105 CSKY::F25_128, CSKY::F26_128, CSKY::F27_128, CSKY::F28_128, CSKY::F29_128,
106 CSKY::F30_128, CSKY::F31_128};
217 bool hasHighReg = FeatureBits[CSKY::FeatureHighreg];
219 if (RegNo >= 32 || (!hasHighReg && RegNo >= 16))
226template <
unsigned N,
unsigned S>
230 assert(isUInt<N>(Imm) &&
"Invalid immediate");
239 assert(isUInt<N>(Imm) &&
"Invalid immediate");
246 assert(isUInt<8>(Imm) &&
"Invalid immediate");
247 if ((Imm >> 7) & 0x1) {
250 uint64_t V = ((Imm ^ 0xFFFFFFFF) & 0xFF);
260 assert(isUInt<2>(Imm) &&
"Invalid immediate");
279 assert(isUInt<10>(Imm) &&
"Invalid immediate");
281 auto Imm5 = Imm & 0x1f;
282 auto Ry = (Imm >> 5) & 0x1f;
296 assert(isUInt<10>(Imm) &&
"Invalid immediate");
298 auto Imm5 = Imm & 0x1f;
299 auto Ry = (Imm >> 5) & 0x1f;
313 assert(isUInt<10>(Imm) &&
"Invalid immediate");
315 auto Imm5 = Imm & 0x1f;
316 auto Ry = (Imm >> 5) & 0x1f;
330 assert(isUInt<10>(Imm) &&
"Invalid immediate");
332 auto Imm5 = Imm & 0x1f;
333 auto Ry = (Imm >> 5) & 0x1f;
347 assert(isUInt<10>(Imm) &&
"Invalid immediate");
349 auto Imm5 = Imm & 0x1f;
350 auto Ry = (Imm >> 5) & 0x1f;
368template <
unsigned N,
unsigned S>
372 assert(isUInt<N>(Imm) &&
"Invalid immediate");
378#include "CSKYGenDisassemblerTables.inc"
383 switch (
MI.getOpcode()) {
388 case CSKY::ADDI16ZSP:
391 case CSKY::ADDI16SPSP:
392 case CSKY::SUBI16SPSP:
404 case CSKY::FCMPZHS_S:
405 case CSKY::FCMPZHS_D:
406 case CSKY::FCMPZLS_S:
407 case CSKY::FCMPZLS_D:
408 case CSKY::FCMPZNE_S:
409 case CSKY::FCMPZNE_D:
410 case CSKY::FCMPZUO_S:
411 case CSKY::FCMPZUO_D:
412 case CSKY::f2FCMPHS_S:
413 case CSKY::f2FCMPHS_D:
414 case CSKY::f2FCMPLT_S:
415 case CSKY::f2FCMPLT_D:
416 case CSKY::f2FCMPNE_S:
417 case CSKY::f2FCMPNE_D:
418 case CSKY::f2FCMPUO_S:
419 case CSKY::f2FCMPUO_D:
420 case CSKY::f2FCMPHSZ_S:
421 case CSKY::f2FCMPHSZ_D:
422 case CSKY::f2FCMPHZ_S:
423 case CSKY::f2FCMPHZ_D:
424 case CSKY::f2FCMPLSZ_S:
425 case CSKY::f2FCMPLSZ_D:
426 case CSKY::f2FCMPLTZ_S:
427 case CSKY::f2FCMPLTZ_D:
428 case CSKY::f2FCMPNEZ_S:
429 case CSKY::f2FCMPNEZ_D:
430 case CSKY::f2FCMPUOZ_S:
431 case CSKY::f2FCMPUOZ_D:
489 MI.getOperand(3).setImm(
MI.getOperand(3).getImm() +
490 MI.getOperand(4).getImm());
505 decodeInstruction(DecoderTableFPUV332,
MI, insn,
Address, DisAsm, STI);
525 if ((
Insn >> 14) == 0x3) {
526 if (Bytes.
size() < 4) {
536 Result = decodeInstruction(DecoderTable32,
MI,
Insn, Address,
this, STI);
541 if (Bytes.
size() < 2) {
546 Result = decodeInstruction(DecoderTable16,
MI,
Insn, Address,
this, STI);
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
static const uint16_t GPRPairDecoderTable[]
static LLVM_ATTRIBUTE_UNUSED DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static const uint16_t FPR32DecoderTable[]
static DecodeStatus DecodeRegSeqOperandF2(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYDisassembler()
static DecodeStatus decodeJMPIXImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static const uint16_t FPR128DecoderTable[]
static MCDisassembler * createCSKYDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegSeqOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegSeqOperandF1(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegSeqOperandD2(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static LLVM_ATTRIBUTE_UNUSED DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeImmShiftOpValue(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegSeqOperandD1(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static const uint16_t GPRDecoderTable[]
static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address, const MCDisassembler *DisAsm, const MCSubtargetInfo &STI)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static const uint16_t FPR64DecoderTable[]
static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
#define LLVM_ATTRIBUTE_UNUSED
#define LLVM_EXTERNAL_VISIBILITY
This file defines the DenseMap class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Container class for subtarget features.
Context object for machine code objects.
Superclass for all disassemblers.
const MCSubtargetInfo & getSubtargetInfo() const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
Interface to description of machine instruction set.
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
uint16_t read16le(const void *P)
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Target & getTheCSKYTarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.