LLVM  16.0.0git
CSKYDisassembler.cpp
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1 //===-- CSKYDisassembler.cpp - Disassembler for CSKY ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the CSKYDisassembler class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDecoderOps.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/TargetRegistry.h"
25 #include "llvm/Support/Endian.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "csky-disassembler"
30 
32 
33 namespace {
34 class CSKYDisassembler : public MCDisassembler {
35  std::unique_ptr<MCInstrInfo const> const MCII;
36  mutable StringRef symbolName;
37 
38  DecodeStatus handleCROperand(MCInst &Instr) const;
39 
40 public:
41  CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
42  MCInstrInfo const *MCII);
43 
44  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
45  ArrayRef<uint8_t> Bytes, uint64_t Address,
46  raw_ostream &CStream) const override;
47 };
48 } // end anonymous namespace
49 
50 CSKYDisassembler::CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
51  MCInstrInfo const *MCII)
52  : MCDisassembler(STI, Ctx), MCII(MCII) {}
53 
55  const MCSubtargetInfo &STI,
56  MCContext &Ctx) {
57  return new CSKYDisassembler(STI, Ctx, T.createMCInstrInfo());
58 }
59 
61  TargetRegistry::RegisterMCDisassembler(getTheCSKYTarget(),
63 }
64 
65 static const uint16_t GPRDecoderTable[] = {
66  CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3, CSKY::R4, CSKY::R5, CSKY::R6,
67  CSKY::R7, CSKY::R8, CSKY::R9, CSKY::R10, CSKY::R11, CSKY::R12, CSKY::R13,
68  CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
69  CSKY::R21, CSKY::R22, CSKY::R23, CSKY::R24, CSKY::R25, CSKY::R26, CSKY::R27,
70  CSKY::R28, CSKY::R29, CSKY::R30, CSKY::R31};
71 
72 static const uint16_t GPRPairDecoderTable[] = {
73  CSKY::R0_R1, CSKY::R1_R2, CSKY::R2_R3, CSKY::R3_R4, CSKY::R4_R5,
74  CSKY::R5_R6, CSKY::R6_R7, CSKY::R7_R8, CSKY::R8_R9, CSKY::R9_R10,
75  CSKY::R10_R11, CSKY::R11_R12, CSKY::R12_R13, CSKY::R13_R14, CSKY::R14_R15,
76  CSKY::R15_R16, CSKY::R16_R17, CSKY::R17_R18, CSKY::R18_R19, CSKY::R19_R20,
77  CSKY::R20_R21, CSKY::R21_R22, CSKY::R22_R23, CSKY::R23_R24, CSKY::R24_R25,
78  CSKY::R25_R26, CSKY::R26_R27, CSKY::R27_R28, CSKY::R28_R29, CSKY::R29_R30,
79  CSKY::R30_R31, CSKY::R31_R32};
80 
81 static const uint16_t FPR32DecoderTable[] = {
82  CSKY::F0_32, CSKY::F1_32, CSKY::F2_32, CSKY::F3_32, CSKY::F4_32,
83  CSKY::F5_32, CSKY::F6_32, CSKY::F7_32, CSKY::F8_32, CSKY::F9_32,
84  CSKY::F10_32, CSKY::F11_32, CSKY::F12_32, CSKY::F13_32, CSKY::F14_32,
85  CSKY::F15_32, CSKY::F16_32, CSKY::F17_32, CSKY::F18_32, CSKY::F19_32,
86  CSKY::F20_32, CSKY::F21_32, CSKY::F22_32, CSKY::F23_32, CSKY::F24_32,
87  CSKY::F25_32, CSKY::F26_32, CSKY::F27_32, CSKY::F28_32, CSKY::F29_32,
88  CSKY::F30_32, CSKY::F31_32};
89 
90 static const uint16_t FPR64DecoderTable[] = {
91  CSKY::F0_64, CSKY::F1_64, CSKY::F2_64, CSKY::F3_64, CSKY::F4_64,
92  CSKY::F5_64, CSKY::F6_64, CSKY::F7_64, CSKY::F8_64, CSKY::F9_64,
93  CSKY::F10_64, CSKY::F11_64, CSKY::F12_64, CSKY::F13_64, CSKY::F14_64,
94  CSKY::F15_64, CSKY::F16_64, CSKY::F17_64, CSKY::F18_64, CSKY::F19_64,
95  CSKY::F20_64, CSKY::F21_64, CSKY::F22_64, CSKY::F23_64, CSKY::F24_64,
96  CSKY::F25_64, CSKY::F26_64, CSKY::F27_64, CSKY::F28_64, CSKY::F29_64,
97  CSKY::F30_64, CSKY::F31_64};
98 
99 static const uint16_t FPR128DecoderTable[] = {
100  CSKY::F0_128, CSKY::F1_128, CSKY::F2_128, CSKY::F3_128, CSKY::F4_128,
101  CSKY::F5_128, CSKY::F6_128, CSKY::F7_128, CSKY::F8_128, CSKY::F9_128,
102  CSKY::F10_128, CSKY::F11_128, CSKY::F12_128, CSKY::F13_128, CSKY::F14_128,
103  CSKY::F15_128, CSKY::F16_128, CSKY::F17_128, CSKY::F18_128, CSKY::F19_128,
104  CSKY::F20_128, CSKY::F21_128, CSKY::F22_128, CSKY::F23_128, CSKY::F24_128,
105  CSKY::F25_128, CSKY::F26_128, CSKY::F27_128, CSKY::F28_128, CSKY::F29_128,
106  CSKY::F30_128, CSKY::F31_128};
107 
109  uint64_t Address,
110  const MCDisassembler *Decoder) {
111  if (RegNo >= 32)
112  return MCDisassembler::Fail;
113 
114  Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
116 }
117 
119  uint64_t Address,
120  const MCDisassembler *Decoder) {
121  if (RegNo >= 32)
122  return MCDisassembler::Fail;
123 
124  Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
126 }
127 
129  uint64_t Address,
130  const MCDisassembler *Decoder) {
131  if (RegNo >= 16)
132  return MCDisassembler::Fail;
133 
134  Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
136 }
137 
139  uint64_t Address,
140  const MCDisassembler *Decoder) {
141  if (RegNo >= 16)
142  return MCDisassembler::Fail;
143 
144  Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
146 }
147 
149  uint64_t Address,
150  const MCDisassembler *Decoder) {
151  if (RegNo >= 16)
152  return MCDisassembler::Fail;
153 
154  Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
156 }
157 
159  uint64_t Address,
160  const MCDisassembler *Decoder) {
161  if (RegNo >= 32)
162  return MCDisassembler::Fail;
163 
164  Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
166 }
167 
168 // TODO
171  uint64_t Address,
172  const MCDisassembler *Decoder) {
173  if (RegNo >= 16)
174  return MCDisassembler::Fail;
175 
176  Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo]));
178 }
179 
181  uint64_t Address,
182  const MCDisassembler *Decoder) {
183  if (RegNo >= 16)
184  return MCDisassembler::Fail;
185 
186  Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
188 }
189 
191  uint64_t Address,
192  const MCDisassembler *Decoder) {
193  if (RegNo >= 8)
194  return MCDisassembler::Fail;
195 
196  Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
198 }
199 
200 // TODO
203  uint64_t Address,
204  const MCDisassembler *Decoder) {
205  if (RegNo != 14)
206  return MCDisassembler::Fail;
207 
208  Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
210 }
211 
213  uint64_t Address,
214  const MCDisassembler *Decoder) {
215  const FeatureBitset &FeatureBits =
216  Decoder->getSubtargetInfo().getFeatureBits();
217  bool hasHighReg = FeatureBits[CSKY::FeatureHighreg];
218 
219  if (RegNo >= 32 || (!hasHighReg && RegNo >= 16))
220  return MCDisassembler::Fail;
221 
222  Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[RegNo]));
224 }
225 
226 template <unsigned N, unsigned S>
228  int64_t Address,
229  const MCDisassembler *Decoder) {
230  assert(isUInt<N>(Imm) && "Invalid immediate");
231  Inst.addOperand(MCOperand::createImm(Imm << S));
233 }
234 
235 template <unsigned N>
237  int64_t Address,
238  const MCDisassembler *Decoder) {
239  assert(isUInt<N>(Imm) && "Invalid immediate");
240  Inst.addOperand(MCOperand::createImm(Imm + 1));
242 }
243 
244 static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address,
245  const MCDisassembler *Decoder) {
246  assert(isUInt<8>(Imm) && "Invalid immediate");
247  if ((Imm >> 7) & 0x1) {
248  Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2));
249  } else {
250  uint64_t V = ((Imm ^ 0xFFFFFFFF) & 0xFF);
251  Inst.addOperand(MCOperand::createImm(V << 2));
252  }
253 
255 }
256 
258  int64_t Address,
259  const MCDisassembler *Decoder) {
260  assert(isUInt<2>(Imm) && "Invalid immediate");
261 
262  if (Imm == 0)
263  Inst.addOperand(MCOperand::createImm(16));
264  else if (Imm == 1)
265  Inst.addOperand(MCOperand::createImm(24));
266  else if (Imm == 2)
267  Inst.addOperand(MCOperand::createImm(32));
268  else if (Imm == 3)
269  Inst.addOperand(MCOperand::createImm(40));
270  else
271  return MCDisassembler::Fail;
272 
274 }
275 
277  int64_t Address,
278  const MCDisassembler *Decoder) {
279  assert(isUInt<10>(Imm) && "Invalid immediate");
280 
281  auto Imm5 = Imm & 0x1f;
282  auto Ry = (Imm >> 5) & 0x1f;
283 
284  if (DecodeGPRRegisterClass(Inst, Ry, Address, Decoder) ==
286  return MCDisassembler::Fail;
287 
288  Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Ry + Imm5]));
289 
291 }
292 
294  int64_t Address,
295  const MCDisassembler *Decoder) {
296  assert(isUInt<10>(Imm) && "Invalid immediate");
297 
298  auto Imm5 = Imm & 0x1f;
299  auto Ry = (Imm >> 5) & 0x1f;
300 
301  if (DecodesFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
303  return MCDisassembler::Fail;
304 
305  Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
306 
308 }
309 
311  int64_t Address,
312  const MCDisassembler *Decoder) {
313  assert(isUInt<10>(Imm) && "Invalid immediate");
314 
315  auto Imm5 = Imm & 0x1f;
316  auto Ry = (Imm >> 5) & 0x1f;
317 
318  if (DecodesFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
320  return MCDisassembler::Fail;
321 
322  Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
323 
325 }
326 
328  int64_t Address,
329  const MCDisassembler *Decoder) {
330  assert(isUInt<10>(Imm) && "Invalid immediate");
331 
332  auto Imm5 = Imm & 0x1f;
333  auto Ry = (Imm >> 5) & 0x1f;
334 
335  if (DecodeFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
337  return MCDisassembler::Fail;
338 
339  Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
340 
342 }
343 
345  int64_t Address,
346  const MCDisassembler *Decoder) {
347  assert(isUInt<10>(Imm) && "Invalid immediate");
348 
349  auto Imm5 = Imm & 0x1f;
350  auto Ry = (Imm >> 5) & 0x1f;
351 
352  if (DecodeFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
354  return MCDisassembler::Fail;
355 
356  Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
357 
359 }
360 
362  int64_t Address,
363  const MCDisassembler *Decoder) {
364  Inst.addOperand(MCOperand::createImm(Log2_64(Imm)));
366 }
367 
368 template <unsigned N, unsigned S>
370  int64_t Address,
371  const MCDisassembler *Decoder) {
372  assert(isUInt<N>(Imm) && "Invalid immediate");
373  // Sign-extend the number in the bottom N bits of Imm
374  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) << S));
376 }
377 
378 #include "CSKYGenDisassemblerTables.inc"
379 
380 DecodeStatus CSKYDisassembler::handleCROperand(MCInst &MI) const {
381 
382  // FIXME: To query instruction info from td file or a table inc file
383  switch (MI.getOpcode()) {
384  default:
386  case CSKY::LD16WSP:
387  case CSKY::ST16WSP:
388  case CSKY::ADDI16ZSP:
389  MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::R14));
391  case CSKY::ADDI16SPSP:
392  case CSKY::SUBI16SPSP:
393  MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
394  MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
396  case CSKY::FCMPHS_S:
397  case CSKY::FCMPHS_D:
398  case CSKY::FCMPLT_S:
399  case CSKY::FCMPLT_D:
400  case CSKY::FCMPNE_S:
401  case CSKY::FCMPNE_D:
402  case CSKY::FCMPUO_S:
403  case CSKY::FCMPUO_D:
404  case CSKY::FCMPZHS_S:
405  case CSKY::FCMPZHS_D:
406  case CSKY::FCMPZLS_S:
407  case CSKY::FCMPZLS_D:
408  case CSKY::FCMPZNE_S:
409  case CSKY::FCMPZNE_D:
410  case CSKY::FCMPZUO_S:
411  case CSKY::FCMPZUO_D:
412  case CSKY::f2FCMPHS_S:
413  case CSKY::f2FCMPHS_D:
414  case CSKY::f2FCMPLT_S:
415  case CSKY::f2FCMPLT_D:
416  case CSKY::f2FCMPNE_S:
417  case CSKY::f2FCMPNE_D:
418  case CSKY::f2FCMPUO_S:
419  case CSKY::f2FCMPUO_D:
420  case CSKY::f2FCMPHSZ_S:
421  case CSKY::f2FCMPHSZ_D:
422  case CSKY::f2FCMPHZ_S:
423  case CSKY::f2FCMPHZ_D:
424  case CSKY::f2FCMPLSZ_S:
425  case CSKY::f2FCMPLSZ_D:
426  case CSKY::f2FCMPLTZ_S:
427  case CSKY::f2FCMPLTZ_D:
428  case CSKY::f2FCMPNEZ_S:
429  case CSKY::f2FCMPNEZ_D:
430  case CSKY::f2FCMPUOZ_S:
431  case CSKY::f2FCMPUOZ_D:
432 
433  case CSKY::BT32:
434  case CSKY::BF32:
435  case CSKY::BT16:
436  case CSKY::BF16:
437  case CSKY::CMPNEI32:
438  case CSKY::CMPNEI16:
439  case CSKY::CMPNE32:
440  case CSKY::CMPNE16:
441  case CSKY::CMPHSI32:
442  case CSKY::CMPHSI16:
443  case CSKY::CMPHS32:
444  case CSKY::CMPHS16:
445  case CSKY::CMPLTI32:
446  case CSKY::CMPLTI16:
447  case CSKY::CMPLT32:
448  case CSKY::CMPLT16:
449  case CSKY::BTSTI32:
450  case CSKY::BTSTI16:
451  case CSKY::TSTNBZ32:
452  case CSKY::TSTNBZ16:
453  case CSKY::TST32:
454  case CSKY::TST16:
455  MI.insert(MI.begin(), MCOperand::createReg(CSKY::C));
457  case CSKY::LSLC32:
458  case CSKY::LSRC32:
459  case CSKY::ASRC32:
460  MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
462  case CSKY::MOVF32:
463  case CSKY::MOVT32:
464  case CSKY::MVC32:
465  case CSKY::MVCV32:
466  case CSKY::MVCV16:
467  case CSKY::INCT32:
468  case CSKY::INCF32:
469  case CSKY::DECT32:
470  case CSKY::DECF32:
471  case CSKY::DECGT32:
472  case CSKY::DECLT32:
473  case CSKY::DECNE32:
474  case CSKY::CLRF32:
475  case CSKY::CLRT32:
476  case CSKY::f2FSEL_S:
477  case CSKY::f2FSEL_D:
478  MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
480  case CSKY::ADDC32:
481  case CSKY::ADDC16:
482  case CSKY::SUBC32:
483  case CSKY::SUBC16:
484  case CSKY::XSR32:
485  MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
486  MI.insert(MI.end(), MCOperand::createReg(CSKY::C));
488  case CSKY::INS32:
489  MI.getOperand(3).setImm(MI.getOperand(3).getImm() +
490  MI.getOperand(4).getImm());
492  }
493 }
494 
495 static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address,
496  const MCDisassembler *DisAsm,
497  const MCSubtargetInfo &STI) {
498  LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit fpuv3 table :\n");
499  if (!STI.getFeatureBits()[CSKY::FeatureFPUV3_HF] &&
500  !STI.getFeatureBits()[CSKY::FeatureFPUV3_SF] &&
501  !STI.getFeatureBits()[CSKY::FeatureFPUV3_DF])
502  return false;
503 
504  DecodeStatus Result =
505  decodeInstruction(DecoderTableFPUV332, MI, insn, Address, DisAsm, STI);
506 
507  if (Result == MCDisassembler::Fail) {
508  MI.clear();
509  return false;
510  }
511 
512  return true;
513 }
514 
515 DecodeStatus CSKYDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
516  ArrayRef<uint8_t> Bytes,
517  uint64_t Address,
518  raw_ostream &CS) const {
519 
520  uint32_t Insn;
522 
524 
525  if ((Insn >> 14) == 0x3) {
526  if (Bytes.size() < 4) {
527  Size = 0;
528  return MCDisassembler::Fail;
529  }
530  Insn = (Insn << 16) | support::endian::read16le(&Bytes[2]);
531 
532  if (decodeFPUV3Instruction(MI, Insn, Address, this, STI))
533  Result = MCDisassembler::Success;
534  else {
535  LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit table :\n");
536  Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
537  }
538 
539  Size = 4;
540  } else {
541  if (Bytes.size() < 2) {
542  Size = 0;
543  return MCDisassembler::Fail;
544  }
545  LLVM_DEBUG(dbgs() << "Trying CSKY 16-bit table :\n");
546  Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
547  Size = 2;
548  }
549 
550  handleCROperand(MI);
551 
552  return Result;
553 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
DecodeRegSeqOperandD1
static DecodeStatus DecodeRegSeqOperandD1(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:310
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IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCDisassembler.h
DecodeRegSeqOperand
static DecodeStatus DecodeRegSeqOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:276
CSKYBaseInfo.h
T
FPR32DecoderTable
static const uint16_t FPR32DecoderTable[]
Definition: CSKYDisassembler.cpp:81
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
DecodeRegSeqOperandF2
static DecodeStatus DecodeRegSeqOperandF2(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:327
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static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address, const MCDisassembler *DisAsm, const MCSubtargetInfo &STI)
Definition: CSKYDisassembler.cpp:495
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Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
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uint16_t read16le(const void *P)
Definition: Endian.h:380
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static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:148
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#define Fail
Definition: AArch64Disassembler.cpp:281
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#define R4(n)
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static DecodeStatus decodeJMPIXImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:257
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Container class for subtarget features.
Definition: SubtargetFeature.h:40
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LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYDisassembler()
Definition: CSKYDisassembler.cpp:60
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Definition: MCInst.h:184
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#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:172
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:369
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#define LLVM_DEBUG(X)
Definition: Debug.h:101
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const T * data() const
Definition: ArrayRef.h:161
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static const uint16_t GPRPairDecoderTable[]
Definition: CSKYDisassembler.cpp:72
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MCDisassembler::DecodeStatus DecodeStatus
Definition: CSKYDisassembler.cpp:31
llvm::getTheCSKYTarget
Target & getTheCSKYTarget()
Definition: CSKYTargetInfo.cpp:13
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Definition: Debug.cpp:163
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
R2
#define R2(n)
llvm::Log2_64
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:553
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:118
MCContext.h
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:108
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
MCInst.h
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:227
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
DecodesGPRRegisterClass
static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:180
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
decodeOImmOperand
static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:236
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
CSKYMCTargetDesc.h
R6
#define R6(n)
createCSKYDisassembler
static MCDisassembler * createCSKYDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: CSKYDisassembler.cpp:54
FPR128DecoderTable
static const uint16_t FPR128DecoderTable[]
Definition: CSKYDisassembler.cpp:99
llvm::ArrayRef< uint8_t >
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
DecodesFPR32RegisterClass
static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:128
DecodeGPRSPRegisterClass
static LLVM_ATTRIBUTE_UNUSED DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:202
DecodeGPRPairRegisterClass
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:212
uint32_t
GPRDecoderTable
static const uint16_t GPRDecoderTable[]
Definition: CSKYDisassembler.cpp:65
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:158
decodeLRW16Imm8
static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:244
decodeImmShiftOpValue
static DecodeStatus decodeImmShiftOpValue(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:361
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:130
uint16_t
DecodeRegSeqOperandF1
static DecodeStatus DecodeRegSeqOperandF1(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:293
Success
#define Success
Definition: AArch64Disassembler.cpp:280
DecodeRegSeqOperandD2
static DecodeStatus DecodeRegSeqOperandD2(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:344
DecodesFPR64RegisterClass
static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:138
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:219
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
CSKYTargetInfo.h
DecodesFPR128RegisterClass
static LLVM_ATTRIBUTE_UNUSED DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:170
DecodemGPRRegisterClass
static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: CSKYDisassembler.cpp:190
Endian.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
FPR64DecoderTable
static const uint16_t FPR64DecoderTable[]
Definition: CSKYDisassembler.cpp:90