30#define DEBUG_TYPE "xtensa-asm-parser"
39 bool ParseDirective(
AsmToken DirectiveID)
override;
44 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
47 bool MatchingInlineAsm)
override;
49 unsigned Kind)
override;
52#define GET_ASSEMBLER_HEADER
53#include "XtensaGenAsmMatcher.inc"
57 bool AllowParens =
false,
bool SR =
false);
64 SMLoc &EndLoc)
override {
72#define GET_OPERAND_DIAGNOSTIC_TYPES
73#include "XtensaGenAsmMatcher.inc"
74#undef GET_OPERAND_DIAGNOSTIC_TYPES
85static bool inRange(
const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
86 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
87 int64_t
Value = CE->getValue();
139 bool isMem()
const override {
return false; }
141 bool isImm(int64_t MinValue, int64_t MaxValue)
const {
148 return isImm(-32768, 32512) &&
149 ((cast<MCConstantExpr>(
getImm())->getValue() & 0xFF) == 0);
157 return isImm(0, 60) &&
158 ((cast<MCConstantExpr>(
getImm())->getValue() & 0x3) == 0);
164 return isImm(0, 510) &&
165 ((cast<MCConstantExpr>(
getImm())->getValue() & 0x1) == 0);
169 return isImm(0, 1020) &&
170 ((cast<MCConstantExpr>(
getImm())->getValue() & 0x3) == 0);
188 if (
auto *CE = dyn_cast<MCConstantExpr>(
getImm())) {
189 int64_t
Value = CE->getValue();
218 if (
auto *CE = dyn_cast<MCConstantExpr>(
getImm())) {
219 int64_t
Value = CE->getValue();
281 auto Op = std::make_unique<XtensaOperand>(
Token);
290 auto Op = std::make_unique<XtensaOperand>(
Register);
291 Op->Reg.RegNum = RegNo;
299 auto Op = std::make_unique<XtensaOperand>(
Immediate);
307 assert(Expr &&
"Expr shouldn't be null!");
309 bool IsConstant =
false;
311 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
313 Imm = CE->getValue();
324 assert(
N == 1 &&
"Invalid number of operands!");
329 assert(
N == 1 &&
"Invalid number of operands!");
334#define GET_REGISTER_MATCHER
335#define GET_MATCHER_IMPLEMENTATION
336#include "XtensaGenAsmMatcher.inc"
347 if (ErrorLoc ==
SMLoc())
354bool XtensaAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
358 bool MatchingInlineAsm) {
371 return Error(IDLoc,
"instruction use requires an option to be enabled");
373 return Error(IDLoc,
"unrecognized instruction mnemonic");
375 SMLoc ErrorLoc = IDLoc;
378 return Error(ErrorLoc,
"too few operands for instruction");
381 if (ErrorLoc ==
SMLoc())
384 return Error(ErrorLoc,
"invalid operand for instruction");
386 case Match_InvalidImm8:
388 "expected immediate in range [-128, 127]");
389 case Match_InvalidImm8_sh8:
391 "expected immediate in range [-32768, 32512], first 8 bits "
393 case Match_InvalidB4const:
395 "expected b4const immediate");
396 case Match_InvalidB4constu:
398 "expected b4constu immediate");
399 case Match_InvalidImm12:
401 "expected immediate in range [-2048, 2047]");
402 case Match_InvalidImm12m:
404 "expected immediate in range [-2048, 2047]");
405 case Match_InvalidImm1_16:
407 "expected immediate in range [1, 16]");
408 case Match_InvalidShimm1_31:
410 "expected immediate in range [1, 31]");
411 case Match_InvalidUimm4:
413 "expected immediate in range [0, 15]");
414 case Match_InvalidUimm5:
416 "expected immediate in range [0, 31]");
417 case Match_InvalidOffset8m8:
419 "expected immediate in range [0, 255]");
420 case Match_InvalidOffset8m16:
422 "expected immediate in range [0, 510], first bit "
424 case Match_InvalidOffset8m32:
426 "expected immediate in range [0, 1020], first 2 bits "
428 case Match_InvalidOffset4m32:
430 "expected immediate in range [0, 60], first 2 bits "
445 const MCExpr *Expr =
nullptr;
452 if (Expr->
getKind() == MCExpr::ExprKind::Constant) {
453 Error(getLoc(),
"unknown operand");
474 return Error(StartLoc,
"invalid register name");
478 bool AllowParens,
bool SR) {
479 SMLoc FirstS = getLoc();
480 bool HadParens =
false;
555 if (
getParser().parseIdentifier(Identifier))
563 return parseOperandWithModifier(
Operands);
603 Error(getLoc(),
"unknown operand");
610 if ((
Name.startswith(
"wsr.") ||
Name.startswith(
"rsr.") ||
611 Name.startswith(
"xsr.")) &&
626 Error(NameLoc,
"invalid register name");
648 return Error(Loc,
"unexpected token");
661 return Error(Loc,
"unexpected token");
671 if (
Name.startswith(
"wsr") ||
Name.startswith(
"rsr") ||
672 Name.startswith(
"xsr")) {
673 return ParseInstructionWithSR(Info,
Name, NameLoc,
Operands);
700 return Error(Loc,
"unexpected token");
707bool XtensaAsmParser::ParseDirective(
AsmToken DirectiveID) {
return true; }
static unsigned MatchRegisterName(StringRef Name)
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
mir Rename Register Operands
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmParser()
static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, uint64_t ErrorInfo)
XtensaAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options)
Target independent representation for an assembler token.
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Base class for user error types.
Lightweight error class with error context and mandatory checking.
void UnLex(AsmToken const &Token)
SMLoc getLoc() const
Get the current source location.
const AsmToken & getTok() const
Get the current (last) lexed token.
const AsmToken & Lex()
Consume the next token from the input stream and return it.
virtual size_t peekTokens(MutableArrayRef< AsmToken > Buf, bool ShouldSkipSpace=true)=0
Look ahead an arbitrary number of tokens.
const AsmToken & getTok()
MCAsmParser & getParser()
Generic assembler parser interface, for use by target specific assembly parsers.
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Base class for the full range of assembler expressions which are needed for parsing.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
Interface to description of machine instruction set.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
MCTargetAsmParser - Generic interface to target specific assembly parsers.
@ FIRST_TARGET_MATCH_RESULT_TY
void setAvailableFeatures(const FeatureBitset &Value)
const MCSubtargetInfo & getSTI() const
const MCSubtargetInfo * STI
Current STI.
Wrapper class representing virtual and physical registers.
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
const char * getPointer() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Target & getTheXtensaTarget()
bool isOffset4m32() const
bool isOffset8m16() const
static std::unique_ptr< XtensaOperand > createToken(StringRef Str, SMLoc S)
void addRegOperands(MCInst &Inst, unsigned N) const
void addExpr(MCInst &Inst, const MCExpr *Expr) const
void addImmOperands(MCInst &Inst, unsigned N) const
StringRef getToken() const
unsigned getReg() const override
enum XtensaOperand::KindTy Kind
bool isMem() const override
isMem - Is this a memory operand?
bool isToken() const override
isToken - Is this a token operand?
SMLoc getStartLoc() const override
getStartLoc - Gets location of the first token of this operand
bool isImm(int64_t MinValue, int64_t MaxValue) const
void print(raw_ostream &OS) const override
print - Print a debug representation of the operand to the given stream.
bool isReg() const override
isReg - Is this a register operand?
bool isImm() const override
isImm - Is this an immediate operand?
static std::unique_ptr< XtensaOperand > createReg(unsigned RegNo, SMLoc S, SMLoc E)
SMLoc getEndLoc() const override
getEndLoc - Gets location of the last token of this operand
const MCExpr * getImm() const
XtensaOperand(const XtensaOperand &o)
static std::unique_ptr< XtensaOperand > createImm(const MCExpr *Val, SMLoc S, SMLoc E)
bool isOffset8m32() const
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...