LLVM 19.0.0git
VEAsmPrinter.cpp
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1//===-- VEAsmPrinter.cpp - VE LLVM assembly writer ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format VE assembly language.
11//
12//===----------------------------------------------------------------------===//
13
18#include "VE.h"
19#include "VEInstrInfo.h"
20#include "VETargetMachine.h"
26#include "llvm/IR/Mangler.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/MC/MCContext.h"
29#include "llvm/MC/MCInst.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSymbol.h"
35using namespace llvm;
36
37#define DEBUG_TYPE "ve-asmprinter"
38
39namespace {
40class VEAsmPrinter : public AsmPrinter {
41 VETargetStreamer &getTargetStreamer() {
42 return static_cast<VETargetStreamer &>(*OutStreamer->getTargetStreamer());
43 }
44
45public:
46 explicit VEAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
47 : AsmPrinter(TM, std::move(Streamer)) {}
48
49 StringRef getPassName() const override { return "VE Assembly Printer"; }
50
51 void lowerGETGOTAndEmitMCInsts(const MachineInstr *MI,
52 const MCSubtargetInfo &STI);
53 void lowerGETFunPLTAndEmitMCInsts(const MachineInstr *MI,
54 const MCSubtargetInfo &STI);
55 void lowerGETTLSAddrAndEmitMCInsts(const MachineInstr *MI,
56 const MCSubtargetInfo &STI);
57
58 void emitInstruction(const MachineInstr *MI) override;
59
60 static const char *getRegisterName(MCRegister Reg) {
62 }
63 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &OS);
64 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
65 const char *ExtraCode, raw_ostream &O) override;
66 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
67 const char *ExtraCode, raw_ostream &O) override;
68};
69} // end of anonymous namespace
70
72 MCContext &OutContext) {
73 const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym, OutContext);
74 const VEMCExpr *expr = VEMCExpr::create(Kind, MCSym, OutContext);
75 return MCOperand::createExpr(expr);
76}
77
79 MCSymbol *GOTLabel, MCContext &OutContext) {
80 const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
81 const VEMCExpr *expr = VEMCExpr::create(Kind, GOT, OutContext);
82 return MCOperand::createExpr(expr);
83}
84
85static void emitSIC(MCStreamer &OutStreamer, MCOperand &RD,
86 const MCSubtargetInfo &STI) {
87 MCInst SICInst;
88 SICInst.setOpcode(VE::SIC);
89 SICInst.addOperand(RD);
90 OutStreamer.emitInstruction(SICInst, STI);
91}
92
93static void emitBSIC(MCStreamer &OutStreamer, MCOperand &R1, MCOperand &R2,
94 const MCSubtargetInfo &STI) {
95 MCInst BSICInst;
96 BSICInst.setOpcode(VE::BSICrii);
97 BSICInst.addOperand(R1);
98 BSICInst.addOperand(R2);
100 BSICInst.addOperand(czero);
101 BSICInst.addOperand(czero);
102 OutStreamer.emitInstruction(BSICInst, STI);
103}
104
105static void emitLEAzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD,
106 const MCSubtargetInfo &STI) {
107 MCInst LEAInst;
108 LEAInst.setOpcode(VE::LEAzii);
109 LEAInst.addOperand(RD);
111 LEAInst.addOperand(CZero);
112 LEAInst.addOperand(CZero);
113 LEAInst.addOperand(Imm);
114 OutStreamer.emitInstruction(LEAInst, STI);
115}
116
117static void emitLEASLzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD,
118 const MCSubtargetInfo &STI) {
119 MCInst LEASLInst;
120 LEASLInst.setOpcode(VE::LEASLzii);
121 LEASLInst.addOperand(RD);
123 LEASLInst.addOperand(CZero);
124 LEASLInst.addOperand(CZero);
125 LEASLInst.addOperand(Imm);
126 OutStreamer.emitInstruction(LEASLInst, STI);
127}
128
129static void emitLEAzii(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm,
130 MCOperand &RD, const MCSubtargetInfo &STI) {
131 MCInst LEAInst;
132 LEAInst.setOpcode(VE::LEAzii);
133 LEAInst.addOperand(RD);
135 LEAInst.addOperand(CZero);
136 LEAInst.addOperand(RS1);
137 LEAInst.addOperand(Imm);
138 OutStreamer.emitInstruction(LEAInst, STI);
139}
140
141static void emitLEASLrri(MCStreamer &OutStreamer, MCOperand &RS1,
142 MCOperand &RS2, MCOperand &Imm, MCOperand &RD,
143 const MCSubtargetInfo &STI) {
144 MCInst LEASLInst;
145 LEASLInst.setOpcode(VE::LEASLrri);
146 LEASLInst.addOperand(RD);
147 LEASLInst.addOperand(RS1);
148 LEASLInst.addOperand(RS2);
149 LEASLInst.addOperand(Imm);
150 OutStreamer.emitInstruction(LEASLInst, STI);
151}
152
153static void emitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1,
154 MCOperand &Src2, MCOperand &RD,
155 const MCSubtargetInfo &STI) {
156 MCInst Inst;
157 Inst.setOpcode(Opcode);
158 Inst.addOperand(RD);
159 Inst.addOperand(RS1);
160 Inst.addOperand(Src2);
161 OutStreamer.emitInstruction(Inst, STI);
162}
163
164static void emitANDrm(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm,
165 MCOperand &RD, const MCSubtargetInfo &STI) {
166 emitBinary(OutStreamer, VE::ANDrm, RS1, Imm, RD, STI);
167}
168
169static void emitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
171 MCOperand &RD, MCContext &OutContext,
172 const MCSubtargetInfo &STI) {
173
174 MCOperand hi = createVEMCOperand(HiKind, GOTSym, OutContext);
175 MCOperand lo = createVEMCOperand(LoKind, GOTSym, OutContext);
176 emitLEAzzi(OutStreamer, lo, RD, STI);
178 emitANDrm(OutStreamer, RD, M032, RD, STI);
179 emitLEASLzzi(OutStreamer, hi, RD, STI);
180}
181
182void VEAsmPrinter::lowerGETGOTAndEmitMCInsts(const MachineInstr *MI,
183 const MCSubtargetInfo &STI) {
184 MCSymbol *GOTLabel =
185 OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
186
187 const MachineOperand &MO = MI->getOperand(0);
188 MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
189
190 if (!isPositionIndependent()) {
191 // Just load the address of GOT to MCRegOP.
192 switch (TM.getCodeModel()) {
193 default:
194 llvm_unreachable("Unsupported absolute code model");
195 case CodeModel::Small:
197 case CodeModel::Large:
198 emitHiLo(*OutStreamer, GOTLabel, VEMCExpr::VK_VE_HI32,
199 VEMCExpr::VK_VE_LO32, MCRegOP, OutContext, STI);
200 break;
201 }
202 return;
203 }
204
205 MCOperand RegGOT = MCOperand::createReg(VE::SX15); // GOT
206 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT
207
208 // lea %got, _GLOBAL_OFFSET_TABLE_@PC_LO(-24)
209 // and %got, %got, (32)0
210 // sic %plt
211 // lea.sl %got, _GLOBAL_OFFSET_TABLE_@PC_HI(%plt, %got)
212 MCOperand cim24 = MCOperand::createImm(-24);
213 MCOperand loImm =
214 createGOTRelExprOp(VEMCExpr::VK_VE_PC_LO32, GOTLabel, OutContext);
215 emitLEAzii(*OutStreamer, cim24, loImm, MCRegOP, STI);
217 emitANDrm(*OutStreamer, MCRegOP, M032, MCRegOP, STI);
218 emitSIC(*OutStreamer, RegPLT, STI);
219 MCOperand hiImm =
220 createGOTRelExprOp(VEMCExpr::VK_VE_PC_HI32, GOTLabel, OutContext);
221 emitLEASLrri(*OutStreamer, RegGOT, RegPLT, hiImm, MCRegOP, STI);
222}
223
224void VEAsmPrinter::lowerGETFunPLTAndEmitMCInsts(const MachineInstr *MI,
225 const MCSubtargetInfo &STI) {
226 const MachineOperand &MO = MI->getOperand(0);
227 MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
228 const MachineOperand &Addr = MI->getOperand(1);
229 MCSymbol *AddrSym = nullptr;
230
231 switch (Addr.getType()) {
232 default:
233 llvm_unreachable("<unknown operand type>");
234 return;
236 report_fatal_error("MBB is not supported yet");
237 return;
239 report_fatal_error("ConstantPool is not supported yet");
240 return;
242 AddrSym = GetExternalSymbolSymbol(Addr.getSymbolName());
243 break;
245 AddrSym = getSymbol(Addr.getGlobal());
246 break;
247 }
248
249 if (!isPositionIndependent()) {
250 llvm_unreachable("Unsupported uses of %plt in not PIC code");
251 return;
252 }
253
254 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT
255
256 // lea %dst, func@plt_lo(-24)
257 // and %dst, %dst, (32)0
258 // sic %plt ; FIXME: is it safe to use %plt here?
259 // lea.sl %dst, func@plt_hi(%plt, %dst)
260 MCOperand cim24 = MCOperand::createImm(-24);
261 MCOperand loImm =
262 createGOTRelExprOp(VEMCExpr::VK_VE_PLT_LO32, AddrSym, OutContext);
263 emitLEAzii(*OutStreamer, cim24, loImm, MCRegOP, STI);
265 emitANDrm(*OutStreamer, MCRegOP, M032, MCRegOP, STI);
266 emitSIC(*OutStreamer, RegPLT, STI);
267 MCOperand hiImm =
268 createGOTRelExprOp(VEMCExpr::VK_VE_PLT_HI32, AddrSym, OutContext);
269 emitLEASLrri(*OutStreamer, MCRegOP, RegPLT, hiImm, MCRegOP, STI);
270}
271
272void VEAsmPrinter::lowerGETTLSAddrAndEmitMCInsts(const MachineInstr *MI,
273 const MCSubtargetInfo &STI) {
274 const MachineOperand &Addr = MI->getOperand(0);
275 MCSymbol *AddrSym = nullptr;
276
277 switch (Addr.getType()) {
278 default:
279 llvm_unreachable("<unknown operand type>");
280 return;
282 report_fatal_error("MBB is not supported yet");
283 return;
285 report_fatal_error("ConstantPool is not supported yet");
286 return;
288 AddrSym = GetExternalSymbolSymbol(Addr.getSymbolName());
289 break;
291 AddrSym = getSymbol(Addr.getGlobal());
292 break;
293 }
294
295 MCOperand RegLR = MCOperand::createReg(VE::SX10); // LR
296 MCOperand RegS0 = MCOperand::createReg(VE::SX0); // S0
297 MCOperand RegS12 = MCOperand::createReg(VE::SX12); // S12
298 MCSymbol *GetTLSLabel = OutContext.getOrCreateSymbol(Twine("__tls_get_addr"));
299
300 // lea %s0, sym@tls_gd_lo(-24)
301 // and %s0, %s0, (32)0
302 // sic %lr
303 // lea.sl %s0, sym@tls_gd_hi(%lr, %s0)
304 // lea %s12, __tls_get_addr@plt_lo(8)
305 // and %s12, %s12, (32)0
306 // lea.sl %s12, __tls_get_addr@plt_hi(%s12, %lr)
307 // bsic %lr, (, %s12)
308 MCOperand cim24 = MCOperand::createImm(-24);
309 MCOperand loImm =
311 emitLEAzii(*OutStreamer, cim24, loImm, RegS0, STI);
313 emitANDrm(*OutStreamer, RegS0, M032, RegS0, STI);
314 emitSIC(*OutStreamer, RegLR, STI);
315 MCOperand hiImm =
317 emitLEASLrri(*OutStreamer, RegS0, RegLR, hiImm, RegS0, STI);
319 MCOperand loImm2 =
320 createGOTRelExprOp(VEMCExpr::VK_VE_PLT_LO32, GetTLSLabel, OutContext);
321 emitLEAzii(*OutStreamer, ci8, loImm2, RegS12, STI);
322 emitANDrm(*OutStreamer, RegS12, M032, RegS12, STI);
323 MCOperand hiImm2 =
324 createGOTRelExprOp(VEMCExpr::VK_VE_PLT_HI32, GetTLSLabel, OutContext);
325 emitLEASLrri(*OutStreamer, RegS12, RegLR, hiImm2, RegS12, STI);
326 emitBSIC(*OutStreamer, RegLR, RegS12, STI);
327}
328
329void VEAsmPrinter::emitInstruction(const MachineInstr *MI) {
330 VE_MC::verifyInstructionPredicates(MI->getOpcode(),
331 getSubtargetInfo().getFeatureBits());
332
333 switch (MI->getOpcode()) {
334 default:
335 break;
336 case TargetOpcode::DBG_VALUE:
337 // FIXME: Debug Value.
338 return;
339 case VE::GETGOT:
340 lowerGETGOTAndEmitMCInsts(MI, getSubtargetInfo());
341 return;
342 case VE::GETFUNPLT:
343 lowerGETFunPLTAndEmitMCInsts(MI, getSubtargetInfo());
344 return;
345 case VE::GETTLSADDR:
346 lowerGETTLSAddrAndEmitMCInsts(MI, getSubtargetInfo());
347 return;
348 }
349
351 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
352 do {
353 MCInst TmpInst;
354 LowerVEMachineInstrToMCInst(&*I, TmpInst, *this);
355 EmitToStreamer(*OutStreamer, TmpInst);
356 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
357}
358
359void VEAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
360 raw_ostream &O) {
361 const MachineOperand &MO = MI->getOperand(OpNum);
362
363 switch (MO.getType()) {
365 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
366 break;
368 O << (int)MO.getImm();
369 break;
370 default:
371 llvm_unreachable("<unknown operand type>");
372 }
373}
374
375// PrintAsmOperand - Print out an operand for an inline asm expression.
376bool VEAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
377 const char *ExtraCode, raw_ostream &O) {
378 if (ExtraCode && ExtraCode[0]) {
379 if (ExtraCode[1] != 0)
380 return true; // Unknown modifier.
381
382 switch (ExtraCode[0]) {
383 default:
384 // See if this is a generic print operand
385 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
386 case 'r':
387 case 'v':
388 break;
389 }
390 }
391
392 printOperand(MI, OpNo, O);
393
394 return false;
395}
396
397bool VEAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
398 const char *ExtraCode,
399 raw_ostream &O) {
400 if (ExtraCode && ExtraCode[0])
401 return true; // Unknown modifier
402
403 if (MI->getOperand(OpNo+1).isImm() &&
404 MI->getOperand(OpNo+1).getImm() == 0) {
405 // don't print "+0"
406 } else {
407 printOperand(MI, OpNo+1, O);
408 }
409 if (MI->getOperand(OpNo).isImm() &&
410 MI->getOperand(OpNo).getImm() == 0) {
411 if (MI->getOperand(OpNo+1).isImm() &&
412 MI->getOperand(OpNo+1).getImm() == 0) {
413 O << "0";
414 } else {
415 // don't print "(0)"
416 }
417 } else {
418 O << "(";
419 printOperand(MI, OpNo, O);
420 O << ")";
421 }
422 return false;
423}
424
425// Force static initialization.
428}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
uint64_t Addr
Symbol * Sym
Definition: ELF_riscv.cpp:479
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Definition: MIParser.cpp:1414
#define R2(n)
const char LLVMTargetMachineRef TM
raw_pwrite_stream & OS
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
static MCOperand createGOTRelExprOp(VEMCExpr::VariantKind Kind, MCSymbol *GOTLabel, MCContext &OutContext)
static void emitSIC(MCStreamer &OutStreamer, MCOperand &RD, const MCSubtargetInfo &STI)
static void emitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI)
static void emitLEAzii(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static MCOperand createVEMCOperand(VEMCExpr::VariantKind Kind, MCSymbol *Sym, MCContext &OutContext)
static void emitLEASLzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static void emitBSIC(MCStreamer &OutStreamer, MCOperand &R1, MCOperand &R2, const MCSubtargetInfo &STI)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmPrinter()
static void emitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, VEMCExpr::VariantKind HiKind, VEMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI)
static void emitLEAzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static void emitANDrm(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
static void emitLEASLrri(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:85
virtual void emitInstruction(const MachineInstr *)
Targets should implement this to emit instructions.
Definition: AsmPrinter.h:568
virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Context object for machine code objects.
Definition: MCContext.h:82
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:397
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Instructions::const_iterator const_instr_iterator
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string lower() const
Definition: StringRef.cpp:111
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=VE::NoRegAltName)
static const VEMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: VEMCExpr.cpp:27
@ VK_VE_TLS_GD_HI32
Definition: VEMCExpr.h:38
@ VK_VE_TLS_GD_LO32
Definition: VEMCExpr.h:39
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
Target & getTheVETarget()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
unsigned M0(unsigned Val)
Definition: VE.h:375
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...