23using namespace TargetOpcode;
24using namespace LegalizeActions;
38 for (
unsigned i = 0; i < v.size(); ++i) {
39 result.push_back(v[i]);
40 if (i + 1 < v[i].first && i + 1 < v.size() &&
41 v[i + 1].first != v[i].first + 1)
54 auto Largest = result.back().first;
61 : Subtarget(STI),
TM(
TM) {
63 setLegalizerInfo32bit();
64 setLegalizerInfo64bit();
65 setLegalizerInfoSSE1();
66 setLegalizerInfoSSE2();
67 setLegalizerInfoSSE41();
68 setLegalizerInfoSSE42();
69 setLegalizerInfoAVX();
70 setLegalizerInfoAVX2();
71 setLegalizerInfoAVX512();
72 setLegalizerInfoAVX512DQ();
73 setLegalizerInfoAVX512BW();
85 LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(G_PHI, 0,
widen_1);
86 for (
unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
87 LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(BinOp, 0,
widen_1);
88 for (
unsigned MemOp : {G_LOAD, G_STORE})
89 LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(
91 LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(
94 LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(
101 if (Subtarget.is64Bit()) {
102 if (Subtarget.hasPOPCNT()) {
105 .
legalFor({{s16, s16}, {s32, s32}, {s64, s64}})
106 .widenScalarToNextPow2(1, 16)
110 if (Subtarget.hasLZCNT()) {
113 .
legalFor({{s16, s16}, {s32, s32}, {s64, s64}})
114 .widenScalarToNextPow2(1, 16)
118 if (Subtarget.hasPOPCNT()) {
122 .widenScalarToNextPow2(1, 16)
126 if (Subtarget.hasLZCNT()) {
130 .widenScalarToNextPow2(1, 16)
135 LegacyInfo.computeTables();
144void X86LegalizerInfo::setLegalizerInfo32bit() {
156 for (
auto Ty : {p0, s1, s8, s16, s32})
159 for (
auto Ty : {s8, s16, s32, p0})
162 for (
unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
163 for (
auto Ty : {s8, s16, s32})
166 for (
unsigned Op : {G_UADDE}) {
171 for (
unsigned MemOp : {G_LOAD, G_STORE}) {
172 for (
auto Ty : {s8, s16, s32, p0})
186 if (!Subtarget.is64Bit()) {
195 {G_SDIV, G_SREM, G_UDIV, G_UREM})
196 .legalFor({s8, s16, s32})
197 .clampScalar(0, s8, s32);
200 {G_SHL, G_LSHR, G_ASHR})
201 .legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
202 .clampScalar(0, s8, s32)
208 .clampScalar(0, s8, s8);
215 for (
auto Ty : {s8, s16, s32, p0})
216 LegacyInfo.setAction({TargetOpcode::G_CONSTANT, Ty},
220 for (
auto Ty : {s8, s16, s32}) {
229 for (
const auto &Ty : {s16, s32, s64}) {
231 LegacyInfo.setAction({G_UNMERGE_VALUES, 1, Ty},
234 for (
const auto &Ty : {s8, s16, s32}) {
240void X86LegalizerInfo::setLegalizerInfo64bit() {
242 if (!Subtarget.is64Bit())
262 for (
unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
265 for (
unsigned MemOp : {G_LOAD, G_STORE})
277 LegacyInfo.setAction({TargetOpcode::G_CONSTANT, s64},
281 for (
unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
287 .clampScalar(1, s32, s64)
294 .clampScalar(1, s32, s64)
302 .clampScalar(0, s8, s8);
306 .clampScalar(0, s8, s8)
312 {G_SDIV, G_SREM, G_UDIV, G_UREM})
313 .legalFor({s8, s16, s32, s64})
314 .clampScalar(0, s8, s64);
318 {G_SHL, G_LSHR, G_ASHR})
319 .legalFor({{s8, s8}, {s16, s8}, {s32, s8}, {s64, s8}})
320 .clampScalar(0, s8, s64)
325 LegacyInfo.setAction({G_UNMERGE_VALUES, 1, s128},
332void X86LegalizerInfo::setLegalizerInfoSSE1() {
343 for (
unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
344 for (
auto Ty : {s32, v4s32})
347 for (
unsigned MemOp : {G_LOAD, G_STORE})
348 for (
auto Ty : {v4s32, v2s64})
352 LegacyInfo.setAction({TargetOpcode::G_FCONSTANT, s32},
356 for (
const auto &Ty : {v4s32, v2s64}) {
358 LegacyInfo.setAction({G_UNMERGE_VALUES, 1, Ty},
365void X86LegalizerInfo::setLegalizerInfoSSE2() {
383 for (
unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
384 for (
auto Ty : {s64, v2s64})
387 for (
unsigned BinOp : {G_ADD, G_SUB})
388 for (
auto Ty : {v16s8, v8s16, v4s32, v2s64})
400 LegacyInfo.setAction({TargetOpcode::G_FCONSTANT, s64},
404 for (
const auto &Ty :
405 {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
407 LegacyInfo.setAction({G_UNMERGE_VALUES, 1, Ty},
410 for (
const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) {
411 LegacyInfo.setAction({G_CONCAT_VECTORS, 1, Ty},
417void X86LegalizerInfo::setLegalizerInfoSSE41() {
428void X86LegalizerInfo::setLegalizerInfoSSE42() {
434void X86LegalizerInfo::setLegalizerInfoAVX() {
454 for (
unsigned MemOp : {G_LOAD, G_STORE})
455 for (
auto Ty : {v8s32, v4s64})
458 for (
auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
462 for (
auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
467 for (
const auto &Ty :
468 {v32s8, v64s8, v16s16, v32s16, v8s32, v16s32, v4s64, v8s64}) {
470 LegacyInfo.setAction({G_UNMERGE_VALUES, 1, Ty},
473 for (
const auto &Ty :
474 {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
475 LegacyInfo.setAction({G_CONCAT_VECTORS, 1, Ty},
481void X86LegalizerInfo::setLegalizerInfoAVX2() {
497 for (
unsigned BinOp : {G_ADD, G_SUB})
498 for (
auto Ty : {v32s8, v16s16, v8s32, v4s64})
501 for (
auto Ty : {v16s16, v8s32})
505 for (
const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) {
507 LegacyInfo.setAction({G_UNMERGE_VALUES, 1, Ty},
510 for (
const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
511 LegacyInfo.setAction({G_CONCAT_VECTORS, 1, Ty},
517 .legalFor({v8s32, v4s64});
520void X86LegalizerInfo::setLegalizerInfoAVX512() {
541 for (
unsigned BinOp : {G_ADD, G_SUB})
542 for (
auto Ty : {v16s32, v8s64})
547 for (
unsigned MemOp : {G_LOAD, G_STORE})
548 for (
auto Ty : {v16s32, v8s64})
551 for (
auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
555 for (
auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
561 if (!Subtarget.hasVLX())
564 for (
auto Ty : {v4s32, v8s32})
568void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
569 if (!(Subtarget.
hasAVX512() && Subtarget.hasDQI()))
579 if (!Subtarget.hasVLX())
585 for (
auto Ty : {v2s64, v4s64})
589void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
590 if (!(Subtarget.
hasAVX512() && Subtarget.hasBWI()))
598 for (
unsigned BinOp : {G_ADD, G_SUB})
599 for (
auto Ty : {v64s8, v32s16})
605 if (!Subtarget.hasVLX())
611 for (
auto Ty : {v8s16, v16s16})
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static LegacyLegalizerInfo::SizeAndActionsVec widen_1(const LegacyLegalizerInfo::SizeAndActionsVec &v)
static void addAndInterleaveWithUnsupported(LegacyLegalizerInfo::SizeAndActionsVec &result, const LegacyLegalizerInfo::SizeAndActionsVec &v)
FIXME: The following static functions are SizeChangeStrategy functions that are meant to temporarily ...
This file declares the targeting of the Machinelegalizer class for X86.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
static SizeAndActionsVec narrowToSmallerAndWidenToSmallest(const SizeAndActionsVec &v)
static SizeAndActionsVec widenToLargerTypesUnsupportedOtherwise(const SizeAndActionsVec &v)
std::vector< SizeAndAction > SizeAndActionsVec
static SizeAndActionsVec widenToLargerTypesAndNarrowToLargest(const SizeAndActionsVec &v)
A SizeChangeStrategy for the common case where legalization for a particular operation consists of wi...
LegalizeRuleSet & minScalar(unsigned TypeIdx, const LLT Ty)
Ensure the scalar is at least as wide as Ty.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & libcall()
The instruction is emitted as a library call.
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & clampScalar(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the range of scalar sizes to MinTy and MaxTy.
LegalizeRuleSet & widenScalarToNextPow2(unsigned TypeIdx, unsigned MinSize=0)
Widen the scalar to the next power of two that is at least MinSize.
LegalizeRuleSet & scalarize(unsigned TypeIdx)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
Representation of each machine instruction.
unsigned getPointerSizeInBits(unsigned AS) const
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM)
const X86InstrInfo * getInstrInfo() const override
@ Legal
The operation is expected to be selectable directly by the target, and no transformation is necessary...
@ Unsupported
This operation is completely unsupported on the target.
@ WidenScalar
The operation should be implemented in terms of a wider scalar base-type.
This is an optimization pass for GlobalISel generic memory operations.