LLVM  12.0.0git
llvm::AMDGPURegisterBankInfo Member List

This is the complete list of members for llvm::AMDGPURegisterBankInfo, including all inherited members.

addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps >> Table) constllvm::AMDGPURegisterBankInfo
addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps >> Table) constllvm::AMDGPURegisterBankInfo
AMDGPURegisterBankInfo(const GCNSubtarget &STI)llvm::AMDGPURegisterBankInfo
applyDefaultMapping(const OperandsMapper &OpdMapper)llvm::RegisterBankInfostatic
applyMappingBFEIntrinsic(const OperandsMapper &OpdMapper, bool Signed) constllvm::AMDGPURegisterBankInfo
applyMappingDynStackAlloc(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) constllvm::AMDGPURegisterBankInfo
applyMappingImage(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI, int RSrcIdx) constllvm::AMDGPURegisterBankInfo
applyMappingImpl(const OperandsMapper &OpdMapper) const overridellvm::AMDGPURegisterBankInfovirtual
applyMappingLoad(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) constllvm::AMDGPURegisterBankInfo
applyMappingSBufferLoad(const OperandsMapper &OpdMapper) constllvm::AMDGPURegisterBankInfo
buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) constllvm::AMDGPURegisterBankInfo
cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) constllvm::RegisterBankInfoinline
collectWaterfallOperands(SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) constllvm::AMDGPURegisterBankInfo
constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)llvm::RegisterBankInfostatic
constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) constllvm::AMDGPURegisterBankInfo
copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const overridellvm::AMDGPURegisterBankInfovirtual
DefaultMappingIDllvm::RegisterBankInfostatic
executeInWaterfallLoop(MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs, MachineRegisterInfo &MRI) constllvm::AMDGPURegisterBankInfo
executeInWaterfallLoop(MachineIRBuilder &B, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) constllvm::AMDGPURegisterBankInfo
executeInWaterfallLoop(MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) constllvm::AMDGPURegisterBankInfo
getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) constllvm::AMDGPURegisterBankInfo
getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const overridellvm::AMDGPURegisterBankInfovirtual
getDefaultMappingAllVGPR(const MachineInstr &MI) constllvm::AMDGPURegisterBankInfo
getDefaultMappingSOP(const MachineInstr &MI) constllvm::AMDGPURegisterBankInfo
getDefaultMappingVOP(const MachineInstr &MI) constllvm::AMDGPURegisterBankInfo
getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) constllvm::AMDGPURegisterBankInfo
getInstrAlternativeMappings(const MachineInstr &MI) const overridellvm::AMDGPURegisterBankInfovirtual
getInstrAlternativeMappingsIntrinsic(const MachineInstr &MI, const MachineRegisterInfo &MRI) constllvm::AMDGPURegisterBankInfo
getInstrAlternativeMappingsIntrinsicWSideEffects(const MachineInstr &MI, const MachineRegisterInfo &MRI) constllvm::AMDGPURegisterBankInfo
getInstrMapping(const MachineInstr &MI) const overridellvm::AMDGPURegisterBankInfovirtual
getInstrMappingForLoad(const MachineInstr &MI) constllvm::AMDGPURegisterBankInfo
getInstrMappingImpl(const MachineInstr &MI) constllvm::RegisterBankInfoprotected
getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) constllvm::RegisterBankInfoinline
getInvalidInstructionMapping() constllvm::RegisterBankInfoinline
getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) constllvm::RegisterBankInfoprotected
getNumRegBanks() constllvm::RegisterBankInfoinline
getOperandsMapping(Iterator Begin, Iterator End) constllvm::RegisterBankInfoprotected
getOperandsMapping(const SmallVectorImpl< const ValueMapping *> &OpdsMapping) constllvm::RegisterBankInfoprotected
getOperandsMapping(std::initializer_list< const ValueMapping *> OpdsMapping) constllvm::RegisterBankInfoprotected
getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) constllvm::RegisterBankInfoprotected
getRegBank(unsigned ID)llvm::RegisterBankInfoinlineprotected
getRegBank(unsigned ID) constllvm::RegisterBankInfoinline
getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) constllvm::RegisterBankInfo
getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) constllvm::RegisterBankInfo
getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const overridellvm::AMDGPURegisterBankInfovirtual
getRegBankID(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, unsigned Default=AMDGPU::VGPRRegBankID) constllvm::AMDGPURegisterBankInfo
getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) constllvm::AMDGPURegisterBankInfo
getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) constllvm::RegisterBankInfoprotected
getValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) constllvm::RegisterBankInfoprotected
getValueMappingForPtr(const MachineRegisterInfo &MRI, Register Ptr) constllvm::AMDGPURegisterBankInfo
getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) constllvm::AMDGPURegisterBankInfo
handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) constllvm::AMDGPURegisterBankInfo
InstructionMappings typedefllvm::RegisterBankInfo
InvalidMappingIDllvm::RegisterBankInfostatic
isSALUMapping(const MachineInstr &MI) constllvm::AMDGPURegisterBankInfo
lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) constllvm::AMDGPURegisterBankInfo
MapOfInstructionMappingsllvm::RegisterBankInfomutableprotected
MapOfOperandsMappingsllvm::RegisterBankInfomutableprotected
MapOfPartialMappingsllvm::RegisterBankInfomutableprotected
MapOfValueMappingsllvm::RegisterBankInfomutableprotected
NumRegBanksllvm::RegisterBankInfoprotected
PhysRegMinimalRCsllvm::RegisterBankInfomutableprotected
RegBanksllvm::RegisterBankInfoprotected
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)llvm::RegisterBankInfoprotected
RegisterBankInfo()llvm::RegisterBankInfoinlineprotected
ScalarAddx2llvm::RegisterBankInfo
selectStoreIntrinsic(MachineIRBuilder &B, MachineInstr &MI) constllvm::AMDGPURegisterBankInfo
split64BitValueForMapping(MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) constllvm::AMDGPURegisterBankInfo
splitBufferOffsets(MachineIRBuilder &B, Register Offset) constllvm::AMDGPURegisterBankInfo
Subtargetllvm::AMDGPURegisterBankInfo
TIIllvm::AMDGPURegisterBankInfo
TRIllvm::AMDGPURegisterBankInfo
VectorAddllvm::RegisterBankInfo
~RegisterBankInfo()=defaultllvm::RegisterBankInfovirtual