LLVM 23.0.0git
WebAssemblyRegisterBankInfo.cpp
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1//===-- WebAssemblyRegisterBankInfo.cpp -------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the RegisterBankInfo class for
10/// WebAssembly.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
17
18#define GET_TARGET_REGBANK_IMPL
19
20#include "WebAssemblyGenRegisterBank.inc"
21
22namespace llvm {
23namespace WebAssembly {} // namespace WebAssembly
24} // namespace llvm
25
26using namespace llvm;
27
30
IRTranslator LLVM IR MI
Register const TargetRegisterInfo * TRI
This file provides WebAssembly-specific target descriptions.
This file declares the targeting of the RegisterBankInfo class for WebAssembly.
Representation of each machine instruction.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
WebAssemblyRegisterBankInfo(const TargetRegisterInfo &TRI)
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26