LLVM 19.0.0git
M68kRegisterBankInfo.cpp
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1//===-- M68kRegisterBankInfo.cpp --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the RegisterBankInfo class for M68k.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
14#include "M68kInstrInfo.h" // For the register classes
15#include "M68kSubtarget.h"
20
21#define GET_TARGET_REGBANK_IMPL
22#include "M68kGenRegisterBank.inc"
23
24using namespace llvm;
25
26// FIXME: TableGen this.
27// If it grows too much and TableGen still isn't ready to do the job, extract it
28// into an M68kGenRegisterBankInfo.def (similar to AArch64).
29namespace llvm {
30namespace M68k {
34};
35
37 // GPR Partial Mapping
38 {0, 32, GPRRegBank},
39};
40
44};
45
47 // invalid
48 {nullptr, 0},
49 // 3 operands in GPRs
53
54};
55} // end namespace M68k
56} // end namespace llvm
57
60
61const RegisterBank &
63 LLT) const {
64 return getRegBank(M68k::GPRRegBankID);
65}
66
69 auto Opc = MI.getOpcode();
70
71 if (!isPreISelGenericOpcode(Opc)) {
73 if (Mapping.isValid())
74 return Mapping;
75 }
76
77 using namespace TargetOpcode;
78
79 unsigned NumOperands = MI.getNumOperands();
80 const ValueMapping *OperandsMapping = &M68k::ValueMappings[M68k::GPR3OpsIdx];
81
82 switch (Opc) {
83 case G_ADD:
84 case G_SUB:
85 case G_MUL:
86 case G_SDIV:
87 case G_UDIV:
88 case G_LOAD:
89 case G_STORE: {
90 OperandsMapping = &M68k::ValueMappings[M68k::GPR3OpsIdx];
91 break;
92 }
93
94 case G_CONSTANT:
95 case G_FRAME_INDEX:
96 OperandsMapping =
98 break;
99 default:
101 }
102
103 return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
104 NumOperands);
105}
IRTranslator LLVM IR MI
This file contains the M68k implementation of the TargetInstrInfo class.
This file declares the targeting of the RegisterBankInfo class for M68k.
This file declares the M68k specific subclass of TargetSubtargetInfo.
unsigned const TargetRegisterInfo * TRI
M68kRegisterBankInfo(const TargetRegisterInfo &TRI)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Definition: RegisterBank.h:28
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const RegisterBankInfo::PartialMapping PartMappings[]
const RegisterBankInfo::ValueMapping ValueMappings[]
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.