LLVM 20.0.0git
|
#include "Target/SPIRV/SPIRVRegisterBankInfo.h"
Public Member Functions | |
const RegisterBank & | getRegBankFromRegClass (const TargetRegisterClass &RC, LLT Ty) const override |
Get a register bank that covers RC . | |
Public Member Functions inherited from llvm::RegisterBankInfo | |
const RegisterBank * | getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const |
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any. | |
virtual void | applyMappingImpl (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const |
See applyMapping. | |
virtual | ~RegisterBankInfo ()=default |
const RegisterBank & | getRegBank (unsigned ID) const |
Get the register bank identified by ID . | |
unsigned | getMaximumSize (unsigned RegBankID) const |
Get the maximum size in bits that fits in the given register bank. | |
const RegisterBank * | getRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const |
Get the register bank of Reg . | |
unsigned | getNumRegBanks () const |
Get the total number of register banks. | |
virtual bool | isDivergentRegBank (const RegisterBank *RB) const |
Returns true if the register bank is considered divergent. | |
virtual const RegisterBank & | getRegBankFromRegClass (const TargetRegisterClass &RC, LLT Ty) const |
Get a register bank that covers RC . | |
virtual unsigned | copyCost (const RegisterBank &A, const RegisterBank &B, TypeSize Size) const |
Get the cost of a copy from B to A , or put differently, get the cost of A = COPY B. | |
bool | cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const |
virtual unsigned | getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const |
Get the cost of using ValMapping to decompose a register. | |
virtual const InstructionMapping & | getInstrMapping (const MachineInstr &MI) const |
Get the mapping of the different operands of MI on the register bank. | |
virtual InstructionMappings | getInstrAlternativeMappings (const MachineInstr &MI) const |
Get the alternative mappings for MI . | |
InstructionMappings | getInstrPossibleMappings (const MachineInstr &MI) const |
Get the possible mapping for MI . | |
void | applyMapping (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const |
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI() . | |
TypeSize | getSizeInBits (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const |
Get the size in bits of Reg . | |
bool | verify (const TargetRegisterInfo &TRI) const |
Check that information hold by this instance make sense for the given TRI . | |
const InstructionMapping & | getInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const |
Method to get a uniquely generated InstructionMapping. | |
const InstructionMapping & | getInvalidInstructionMapping () const |
Method to get a uniquely generated invalid InstructionMapping. | |
Additional Inherited Members | |
Public Types inherited from llvm::RegisterBankInfo | |
using | InstructionMappings = SmallVector< const InstructionMapping *, 4 > |
Convenient type to represent the alternatives for mapping an instruction. | |
Static Public Member Functions inherited from llvm::RegisterBankInfo | |
static void | applyDefaultMapping (const OperandsMapper &OpdMapper) |
Helper method to apply something that is like the default mapping. | |
static const TargetRegisterClass * | constrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) |
Constrain the (possibly generic) virtual register Reg to RC . | |
Static Public Attributes inherited from llvm::RegisterBankInfo | |
static const unsigned | DefaultMappingID = UINT_MAX |
Identifier used when the related instruction mapping instance is generated by target independent code. | |
static const unsigned | InvalidMappingID = UINT_MAX - 1 |
Identifier used when the related instruction mapping instance is generated by the default constructor. | |
Protected Member Functions inherited from llvm::RegisterBankInfo | |
RegisterBankInfo (const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode) | |
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. | |
RegisterBankInfo () | |
This constructor is meaningless. | |
const RegisterBank & | getRegBank (unsigned ID) |
Get the register bank identified by ID . | |
const TargetRegisterClass * | getMinimalPhysRegClass (Register Reg, const TargetRegisterInfo &TRI) const |
Get the MinimalPhysRegClass for Reg. | |
const InstructionMapping & | getInstrMappingImpl (const MachineInstr &MI) const |
Try to get the mapping of MI . | |
const PartialMapping & | getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
Get the uniquely generated PartialMapping for the given arguments. | |
const ValueMapping & | getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
The most common ValueMapping consists of a single PartialMapping. | |
const ValueMapping & | getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const |
Get the ValueMapping for the given arguments. | |
template<typename Iterator > | |
const ValueMapping * | getOperandsMapping (Iterator Begin, Iterator End) const |
Get the uniquely generated array of ValueMapping for the elements of between Begin and End . | |
const ValueMapping * | getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const |
Get the uniquely generated array of ValueMapping for the elements of OpdsMapping . | |
const ValueMapping * | getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const |
Get the uniquely generated array of ValueMapping for the given arguments. | |
Protected Attributes inherited from llvm::RegisterBankInfo | |
const RegisterBank ** | RegBanks |
Hold the set of supported register banks. | |
unsigned | NumRegBanks |
Total number of register banks. | |
const unsigned * | Sizes |
Hold the sizes of the register banks for all HwModes. | |
unsigned | HwMode |
Current HwMode for the target. | |
DenseMap< hash_code, std::unique_ptr< const PartialMapping > > | MapOfPartialMappings |
Keep dynamically allocated PartialMapping in a separate map. | |
DenseMap< hash_code, std::unique_ptr< const ValueMapping > > | MapOfValueMappings |
Keep dynamically allocated ValueMapping in a separate map. | |
DenseMap< hash_code, std::unique_ptr< ValueMapping[]> > | MapOfOperandsMappings |
Keep dynamically allocated array of ValueMapping in a separate map. | |
DenseMap< hash_code, std::unique_ptr< const InstructionMapping > > | MapOfInstructionMappings |
Keep dynamically allocated InstructionMapping in a separate map. | |
DenseMap< unsigned, const TargetRegisterClass * > | PhysRegMinimalRCs |
Getting the minimal register class of a physreg is expensive. | |
Definition at line 32 of file SPIRVRegisterBankInfo.h.
|
overridevirtual |
Get a register bank that covers RC
.
RC
is a user-defined register class (as opposed as one generated by TableGen).Reimplemented from llvm::RegisterBankInfo.
Definition at line 29 of file SPIRVRegisterBankInfo.cpp.
References llvm::TargetRegisterClass::getID().