LLVM  14.0.0git
GCNHazardRecognizer.h
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1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines hazard recognizers for scheduling on GCN processors.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
14 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
15 
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/STLExtras.h"
20 #include <list>
21 
22 namespace llvm {
23 
24 class MachineFunction;
25 class MachineInstr;
26 class MachineOperand;
27 class MachineRegisterInfo;
28 class ScheduleDAG;
29 class SIInstrInfo;
30 class SIRegisterInfo;
31 class GCNSubtarget;
32 
34 public:
35  typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
36 
37 private:
38  // Distinguish if we are called from scheduler or hazard recognizer
39  bool IsHazardRecognizerMode;
40 
41  // This variable stores the instruction that has been emitted this cycle. It
42  // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
43  // called.
44  MachineInstr *CurrCycleInstr;
45  std::list<MachineInstr*> EmittedInstrs;
46  const MachineFunction &MF;
47  const GCNSubtarget &ST;
48  const SIInstrInfo &TII;
49  const SIRegisterInfo &TRI;
50  TargetSchedModel TSchedModel;
51  bool RunLdsBranchVmemWARHazardFixup;
52 
53  /// RegUnits of uses in the current soft memory clause.
54  BitVector ClauseUses;
55 
56  /// RegUnits of defs in the current soft memory clause.
57  BitVector ClauseDefs;
58 
59  void resetClause() {
60  ClauseUses.reset();
61  ClauseDefs.reset();
62  }
63 
64  void addClauseInst(const MachineInstr &MI);
65 
66  // Advance over a MachineInstr bundle. Look for hazards in the bundled
67  // instructions.
68  void processBundle();
69 
70  int getWaitStatesSince(IsHazardFn IsHazard, int Limit);
71  int getWaitStatesSinceDef(unsigned Reg, IsHazardFn IsHazardDef, int Limit);
72  int getWaitStatesSinceSetReg(IsHazardFn IsHazard, int Limit);
73 
74  int checkSoftClauseHazards(MachineInstr *SMEM);
75  int checkSMRDHazards(MachineInstr *SMRD);
76  int checkVMEMHazards(MachineInstr* VMEM);
77  int checkDPPHazards(MachineInstr *DPP);
78  int checkDivFMasHazards(MachineInstr *DivFMas);
79  int checkGetRegHazards(MachineInstr *GetRegInstr);
80  int checkSetRegHazards(MachineInstr *SetRegInstr);
81  int createsVALUHazard(const MachineInstr &MI);
82  int checkVALUHazards(MachineInstr *VALU);
83  int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
84  int checkRWLaneHazards(MachineInstr *RWLane);
85  int checkRFEHazards(MachineInstr *RFE);
86  int checkInlineAsmHazards(MachineInstr *IA);
87  int checkReadM0Hazards(MachineInstr *SMovRel);
88  int checkNSAtoVMEMHazard(MachineInstr *MI);
89  int checkFPAtomicToDenormModeHazard(MachineInstr *MI);
90  void fixHazards(MachineInstr *MI);
91  bool fixVcmpxPermlaneHazards(MachineInstr *MI);
92  bool fixVMEMtoScalarWriteHazards(MachineInstr *MI);
93  bool fixSMEMtoVectorWriteHazards(MachineInstr *MI);
94  bool fixVcmpxExecWARHazard(MachineInstr *MI);
95  bool fixLdsBranchVmemWARHazard(MachineInstr *MI);
96 
97  int checkMAIHazards(MachineInstr *MI);
98  int checkMAIHazards908(MachineInstr *MI);
99  int checkMAIHazards90A(MachineInstr *MI);
100  int checkMAIVALUHazards(MachineInstr *MI);
101  int checkMAILdStHazards(MachineInstr *MI);
102 
103 public:
105  // We can only issue one instruction per cycle.
106  bool atIssueLimit() const override { return true; }
107  void EmitInstruction(SUnit *SU) override;
108  void EmitInstruction(MachineInstr *MI) override;
109  HazardType getHazardType(SUnit *SU, int Stalls) override;
110  void EmitNoop() override;
111  unsigned PreEmitNoops(MachineInstr *) override;
112  unsigned PreEmitNoopsCommon(MachineInstr *);
113  void AdvanceCycle() override;
114  void RecedeCycle() override;
115  bool ShouldPreferAnother(SUnit *SU) override;
116  void Reset() override;
117 };
118 
119 } // end namespace llvm
120 
121 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::GCNHazardRecognizer::getHazardType
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
Definition: GCNHazardRecognizer.cpp:152
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::GCNHazardRecognizer::GCNHazardRecognizer
GCNHazardRecognizer(const MachineFunction &MF)
Definition: GCNHazardRecognizer.cpp:29
llvm::GCNHazardRecognizer::atIssueLimit
bool atIssueLimit() const override
atIssueLimit - Return true if no more instructions may be issued in this cycle.
Definition: GCNHazardRecognizer.h:106
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
STLExtras.h
ScheduleHazardRecognizer.h
llvm::SIInstrFlags::DPP
@ DPP
Definition: SIDefines.h:49
llvm::GCNHazardRecognizer
Definition: GCNHazardRecognizer.h:33
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
BitVector.h
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:74
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:168
llvm::ScheduleHazardRecognizer::HazardType
HazardType
Definition: ScheduleHazardRecognizer.h:37
TargetSchedule.h
llvm::SIInstrFlags::VALU
@ VALU
Definition: SIDefines.h:29
llvm::GCNHazardRecognizer::PreEmitNoopsCommon
unsigned PreEmitNoopsCommon(MachineInstr *)
Definition: GCNHazardRecognizer.cpp:273
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::GCNHazardRecognizer::PreEmitNoops
unsigned PreEmitNoops(MachineInstr *) override
This overload will be used when the hazard recognizer is being used by a non-scheduling pass,...
Definition: GCNHazardRecognizer.cpp:264
llvm::GCNHazardRecognizer::EmitInstruction
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
Definition: GCNHazardRecognizer.cpp:47
llvm::GCNHazardRecognizer::EmitNoop
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
Definition: GCNHazardRecognizer.cpp:340
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::GCNHazardRecognizer::Reset
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
Definition: GCNHazardRecognizer.cpp:43
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:55
llvm::GCNHazardRecognizer::RecedeCycle
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
Definition: GCNHazardRecognizer.cpp:382
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:384
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::GCNHazardRecognizer::AdvanceCycle
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
Definition: GCNHazardRecognizer.cpp:344
llvm::GCNHazardRecognizer::ShouldPreferAnother
bool ShouldPreferAnother(SUnit *SU) override
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
Definition: GCNHazardRecognizer.cpp:1824
llvm::GCNHazardRecognizer::IsHazardFn
function_ref< bool(const MachineInstr &)> IsHazardFn
Definition: GCNHazardRecognizer.h:35
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25