LLVM  14.0.0git
CSKYMCCodeEmitter.cpp
Go to the documentation of this file.
1 //===-- CSKYMCCodeEmitter.cpp - CSKY Code Emitter interface ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the CSKYMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "CSKYMCCodeEmitter.h"
14 #include "CSKYMCExpr.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCInstBuilder.h"
18 #include "llvm/MC/MCInstrInfo.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "csky-mccode-emitter"
24 
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
26 
27 unsigned CSKYMCCodeEmitter::getOImmOpValue(const MCInst &MI, unsigned Idx,
29  const MCSubtargetInfo &STI) const {
30  const MCOperand &MO = MI.getOperand(Idx);
31  assert(MO.isImm() && "Unexpected MO type.");
32  return MO.getImm() - 1;
33 }
34 
35 unsigned
38  const MCSubtargetInfo &STI) const {
39  const MCOperand &MO = MI.getOperand(Idx);
40  assert(MO.isImm() && "Unexpected MO type.");
41 
42  auto V = (MO.getImm() <= 3) ? 4 : MO.getImm();
43  return V - 1;
44 }
45 
46 unsigned
49  const MCSubtargetInfo &STI) const {
50  const MCOperand &MSB = MI.getOperand(Idx);
51  const MCOperand &LSB = MI.getOperand(Idx + 1);
52  assert(MSB.isImm() && LSB.isImm() && "Unexpected MO type.");
53 
54  return MSB.getImm() - LSB.getImm();
55 }
56 
57 static void writeData(uint32_t Bin, unsigned Size, raw_ostream &OS) {
58  uint16_t LO16 = static_cast<uint16_t>(Bin);
59  uint16_t HI16 = static_cast<uint16_t>(Bin >> 16);
60 
61  if (Size == 4)
62  support::endian::write<uint16_t>(OS, HI16, support::little);
63 
64  support::endian::write<uint16_t>(OS, LO16, support::little);
65 }
66 
69  const MCSubtargetInfo &STI) const {
70  const MCInstrDesc &Desc = MII.get(MI.getOpcode());
71  unsigned Size = Desc.getSize();
72 
73  ++MCNumEmitted;
74 
76 
77  uint16_t LO16 = static_cast<uint16_t>(Bin);
78  uint16_t HI16 = static_cast<uint16_t>(Bin >> 16);
79 
80  if (Size == 4)
81  support::endian::write<uint16_t>(OS, HI16, support::little);
82 
83  support::endian::write<uint16_t>(OS, LO16, support::little);
84 }
85 
86 unsigned
89  const MCSubtargetInfo &STI) const {
90  if (MO.isReg())
91  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
92 
93  if (MO.isImm())
94  return static_cast<unsigned>(MO.getImm());
95 
96  llvm_unreachable("Unhandled expression!");
97  return 0;
98 }
99 
100 unsigned
103  const MCSubtargetInfo &STI) const {
104  assert(MI.getOperand(Idx).isReg() && "Unexpected MO type.");
105  assert(MI.getOperand(Idx + 1).isImm() && "Unexpected MO type.");
106 
107  unsigned Ry = MI.getOperand(Idx).getReg();
108  unsigned Rz = MI.getOperand(Idx + 1).getImm();
109 
110  unsigned Imm = Ctx.getRegisterInfo()->getEncodingValue(Rz) -
112 
113  return ((Ctx.getRegisterInfo()->getEncodingValue(Ry) << 5) | Imm);
114 }
115 
116 unsigned
119  const MCSubtargetInfo &STI) const {
120  unsigned Reg1 =
121  Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(Op).getReg());
122  unsigned Reg2 =
123  Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(Op + 1).getReg());
124 
125  unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1);
126 
127  return Binary;
128 }
129 
130 unsigned CSKYMCCodeEmitter::getImmJMPIX(const MCInst &MI, unsigned Idx,
132  const MCSubtargetInfo &STI) const {
133  if (MI.getOperand(Idx).getImm() == 16)
134  return 0;
135  else if (MI.getOperand(Idx).getImm() == 24)
136  return 1;
137  else if (MI.getOperand(Idx).getImm() == 32)
138  return 2;
139  else if (MI.getOperand(Idx).getImm() == 40)
140  return 3;
141  else
142  assert(0);
143 }
144 
146  const CSKYMCExpr *CSKYExpr = cast<CSKYMCExpr>(Expr);
147 
148  switch (CSKYExpr->getKind()) {
149  default:
150  llvm_unreachable("Unhandled fixup kind!");
169  }
170 }
171 
173  const MCRegisterInfo &MRI,
174  MCContext &Ctx) {
175  return new CSKYMCCodeEmitter(Ctx, MCII);
176 }
177 
178 #include "CSKYGenMCCodeEmitter.inc"
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CSKYMCExpr::VK_CSKY_GOTOFF
@ VK_CSKY_GOTOFF
Definition: CSKYMCExpr.h:28
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::CSKYMCExpr::VK_CSKY_GOTPC
@ VK_CSKY_GOTPC
Definition: CSKYMCExpr.h:27
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:425
Statistic.h
llvm::createCSKYMCCodeEmitter
MCCodeEmitter * createCSKYMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: CSKYMCCodeEmitter.cpp:172
MCInstBuilder.h
llvm::CSKY::fixup_csky_gotpc
@ fixup_csky_gotpc
Definition: CSKYFixupKinds.h:31
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
llvm::CSKY::fixup_csky_got32
@ fixup_csky_got32
Definition: CSKYFixupKinds.h:35
llvm::CSKYMCExpr::VK_CSKY_GOT
@ VK_CSKY_GOT
Definition: CSKYMCExpr.h:25
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::CSKY::fixup_csky_got_imm18_scale4
@ fixup_csky_got_imm18_scale4
Definition: CSKYFixupKinds.h:37
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:616
llvm::CSKYMCExpr::VK_CSKY_ADDR_HI16
@ VK_CSKY_ADDR_HI16
Definition: CSKYMCExpr.h:22
llvm::CSKYMCCodeEmitter::getBinaryCodeForInstr
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
llvm::CSKY::fixup_csky_plt32
@ fixup_csky_plt32
Definition: CSKYFixupKinds.h:39
llvm::support::little
@ little
Definition: Endian.h:27
llvm::CSKYMCExpr::VK_CSKY_ADDR
@ VK_CSKY_ADDR
Definition: CSKYMCExpr.h:21
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::CSKYMCExpr::getKind
VariantKind getKind() const
Definition: CSKYMCExpr.h:51
llvm::CSKYMCCodeEmitter::getRegSeqImmOpValue
unsigned getRegSeqImmOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: CSKYMCCodeEmitter.cpp:101
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::CSKYMCExpr::VK_CSKY_PLT
@ VK_CSKY_PLT
Definition: CSKYMCExpr.h:29
llvm::CSKYMCCodeEmitter::getOImmOpValue
unsigned getOImmOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: CSKYMCCodeEmitter.cpp:27
CSKYMCCodeEmitter.h
llvm::CSKY::fixup_csky_addr_lo16
@ fixup_csky_addr_lo16
Definition: CSKYFixupKinds.h:21
llvm::CSKYMCExpr::VK_CSKY_ADDR_LO16
@ VK_CSKY_ADDR_LO16
Definition: CSKYMCExpr.h:23
llvm::CSKYMCCodeEmitter::getTargetFixup
MCFixupKind getTargetFixup(const MCExpr *Expr) const
Definition: CSKYMCCodeEmitter.cpp:145
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::CSKYMCExpr
Definition: CSKYMCExpr.h:17
llvm::CSKYMCCodeEmitter::encodeInstruction
void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Definition: CSKYMCCodeEmitter.cpp:67
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::CSKYMCCodeEmitter
Definition: CSKYMCCodeEmitter.h:23
llvm::CSKY::fixup_csky_addr_hi16
@ fixup_csky_addr_hi16
Definition: CSKYFixupKinds.h:19
CSKYMCTargetDesc.h
llvm::CSKYMCCodeEmitter::getImmJMPIX
unsigned getImmJMPIX(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: CSKYMCCodeEmitter.cpp:130
llvm::CSKYMCCodeEmitter::getRegisterSeqOpValue
unsigned getRegisterSeqOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: CSKYMCCodeEmitter.cpp:117
llvm::CSKY::fixup_csky_gotoff
@ fixup_csky_gotoff
Definition: CSKYFixupKinds.h:33
llvm::CSKY::fixup_csky_plt_imm18_scale4
@ fixup_csky_plt_imm18_scale4
Definition: CSKYFixupKinds.h:41
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
writeData
static void writeData(uint32_t Bin, unsigned Size, raw_ostream &OS)
Definition: CSKYMCCodeEmitter.cpp:57
uint32_t
llvm::CSKYMCExpr::VK_CSKY_PLT_IMM18_BY4
@ VK_CSKY_PLT_IMM18_BY4
Definition: CSKYMCExpr.h:30
llvm::CSKYMCCodeEmitter::getImmOpValueIDLY
unsigned getImmOpValueIDLY(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: CSKYMCCodeEmitter.cpp:36
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::CSKYMCExpr::VK_CSKY_GOT_IMM18_BY4
@ VK_CSKY_GOT_IMM18_BY4
Definition: CSKYMCExpr.h:26
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
EndianStream.h
uint16_t
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::CSKYMCCodeEmitter::getImmOpValueMSBSize
unsigned getImmOpValueMSBSize(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: CSKYMCCodeEmitter.cpp:47
CSKYMCExpr.h
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::CSKY::fixup_csky_addr32
@ fixup_csky_addr32
Definition: CSKYFixupKinds.h:17
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::CSKYMCCodeEmitter::getMachineOpValue
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: CSKYMCCodeEmitter.cpp:87
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69