LLVM 17.0.0git
CSKYMCCodeEmitter.h
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1//===-- CSKYMCCodeEmitter.cpp - CSKY Code Emitter interface ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the CSKYMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
14#define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
15
19#include "llvm/MC/MCContext.h"
20
21namespace llvm {
22
23class MCInstrInfo;
24
26 MCContext &Ctx;
27 const MCInstrInfo &MII;
28
29public:
31 : Ctx(Ctx), MII(MII) {}
32
34
35 void encodeInstruction(const MCInst &Inst, raw_ostream &OS,
37 const MCSubtargetInfo &STI) const override;
38
39 // Generated by tablegen.
42 const MCSubtargetInfo &STI) const;
43
44 // Default encoding method used by tablegen.
45 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
47 const MCSubtargetInfo &STI) const;
48
49 template <int shift = 0>
50 unsigned getImmOpValue(const MCInst &MI, unsigned Idx,
52 const MCSubtargetInfo &STI) const {
53 const MCOperand &MO = MI.getOperand(Idx);
54 if (MO.isImm())
55 return (MO.getImm() >> shift);
56
57 assert(MO.isExpr() && "Unexpected MO type.");
58
60 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
61 return 0;
62 }
63
64 unsigned getRegSeqImmOpValue(const MCInst &MI, unsigned Idx,
66 const MCSubtargetInfo &STI) const;
67
68 unsigned getRegisterSeqOpValue(const MCInst &MI, unsigned Op,
70 const MCSubtargetInfo &STI) const;
71
72 unsigned getOImmOpValue(const MCInst &MI, unsigned Idx,
74 const MCSubtargetInfo &STI) const;
75
76 unsigned getImmOpValueIDLY(const MCInst &MI, unsigned Idx,
78 const MCSubtargetInfo &STI) const;
79
80 unsigned getImmJMPIX(const MCInst &MI, unsigned Idx,
82 const MCSubtargetInfo &STI) const;
83
84 unsigned getImmOpValueMSBSize(const MCInst &MI, unsigned Idx,
86 const MCSubtargetInfo &STI) const;
87
88 unsigned getImmShiftOpValue(const MCInst &MI, unsigned Idx,
90 const MCSubtargetInfo &STI) const {
91 const MCOperand &MO = MI.getOperand(Idx);
92 assert(MO.isImm() && "Unexpected MO type.");
93 return 1 << MO.getImm();
94 }
95
96 MCFixupKind getTargetFixup(const MCExpr *Expr) const;
97
98 template <llvm::CSKY::Fixups FIXUP>
99 unsigned getBranchSymbolOpValue(const MCInst &MI, unsigned Idx,
101 const MCSubtargetInfo &STI) const {
102 const MCOperand &MO = MI.getOperand(Idx);
103
104 if (MO.isImm())
105 return MO.getImm() >> 1;
106
107 assert(MO.isExpr() && "Unexpected MO type.");
108
109 MCFixupKind Kind = MCFixupKind(FIXUP);
110 if (MO.getExpr()->getKind() == MCExpr::Target)
111 Kind = getTargetFixup(MO.getExpr());
112
113 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
114 return 0;
115 }
116
117 template <llvm::CSKY::Fixups FIXUP>
118 unsigned getConstpoolSymbolOpValue(const MCInst &MI, unsigned Idx,
120 const MCSubtargetInfo &STI) const {
121 const MCOperand &MO = MI.getOperand(Idx);
122 assert(MO.isExpr() && "Unexpected MO type.");
123
124 MCFixupKind Kind = MCFixupKind(FIXUP);
125 if (MO.getExpr()->getKind() == MCExpr::Target)
126 Kind = getTargetFixup(MO.getExpr());
127
128 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
129 return 0;
130 }
131
132 template <llvm::CSKY::Fixups FIXUP>
133 unsigned getDataSymbolOpValue(const MCInst &MI, unsigned Idx,
135 const MCSubtargetInfo &STI) const {
136 const MCOperand &MO = MI.getOperand(Idx);
137 assert(MO.isExpr() && "Unexpected MO type.");
138
139 MCFixupKind Kind = MCFixupKind(FIXUP);
140 if (MO.getExpr()->getKind() == MCExpr::Target)
141 Kind = getTargetFixup(MO.getExpr());
142
143 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
144 return 0;
145 }
146
147 unsigned getCallSymbolOpValue(const MCInst &MI, unsigned Idx,
149 const MCSubtargetInfo &STI) const {
150 const MCOperand &MO = MI.getOperand(Idx);
151 assert(MO.isExpr() && "Unexpected MO type.");
152
154 if (MO.getExpr()->getKind() == MCExpr::Target)
155 Kind = getTargetFixup(MO.getExpr());
156
157 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
158 return 0;
159 }
160
161 unsigned getBareSymbolOpValue(const MCInst &MI, unsigned Idx,
163 const MCSubtargetInfo &STI) const {
164 const MCOperand &MO = MI.getOperand(Idx);
165 assert(MO.isExpr() && "Unexpected MO type.");
166
168 if (MO.getExpr()->getKind() == MCExpr::Target)
169 Kind = getTargetFixup(MO.getExpr());
170
171 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
172 return 0;
173 }
174
175 void expandJBTF(const MCInst &MI, raw_ostream &OS,
177 const MCSubtargetInfo &STI) const;
178 void expandNEG(const MCInst &MI, raw_ostream &OS,
180 const MCSubtargetInfo &STI) const;
181 void expandRSUBI(const MCInst &MI, raw_ostream &OS,
183 const MCSubtargetInfo &STI) const;
184};
185
186} // namespace llvm
187
188#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
unsigned getRegisterSeqOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getCallSymbolOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getOImmOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImmOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getConstpoolSymbolOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void expandJBTF(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getDataSymbolOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImmOpValueMSBSize(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImmShiftOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
CSKYMCCodeEmitter(MCContext &Ctx, const MCInstrInfo &MII)
void expandRSUBI(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
MCFixupKind getTargetFixup(const MCExpr *Expr) const
unsigned getRegSeqImmOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImmOpValueIDLY(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBareSymbolOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImmJMPIX(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchSymbolOpValue(const MCInst &MI, unsigned Idx, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void expandNEG(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ Target
Target specific expression.
Definition: MCExpr.h:42
ExprKind getKind() const
Definition: MCExpr.h:81
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ fixup_csky_pcrel_imm18_scale2
@ fixup_csky_pcrel_imm26_scale2
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21