LLVM  14.0.0git
Context.cpp
Go to the documentation of this file.
1 //===---------------------------- Context.cpp -------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines a class for holding ownership of various simulated
11 /// hardware units. A Context also provides a utility routine for constructing
12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13 /// stages.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #include "llvm/MCA/Context.h"
27 
28 namespace llvm {
29 namespace mca {
30 
31 std::unique_ptr<Pipeline>
33  CustomBehaviour &CB) {
34  const MCSchedModel &SM = STI.getSchedModel();
35 
36  if (!SM.isOutOfOrder())
37  return createInOrderPipeline(Opts, SrcMgr, CB);
38 
39  // Create the hardware units defining the backend.
40  auto RCU = std::make_unique<RetireControlUnit>(SM);
41  auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
42  auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
43  Opts.StoreQueueSize, Opts.AssumeNoAlias);
44  auto HWS = std::make_unique<Scheduler>(SM, *LSU);
45 
46  // Create the pipeline stages.
47  auto Fetch = std::make_unique<EntryStage>(SrcMgr);
48  auto Dispatch =
49  std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF);
50  auto Execute =
51  std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
52  auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
53 
54  // Pass the ownership of all the hardware units to this Context.
59 
60  // Build the pipeline.
61  auto StagePipeline = std::make_unique<Pipeline>();
62  StagePipeline->appendStage(std::move(Fetch));
63  if (Opts.MicroOpQueueSize)
64  StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>(
66  StagePipeline->appendStage(std::move(Dispatch));
67  StagePipeline->appendStage(std::move(Execute));
68  StagePipeline->appendStage(std::move(Retire));
69  return StagePipeline;
70 }
71 
72 std::unique_ptr<Pipeline>
74  CustomBehaviour &CB) {
75  const MCSchedModel &SM = STI.getSchedModel();
76  auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
77  auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
78  Opts.StoreQueueSize, Opts.AssumeNoAlias);
79 
80  // Create the pipeline stages.
81  auto Entry = std::make_unique<EntryStage>(SrcMgr);
82  auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU);
83  auto StagePipeline = std::make_unique<Pipeline>();
84 
85  // Pass the ownership of all the hardware units to this Context.
88 
89  // Build the pipeline.
90  StagePipeline->appendStage(std::move(Entry));
91  StagePipeline->appendStage(std::move(InOrderIssue));
92  return StagePipeline;
93 }
94 
95 } // namespace mca
96 } // namespace llvm
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::mca::PipelineOptions::StoreQueueSize
unsigned StoreQueueSize
Definition: Context.h:46
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:162
RetireControlUnit.h
llvm::MCSchedModel::isOutOfOrder
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:333
RetireStage.h
llvm::mca::PipelineOptions::MicroOpQueueSize
unsigned MicroOpQueueSize
Definition: Context.h:41
llvm::mca::PipelineOptions::LoadQueueSize
unsigned LoadQueueSize
Definition: Context.h:45
DispatchStage.h
llvm::SrcMgr
SourceMgr SrcMgr
Definition: Error.cpp:24
llvm::mca::PipelineOptions
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...
Definition: Context.h:33
llvm::mca::PipelineOptions::RegisterFileSize
unsigned RegisterFileSize
Definition: Context.h:44
InOrderIssueStage.h
MicroOpQueueStage.h
llvm::mca::CustomBehaviour
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
Definition: CustomBehaviour.h:56
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::mca::Context::createDefaultPipeline
std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an out-of-order pipeline.
Definition: Context.cpp:32
Scheduler.h
llvm::mca::Context::createInOrderPipeline
std::unique_ptr< Pipeline > createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an in-order pipeline.
Definition: Context.cpp:73
llvm::mca::PipelineOptions::AssumeNoAlias
bool AssumeNoAlias
Definition: Context.h:47
llvm::mca::PipelineOptions::DecodersThroughput
unsigned DecodersThroughput
Definition: Context.h:42
ExecuteStage.h
llvm::mca::SourceMgr
Definition: SourceMgr.h:28
llvm::mca::Context::addHardwareUnit
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
Definition: Context.h:64
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::mca::PipelineOptions::DispatchWidth
unsigned DispatchWidth
Definition: Context.h:43
EntryStage.h
RegisterFile.h
llvm::mca::PipelineOptions::EnableBottleneckAnalysis
bool EnableBottleneckAnalysis
Definition: Context.h:48
Context.h