30 std::unique_ptr<Pipeline>
35 auto RCU = std::make_unique<RetireControlUnit>(SM);
39 auto HWS = std::make_unique<Scheduler>(SM, *LSU);
42 auto Fetch = std::make_unique<EntryStage>(
SrcMgr);
43 auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.
DispatchWidth,
47 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
56 auto StagePipeline = std::make_unique<Pipeline>();
57 StagePipeline->appendStage(
std::move(Fetch));
59 StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>(
61 StagePipeline->appendStage(
std::move(Dispatch));
62 StagePipeline->appendStage(
std::move(Execute));
63 StagePipeline->appendStage(
std::move(Retire));
This file defines the retire stage of a default instruction pipeline.
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr)
Construct a basic pipeline for simulating an out-of-order pipeline.
This class represents lattice values for constants.
This file simulates the hardware responsible for retiring instructions.
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...
This file defines the execution stage of a default instruction pipeline.
unsigned MicroOpQueueSize
unsigned DecodersThroughput
This file defines a class for holding ownership of various simulated hardware units.
unsigned RegisterFileSize
This file defines the Entry stage of an instruction pipeline.
This file defines a register mapping file class.
This file defines a stage that implements a queue of micro opcodes.
This file models the dispatch component of an instruction pipeline.
A scheduler for Processor Resource Units and Processor Resource Groups.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool EnableBottleneckAnalysis
Machine model for scheduling, bundling, and heuristics.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.