LLVM  13.0.0git
Context.h
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1 //===---------------------------- Context.h ---------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file defines a class for holding ownership of various simulated
11 /// hardware units. A Context also provides a utility routine for constructing
12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13 /// stages.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_MCA_CONTEXT_H
18 #define LLVM_MCA_CONTEXT_H
19 
20 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MCA/Pipeline.h"
24 #include "llvm/MCA/SourceMgr.h"
25 #include <memory>
26 
27 namespace llvm {
28 namespace mca {
29 
30 /// This is a convenience struct to hold the parameters necessary for creating
31 /// the pre-built "default" out-of-order pipeline.
33  PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
34  unsigned LQS, unsigned SQS, bool NoAlias,
35  bool ShouldEnableBottleneckAnalysis = false)
36  : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
39  EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
40  unsigned MicroOpQueueSize;
41  unsigned DecodersThroughput; // Instructions per cycle.
42  unsigned DispatchWidth;
43  unsigned RegisterFileSize;
44  unsigned LoadQueueSize;
45  unsigned StoreQueueSize;
48 };
49 
50 class Context {
52  const MCRegisterInfo &MRI;
53  const MCSubtargetInfo &STI;
54 
55 public:
56  Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
57  Context(const Context &C) = delete;
58  Context &operator=(const Context &C) = delete;
59 
60  const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
61  const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
62 
63  void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
64  Hardware.push_back(std::move(H));
65  }
66 
67  /// Construct a basic pipeline for simulating an out-of-order pipeline.
68  /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
69  std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
70  SourceMgr &SrcMgr);
71 
72  /// Construct a basic pipeline for simulating an in-order pipeline.
73  /// This pipeline consists of Fetch, InOrderIssue, and Retire stages.
74  std::unique_ptr<Pipeline> createInOrderPipeline(const PipelineOptions &Opts,
75  SourceMgr &SrcMgr);
76 };
77 
78 } // namespace mca
79 } // namespace llvm
80 #endif // LLVM_MCA_CONTEXT_H
llvm::mca::Context::createDefaultPipeline
std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr)
Construct a basic pipeline for simulating an out-of-order pipeline.
Definition: Context.cpp:32
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::mca::PipelineOptions::StoreQueueSize
unsigned StoreQueueSize
Definition: Context.h:45
llvm::NoAlias
@ NoAlias
The two locations do not alias at all.
Definition: AliasAnalysis.h:87
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Pipeline.h
llvm::mca::PipelineOptions::MicroOpQueueSize
unsigned MicroOpQueueSize
Definition: Context.h:40
llvm::mca::Context::createInOrderPipeline
std::unique_ptr< Pipeline > createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr)
Construct a basic pipeline for simulating an in-order pipeline.
Definition: Context.cpp:72
llvm::mca::PipelineOptions::LoadQueueSize
unsigned LoadQueueSize
Definition: Context.h:44
llvm::mca::Context::getMCRegisterInfo
const MCRegisterInfo & getMCRegisterInfo() const
Definition: Context.h:60
SourceMgr.h
llvm::mca::PipelineOptions::PipelineOptions
PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS, bool NoAlias, bool ShouldEnableBottleneckAnalysis=false)
Definition: Context.h:33
llvm::mca::Context::Context
Context(const MCRegisterInfo &R, const MCSubtargetInfo &S)
Definition: Context.h:56
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SrcMgr
SourceMgr SrcMgr
Definition: Error.cpp:24
llvm::mca::PipelineOptions
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...
Definition: Context.h:32
llvm::mca::PipelineOptions::RegisterFileSize
unsigned RegisterFileSize
Definition: Context.h:43
MCSubtargetInfo.h
HardwareUnit.h
llvm::mca::Context
Definition: Context.h:50
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
MCRegisterInfo.h
llvm::mca::Context::operator=
Context & operator=(const Context &C)=delete
llvm::mca::PipelineOptions::AssumeNoAlias
bool AssumeNoAlias
Definition: Context.h:46
llvm::mca::PipelineOptions::DecodersThroughput
unsigned DecodersThroughput
Definition: Context.h:41
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:128
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::mca::SourceMgr
Definition: SourceMgr.h:28
H
#define H(x, y, z)
Definition: MD5.cpp:58
llvm::mca::Context::addHardwareUnit
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
Definition: Context.h:63
llvm::mca::PipelineOptions::DispatchWidth
unsigned DispatchWidth
Definition: Context.h:42
llvm::mca::Context::getMCSubtargetInfo
const MCSubtargetInfo & getMCSubtargetInfo() const
Definition: Context.h:61
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::mca::PipelineOptions::EnableBottleneckAnalysis
bool EnableBottleneckAnalysis
Definition: Context.h:47