LLVM 18.0.0git
Context.h
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1//===---------------------------- Context.h ---------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a class for holding ownership of various simulated
11/// hardware units. A Context also provides a utility routine for constructing
12/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
13/// stages.
14///
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_MCA_CONTEXT_H
18#define LLVM_MCA_CONTEXT_H
19
24#include "llvm/MCA/Pipeline.h"
25#include "llvm/MCA/SourceMgr.h"
26#include <memory>
27
28namespace llvm {
29namespace mca {
30
31/// This is a convenience struct to hold the parameters necessary for creating
32/// the pre-built "default" out-of-order pipeline.
34 PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
35 unsigned LQS, unsigned SQS, bool NoAlias,
36 bool ShouldEnableBottleneckAnalysis = false)
37 : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
39 StoreQueueSize(SQS), AssumeNoAlias(NoAlias),
40 EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
42 unsigned DecodersThroughput; // Instructions per cycle.
43 unsigned DispatchWidth;
45 unsigned LoadQueueSize;
49};
50
51class Context {
53 const MCRegisterInfo &MRI;
54 const MCSubtargetInfo &STI;
55
56public:
57 Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
58 Context(const Context &C) = delete;
59 Context &operator=(const Context &C) = delete;
60
61 const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
62 const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
63
64 void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
65 Hardware.push_back(std::move(H));
66 }
67
68 /// Construct a basic pipeline for simulating an out-of-order pipeline.
69 /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
70 std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
72 CustomBehaviour &CB);
73
74 /// Construct a basic pipeline for simulating an in-order pipeline.
75 /// This pipeline consists of Fetch, InOrderIssue, and Retire stages.
76 std::unique_ptr<Pipeline> createInOrderPipeline(const PipelineOptions &Opts,
78 CustomBehaviour &CB);
79};
80
81} // namespace mca
82} // namespace llvm
83#endif // LLVM_MCA_CONTEXT_H
unsigned const MachineRegisterInfo * MRI
This file defines the base class CustomBehaviour which can be inherited from by specific targets (ex.
This file defines a base class for describing a simulated hardware unit.
This file contains abstract class SourceMgr and the default implementation, CircularSourceMgr.
#define H(x, y, z)
Definition: MD5.cpp:57
This file implements an ordered container of stages that simulate the pipeline of a hardware backend.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
const MCSubtargetInfo & getMCSubtargetInfo() const
Definition: Context.h:62
std::unique_ptr< Pipeline > createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an in-order pipeline.
Definition: Context.cpp:73
const MCRegisterInfo & getMCRegisterInfo() const
Definition: Context.h:61
Context & operator=(const Context &C)=delete
Context(const MCRegisterInfo &R, const MCSubtargetInfo &S)
Definition: Context.h:57
void addHardwareUnit(std::unique_ptr< HardwareUnit > H)
Definition: Context.h:64
std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)
Construct a basic pipeline for simulating an out-of-order pipeline.
Definition: Context.cpp:32
Context(const Context &C)=delete
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SourceMgr SrcMgr
Definition: Error.cpp:24
This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...
Definition: Context.h:33
PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS, bool NoAlias, bool ShouldEnableBottleneckAnalysis=false)
Definition: Context.h:34
unsigned DecodersThroughput
Definition: Context.h:42
Abstracting the input code sequence (a sequence of MCInst) and assigning unique identifiers to every ...
Definition: SourceMgr.h:29