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35 #define GET_INSTRINFO_MC_DESC
36 #include "RISCVGenInstrInfo.inc"
38 #define GET_REGINFO_MC_DESC
39 #include "RISCVGenRegisterInfo.inc"
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "RISCVGenSubtargetInfo.inc"
48 InitRISCVMCInstrInfo(
X);
54 InitRISCVMCRegisterInfo(
X, RISCV::X1);
72 bool LargeCodeModel =
false) {
80 if (CPU.
empty() || CPU ==
"generic")
81 CPU = TT.isArch64Bit() ?
"generic-rv64" :
"generic-rv32";
83 return createRISCVMCSubtargetInfoImpl(TT, CPU, CPU,
FS);
87 unsigned SyntaxVariant,
97 if (TT.isOSBinFormatELF())
122 if (isConditionalBranch(Inst)) {
149 return new RISCVMCInstrAnalysis(
Info);
154 std::unique_ptr<MCAsmBackend> &&MAB,
155 std::unique_ptr<MCObjectWriter> &&MOW,
156 std::unique_ptr<MCCodeEmitter> &&MCE,
MCELFStreamer * createRISCVELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE, bool RelaxAll)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheRISCV64Target()
Context object for machine code objects.
Target - Wrapper for Target specific information.
This class is intended to be used as a base class for asm properties and features specific to the tar...
static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Triple - Helper class for working with autoconf configuration names.
PassInstrumentationCallbacks PIC
static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)
Register a MCObjectFileInfo implementation for the given target.
Instances of this class represent a single low-level machine instruction.
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Streaming machine code generation interface.
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()
const Triple & getTargetTriple() const
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Target specific streamer interface.
Analysis containing CSE Info
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
#define LLVM_EXTERNAL_VISIBILITY
static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
void addInitialFrameState(const MCCFIInstruction &Inst)
static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)
static MCInstrInfo * createRISCVMCInstrInfo()
static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)
StringRef - Represent a constant reference to a string, i.e.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Interface to description of machine instruction set.
static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
unsigned getOpcode() const
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
const MCOperand & getOperand(unsigned i) const
Generic base class for all target subtargets.
static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)
Target & getTheRISCV32Target()
Wrapper class representing physical registers. Should be passed by value.