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32 #define DEBUG_TYPE "mccodeemitter"
34 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
51 unsigned Opcode =
MI.getOpcode();
102 assert(
MI.getOperand(OpNo).isReg() &&
"Operand should be a register");
125 assert(!MO.
isReg() &&
"Not expecting a register for this operand.");
155 assert(
MI.getOperand(OpNo+1).isReg());
173 assert(
MI.getOperand(OpNo+1).isReg());
191 assert(
MI.getOperand(OpNo+1).isReg());
197 "Expecting an immediate that is a multiple of 16");
216 assert(RegMO.
isReg() &&
"Base address must be a register.");
217 assert(MO.
isImm() &&
"Expecting an immediate operand.");
218 assert(!(MO.
getImm() % 8) &&
"Expecting offset to be 8 byte aligned.");
221 unsigned DX = (MO.
getImm() >> 3) & 0x3F;
239 assert(
MI.getOperand(OpNo + 1).isImm() &&
"Expecting an immediate.");
242 assert(RegBits == 0 &&
"Operand must be 0.");
267 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
268 "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
269 "VK_PPC_GOT_TPREL_PCREL.");
282 "Binary expression opcode must be an add.");
297 assert(isInt<34>(cast<MCConstantExpr>(
RHS)->getValue()) &&
298 "Value must fit in 34 bits.");
303 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
321 assert(
MI.getOperand(OpNo + 1).isReg() &&
"Expecting a register.");
334 assert(
MI.getOperand(OpNo+1).isReg());
349 assert(
MI.getOperand(OpNo+1).isReg());
364 assert(
MI.getOperand(OpNo+1).isReg());
389 bool isPPC64 = TT.isPPC64();
410 assert((
MI.getOpcode() == PPC::MTOCRF ||
MI.getOpcode() == PPC::MTOCRF8 ||
421 for (
unsigned i = 0;
i <
MI.getNumOperands();
i++) {
437 assert((
MI.getOpcode() != PPC::MTOCRF &&
MI.getOpcode() != PPC::MTOCRF8 &&
448 "Relocation required in an instruction that we cannot encode!");
464 support::endian::write<uint32_t>(OS,
Bits,
E);
469 support::endian::write<uint32_t>(OS,
Bits >> 32,
E);
470 support::endian::write<uint32_t>(OS,
Bits,
E);
481 unsigned Opcode =
MI.getOpcode();
487 unsigned Opcode =
MI.getOpcode();
492 #include "PPCGenMCCodeEmitter.inc"
VariantKind getKind() const
unsigned getInstSizeInBytes(const MCInst &MI) const
bool isPrefixedInstruction(const MCInst &MI) const
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
This is an optimization pass for GlobalISel generic memory operations.
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
Context object for machine code objects.
T reverseBits(T Val)
Reverse the bits in Val.
const MCRegisterInfo * getRegisterInfo() const
unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Reg
All possible values of the reg field in the ModR/M byte.
Triple - Helper class for working with autoconf configuration names.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Instances of this class represent a single low-level machine instruction.
Binary assembler expressions.
unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
const Triple & getTargetTriple() const
unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Describe properties that are true of each instruction in the target description file.
STATISTIC(NumFunctions, "Total number of functions")
This class implements an extremely fast bulk output stream that can only output to a stream.
uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getMachineOpValue - Return binary encoding of operand.
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
@ Binary
Binary expressions.
unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO)
uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Represent a reference to a symbol from inside an expression.
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
PowerPC TLS Dynamic Call Fixup
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getMemRI34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Opcode getOpcode() const
Get the kind of this binary expression.
Interface to description of machine instruction set.
MCCodeEmitter - Generic instruction encoding interface.
unsigned getMemRIHashEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
const MCExpr * getExpr() const
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, MCFixupKind Fixup) const
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
@ SymbolRef
References to labels and assigned expressions.
unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
@ Constant
Constant expressions.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Instances of this class represent operands of the MCInst class.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Generic base class for all target subtargets.
Base class for the full range of assembler expressions which are needed for parsing.
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
unsigned getReg() const
Returns the register number.