LLVM 17.0.0git
PPCMCCodeEmitter.cpp
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1//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCMCCodeEmitter.h"
15#include "PPCInstrInfo.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCFixup.h"
19#include "llvm/MC/MCInstrDesc.h"
21#include "llvm/Support/Endian.h"
27#include <cassert>
28#include <cstdint>
29
30using namespace llvm;
31
32#define DEBUG_TYPE "mccodeemitter"
33
34STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35
37 MCContext &Ctx) {
38 return new PPCMCCodeEmitter(MCII, Ctx);
39}
40
42getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
44 const MCSubtargetInfo &STI) const {
45 const MCOperand &MO = MI.getOperand(OpNo);
46
47 if (MO.isReg() || MO.isImm())
48 return getMachineOpValue(MI, MO, Fixups, STI);
49
50 const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo *>(&MCII);
51 unsigned Opcode = MI.getOpcode();
52 // Add a fixup for the branch target.
53 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
54 (InstrInfo->isNoTOCCallInstr(Opcode)
57 return 0;
58}
59
60unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
62 const MCSubtargetInfo &STI) const {
63 const MCOperand &MO = MI.getOperand(OpNo);
64 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
65
66 // Add a fixup for the branch target.
67 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
69 return 0;
70}
71
73getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
75 const MCSubtargetInfo &STI) const {
76 const MCOperand &MO = MI.getOperand(OpNo);
77 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
78
79 // Add a fixup for the branch target.
80 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
82 return 0;
83}
84
86getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
88 const MCSubtargetInfo &STI) const {
89 const MCOperand &MO = MI.getOperand(OpNo);
90 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
91
92 // Add a fixup for the branch target.
93 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
95 return 0;
96}
97
98unsigned
101 const MCSubtargetInfo &STI) const {
102 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
103 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
104 << 1;
105 return RegBits;
106}
107
108unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
110 const MCSubtargetInfo &STI) const {
111 const MCOperand &MO = MI.getOperand(OpNo);
112 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
113
114 // Add a fixup for the immediate field.
115 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
117 return 0;
118}
119
122 const MCSubtargetInfo &STI,
123 MCFixupKind Fixup) const {
124 const MCOperand &MO = MI.getOperand(OpNo);
125 assert(!MO.isReg() && "Not expecting a register for this operand.");
126 if (MO.isImm())
127 return getMachineOpValue(MI, MO, Fixups, STI);
128
129 // Add a fixup for the immediate field.
130 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
131 return 0;
132}
133
137 const MCSubtargetInfo &STI) const {
138 return getImm34Encoding(MI, OpNo, Fixups, STI,
140}
141
145 const MCSubtargetInfo &STI) const {
146 return getImm34Encoding(MI, OpNo, Fixups, STI,
148}
149
150unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
152 const MCSubtargetInfo &STI) const {
153 const MCOperand &MO = MI.getOperand(OpNo);
154 if (MO.isImm())
155 return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
156
157 // Add a fixup for the displacement field.
158 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
160 return 0;
161}
162
163unsigned
166 const MCSubtargetInfo &STI) const {
167 const MCOperand &MO = MI.getOperand(OpNo);
168 if (MO.isImm())
169 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
170
171 // Add a fixup for the displacement field.
172 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
174 return 0;
175}
176
177unsigned
180 const MCSubtargetInfo &STI) const {
181 const MCOperand &MO = MI.getOperand(OpNo);
182 if (MO.isImm()) {
183 assert(!(MO.getImm() % 16) &&
184 "Expecting an immediate that is a multiple of 16");
185 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);
186 }
187
188 // Otherwise add a fixup for the displacement field.
189 Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
191 return 0;
192}
193
194unsigned
197 const MCSubtargetInfo &STI) const {
198 // Encode imm for the hash load/store to stack for the ROP Protection
199 // instructions.
200 const MCOperand &MO = MI.getOperand(OpNo);
201
202 assert(MO.isImm() && "Expecting an immediate operand.");
203 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
204
205 unsigned DX = (MO.getImm() >> 3) & 0x3F;
206 return DX;
207}
208
212 const MCSubtargetInfo &STI) const {
213 // Encode the displacement part of pc-relative memri34, which is an imm34.
214 // The 34 bit immediate can fall into one of three cases:
215 // 1) It is a relocation to be filled in by the linker represented as:
216 // (MCExpr::SymbolRef)
217 // 2) It is a relocation + SignedOffset represented as:
218 // (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
219 // 3) It is a known value at compile time.
220
221 // If this is not a MCExpr then we are in case 3) and we are dealing with
222 // a value known at compile time, not a relocation.
223 const MCOperand &MO = MI.getOperand(OpNo);
224 if (!MO.isExpr())
225 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
226
227 // At this point in the function it is known that MO is of type MCExpr.
228 // Therefore we are dealing with either case 1) a symbol ref or
229 // case 2) a symbol ref plus a constant.
230 const MCExpr *Expr = MO.getExpr();
231 switch (Expr->getKind()) {
232 default:
233 llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
234 case MCExpr::SymbolRef: {
235 // Relocation alone.
236 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
237 (void)SRE;
238 // Currently these are the only valid PCRelative Relocations.
244 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
245 "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
246 "VK_PPC_GOT_TPREL_PCREL.");
247 // Generate the fixup for the relocation.
248 Fixups.push_back(
249 MCFixup::create(0, Expr,
250 static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
251 // Put zero in the location of the immediate. The linker will fill in the
252 // correct value based on the relocation.
253 return 0;
254 }
255 case MCExpr::Binary: {
256 // Relocation plus some offset.
257 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
259 "Binary expression opcode must be an add.");
260
261 const MCExpr *LHS = BE->getLHS();
262 const MCExpr *RHS = BE->getRHS();
263
264 // Need to check in both directions. Reloc+Offset and Offset+Reloc.
265 if (LHS->getKind() != MCExpr::SymbolRef)
266 std::swap(LHS, RHS);
267
268 if (LHS->getKind() != MCExpr::SymbolRef ||
269 RHS->getKind() != MCExpr::Constant)
270 llvm_unreachable("Expecting to have one constant and one relocation.");
271
272 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
273 (void)SRE;
274 assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) &&
275 "Value must fit in 34 bits.");
276
277 // Currently these are the only valid PCRelative Relocations.
280 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
281 // Generate the fixup for the relocation.
282 Fixups.push_back(
283 MCFixup::create(0, Expr,
284 static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
285 // Put zero in the location of the immediate. The linker will fill in the
286 // correct value based on the relocation.
287 return 0;
288 }
289 }
290}
291
295 const MCSubtargetInfo &STI) const {
296 // Encode the displacement part of a memri34.
297 const MCOperand &MO = MI.getOperand(OpNo);
298 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
299}
300
301unsigned
304 const MCSubtargetInfo &STI) const {
305 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 8).
306 const MCOperand &MO = MI.getOperand(OpNo);
307 assert(MO.isImm());
308 return getMachineOpValue(MI, MO, Fixups, STI) >> 3;
309}
310
311unsigned
314 const MCSubtargetInfo &STI) const {
315 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 4).
316 const MCOperand &MO = MI.getOperand(OpNo);
317 assert(MO.isImm());
318 return getMachineOpValue(MI, MO, Fixups, STI) >> 2;
319}
320
321unsigned
324 const MCSubtargetInfo &STI) const {
325 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 2).
326 const MCOperand &MO = MI.getOperand(OpNo);
327 assert(MO.isImm());
328 return getMachineOpValue(MI, MO, Fixups, STI) >> 1;
329}
330
331unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
333 const MCSubtargetInfo &STI) const {
334 const MCOperand &MO = MI.getOperand(OpNo);
335 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
336
337 // Add a fixup for the TLS register, which simply provides a relocation
338 // hint to the linker that this statement is part of a relocation sequence.
339 // Return the thread-pointer register's encoding. Add a one byte displacement
340 // if using PC relative memops.
341 const MCExpr *Expr = MO.getExpr();
342 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
343 bool IsPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL;
344 Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
346 const Triple &TT = STI.getTargetTriple();
347 bool isPPC64 = TT.isPPC64();
348 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
349}
350
351unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
353 const MCSubtargetInfo &STI) const {
354 // For special TLS calls, we need two fixups; one for the branch target
355 // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
356 // and one for the TLSGD or TLSLD symbol, which is emitted here.
357 const MCOperand &MO = MI.getOperand(OpNo+1);
358 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
360 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
361}
362
364get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
366 const MCSubtargetInfo &STI) const {
367 const MCOperand &MO = MI.getOperand(OpNo);
368 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
369 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
370 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
371 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
372}
373
374// Get the index for this operand in this instruction. This is needed for
375// computing the register number in PPCInstrInfo::getRegNumForOperand() for
376// any instructions that use a different numbering scheme for registers in
377// different operands.
378static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
379 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
380 const MCOperand &Op = MI.getOperand(i);
381 if (&Op == &MO)
382 return i;
383 }
384 llvm_unreachable("This operand is not part of this instruction");
385 return ~0U; // Silence any warnings about no return.
386}
387
389getMachineOpValue(const MCInst &MI, const MCOperand &MO,
391 const MCSubtargetInfo &STI) const {
392 if (MO.isReg()) {
393 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
394 // The GPR operand should come through here though.
395 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
396 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
397 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
398 unsigned OpNo = getOpIdxForMO(MI, MO);
399 unsigned Reg =
400 PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
401 MO.getReg(), OpNo);
402 return CTX.getRegisterInfo()->getEncodingValue(Reg);
403 }
404
405 assert(MO.isImm() &&
406 "Relocation required in an instruction that we cannot encode!");
407 return MO.getImm();
408}
409
412 const MCSubtargetInfo &STI) const {
413 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
414
415 // Output the constant in big/little endian byte order.
416 unsigned Size = getInstSizeInBytes(MI);
418 switch (Size) {
419 case 0:
420 break;
421 case 4:
422 support::endian::write<uint32_t>(OS, Bits, E);
423 break;
424 case 8:
425 // If we emit a pair of instructions, the first one is
426 // always in the top 32 bits, even on little-endian.
427 support::endian::write<uint32_t>(OS, Bits >> 32, E);
428 support::endian::write<uint32_t>(OS, Bits, E);
429 break;
430 default:
431 llvm_unreachable("Invalid instruction size");
432 }
433
434 ++MCNumEmitted; // Keep track of the # of mi's emitted.
435}
436
437// Get the number of bytes used to encode the given MCInst.
439 unsigned Opcode = MI.getOpcode();
440 const MCInstrDesc &Desc = MCII.get(Opcode);
441 return Desc.getSize();
442}
443
445 unsigned Opcode = MI.getOpcode();
446 const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII);
447 return InstrInfo->isPrefixed(Opcode);
448}
449
450#include "PPCGenMCCodeEmitter.inc"
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint64_t Size
IRTranslator LLVM IR MI
static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO)
PowerPC TLS Dynamic Call Fixup
return InstrInfo
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
Value * RHS
Value * LHS
Binary assembler expressions.
Definition: MCExpr.h:481
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:628
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:631
Opcode getOpcode() const
Get the kind of this binary expression.
Definition: MCExpr.h:625
@ Add
Addition.
Definition: MCExpr.h:484
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:76
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ Constant
Constant expressions.
Definition: MCExpr.h:39
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
@ Binary
Binary expressions.
Definition: MCExpr.h:38
ExprKind getKind() const
Definition: MCExpr.h:81
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:605
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
VariantKind getKind() const
Definition: MCExpr.h:401
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:796
unsigned getDispSPE2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getDispRIHashEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getDispRI34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getDispRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getDispSPE8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getDispRIX16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
bool isPrefixedInstruction(const MCInst &MI) const
unsigned getDispSPE4Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getMachineOpValue - Return binary encoding of operand.
unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, MCFixupKind Fixup) const
unsigned getInstSizeInBytes(const MCInst &MI) const
unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_ppc_pcrel34
Definition: PPCFixupKinds.h:44
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
Definition: PPCFixupKinds.h:33
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
Definition: PPCFixupKinds.h:37
@ fixup_ppc_br24_notoc
Definition: PPCFixupKinds.h:24
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
Definition: PPCFixupKinds.h:27
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
Definition: PPCFixupKinds.h:57
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
Definition: PPCFixupKinds.h:41
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
Definition: PPCFixupKinds.h:53
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
Definition: PPCFixupKinds.h:30
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860