13#ifndef LLVM_LIB_TARGET_PPC_MCCODEEMITTER_PPCCODEEMITTER_H 
   14#define LLVM_LIB_TARGET_PPC_MCCODEEMITTER_PPCCODEEMITTER_H 
   32      : MCII(mcii), CTX(ctx),
 
   33        IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
 
 
   50  template <MCFixupKind Fixup>
 
 
Context object for machine code objects.
 
Instances of this class represent a single low-level machine instruction.
 
Interface to description of machine instruction set.
 
Instances of this class represent operands of the MCInst class.
 
Generic base class for all target subtargets.
 
unsigned getDispSPE2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
void operator=(const PPCMCCodeEmitter &)=delete
 
unsigned getDispRIHashEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
uint64_t getDispRI34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getDispRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getDispSPE8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
Encode the given Inst to bytes and append to CB.
 
unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
 
bool isNoTOCCallInstr(const MCInst &MI) const
Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.
 
unsigned getDispRIX16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
~PPCMCCodeEmitter() override=default
 
uint64_t getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
bool isPrefixedInstruction(const MCInst &MI) const
 
unsigned getDispSPE4Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getMachineOpValue - Return binary encoding of operand.
 
unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
PPCMCCodeEmitter(const PPCMCCodeEmitter &)=delete
 
uint64_t getImmEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getInstSizeInBytes(const MCInst &MI) const
 
unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
 
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
 
This is an optimization pass for GlobalISel generic memory operations.