LLVM  14.0.0git
AVRAsmBackend.cpp
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1 //===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AVRAsmBackend class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "llvm/MC/MCAsmBackend.h"
17 #include "llvm/MC/MCAssembler.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCDirectives.h"
21 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCValue.h"
29 
30 // FIXME: we should be doing checks to make sure asm operands
31 // are not out of bounds.
32 
33 namespace adjust {
34 
35 using namespace llvm;
36 
37 static void signed_width(unsigned Width, uint64_t Value,
38  std::string Description, const MCFixup &Fixup,
39  MCContext *Ctx = nullptr) {
40  if (!isIntN(Width, Value)) {
41  std::string Diagnostic = "out of range " + Description;
42 
43  int64_t Min = minIntN(Width);
44  int64_t Max = maxIntN(Width);
45 
46  Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
47  " to " + std::to_string(Max) + ")";
48 
49  if (Ctx) {
50  Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
51  } else {
52  llvm_unreachable(Diagnostic.c_str());
53  }
54  }
55 }
56 
57 static void unsigned_width(unsigned Width, uint64_t Value,
58  std::string Description, const MCFixup &Fixup,
59  MCContext *Ctx = nullptr) {
60  if (!isUIntN(Width, Value)) {
61  std::string Diagnostic = "out of range " + Description;
62 
63  int64_t Max = maxUIntN(Width);
64 
65  Diagnostic +=
66  " (expected an integer in the range 0 to " + std::to_string(Max) + ")";
67 
68  if (Ctx) {
69  Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
70  } else {
71  llvm_unreachable(Diagnostic.c_str());
72  }
73  }
74 }
75 
76 /// Adjusts the value of a branch target before fixup application.
77 static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
78  MCContext *Ctx = nullptr) {
79  // We have one extra bit of precision because the value is rightshifted by
80  // one.
81  unsigned_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
82 
83  // Rightshifts the value by one.
85 }
86 
87 /// Adjusts the value of a relative branch target before fixup application.
88 static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup,
89  uint64_t &Value, MCContext *Ctx = nullptr) {
90  // We have one extra bit of precision because the value is rightshifted by
91  // one.
92  signed_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
93 
94  // Rightshifts the value by one.
96 }
97 
98 /// 22-bit absolute fixup.
99 ///
100 /// Resolves to:
101 /// 1001 kkkk 010k kkkk kkkk kkkk 111k kkkk
102 ///
103 /// Offset of 0 (so the result is left shifted by 3 bits before application).
104 static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
105  MCContext *Ctx = nullptr) {
106  adjustBranch(Size, Fixup, Value, Ctx);
107 
108  auto top = Value & (0xf00000 << 6); // the top four bits
109  auto middle = Value & (0x1ffff << 5); // the middle 13 bits
110  auto bottom = Value & 0x1f; // end bottom 5 bits
111 
112  Value = (top << 6) | (middle << 3) | (bottom << 0);
113 }
114 
115 /// 7-bit PC-relative fixup.
116 ///
117 /// Resolves to:
118 /// 0000 00kk kkkk k000
119 /// Offset of 0 (so the result is left shifted by 3 bits before application).
120 static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
121  MCContext *Ctx = nullptr) {
123 
124  // Because the value may be negative, we must mask out the sign bits
125  Value &= 0x7f;
126 }
127 
128 /// 12-bit PC-relative fixup.
129 /// Yes, the fixup is 12 bits even though the name says otherwise.
130 ///
131 /// Resolves to:
132 /// 0000 kkkk kkkk kkkk
133 /// Offset of 0 (so the result isn't left-shifted before application).
134 static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
135  MCContext *Ctx = nullptr) {
137 
138  // Because the value may be negative, we must mask out the sign bits
139  Value &= 0xfff;
140 }
141 
142 /// 6-bit fixup for the immediate operand of the STD/LDD family of
143 /// instructions.
144 ///
145 /// Resolves to:
146 /// 10q0 qq10 0000 1qqq
147 static void fixup_6(const MCFixup &Fixup, uint64_t &Value,
148  MCContext *Ctx = nullptr) {
149  unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
150 
151  Value = ((Value & 0x20) << 8) | ((Value & 0x18) << 7) | (Value & 0x07);
152 }
153 
154 /// 6-bit fixup for the immediate operand of the ADIW family of
155 /// instructions.
156 ///
157 /// Resolves to:
158 /// 0000 0000 kk00 kkkk
159 static void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value,
160  MCContext *Ctx = nullptr) {
161  unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
162 
163  Value = ((Value & 0x30) << 2) | (Value & 0x0f);
164 }
165 
166 /// 5-bit port number fixup on the SBIC family of instructions.
167 ///
168 /// Resolves to:
169 /// 0000 0000 AAAA A000
170 static void fixup_port5(const MCFixup &Fixup, uint64_t &Value,
171  MCContext *Ctx = nullptr) {
172  unsigned_width(5, Value, std::string("port number"), Fixup, Ctx);
173 
174  Value &= 0x1f;
175 
176  Value <<= 3;
177 }
178 
179 /// 6-bit port number fixup on the `IN` family of instructions.
180 ///
181 /// Resolves to:
182 /// 1011 0AAd dddd AAAA
183 static void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
184  MCContext *Ctx = nullptr) {
185  unsigned_width(6, Value, std::string("port number"), Fixup, Ctx);
186 
187  Value = ((Value & 0x30) << 5) | (Value & 0x0f);
188 }
189 
190 /// Adjusts a program memory address.
191 /// This is a simple right-shift.
192 static void pm(uint64_t &Value) { Value >>= 1; }
193 
194 /// Fixups relating to the LDI instruction.
195 namespace ldi {
196 
197 /// Adjusts a value to fix up the immediate of an `LDI Rd, K` instruction.
198 ///
199 /// Resolves to:
200 /// 0000 KKKK 0000 KKKK
201 /// Offset of 0 (so the result isn't left-shifted before application).
202 static void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
203  MCContext *Ctx = nullptr) {
204  uint64_t upper = Value & 0xf0;
205  uint64_t lower = Value & 0x0f;
206 
207  Value = (upper << 4) | lower;
208 }
209 
210 static void neg(uint64_t &Value) { Value *= -1; }
211 
212 static void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
213  MCContext *Ctx = nullptr) {
214  Value &= 0xff;
215  ldi::fixup(Size, Fixup, Value, Ctx);
216 }
217 
218 static void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
219  MCContext *Ctx = nullptr) {
220  Value = (Value & 0xff00) >> 8;
221  ldi::fixup(Size, Fixup, Value, Ctx);
222 }
223 
224 static void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
225  MCContext *Ctx = nullptr) {
226  Value = (Value & 0xff0000) >> 16;
227  ldi::fixup(Size, Fixup, Value, Ctx);
228 }
229 
230 static void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
231  MCContext *Ctx = nullptr) {
232  Value = (Value & 0xff000000) >> 24;
233  ldi::fixup(Size, Fixup, Value, Ctx);
234 }
235 
236 } // namespace ldi
237 } // namespace adjust
238 
239 namespace llvm {
240 
241 // Prepare value for the target space for it
243  const MCValue &Target, uint64_t &Value,
244  MCContext *Ctx) const {
245  // The size of the fixup in bits.
247 
248  unsigned Kind = Fixup.getKind();
249  switch (Kind) {
250  default:
251  llvm_unreachable("unhandled fixup");
252  case AVR::fixup_7_pcrel:
254  break;
255  case AVR::fixup_13_pcrel:
257  break;
258  case AVR::fixup_call:
260  break;
261  case AVR::fixup_ldi:
263  break;
264  case AVR::fixup_lo8_ldi:
266  break;
269  adjust::pm(Value);
271  break;
272  case AVR::fixup_hi8_ldi:
274  break;
277  adjust::pm(Value);
279  break;
280  case AVR::fixup_hh8_ldi:
283  adjust::pm(Value);
284 
286  break;
287  case AVR::fixup_ms8_ldi:
289  break;
290 
294  adjust::pm(Value);
295 
298  break;
302  adjust::pm(Value);
303 
306  break;
310  adjust::pm(Value);
311 
314  break;
318  break;
319  case AVR::fixup_16:
320  adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
321 
322  Value &= 0xffff;
323  break;
324  case AVR::fixup_16_pm:
325  Value >>= 1; // Flash addresses are always shifted.
326  adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
327 
328  Value &= 0xffff;
329  break;
330 
331  case AVR::fixup_6:
332  adjust::fixup_6(Fixup, Value, Ctx);
333  break;
334  case AVR::fixup_6_adiw:
336  break;
337 
338  case AVR::fixup_port5:
340  break;
341 
342  case AVR::fixup_port6:
344  break;
345 
346  // Fixups which do not require adjustments.
347  case FK_Data_1:
348  case FK_Data_2:
349  case FK_Data_4:
350  case FK_Data_8:
351  break;
352 
353  case FK_GPRel_4:
354  llvm_unreachable("don't know how to adjust this fixup");
355  break;
356  }
357 }
358 
359 std::unique_ptr<MCObjectTargetWriter>
362 }
363 
365  const MCValue &Target,
367  bool IsResolved,
368  const MCSubtargetInfo *STI) const {
369  adjustFixupValue(Fixup, Target, Value, &Asm.getContext());
370  if (Value == 0)
371  return; // Doesn't change encoding.
372 
374 
375  // The number of bits in the fixup mask
376  auto NumBits = Info.TargetSize + Info.TargetOffset;
377  auto NumBytes = (NumBits / 8) + ((NumBits % 8) == 0 ? 0 : 1);
378 
379  // Shift the value into position.
380  Value <<= Info.TargetOffset;
381 
382  unsigned Offset = Fixup.getOffset();
383  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
384 
385  // For each byte of the fragment that the fixup touches, mask in the
386  // bits from the fixup value.
387  for (unsigned i = 0; i < NumBytes; ++i) {
388  uint8_t mask = (((Value >> (i * 8)) & 0xff));
389  Data[Offset + i] |= mask;
390  }
391 }
392 
394  // NOTE: Many AVR fixups work on sets of non-contignous bits. We work around
395  // this by saying that the fixup is the size of the entire instruction.
396  const static MCFixupKindInfo Infos[AVR::NumTargetFixupKinds] = {
397  // This table *must* be in same the order of fixup_* kinds in
398  // AVRFixupKinds.h.
399  //
400  // name offset bits flags
401  {"fixup_32", 0, 32, 0},
402 
403  {"fixup_7_pcrel", 3, 7, MCFixupKindInfo::FKF_IsPCRel},
404  {"fixup_13_pcrel", 0, 12, MCFixupKindInfo::FKF_IsPCRel},
405 
406  {"fixup_16", 0, 16, 0},
407  {"fixup_16_pm", 0, 16, 0},
408 
409  {"fixup_ldi", 0, 8, 0},
410 
411  {"fixup_lo8_ldi", 0, 8, 0},
412  {"fixup_hi8_ldi", 0, 8, 0},
413  {"fixup_hh8_ldi", 0, 8, 0},
414  {"fixup_ms8_ldi", 0, 8, 0},
415 
416  {"fixup_lo8_ldi_neg", 0, 8, 0},
417  {"fixup_hi8_ldi_neg", 0, 8, 0},
418  {"fixup_hh8_ldi_neg", 0, 8, 0},
419  {"fixup_ms8_ldi_neg", 0, 8, 0},
420 
421  {"fixup_lo8_ldi_pm", 0, 8, 0},
422  {"fixup_hi8_ldi_pm", 0, 8, 0},
423  {"fixup_hh8_ldi_pm", 0, 8, 0},
424 
425  {"fixup_lo8_ldi_pm_neg", 0, 8, 0},
426  {"fixup_hi8_ldi_pm_neg", 0, 8, 0},
427  {"fixup_hh8_ldi_pm_neg", 0, 8, 0},
428 
429  {"fixup_call", 0, 22, 0},
430 
431  {"fixup_6", 0, 16, 0}, // non-contiguous
432  {"fixup_6_adiw", 0, 6, 0},
433 
434  {"fixup_lo8_ldi_gs", 0, 8, 0},
435  {"fixup_hi8_ldi_gs", 0, 8, 0},
436 
437  {"fixup_8", 0, 8, 0},
438  {"fixup_8_lo8", 0, 8, 0},
439  {"fixup_8_hi8", 0, 8, 0},
440  {"fixup_8_hlo8", 0, 8, 0},
441 
442  {"fixup_diff8", 0, 8, 0},
443  {"fixup_diff16", 0, 16, 0},
444  {"fixup_diff32", 0, 32, 0},
445 
446  {"fixup_lds_sts_16", 0, 16, 0},
447 
448  {"fixup_port6", 0, 16, 0}, // non-contiguous
449  {"fixup_port5", 3, 5, 0},
450  };
451 
454 
456  "Invalid kind!");
457 
458  return Infos[Kind - FirstTargetFixupKind];
459 }
460 
462  const MCSubtargetInfo *STI) const {
463  // If the count is not 2-byte aligned, we must be writing data into the text
464  // section (otherwise we have unaligned instructions, and thus have far
465  // bigger problems), so just write zeros instead.
466  assert((Count % 2) == 0 && "NOP instructions must be 2 bytes");
467 
468  OS.write_zeros(Count);
469  return true;
470 }
471 
473  const MCFixup &Fixup,
474  const MCValue &Target) {
475  switch ((unsigned)Fixup.getKind()) {
476  default:
477  return false;
478  // Fixups which should always be recorded as relocations.
479  case AVR::fixup_7_pcrel:
480  case AVR::fixup_13_pcrel:
481  case AVR::fixup_call:
482  return true;
483  }
484 }
485 
487  const MCRegisterInfo &MRI,
488  const llvm::MCTargetOptions &TO) {
489  return new AVRAsmBackend(STI.getTargetTriple().getOS());
490 }
491 
492 } // end of namespace llvm
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
MathExtras.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:74
llvm::raw_ostream::write_zeros
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
Definition: raw_ostream.cpp:502
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
MCDirectives.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
ErrorHandling.h
adjust::fixup_call
static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
22-bit absolute fixup.
Definition: AVRAsmBackend.cpp:104
llvm::AVRAsmBackend::adjustFixupValue
void adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t &Value, MCContext *Ctx=nullptr) const
Definition: AVRAsmBackend.cpp:242
MCAssembler.h
llvm::AVR::fixup_hh8_ldi_neg
@ fixup_hh8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated negat...
Definition: AVRFixupKinds.h:72
llvm::AVR::fixups::adjustBranchTarget
void adjustBranchTarget(T &val)
Adjusts the value of a branch target.
Definition: AVRFixupKinds.h:141
llvm::maxIntN
int64_t maxIntN(int64_t N)
Gets the maximum value for a N-bit signed integer.
Definition: MathExtras.h:446
MCFixupKindInfo.h
llvm::AVR::fixup_lo8_ldi_pm_neg
@ fixup_lo8_ldi_pm_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:92
llvm::AVR::fixup_port5
@ fixup_port5
A 5-bit port address.
Definition: AVRFixupKinds.h:126
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::AVR::fixup_hh8_ldi_pm
@ fixup_hh8_ldi_pm
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 24-bit progra...
Definition: AVRFixupKinds.h:87
llvm::AVR::fixup_hh8_ldi
@ fixup_hh8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 24-bit value ...
Definition: AVRFixupKinds.h:59
llvm::AVRAsmBackend::shouldForceRelocation
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
Definition: AVRAsmBackend.cpp:472
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::AVR::fixup_lo8_ldi
@ fixup_lo8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a 16-bit value ...
Definition: AVRFixupKinds.h:53
llvm::AVR::fixup_hi8_ldi_neg
@ fixup_hi8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:69
adjust::fixup_6
static void fixup_6(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
6-bit fixup for the immediate operand of the STD/LDD family of instructions.
Definition: AVRAsmBackend.cpp:147
llvm::createAVRELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAVRELFObjectWriter(uint8_t OSABI)
Creates an ELF object writer for AVR.
Definition: AVRELFObjectWriter.cpp:153
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
llvm::FK_GPRel_4
@ FK_GPRel_4
A four-byte gp relative fixup.
Definition: MCFixup.h:34
MCAsmBackend.h
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
llvm::AVR::fixup_13_pcrel
@ fixup_13_pcrel
A 12-bit PC-relative fixup for the family of branches which take 12-bit targets (RJMP,...
Definition: AVRFixupKinds.h:41
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCContext.h
adjust::signed_width
static void signed_width(unsigned Width, uint64_t Value, std::string Description, const MCFixup &Fixup, MCContext *Ctx=nullptr)
Definition: AVRAsmBackend.cpp:37
llvm::isUIntN
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:455
MCSubtargetInfo.h
llvm::AVR::fixup_port6
@ fixup_port6
A 6-bit port address.
Definition: AVRFixupKinds.h:124
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AVR::fixup_lo8_ldi_pm
@ fixup_lo8_ldi_pm
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a 16-bit progra...
Definition: AVRFixupKinds.h:79
llvm::AVR::fixup_6
@ fixup_6
Definition: AVRFixupKinds.h:105
llvm::AVR::fixup_lo8_ldi_neg
@ fixup_lo8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the lower 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:66
llvm::isIntN
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:460
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::AVR::fixup_ms8_ldi_neg
@ fixup_ms8_ldi_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated negat...
Definition: AVRFixupKinds.h:75
llvm::AVR::fixup_hi8_ldi_pm
@ fixup_hi8_ldi_pm
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 16-bit progra...
Definition: AVRFixupKinds.h:83
llvm::AVRAsmBackend
Utilities for manipulating generated AVR machine code.
Definition: AVRAsmBackend.h:29
llvm::MCAssembler
Definition: MCAssembler.h:60
llvm::minIntN
int64_t minIntN(int64_t N)
Gets the minimum value for a N-bit signed integer.
Definition: MathExtras.h:439
adjust::fixup_port6
static void fixup_port6(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
6-bit port number fixup on the IN family of instructions.
Definition: AVRAsmBackend.cpp:183
uint64_t
llvm::Triple::getOS
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:316
MCELFObjectWriter.h
adjust::fixup_port5
static void fixup_port5(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
5-bit port number fixup on the SBIC family of instructions.
Definition: AVRAsmBackend.cpp:170
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
llvm::MCFixupKindInfo::TargetSize
unsigned TargetSize
The number of bits written by this fixup.
Definition: MCFixupKindInfo.h:42
AVRAsmBackend.h
adjust::ldi::hh8
static void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Definition: AVRAsmBackend.cpp:224
llvm::AVR::fixup_call
@ fixup_call
A 22-bit fixup for the target of a CALL k or JMP k instruction.
Definition: AVRFixupKinds.h:103
llvm::AVRAsmBackend::getFixupKindInfo
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
Definition: AVRAsmBackend.cpp:393
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AVRAsmBackend::createObjectTargetWriter
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
Definition: AVRAsmBackend.cpp:360
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
AVRMCTargetDesc.h
llvm::createAVRAsmBackend
MCAsmBackend * createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const llvm::MCTargetOptions &TO)
Creates an assembly backend for AVR.
Definition: AVRAsmBackend.cpp:486
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::AVR::fixup_hi8_ldi_gs
@ fixup_hi8_ldi_gs
Definition: AVRFixupKinds.h:110
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:101
AVRFixupKinds.h
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:235
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
adjust::adjustBranch
static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts the value of a branch target before fixup application.
Definition: AVRAsmBackend.cpp:77
adjust::pm
static void pm(uint64_t &Value)
Adjusts a program memory address.
Definition: AVRAsmBackend.cpp:192
adjust::adjustRelativeBranch
static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts the value of a relative branch target before fixup application.
Definition: AVRAsmBackend.cpp:88
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AVR::fixup_ldi
@ fixup_ldi
Replaces the 8-bit immediate with another value.
Definition: AVRFixupKinds.h:49
adjust
Definition: AVRAsmBackend.cpp:33
adjust::ldi::hi8
static void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Definition: AVRAsmBackend.cpp:218
adjust::ldi::fixup
static void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts a value to fix up the immediate of an LDI Rd, K instruction.
Definition: AVRAsmBackend.cpp:202
MCObjectWriter.h
llvm::AVR::fixup_7_pcrel
@ fixup_7_pcrel
A 7-bit PC-relative fixup for the family of conditional branches which take 7-bit targets (BRNE,...
Definition: AVRFixupKinds.h:32
adjust::unsigned_width
static void unsigned_width(unsigned Width, uint64_t Value, std::string Description, const MCFixup &Fixup, MCContext *Ctx=nullptr)
Definition: AVRAsmBackend.cpp:57
llvm::AVR::fixup_16
@ fixup_16
A 16-bit address.
Definition: AVRFixupKinds.h:44
llvm::AVRAsmBackend::getNumFixupKinds
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: AVRAsmBackend.h:47
adjust::fixup_7_pcrel
static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
7-bit PC-relative fixup.
Definition: AVRAsmBackend.cpp:120
llvm::AVR::fixup_6_adiw
@ fixup_6_adiw
A symbol+addr fixup for the `LDD <x>+<n>, <r>" family of instructions.
Definition: AVRFixupKinds.h:107
adjust::ldi::neg
static void neg(uint64_t &Value)
Definition: AVRAsmBackend.cpp:210
MCValue.h
llvm::AVRAsmBackend::writeNopData
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
Definition: AVRAsmBackend.cpp:461
adjust::fixup_13_pcrel
static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
12-bit PC-relative fixup.
Definition: AVRAsmBackend.cpp:134
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
adjust::ldi::ms8
static void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Definition: AVRAsmBackend.cpp:230
llvm::AVR::fixup_ms8_ldi
@ fixup_ms8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 32-bit value ...
Definition: AVRFixupKinds.h:62
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::AVRAsmBackend::applyFixup
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Definition: AVRAsmBackend.cpp:364
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::AVR::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: AVRFixupKinds.h:130
llvm::to_string
std::string to_string(const T &Value)
Definition: ScopedPrinter.h:63
neg
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 neg
Definition: README.txt:1271
llvm::AVR::fixup_hi8_ldi
@ fixup_hi8_ldi
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a 16-bit value ...
Definition: AVRFixupKinds.h:56
adjust::ldi::lo8
static void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Definition: AVRAsmBackend.cpp:212
llvm::AVR::fixup_hh8_ldi_pm_neg
@ fixup_hh8_ldi_pm_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 24-bi...
Definition: AVRFixupKinds.h:100
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::maxUIntN
uint64_t maxUIntN(uint64_t N)
Gets the maximum value for a N-bit unsigned integer.
Definition: MathExtras.h:428
raw_ostream.h
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
llvm::AVR::fixup_16_pm
@ fixup_16_pm
A 16-bit program memory address.
Definition: AVRFixupKinds.h:46
llvm::AVR::fixup_lo8_ldi_gs
@ fixup_lo8_ldi_gs
Definition: AVRFixupKinds.h:109
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
adjust::fixup_6_adiw
static void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
6-bit fixup for the immediate operand of the ADIW family of instructions.
Definition: AVRAsmBackend.cpp:159
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AVR::fixup_hi8_ldi_pm_neg
@ fixup_hi8_ldi_pm_neg
Replaces the immediate operand of a 16-bit Rd, K instruction with the upper 8 bits of a negated 16-bi...
Definition: AVRFixupKinds.h:96