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39 return Value & 0xfffc;
43 return Value & 0x3fffffc;
45 return Value & 0xffff;
48 return Value & 0xfffc;
51 return Value & 0x3ffffffff;
92 unsigned getNumFixupKinds()
const override {
102 {
"fixup_ppc_br24abs", 6, 24, 0 },
103 {
"fixup_ppc_brcond14abs", 16, 14, 0 },
104 {
"fixup_ppc_half16", 0, 16, 0 },
105 {
"fixup_ppc_half16ds", 0, 14, 0 },
107 {
"fixup_ppc_imm34", 0, 34, 0 },
108 {
"fixup_ppc_nofixup", 0, 0, 0 }
115 {
"fixup_ppc_br24abs", 2, 24, 0 },
116 {
"fixup_ppc_brcond14abs", 2, 14, 0 },
117 {
"fixup_ppc_half16", 0, 16, 0 },
118 {
"fixup_ppc_half16ds", 2, 14, 0 },
120 {
"fixup_ppc_imm34", 0, 34, 0 },
121 {
"fixup_ppc_nofixup", 0, 0, 0 }
155 for (
unsigned i = 0;
i != NumBytes; ++
i) {
164 switch ((
unsigned)Kind) {
174 if (
const auto *
S = dyn_cast<MCSymbolELF>(&
A->getSymbol())) {
178 unsigned Other =
S->getOther() << 2;
187 bool fixupNeedsRelaxation(
const MCFixup &Fixup,
195 void relaxInstruction(
MCInst &Inst,
205 support::endian::write<uint32_t>(OS, 0x60000000, Endian);
218 class ELFPPCAsmBackend :
public PPCAsmBackend {
220 ELFPPCAsmBackend(
const Target &
T,
const Triple &TT) : PPCAsmBackend(
T,
TT) {}
222 std::unique_ptr<MCObjectTargetWriter>
223 createObjectTargetWriter()
const override {
225 bool Is64 =
TT.isPPC64();
229 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override;
232 class XCOFFPPCAsmBackend :
public PPCAsmBackend {
235 : PPCAsmBackend(
T,
TT) {}
237 std::unique_ptr<MCObjectTargetWriter>
238 createObjectTargetWriter()
const override {
245 std::optional<MCFixupKind>
246 ELFPPCAsmBackend::getFixupKind(
StringRef Name)
const {
247 if (
TT.isOSBinFormatELF()) {
251 #define ELF_RELOC(X, Y) .Case(#X, Y)
252 #include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
254 .
Case(
"BFD_RELOC_NONE", ELF::R_PPC64_NONE)
255 .
Case(
"BFD_RELOC_16", ELF::R_PPC64_ADDR16)
256 .
Case(
"BFD_RELOC_32", ELF::R_PPC64_ADDR32)
257 .
Case(
"BFD_RELOC_64", ELF::R_PPC64_ADDR64)
261 #define ELF_RELOC(X, Y) .Case(#X, Y)
262 #include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
264 .
Case(
"BFD_RELOC_NONE", ELF::R_PPC_NONE)
265 .
Case(
"BFD_RELOC_16", ELF::R_PPC_ADDR16)
266 .
Case(
"BFD_RELOC_32", ELF::R_PPC_ADDR32)
280 if (TT.isOSBinFormatXCOFF())
281 return new XCOFFPPCAsmBackend(
T, TT);
283 return new ELFPPCAsmBackend(
T, TT);
StringSwitch & Case(StringLiteral S, T Value)
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
The instances of the Type class are immutable: once they are created, they are never changed.
Instances of this class represent a single low-level machine instruction.
Error applyFixup(LinkGraph &G, Block &B, const Edge &E)
Apply fixup expression for edge to block content.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_4
A four-byte fixup.
Generic interface to target specific assembler backends.
const Triple & getTargetTriple() const
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
This class implements an extremely fast bulk output stream that can only output to a stream.
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target independent information on a fixup kind.
std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Construct an PPC ELF object writer.
@ FK_Data_1
A one-byte fixup.
Represent a reference to a symbol from inside an expression.
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
PowerPC TLS Dynamic Call Fixup
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static unsigned getFixupKindNumBytes(unsigned Kind)
unsigned const MachineRegisterInfo * MRI
Encapsulates the layout of an assembly file at a particular point in time.
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_Data_8
A eight-byte fixup.
std::optional< std::vector< StOtherPiece > > Other
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
A switch()-like statement whose cases are string literals.
This represents an "assembler immediate".
@ FK_Data_2
A two-byte fixup.
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.